1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <drm/drm_managed.h> 7 #include <drm/intel-gtt.h> 8 9 #include "gem/i915_gem_internal.h" 10 #include "gem/i915_gem_lmem.h" 11 #include "pxp/intel_pxp.h" 12 13 #include "i915_drv.h" 14 #include "i915_perf_oa_regs.h" 15 #include "intel_context.h" 16 #include "intel_engine_pm.h" 17 #include "intel_engine_regs.h" 18 #include "intel_ggtt_gmch.h" 19 #include "intel_gt.h" 20 #include "intel_gt_buffer_pool.h" 21 #include "intel_gt_clock_utils.h" 22 #include "intel_gt_debugfs.h" 23 #include "intel_gt_mcr.h" 24 #include "intel_gt_pm.h" 25 #include "intel_gt_regs.h" 26 #include "intel_gt_requests.h" 27 #include "intel_migrate.h" 28 #include "intel_mocs.h" 29 #include "intel_pci_config.h" 30 #include "intel_pm.h" 31 #include "intel_rc6.h" 32 #include "intel_renderstate.h" 33 #include "intel_rps.h" 34 #include "intel_sa_media.h" 35 #include "intel_gt_sysfs.h" 36 #include "intel_uncore.h" 37 #include "shmem_utils.h" 38 39 void intel_gt_common_init_early(struct intel_gt *gt) 40 { 41 spin_lock_init(gt->irq_lock); 42 43 INIT_LIST_HEAD(>->lmem_userfault_list); 44 mutex_init(>->lmem_userfault_lock); 45 INIT_LIST_HEAD(>->closed_vma); 46 spin_lock_init(>->closed_lock); 47 48 init_llist_head(>->watchdog.list); 49 INIT_WORK(>->watchdog.work, intel_gt_watchdog_work); 50 51 intel_gt_init_buffer_pool(gt); 52 intel_gt_init_reset(gt); 53 intel_gt_init_requests(gt); 54 intel_gt_init_timelines(gt); 55 mutex_init(>->tlb.invalidate_lock); 56 seqcount_mutex_init(>->tlb.seqno, >->tlb.invalidate_lock); 57 intel_gt_pm_init_early(gt); 58 59 intel_uc_init_early(>->uc); 60 intel_rps_init_early(>->rps); 61 } 62 63 /* Preliminary initialization of Tile 0 */ 64 int intel_root_gt_init_early(struct drm_i915_private *i915) 65 { 66 struct intel_gt *gt = to_gt(i915); 67 68 gt->i915 = i915; 69 gt->uncore = &i915->uncore; 70 gt->irq_lock = drmm_kzalloc(&i915->drm, sizeof(*gt->irq_lock), GFP_KERNEL); 71 if (!gt->irq_lock) 72 return -ENOMEM; 73 74 intel_gt_common_init_early(gt); 75 76 return 0; 77 } 78 79 static int intel_gt_probe_lmem(struct intel_gt *gt) 80 { 81 struct drm_i915_private *i915 = gt->i915; 82 unsigned int instance = gt->info.id; 83 int id = INTEL_REGION_LMEM_0 + instance; 84 struct intel_memory_region *mem; 85 int err; 86 87 mem = intel_gt_setup_lmem(gt); 88 if (IS_ERR(mem)) { 89 err = PTR_ERR(mem); 90 if (err == -ENODEV) 91 return 0; 92 93 drm_err(&i915->drm, 94 "Failed to setup region(%d) type=%d\n", 95 err, INTEL_MEMORY_LOCAL); 96 return err; 97 } 98 99 mem->id = id; 100 mem->instance = instance; 101 102 intel_memory_region_set_name(mem, "local%u", mem->instance); 103 104 GEM_BUG_ON(!HAS_REGION(i915, id)); 105 GEM_BUG_ON(i915->mm.regions[id]); 106 i915->mm.regions[id] = mem; 107 108 return 0; 109 } 110 111 int intel_gt_assign_ggtt(struct intel_gt *gt) 112 { 113 gt->ggtt = drmm_kzalloc(>->i915->drm, sizeof(*gt->ggtt), GFP_KERNEL); 114 115 return gt->ggtt ? 0 : -ENOMEM; 116 } 117 118 int intel_gt_init_mmio(struct intel_gt *gt) 119 { 120 intel_gt_init_clock_frequency(gt); 121 122 intel_uc_init_mmio(>->uc); 123 intel_sseu_info_init(gt); 124 intel_gt_mcr_init(gt); 125 126 return intel_engines_init_mmio(gt); 127 } 128 129 static void init_unused_ring(struct intel_gt *gt, u32 base) 130 { 131 struct intel_uncore *uncore = gt->uncore; 132 133 intel_uncore_write(uncore, RING_CTL(base), 0); 134 intel_uncore_write(uncore, RING_HEAD(base), 0); 135 intel_uncore_write(uncore, RING_TAIL(base), 0); 136 intel_uncore_write(uncore, RING_START(base), 0); 137 } 138 139 static void init_unused_rings(struct intel_gt *gt) 140 { 141 struct drm_i915_private *i915 = gt->i915; 142 143 if (IS_I830(i915)) { 144 init_unused_ring(gt, PRB1_BASE); 145 init_unused_ring(gt, SRB0_BASE); 146 init_unused_ring(gt, SRB1_BASE); 147 init_unused_ring(gt, SRB2_BASE); 148 init_unused_ring(gt, SRB3_BASE); 149 } else if (GRAPHICS_VER(i915) == 2) { 150 init_unused_ring(gt, SRB0_BASE); 151 init_unused_ring(gt, SRB1_BASE); 152 } else if (GRAPHICS_VER(i915) == 3) { 153 init_unused_ring(gt, PRB1_BASE); 154 init_unused_ring(gt, PRB2_BASE); 155 } 156 } 157 158 int intel_gt_init_hw(struct intel_gt *gt) 159 { 160 struct drm_i915_private *i915 = gt->i915; 161 struct intel_uncore *uncore = gt->uncore; 162 int ret; 163 164 gt->last_init_time = ktime_get(); 165 166 /* Double layer security blanket, see i915_gem_init() */ 167 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 168 169 if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9) 170 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf)); 171 172 if (IS_HASWELL(i915)) 173 intel_uncore_write(uncore, 174 HSW_MI_PREDICATE_RESULT_2, 175 IS_HSW_GT3(i915) ? 176 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); 177 178 /* Apply the GT workarounds... */ 179 intel_gt_apply_workarounds(gt); 180 /* ...and determine whether they are sticking. */ 181 intel_gt_verify_workarounds(gt, "init"); 182 183 intel_gt_init_swizzling(gt); 184 185 /* 186 * At least 830 can leave some of the unused rings 187 * "active" (ie. head != tail) after resume which 188 * will prevent c3 entry. Makes sure all unused rings 189 * are totally idle. 190 */ 191 init_unused_rings(gt); 192 193 ret = i915_ppgtt_init_hw(gt); 194 if (ret) { 195 DRM_ERROR("Enabling PPGTT failed (%d)\n", ret); 196 goto out; 197 } 198 199 /* We can't enable contexts until all firmware is loaded */ 200 ret = intel_uc_init_hw(>->uc); 201 if (ret) { 202 i915_probe_error(i915, "Enabling uc failed (%d)\n", ret); 203 goto out; 204 } 205 206 intel_mocs_init(gt); 207 208 out: 209 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 210 return ret; 211 } 212 213 static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set) 214 { 215 intel_uncore_rmw(uncore, reg, 0, set); 216 } 217 218 static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr) 219 { 220 intel_uncore_rmw(uncore, reg, clr, 0); 221 } 222 223 static void clear_register(struct intel_uncore *uncore, i915_reg_t reg) 224 { 225 intel_uncore_rmw(uncore, reg, 0, 0); 226 } 227 228 static void gen6_clear_engine_error_register(struct intel_engine_cs *engine) 229 { 230 GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0); 231 GEN6_RING_FAULT_REG_POSTING_READ(engine); 232 } 233 234 void 235 intel_gt_clear_error_registers(struct intel_gt *gt, 236 intel_engine_mask_t engine_mask) 237 { 238 struct drm_i915_private *i915 = gt->i915; 239 struct intel_uncore *uncore = gt->uncore; 240 u32 eir; 241 242 if (GRAPHICS_VER(i915) != 2) 243 clear_register(uncore, PGTBL_ER); 244 245 if (GRAPHICS_VER(i915) < 4) 246 clear_register(uncore, IPEIR(RENDER_RING_BASE)); 247 else 248 clear_register(uncore, IPEIR_I965); 249 250 clear_register(uncore, EIR); 251 eir = intel_uncore_read(uncore, EIR); 252 if (eir) { 253 /* 254 * some errors might have become stuck, 255 * mask them. 256 */ 257 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir); 258 rmw_set(uncore, EMR, eir); 259 intel_uncore_write(uncore, GEN2_IIR, 260 I915_MASTER_ERROR_INTERRUPT); 261 } 262 263 if (GRAPHICS_VER(i915) >= 12) { 264 rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID); 265 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG); 266 } else if (GRAPHICS_VER(i915) >= 8) { 267 rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID); 268 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG); 269 } else if (GRAPHICS_VER(i915) >= 6) { 270 struct intel_engine_cs *engine; 271 enum intel_engine_id id; 272 273 for_each_engine_masked(engine, gt, engine_mask, id) 274 gen6_clear_engine_error_register(engine); 275 } 276 } 277 278 static void gen6_check_faults(struct intel_gt *gt) 279 { 280 struct intel_engine_cs *engine; 281 enum intel_engine_id id; 282 u32 fault; 283 284 for_each_engine(engine, gt, id) { 285 fault = GEN6_RING_FAULT_REG_READ(engine); 286 if (fault & RING_FAULT_VALID) { 287 drm_dbg(&engine->i915->drm, "Unexpected fault\n" 288 "\tAddr: 0x%08lx\n" 289 "\tAddress space: %s\n" 290 "\tSource ID: %d\n" 291 "\tType: %d\n", 292 fault & PAGE_MASK, 293 fault & RING_FAULT_GTTSEL_MASK ? 294 "GGTT" : "PPGTT", 295 RING_FAULT_SRCID(fault), 296 RING_FAULT_FAULT_TYPE(fault)); 297 } 298 } 299 } 300 301 static void gen8_check_faults(struct intel_gt *gt) 302 { 303 struct intel_uncore *uncore = gt->uncore; 304 i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg; 305 u32 fault; 306 307 if (GRAPHICS_VER(gt->i915) >= 12) { 308 fault_reg = GEN12_RING_FAULT_REG; 309 fault_data0_reg = GEN12_FAULT_TLB_DATA0; 310 fault_data1_reg = GEN12_FAULT_TLB_DATA1; 311 } else { 312 fault_reg = GEN8_RING_FAULT_REG; 313 fault_data0_reg = GEN8_FAULT_TLB_DATA0; 314 fault_data1_reg = GEN8_FAULT_TLB_DATA1; 315 } 316 317 fault = intel_uncore_read(uncore, fault_reg); 318 if (fault & RING_FAULT_VALID) { 319 u32 fault_data0, fault_data1; 320 u64 fault_addr; 321 322 fault_data0 = intel_uncore_read(uncore, fault_data0_reg); 323 fault_data1 = intel_uncore_read(uncore, fault_data1_reg); 324 325 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) | 326 ((u64)fault_data0 << 12); 327 328 drm_dbg(&uncore->i915->drm, "Unexpected fault\n" 329 "\tAddr: 0x%08x_%08x\n" 330 "\tAddress space: %s\n" 331 "\tEngine ID: %d\n" 332 "\tSource ID: %d\n" 333 "\tType: %d\n", 334 upper_32_bits(fault_addr), lower_32_bits(fault_addr), 335 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT", 336 GEN8_RING_FAULT_ENGINE_ID(fault), 337 RING_FAULT_SRCID(fault), 338 RING_FAULT_FAULT_TYPE(fault)); 339 } 340 } 341 342 void intel_gt_check_and_clear_faults(struct intel_gt *gt) 343 { 344 struct drm_i915_private *i915 = gt->i915; 345 346 /* From GEN8 onwards we only have one 'All Engine Fault Register' */ 347 if (GRAPHICS_VER(i915) >= 8) 348 gen8_check_faults(gt); 349 else if (GRAPHICS_VER(i915) >= 6) 350 gen6_check_faults(gt); 351 else 352 return; 353 354 intel_gt_clear_error_registers(gt, ALL_ENGINES); 355 } 356 357 void intel_gt_flush_ggtt_writes(struct intel_gt *gt) 358 { 359 struct intel_uncore *uncore = gt->uncore; 360 intel_wakeref_t wakeref; 361 362 /* 363 * No actual flushing is required for the GTT write domain for reads 364 * from the GTT domain. Writes to it "immediately" go to main memory 365 * as far as we know, so there's no chipset flush. It also doesn't 366 * land in the GPU render cache. 367 * 368 * However, we do have to enforce the order so that all writes through 369 * the GTT land before any writes to the device, such as updates to 370 * the GATT itself. 371 * 372 * We also have to wait a bit for the writes to land from the GTT. 373 * An uncached read (i.e. mmio) seems to be ideal for the round-trip 374 * timing. This issue has only been observed when switching quickly 375 * between GTT writes and CPU reads from inside the kernel on recent hw, 376 * and it appears to only affect discrete GTT blocks (i.e. on LLC 377 * system agents we cannot reproduce this behaviour, until Cannonlake 378 * that was!). 379 */ 380 381 wmb(); 382 383 if (INTEL_INFO(gt->i915)->has_coherent_ggtt) 384 return; 385 386 intel_gt_chipset_flush(gt); 387 388 with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) { 389 unsigned long flags; 390 391 spin_lock_irqsave(&uncore->lock, flags); 392 intel_uncore_posting_read_fw(uncore, 393 RING_HEAD(RENDER_RING_BASE)); 394 spin_unlock_irqrestore(&uncore->lock, flags); 395 } 396 } 397 398 void intel_gt_chipset_flush(struct intel_gt *gt) 399 { 400 wmb(); 401 if (GRAPHICS_VER(gt->i915) < 6) 402 intel_ggtt_gmch_flush(); 403 } 404 405 void intel_gt_driver_register(struct intel_gt *gt) 406 { 407 intel_gsc_init(>->gsc, gt->i915); 408 409 intel_rps_driver_register(>->rps); 410 411 intel_gt_debugfs_register(gt); 412 intel_gt_sysfs_register(gt); 413 } 414 415 static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size) 416 { 417 struct drm_i915_private *i915 = gt->i915; 418 struct drm_i915_gem_object *obj; 419 struct i915_vma *vma; 420 int ret; 421 422 obj = i915_gem_object_create_lmem(i915, size, 423 I915_BO_ALLOC_VOLATILE | 424 I915_BO_ALLOC_GPU_ONLY); 425 if (IS_ERR(obj)) 426 obj = i915_gem_object_create_stolen(i915, size); 427 if (IS_ERR(obj)) 428 obj = i915_gem_object_create_internal(i915, size); 429 if (IS_ERR(obj)) { 430 drm_err(&i915->drm, "Failed to allocate scratch page\n"); 431 return PTR_ERR(obj); 432 } 433 434 vma = i915_vma_instance(obj, >->ggtt->vm, NULL); 435 if (IS_ERR(vma)) { 436 ret = PTR_ERR(vma); 437 goto err_unref; 438 } 439 440 ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH); 441 if (ret) 442 goto err_unref; 443 444 gt->scratch = i915_vma_make_unshrinkable(vma); 445 446 return 0; 447 448 err_unref: 449 i915_gem_object_put(obj); 450 return ret; 451 } 452 453 static void intel_gt_fini_scratch(struct intel_gt *gt) 454 { 455 i915_vma_unpin_and_release(>->scratch, 0); 456 } 457 458 static struct i915_address_space *kernel_vm(struct intel_gt *gt) 459 { 460 if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING) 461 return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm; 462 else 463 return i915_vm_get(>->ggtt->vm); 464 } 465 466 static int __engines_record_defaults(struct intel_gt *gt) 467 { 468 struct i915_request *requests[I915_NUM_ENGINES] = {}; 469 struct intel_engine_cs *engine; 470 enum intel_engine_id id; 471 int err = 0; 472 473 /* 474 * As we reset the gpu during very early sanitisation, the current 475 * register state on the GPU should reflect its defaults values. 476 * We load a context onto the hw (with restore-inhibit), then switch 477 * over to a second context to save that default register state. We 478 * can then prime every new context with that state so they all start 479 * from the same default HW values. 480 */ 481 482 for_each_engine(engine, gt, id) { 483 struct intel_renderstate so; 484 struct intel_context *ce; 485 struct i915_request *rq; 486 487 /* We must be able to switch to something! */ 488 GEM_BUG_ON(!engine->kernel_context); 489 490 ce = intel_context_create(engine); 491 if (IS_ERR(ce)) { 492 err = PTR_ERR(ce); 493 goto out; 494 } 495 496 err = intel_renderstate_init(&so, ce); 497 if (err) 498 goto err; 499 500 rq = i915_request_create(ce); 501 if (IS_ERR(rq)) { 502 err = PTR_ERR(rq); 503 goto err_fini; 504 } 505 506 err = intel_engine_emit_ctx_wa(rq); 507 if (err) 508 goto err_rq; 509 510 err = intel_renderstate_emit(&so, rq); 511 if (err) 512 goto err_rq; 513 514 err_rq: 515 requests[id] = i915_request_get(rq); 516 i915_request_add(rq); 517 err_fini: 518 intel_renderstate_fini(&so, ce); 519 err: 520 if (err) { 521 intel_context_put(ce); 522 goto out; 523 } 524 } 525 526 /* Flush the default context image to memory, and enable powersaving. */ 527 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) { 528 err = -EIO; 529 goto out; 530 } 531 532 for (id = 0; id < ARRAY_SIZE(requests); id++) { 533 struct i915_request *rq; 534 struct file *state; 535 536 rq = requests[id]; 537 if (!rq) 538 continue; 539 540 if (rq->fence.error) { 541 err = -EIO; 542 goto out; 543 } 544 545 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags)); 546 if (!rq->context->state) 547 continue; 548 549 /* Keep a copy of the state's backing pages; free the obj */ 550 state = shmem_create_from_object(rq->context->state->obj); 551 if (IS_ERR(state)) { 552 err = PTR_ERR(state); 553 goto out; 554 } 555 rq->engine->default_state = state; 556 } 557 558 out: 559 /* 560 * If we have to abandon now, we expect the engines to be idle 561 * and ready to be torn-down. The quickest way we can accomplish 562 * this is by declaring ourselves wedged. 563 */ 564 if (err) 565 intel_gt_set_wedged(gt); 566 567 for (id = 0; id < ARRAY_SIZE(requests); id++) { 568 struct intel_context *ce; 569 struct i915_request *rq; 570 571 rq = requests[id]; 572 if (!rq) 573 continue; 574 575 ce = rq->context; 576 i915_request_put(rq); 577 intel_context_put(ce); 578 } 579 return err; 580 } 581 582 static int __engines_verify_workarounds(struct intel_gt *gt) 583 { 584 struct intel_engine_cs *engine; 585 enum intel_engine_id id; 586 int err = 0; 587 588 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 589 return 0; 590 591 for_each_engine(engine, gt, id) { 592 if (intel_engine_verify_workarounds(engine, "load")) 593 err = -EIO; 594 } 595 596 /* Flush and restore the kernel context for safety */ 597 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) 598 err = -EIO; 599 600 return err; 601 } 602 603 static void __intel_gt_disable(struct intel_gt *gt) 604 { 605 intel_gt_set_wedged_on_fini(gt); 606 607 intel_gt_suspend_prepare(gt); 608 intel_gt_suspend_late(gt); 609 610 GEM_BUG_ON(intel_gt_pm_is_awake(gt)); 611 } 612 613 int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout) 614 { 615 long remaining_timeout; 616 617 /* If the device is asleep, we have no requests outstanding */ 618 if (!intel_gt_pm_is_awake(gt)) 619 return 0; 620 621 while ((timeout = intel_gt_retire_requests_timeout(gt, timeout, 622 &remaining_timeout)) > 0) { 623 cond_resched(); 624 if (signal_pending(current)) 625 return -EINTR; 626 } 627 628 return timeout ? timeout : intel_uc_wait_for_idle(>->uc, 629 remaining_timeout); 630 } 631 632 int intel_gt_init(struct intel_gt *gt) 633 { 634 int err; 635 636 err = i915_inject_probe_error(gt->i915, -ENODEV); 637 if (err) 638 return err; 639 640 intel_gt_init_workarounds(gt); 641 642 /* 643 * This is just a security blanket to placate dragons. 644 * On some systems, we very sporadically observe that the first TLBs 645 * used by the CS may be stale, despite us poking the TLB reset. If 646 * we hold the forcewake during initialisation these problems 647 * just magically go away. 648 */ 649 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); 650 651 err = intel_gt_init_scratch(gt, 652 GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K); 653 if (err) 654 goto out_fw; 655 656 intel_gt_pm_init(gt); 657 658 gt->vm = kernel_vm(gt); 659 if (!gt->vm) { 660 err = -ENOMEM; 661 goto err_pm; 662 } 663 664 intel_set_mocs_index(gt); 665 666 err = intel_engines_init(gt); 667 if (err) 668 goto err_engines; 669 670 err = intel_uc_init(>->uc); 671 if (err) 672 goto err_engines; 673 674 err = intel_gt_resume(gt); 675 if (err) 676 goto err_uc_init; 677 678 err = intel_gt_init_hwconfig(gt); 679 if (err) 680 drm_err(>->i915->drm, "Failed to retrieve hwconfig table: %pe\n", 681 ERR_PTR(err)); 682 683 err = __engines_record_defaults(gt); 684 if (err) 685 goto err_gt; 686 687 err = __engines_verify_workarounds(gt); 688 if (err) 689 goto err_gt; 690 691 intel_uc_init_late(>->uc); 692 693 err = i915_inject_probe_error(gt->i915, -EIO); 694 if (err) 695 goto err_gt; 696 697 intel_migrate_init(>->migrate, gt); 698 699 intel_pxp_init(>->pxp); 700 701 goto out_fw; 702 err_gt: 703 __intel_gt_disable(gt); 704 intel_uc_fini_hw(>->uc); 705 err_uc_init: 706 intel_uc_fini(>->uc); 707 err_engines: 708 intel_engines_release(gt); 709 i915_vm_put(fetch_and_zero(>->vm)); 710 err_pm: 711 intel_gt_pm_fini(gt); 712 intel_gt_fini_scratch(gt); 713 out_fw: 714 if (err) 715 intel_gt_set_wedged_on_init(gt); 716 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL); 717 return err; 718 } 719 720 void intel_gt_driver_remove(struct intel_gt *gt) 721 { 722 __intel_gt_disable(gt); 723 724 intel_migrate_fini(>->migrate); 725 intel_uc_driver_remove(>->uc); 726 727 intel_engines_release(gt); 728 729 intel_gt_flush_buffer_pool(gt); 730 } 731 732 void intel_gt_driver_unregister(struct intel_gt *gt) 733 { 734 intel_wakeref_t wakeref; 735 736 intel_gt_sysfs_unregister(gt); 737 intel_rps_driver_unregister(>->rps); 738 intel_gsc_fini(>->gsc); 739 740 intel_pxp_fini(>->pxp); 741 742 /* 743 * Upon unregistering the device to prevent any new users, cancel 744 * all in-flight requests so that we can quickly unbind the active 745 * resources. 746 */ 747 intel_gt_set_wedged_on_fini(gt); 748 749 /* Scrub all HW state upon release */ 750 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 751 __intel_gt_reset(gt, ALL_ENGINES); 752 } 753 754 void intel_gt_driver_release(struct intel_gt *gt) 755 { 756 struct i915_address_space *vm; 757 758 vm = fetch_and_zero(>->vm); 759 if (vm) /* FIXME being called twice on error paths :( */ 760 i915_vm_put(vm); 761 762 intel_wa_list_free(>->wa_list); 763 intel_gt_pm_fini(gt); 764 intel_gt_fini_scratch(gt); 765 intel_gt_fini_buffer_pool(gt); 766 intel_gt_fini_hwconfig(gt); 767 } 768 769 void intel_gt_driver_late_release_all(struct drm_i915_private *i915) 770 { 771 struct intel_gt *gt; 772 unsigned int id; 773 774 /* We need to wait for inflight RCU frees to release their grip */ 775 rcu_barrier(); 776 777 for_each_gt(gt, i915, id) { 778 intel_uc_driver_late_release(>->uc); 779 intel_gt_fini_requests(gt); 780 intel_gt_fini_reset(gt); 781 intel_gt_fini_timelines(gt); 782 mutex_destroy(>->tlb.invalidate_lock); 783 intel_engines_free(gt); 784 } 785 } 786 787 static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr) 788 { 789 int ret; 790 791 if (!gt_is_root(gt)) { 792 struct intel_uncore *uncore; 793 spinlock_t *irq_lock; 794 795 uncore = drmm_kzalloc(>->i915->drm, sizeof(*uncore), GFP_KERNEL); 796 if (!uncore) 797 return -ENOMEM; 798 799 irq_lock = drmm_kzalloc(>->i915->drm, sizeof(*irq_lock), GFP_KERNEL); 800 if (!irq_lock) 801 return -ENOMEM; 802 803 gt->uncore = uncore; 804 gt->irq_lock = irq_lock; 805 806 intel_gt_common_init_early(gt); 807 } 808 809 intel_uncore_init_early(gt->uncore, gt); 810 intel_wakeref_auto_init(>->userfault_wakeref, gt->uncore->rpm); 811 812 ret = intel_uncore_setup_mmio(gt->uncore, phys_addr); 813 if (ret) 814 return ret; 815 816 gt->phys_addr = phys_addr; 817 818 return 0; 819 } 820 821 int intel_gt_probe_all(struct drm_i915_private *i915) 822 { 823 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 824 struct intel_gt *gt = &i915->gt0; 825 const struct intel_gt_definition *gtdef; 826 phys_addr_t phys_addr; 827 unsigned int mmio_bar; 828 unsigned int i; 829 int ret; 830 831 mmio_bar = GRAPHICS_VER(i915) == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR; 832 phys_addr = pci_resource_start(pdev, mmio_bar); 833 834 /* 835 * We always have at least one primary GT on any device 836 * and it has been already initialized early during probe 837 * in i915_driver_probe() 838 */ 839 gt->i915 = i915; 840 gt->name = "Primary GT"; 841 gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask; 842 843 drm_dbg(&i915->drm, "Setting up %s\n", gt->name); 844 ret = intel_gt_tile_setup(gt, phys_addr); 845 if (ret) 846 return ret; 847 848 i915->gt[0] = gt; 849 850 if (!HAS_EXTRA_GT_LIST(i915)) 851 return 0; 852 853 for (i = 1, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]; 854 gtdef->name != NULL; 855 i++, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]) { 856 gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL); 857 if (!gt) { 858 ret = -ENOMEM; 859 goto err; 860 } 861 862 gt->i915 = i915; 863 gt->name = gtdef->name; 864 gt->type = gtdef->type; 865 gt->info.engine_mask = gtdef->engine_mask; 866 gt->info.id = i; 867 868 drm_dbg(&i915->drm, "Setting up %s\n", gt->name); 869 if (GEM_WARN_ON(range_overflows_t(resource_size_t, 870 gtdef->mapping_base, 871 SZ_16M, 872 pci_resource_len(pdev, mmio_bar)))) { 873 ret = -ENODEV; 874 goto err; 875 } 876 877 switch (gtdef->type) { 878 case GT_TILE: 879 ret = intel_gt_tile_setup(gt, phys_addr + gtdef->mapping_base); 880 break; 881 882 case GT_MEDIA: 883 ret = intel_sa_mediagt_setup(gt, phys_addr + gtdef->mapping_base, 884 gtdef->gsi_offset); 885 break; 886 887 case GT_PRIMARY: 888 /* Primary GT should not appear in extra GT list */ 889 default: 890 MISSING_CASE(gtdef->type); 891 ret = -ENODEV; 892 } 893 894 if (ret) 895 goto err; 896 897 i915->gt[i] = gt; 898 } 899 900 return 0; 901 902 err: 903 i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name, ret); 904 intel_gt_release_all(i915); 905 906 return ret; 907 } 908 909 int intel_gt_tiles_init(struct drm_i915_private *i915) 910 { 911 struct intel_gt *gt; 912 unsigned int id; 913 int ret; 914 915 for_each_gt(gt, i915, id) { 916 ret = intel_gt_probe_lmem(gt); 917 if (ret) 918 return ret; 919 } 920 921 return 0; 922 } 923 924 void intel_gt_release_all(struct drm_i915_private *i915) 925 { 926 struct intel_gt *gt; 927 unsigned int id; 928 929 for_each_gt(gt, i915, id) 930 i915->gt[id] = NULL; 931 } 932 933 void intel_gt_info_print(const struct intel_gt_info *info, 934 struct drm_printer *p) 935 { 936 drm_printf(p, "available engines: %x\n", info->engine_mask); 937 938 intel_sseu_dump(&info->sseu, p); 939 } 940 941 struct reg_and_bit { 942 i915_reg_t reg; 943 u32 bit; 944 }; 945 946 static struct reg_and_bit 947 get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, 948 const i915_reg_t *regs, const unsigned int num) 949 { 950 const unsigned int class = engine->class; 951 struct reg_and_bit rb = { }; 952 953 if (drm_WARN_ON_ONCE(&engine->i915->drm, 954 class >= num || !regs[class].reg)) 955 return rb; 956 957 rb.reg = regs[class]; 958 if (gen8 && class == VIDEO_DECODE_CLASS) 959 rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */ 960 else 961 rb.bit = engine->instance; 962 963 rb.bit = BIT(rb.bit); 964 965 return rb; 966 } 967 968 static void mmio_invalidate_full(struct intel_gt *gt) 969 { 970 static const i915_reg_t gen8_regs[] = { 971 [RENDER_CLASS] = GEN8_RTCR, 972 [VIDEO_DECODE_CLASS] = GEN8_M1TCR, /* , GEN8_M2TCR */ 973 [VIDEO_ENHANCEMENT_CLASS] = GEN8_VTCR, 974 [COPY_ENGINE_CLASS] = GEN8_BTCR, 975 }; 976 static const i915_reg_t gen12_regs[] = { 977 [RENDER_CLASS] = GEN12_GFX_TLB_INV_CR, 978 [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, 979 [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, 980 [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, 981 [COMPUTE_CLASS] = GEN12_COMPCTX_TLB_INV_CR, 982 }; 983 struct drm_i915_private *i915 = gt->i915; 984 struct intel_uncore *uncore = gt->uncore; 985 struct intel_engine_cs *engine; 986 intel_engine_mask_t awake, tmp; 987 enum intel_engine_id id; 988 const i915_reg_t *regs; 989 unsigned int num = 0; 990 991 if (GRAPHICS_VER(i915) == 12) { 992 regs = gen12_regs; 993 num = ARRAY_SIZE(gen12_regs); 994 } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) { 995 regs = gen8_regs; 996 num = ARRAY_SIZE(gen8_regs); 997 } else if (GRAPHICS_VER(i915) < 8) { 998 return; 999 } 1000 1001 if (drm_WARN_ONCE(&i915->drm, !num, 1002 "Platform does not implement TLB invalidation!")) 1003 return; 1004 1005 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 1006 1007 spin_lock_irq(&uncore->lock); /* serialise invalidate with GT reset */ 1008 1009 awake = 0; 1010 for_each_engine(engine, gt, id) { 1011 struct reg_and_bit rb; 1012 1013 if (!intel_engine_pm_is_awake(engine)) 1014 continue; 1015 1016 rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); 1017 if (!i915_mmio_reg_offset(rb.reg)) 1018 continue; 1019 1020 intel_uncore_write_fw(uncore, rb.reg, rb.bit); 1021 awake |= engine->mask; 1022 } 1023 1024 GT_TRACE(gt, "invalidated engines %08x\n", awake); 1025 1026 /* Wa_2207587034:tgl,dg1,rkl,adl-s,adl-p */ 1027 if (awake && 1028 (IS_TIGERLAKE(i915) || 1029 IS_DG1(i915) || 1030 IS_ROCKETLAKE(i915) || 1031 IS_ALDERLAKE_S(i915) || 1032 IS_ALDERLAKE_P(i915))) 1033 intel_uncore_write_fw(uncore, GEN12_OA_TLB_INV_CR, 1); 1034 1035 spin_unlock_irq(&uncore->lock); 1036 1037 for_each_engine_masked(engine, gt, awake, tmp) { 1038 struct reg_and_bit rb; 1039 1040 /* 1041 * HW architecture suggest typical invalidation time at 40us, 1042 * with pessimistic cases up to 100us and a recommendation to 1043 * cap at 1ms. We go a bit higher just in case. 1044 */ 1045 const unsigned int timeout_us = 100; 1046 const unsigned int timeout_ms = 4; 1047 1048 rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); 1049 if (__intel_wait_for_register_fw(uncore, 1050 rb.reg, rb.bit, 0, 1051 timeout_us, timeout_ms, 1052 NULL)) 1053 drm_err_ratelimited(>->i915->drm, 1054 "%s TLB invalidation did not complete in %ums!\n", 1055 engine->name, timeout_ms); 1056 } 1057 1058 /* 1059 * Use delayed put since a) we mostly expect a flurry of TLB 1060 * invalidations so it is good to avoid paying the forcewake cost and 1061 * b) it works around a bug in Icelake which cannot cope with too rapid 1062 * transitions. 1063 */ 1064 intel_uncore_forcewake_put_delayed(uncore, FORCEWAKE_ALL); 1065 } 1066 1067 static bool tlb_seqno_passed(const struct intel_gt *gt, u32 seqno) 1068 { 1069 u32 cur = intel_gt_tlb_seqno(gt); 1070 1071 /* Only skip if a *full* TLB invalidate barrier has passed */ 1072 return (s32)(cur - ALIGN(seqno, 2)) > 0; 1073 } 1074 1075 void intel_gt_invalidate_tlb(struct intel_gt *gt, u32 seqno) 1076 { 1077 intel_wakeref_t wakeref; 1078 1079 if (I915_SELFTEST_ONLY(gt->awake == -ENODEV)) 1080 return; 1081 1082 if (intel_gt_is_wedged(gt)) 1083 return; 1084 1085 if (tlb_seqno_passed(gt, seqno)) 1086 return; 1087 1088 with_intel_gt_pm_if_awake(gt, wakeref) { 1089 mutex_lock(>->tlb.invalidate_lock); 1090 if (tlb_seqno_passed(gt, seqno)) 1091 goto unlock; 1092 1093 mmio_invalidate_full(gt); 1094 1095 write_seqcount_invalidate(>->tlb.seqno); 1096 unlock: 1097 mutex_unlock(>->tlb.invalidate_lock); 1098 } 1099 } 1100