1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include "debugfs_gt.h" 7 8 #include "gem/i915_gem_lmem.h" 9 #include "i915_drv.h" 10 #include "intel_context.h" 11 #include "intel_gt.h" 12 #include "intel_gt_buffer_pool.h" 13 #include "intel_gt_clock_utils.h" 14 #include "intel_gt_pm.h" 15 #include "intel_gt_requests.h" 16 #include "intel_mocs.h" 17 #include "intel_rc6.h" 18 #include "intel_renderstate.h" 19 #include "intel_rps.h" 20 #include "intel_uncore.h" 21 #include "intel_pm.h" 22 #include "shmem_utils.h" 23 24 void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) 25 { 26 gt->i915 = i915; 27 gt->uncore = &i915->uncore; 28 29 spin_lock_init(>->irq_lock); 30 31 INIT_LIST_HEAD(>->closed_vma); 32 spin_lock_init(>->closed_lock); 33 34 init_llist_head(>->watchdog.list); 35 INIT_WORK(>->watchdog.work, intel_gt_watchdog_work); 36 37 intel_gt_init_buffer_pool(gt); 38 intel_gt_init_reset(gt); 39 intel_gt_init_requests(gt); 40 intel_gt_init_timelines(gt); 41 intel_gt_pm_init_early(gt); 42 43 intel_rps_init_early(>->rps); 44 intel_uc_init_early(>->uc); 45 } 46 47 int intel_gt_probe_lmem(struct intel_gt *gt) 48 { 49 struct drm_i915_private *i915 = gt->i915; 50 struct intel_memory_region *mem; 51 int id; 52 int err; 53 54 mem = intel_gt_setup_lmem(gt); 55 if (mem == ERR_PTR(-ENODEV)) 56 mem = intel_gt_setup_fake_lmem(gt); 57 if (IS_ERR(mem)) { 58 err = PTR_ERR(mem); 59 if (err == -ENODEV) 60 return 0; 61 62 drm_err(&i915->drm, 63 "Failed to setup region(%d) type=%d\n", 64 err, INTEL_MEMORY_LOCAL); 65 return err; 66 } 67 68 id = INTEL_REGION_LMEM; 69 70 mem->id = id; 71 72 intel_memory_region_set_name(mem, "local%u", mem->instance); 73 74 GEM_BUG_ON(!HAS_REGION(i915, id)); 75 GEM_BUG_ON(i915->mm.regions[id]); 76 i915->mm.regions[id] = mem; 77 78 return 0; 79 } 80 81 void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt) 82 { 83 gt->ggtt = ggtt; 84 } 85 86 int intel_gt_init_mmio(struct intel_gt *gt) 87 { 88 intel_gt_init_clock_frequency(gt); 89 90 intel_uc_init_mmio(>->uc); 91 intel_sseu_info_init(gt); 92 93 return intel_engines_init_mmio(gt); 94 } 95 96 static void init_unused_ring(struct intel_gt *gt, u32 base) 97 { 98 struct intel_uncore *uncore = gt->uncore; 99 100 intel_uncore_write(uncore, RING_CTL(base), 0); 101 intel_uncore_write(uncore, RING_HEAD(base), 0); 102 intel_uncore_write(uncore, RING_TAIL(base), 0); 103 intel_uncore_write(uncore, RING_START(base), 0); 104 } 105 106 static void init_unused_rings(struct intel_gt *gt) 107 { 108 struct drm_i915_private *i915 = gt->i915; 109 110 if (IS_I830(i915)) { 111 init_unused_ring(gt, PRB1_BASE); 112 init_unused_ring(gt, SRB0_BASE); 113 init_unused_ring(gt, SRB1_BASE); 114 init_unused_ring(gt, SRB2_BASE); 115 init_unused_ring(gt, SRB3_BASE); 116 } else if (GRAPHICS_VER(i915) == 2) { 117 init_unused_ring(gt, SRB0_BASE); 118 init_unused_ring(gt, SRB1_BASE); 119 } else if (GRAPHICS_VER(i915) == 3) { 120 init_unused_ring(gt, PRB1_BASE); 121 init_unused_ring(gt, PRB2_BASE); 122 } 123 } 124 125 int intel_gt_init_hw(struct intel_gt *gt) 126 { 127 struct drm_i915_private *i915 = gt->i915; 128 struct intel_uncore *uncore = gt->uncore; 129 int ret; 130 131 gt->last_init_time = ktime_get(); 132 133 /* Double layer security blanket, see i915_gem_init() */ 134 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 135 136 if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9) 137 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf)); 138 139 if (IS_HASWELL(i915)) 140 intel_uncore_write(uncore, 141 MI_PREDICATE_RESULT_2, 142 IS_HSW_GT3(i915) ? 143 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); 144 145 /* Apply the GT workarounds... */ 146 intel_gt_apply_workarounds(gt); 147 /* ...and determine whether they are sticking. */ 148 intel_gt_verify_workarounds(gt, "init"); 149 150 intel_gt_init_swizzling(gt); 151 152 /* 153 * At least 830 can leave some of the unused rings 154 * "active" (ie. head != tail) after resume which 155 * will prevent c3 entry. Makes sure all unused rings 156 * are totally idle. 157 */ 158 init_unused_rings(gt); 159 160 ret = i915_ppgtt_init_hw(gt); 161 if (ret) { 162 DRM_ERROR("Enabling PPGTT failed (%d)\n", ret); 163 goto out; 164 } 165 166 /* We can't enable contexts until all firmware is loaded */ 167 ret = intel_uc_init_hw(>->uc); 168 if (ret) { 169 i915_probe_error(i915, "Enabling uc failed (%d)\n", ret); 170 goto out; 171 } 172 173 intel_mocs_init(gt); 174 175 out: 176 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 177 return ret; 178 } 179 180 static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set) 181 { 182 intel_uncore_rmw(uncore, reg, 0, set); 183 } 184 185 static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr) 186 { 187 intel_uncore_rmw(uncore, reg, clr, 0); 188 } 189 190 static void clear_register(struct intel_uncore *uncore, i915_reg_t reg) 191 { 192 intel_uncore_rmw(uncore, reg, 0, 0); 193 } 194 195 static void gen8_clear_engine_error_register(struct intel_engine_cs *engine) 196 { 197 GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0); 198 GEN6_RING_FAULT_REG_POSTING_READ(engine); 199 } 200 201 void 202 intel_gt_clear_error_registers(struct intel_gt *gt, 203 intel_engine_mask_t engine_mask) 204 { 205 struct drm_i915_private *i915 = gt->i915; 206 struct intel_uncore *uncore = gt->uncore; 207 u32 eir; 208 209 if (GRAPHICS_VER(i915) != 2) 210 clear_register(uncore, PGTBL_ER); 211 212 if (GRAPHICS_VER(i915) < 4) 213 clear_register(uncore, IPEIR(RENDER_RING_BASE)); 214 else 215 clear_register(uncore, IPEIR_I965); 216 217 clear_register(uncore, EIR); 218 eir = intel_uncore_read(uncore, EIR); 219 if (eir) { 220 /* 221 * some errors might have become stuck, 222 * mask them. 223 */ 224 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir); 225 rmw_set(uncore, EMR, eir); 226 intel_uncore_write(uncore, GEN2_IIR, 227 I915_MASTER_ERROR_INTERRUPT); 228 } 229 230 if (GRAPHICS_VER(i915) >= 12) { 231 rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID); 232 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG); 233 } else if (GRAPHICS_VER(i915) >= 8) { 234 rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID); 235 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG); 236 } else if (GRAPHICS_VER(i915) >= 6) { 237 struct intel_engine_cs *engine; 238 enum intel_engine_id id; 239 240 for_each_engine_masked(engine, gt, engine_mask, id) 241 gen8_clear_engine_error_register(engine); 242 } 243 } 244 245 static void gen6_check_faults(struct intel_gt *gt) 246 { 247 struct intel_engine_cs *engine; 248 enum intel_engine_id id; 249 u32 fault; 250 251 for_each_engine(engine, gt, id) { 252 fault = GEN6_RING_FAULT_REG_READ(engine); 253 if (fault & RING_FAULT_VALID) { 254 drm_dbg(&engine->i915->drm, "Unexpected fault\n" 255 "\tAddr: 0x%08lx\n" 256 "\tAddress space: %s\n" 257 "\tSource ID: %d\n" 258 "\tType: %d\n", 259 fault & PAGE_MASK, 260 fault & RING_FAULT_GTTSEL_MASK ? 261 "GGTT" : "PPGTT", 262 RING_FAULT_SRCID(fault), 263 RING_FAULT_FAULT_TYPE(fault)); 264 } 265 } 266 } 267 268 static void gen8_check_faults(struct intel_gt *gt) 269 { 270 struct intel_uncore *uncore = gt->uncore; 271 i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg; 272 u32 fault; 273 274 if (GRAPHICS_VER(gt->i915) >= 12) { 275 fault_reg = GEN12_RING_FAULT_REG; 276 fault_data0_reg = GEN12_FAULT_TLB_DATA0; 277 fault_data1_reg = GEN12_FAULT_TLB_DATA1; 278 } else { 279 fault_reg = GEN8_RING_FAULT_REG; 280 fault_data0_reg = GEN8_FAULT_TLB_DATA0; 281 fault_data1_reg = GEN8_FAULT_TLB_DATA1; 282 } 283 284 fault = intel_uncore_read(uncore, fault_reg); 285 if (fault & RING_FAULT_VALID) { 286 u32 fault_data0, fault_data1; 287 u64 fault_addr; 288 289 fault_data0 = intel_uncore_read(uncore, fault_data0_reg); 290 fault_data1 = intel_uncore_read(uncore, fault_data1_reg); 291 292 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) | 293 ((u64)fault_data0 << 12); 294 295 drm_dbg(&uncore->i915->drm, "Unexpected fault\n" 296 "\tAddr: 0x%08x_%08x\n" 297 "\tAddress space: %s\n" 298 "\tEngine ID: %d\n" 299 "\tSource ID: %d\n" 300 "\tType: %d\n", 301 upper_32_bits(fault_addr), lower_32_bits(fault_addr), 302 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT", 303 GEN8_RING_FAULT_ENGINE_ID(fault), 304 RING_FAULT_SRCID(fault), 305 RING_FAULT_FAULT_TYPE(fault)); 306 } 307 } 308 309 void intel_gt_check_and_clear_faults(struct intel_gt *gt) 310 { 311 struct drm_i915_private *i915 = gt->i915; 312 313 /* From GEN8 onwards we only have one 'All Engine Fault Register' */ 314 if (GRAPHICS_VER(i915) >= 8) 315 gen8_check_faults(gt); 316 else if (GRAPHICS_VER(i915) >= 6) 317 gen6_check_faults(gt); 318 else 319 return; 320 321 intel_gt_clear_error_registers(gt, ALL_ENGINES); 322 } 323 324 void intel_gt_flush_ggtt_writes(struct intel_gt *gt) 325 { 326 struct intel_uncore *uncore = gt->uncore; 327 intel_wakeref_t wakeref; 328 329 /* 330 * No actual flushing is required for the GTT write domain for reads 331 * from the GTT domain. Writes to it "immediately" go to main memory 332 * as far as we know, so there's no chipset flush. It also doesn't 333 * land in the GPU render cache. 334 * 335 * However, we do have to enforce the order so that all writes through 336 * the GTT land before any writes to the device, such as updates to 337 * the GATT itself. 338 * 339 * We also have to wait a bit for the writes to land from the GTT. 340 * An uncached read (i.e. mmio) seems to be ideal for the round-trip 341 * timing. This issue has only been observed when switching quickly 342 * between GTT writes and CPU reads from inside the kernel on recent hw, 343 * and it appears to only affect discrete GTT blocks (i.e. on LLC 344 * system agents we cannot reproduce this behaviour, until Cannonlake 345 * that was!). 346 */ 347 348 wmb(); 349 350 if (INTEL_INFO(gt->i915)->has_coherent_ggtt) 351 return; 352 353 intel_gt_chipset_flush(gt); 354 355 with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) { 356 unsigned long flags; 357 358 spin_lock_irqsave(&uncore->lock, flags); 359 intel_uncore_posting_read_fw(uncore, 360 RING_HEAD(RENDER_RING_BASE)); 361 spin_unlock_irqrestore(&uncore->lock, flags); 362 } 363 } 364 365 void intel_gt_chipset_flush(struct intel_gt *gt) 366 { 367 wmb(); 368 if (GRAPHICS_VER(gt->i915) < 6) 369 intel_gtt_chipset_flush(); 370 } 371 372 void intel_gt_driver_register(struct intel_gt *gt) 373 { 374 intel_rps_driver_register(>->rps); 375 376 debugfs_gt_register(gt); 377 } 378 379 static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size) 380 { 381 struct drm_i915_private *i915 = gt->i915; 382 struct drm_i915_gem_object *obj; 383 struct i915_vma *vma; 384 int ret; 385 386 obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE); 387 if (IS_ERR(obj)) 388 obj = i915_gem_object_create_stolen(i915, size); 389 if (IS_ERR(obj)) 390 obj = i915_gem_object_create_internal(i915, size); 391 if (IS_ERR(obj)) { 392 drm_err(&i915->drm, "Failed to allocate scratch page\n"); 393 return PTR_ERR(obj); 394 } 395 396 vma = i915_vma_instance(obj, >->ggtt->vm, NULL); 397 if (IS_ERR(vma)) { 398 ret = PTR_ERR(vma); 399 goto err_unref; 400 } 401 402 ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH); 403 if (ret) 404 goto err_unref; 405 406 gt->scratch = i915_vma_make_unshrinkable(vma); 407 408 return 0; 409 410 err_unref: 411 i915_gem_object_put(obj); 412 return ret; 413 } 414 415 static void intel_gt_fini_scratch(struct intel_gt *gt) 416 { 417 i915_vma_unpin_and_release(>->scratch, 0); 418 } 419 420 static struct i915_address_space *kernel_vm(struct intel_gt *gt) 421 { 422 if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING) 423 return &i915_ppgtt_create(gt)->vm; 424 else 425 return i915_vm_get(>->ggtt->vm); 426 } 427 428 static int __engines_record_defaults(struct intel_gt *gt) 429 { 430 struct i915_request *requests[I915_NUM_ENGINES] = {}; 431 struct intel_engine_cs *engine; 432 enum intel_engine_id id; 433 int err = 0; 434 435 /* 436 * As we reset the gpu during very early sanitisation, the current 437 * register state on the GPU should reflect its defaults values. 438 * We load a context onto the hw (with restore-inhibit), then switch 439 * over to a second context to save that default register state. We 440 * can then prime every new context with that state so they all start 441 * from the same default HW values. 442 */ 443 444 for_each_engine(engine, gt, id) { 445 struct intel_renderstate so; 446 struct intel_context *ce; 447 struct i915_request *rq; 448 449 /* We must be able to switch to something! */ 450 GEM_BUG_ON(!engine->kernel_context); 451 452 ce = intel_context_create(engine); 453 if (IS_ERR(ce)) { 454 err = PTR_ERR(ce); 455 goto out; 456 } 457 458 err = intel_renderstate_init(&so, ce); 459 if (err) 460 goto err; 461 462 rq = i915_request_create(ce); 463 if (IS_ERR(rq)) { 464 err = PTR_ERR(rq); 465 goto err_fini; 466 } 467 468 err = intel_engine_emit_ctx_wa(rq); 469 if (err) 470 goto err_rq; 471 472 err = intel_renderstate_emit(&so, rq); 473 if (err) 474 goto err_rq; 475 476 err_rq: 477 requests[id] = i915_request_get(rq); 478 i915_request_add(rq); 479 err_fini: 480 intel_renderstate_fini(&so, ce); 481 err: 482 if (err) { 483 intel_context_put(ce); 484 goto out; 485 } 486 } 487 488 /* Flush the default context image to memory, and enable powersaving. */ 489 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) { 490 err = -EIO; 491 goto out; 492 } 493 494 for (id = 0; id < ARRAY_SIZE(requests); id++) { 495 struct i915_request *rq; 496 struct file *state; 497 498 rq = requests[id]; 499 if (!rq) 500 continue; 501 502 if (rq->fence.error) { 503 err = -EIO; 504 goto out; 505 } 506 507 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags)); 508 if (!rq->context->state) 509 continue; 510 511 /* Keep a copy of the state's backing pages; free the obj */ 512 state = shmem_create_from_object(rq->context->state->obj); 513 if (IS_ERR(state)) { 514 err = PTR_ERR(state); 515 goto out; 516 } 517 rq->engine->default_state = state; 518 } 519 520 out: 521 /* 522 * If we have to abandon now, we expect the engines to be idle 523 * and ready to be torn-down. The quickest way we can accomplish 524 * this is by declaring ourselves wedged. 525 */ 526 if (err) 527 intel_gt_set_wedged(gt); 528 529 for (id = 0; id < ARRAY_SIZE(requests); id++) { 530 struct intel_context *ce; 531 struct i915_request *rq; 532 533 rq = requests[id]; 534 if (!rq) 535 continue; 536 537 ce = rq->context; 538 i915_request_put(rq); 539 intel_context_put(ce); 540 } 541 return err; 542 } 543 544 static int __engines_verify_workarounds(struct intel_gt *gt) 545 { 546 struct intel_engine_cs *engine; 547 enum intel_engine_id id; 548 int err = 0; 549 550 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 551 return 0; 552 553 for_each_engine(engine, gt, id) { 554 if (intel_engine_verify_workarounds(engine, "load")) 555 err = -EIO; 556 } 557 558 /* Flush and restore the kernel context for safety */ 559 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) 560 err = -EIO; 561 562 return err; 563 } 564 565 static void __intel_gt_disable(struct intel_gt *gt) 566 { 567 intel_gt_set_wedged_on_fini(gt); 568 569 intel_gt_suspend_prepare(gt); 570 intel_gt_suspend_late(gt); 571 572 GEM_BUG_ON(intel_gt_pm_is_awake(gt)); 573 } 574 575 int intel_gt_init(struct intel_gt *gt) 576 { 577 int err; 578 579 err = i915_inject_probe_error(gt->i915, -ENODEV); 580 if (err) 581 return err; 582 583 /* 584 * This is just a security blanket to placate dragons. 585 * On some systems, we very sporadically observe that the first TLBs 586 * used by the CS may be stale, despite us poking the TLB reset. If 587 * we hold the forcewake during initialisation these problems 588 * just magically go away. 589 */ 590 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); 591 592 err = intel_gt_init_scratch(gt, 593 GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K); 594 if (err) 595 goto out_fw; 596 597 intel_gt_pm_init(gt); 598 599 gt->vm = kernel_vm(gt); 600 if (!gt->vm) { 601 err = -ENOMEM; 602 goto err_pm; 603 } 604 605 err = intel_engines_init(gt); 606 if (err) 607 goto err_engines; 608 609 err = intel_uc_init(>->uc); 610 if (err) 611 goto err_engines; 612 613 err = intel_gt_resume(gt); 614 if (err) 615 goto err_uc_init; 616 617 err = __engines_record_defaults(gt); 618 if (err) 619 goto err_gt; 620 621 err = __engines_verify_workarounds(gt); 622 if (err) 623 goto err_gt; 624 625 err = i915_inject_probe_error(gt->i915, -EIO); 626 if (err) 627 goto err_gt; 628 629 goto out_fw; 630 err_gt: 631 __intel_gt_disable(gt); 632 intel_uc_fini_hw(>->uc); 633 err_uc_init: 634 intel_uc_fini(>->uc); 635 err_engines: 636 intel_engines_release(gt); 637 i915_vm_put(fetch_and_zero(>->vm)); 638 err_pm: 639 intel_gt_pm_fini(gt); 640 intel_gt_fini_scratch(gt); 641 out_fw: 642 if (err) 643 intel_gt_set_wedged_on_init(gt); 644 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL); 645 return err; 646 } 647 648 void intel_gt_driver_remove(struct intel_gt *gt) 649 { 650 __intel_gt_disable(gt); 651 652 intel_uc_driver_remove(>->uc); 653 654 intel_engines_release(gt); 655 } 656 657 void intel_gt_driver_unregister(struct intel_gt *gt) 658 { 659 intel_wakeref_t wakeref; 660 661 intel_rps_driver_unregister(>->rps); 662 663 /* 664 * Upon unregistering the device to prevent any new users, cancel 665 * all in-flight requests so that we can quickly unbind the active 666 * resources. 667 */ 668 intel_gt_set_wedged(gt); 669 670 /* Scrub all HW state upon release */ 671 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 672 __intel_gt_reset(gt, ALL_ENGINES); 673 } 674 675 void intel_gt_driver_release(struct intel_gt *gt) 676 { 677 struct i915_address_space *vm; 678 679 vm = fetch_and_zero(>->vm); 680 if (vm) /* FIXME being called twice on error paths :( */ 681 i915_vm_put(vm); 682 683 intel_gt_pm_fini(gt); 684 intel_gt_fini_scratch(gt); 685 intel_gt_fini_buffer_pool(gt); 686 } 687 688 void intel_gt_driver_late_release(struct intel_gt *gt) 689 { 690 /* We need to wait for inflight RCU frees to release their grip */ 691 rcu_barrier(); 692 693 intel_uc_driver_late_release(>->uc); 694 intel_gt_fini_requests(gt); 695 intel_gt_fini_reset(gt); 696 intel_gt_fini_timelines(gt); 697 intel_engines_free(gt); 698 } 699 700 void intel_gt_info_print(const struct intel_gt_info *info, 701 struct drm_printer *p) 702 { 703 drm_printf(p, "available engines: %x\n", info->engine_mask); 704 705 intel_sseu_dump(&info->sseu, p); 706 } 707