1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2008-2015 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "i915_scatterlist.h" 9 #include "i915_pvinfo.h" 10 #include "i915_vgpu.h" 11 #include "intel_gt_regs.h" 12 #include "intel_mchbar_regs.h" 13 14 /** 15 * DOC: fence register handling 16 * 17 * Important to avoid confusions: "fences" in the i915 driver are not execution 18 * fences used to track command completion but hardware detiler objects which 19 * wrap a given range of the global GTT. Each platform has only a fairly limited 20 * set of these objects. 21 * 22 * Fences are used to detile GTT memory mappings. They're also connected to the 23 * hardware frontbuffer render tracking and hence interact with frontbuffer 24 * compression. Furthermore on older platforms fences are required for tiled 25 * objects used by the display engine. They can also be used by the render 26 * engine - they're required for blitter commands and are optional for render 27 * commands. But on gen4+ both display (with the exception of fbc) and rendering 28 * have their own tiling state bits and don't need fences. 29 * 30 * Also note that fences only support X and Y tiling and hence can't be used for 31 * the fancier new tiling formats like W, Ys and Yf. 32 * 33 * Finally note that because fences are such a restricted resource they're 34 * dynamically associated with objects. Furthermore fence state is committed to 35 * the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must 36 * explicitly call i915_gem_object_get_fence() to synchronize fencing status 37 * for cpu access. Also note that some code wants an unfenced view, for those 38 * cases the fence can be removed forcefully with i915_gem_object_put_fence(). 39 * 40 * Internally these functions will synchronize with userspace access by removing 41 * CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed. 42 */ 43 44 #define pipelined 0 45 46 static struct drm_i915_private *fence_to_i915(struct i915_fence_reg *fence) 47 { 48 return fence->ggtt->vm.i915; 49 } 50 51 static struct intel_uncore *fence_to_uncore(struct i915_fence_reg *fence) 52 { 53 return fence->ggtt->vm.gt->uncore; 54 } 55 56 static void i965_write_fence_reg(struct i915_fence_reg *fence) 57 { 58 i915_reg_t fence_reg_lo, fence_reg_hi; 59 int fence_pitch_shift; 60 u64 val; 61 62 if (GRAPHICS_VER(fence_to_i915(fence)) >= 6) { 63 fence_reg_lo = FENCE_REG_GEN6_LO(fence->id); 64 fence_reg_hi = FENCE_REG_GEN6_HI(fence->id); 65 fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT; 66 67 } else { 68 fence_reg_lo = FENCE_REG_965_LO(fence->id); 69 fence_reg_hi = FENCE_REG_965_HI(fence->id); 70 fence_pitch_shift = I965_FENCE_PITCH_SHIFT; 71 } 72 73 val = 0; 74 if (fence->tiling) { 75 unsigned int stride = fence->stride; 76 77 GEM_BUG_ON(!IS_ALIGNED(stride, 128)); 78 79 val = fence->start + fence->size - I965_FENCE_PAGE; 80 val <<= 32; 81 val |= fence->start; 82 val |= (u64)((stride / 128) - 1) << fence_pitch_shift; 83 if (fence->tiling == I915_TILING_Y) 84 val |= BIT(I965_FENCE_TILING_Y_SHIFT); 85 val |= I965_FENCE_REG_VALID; 86 } 87 88 if (!pipelined) { 89 struct intel_uncore *uncore = fence_to_uncore(fence); 90 91 /* 92 * To w/a incoherency with non-atomic 64-bit register updates, 93 * we split the 64-bit update into two 32-bit writes. In order 94 * for a partial fence not to be evaluated between writes, we 95 * precede the update with write to turn off the fence register, 96 * and only enable the fence as the last step. 97 * 98 * For extra levels of paranoia, we make sure each step lands 99 * before applying the next step. 100 */ 101 intel_uncore_write_fw(uncore, fence_reg_lo, 0); 102 intel_uncore_posting_read_fw(uncore, fence_reg_lo); 103 104 intel_uncore_write_fw(uncore, fence_reg_hi, upper_32_bits(val)); 105 intel_uncore_write_fw(uncore, fence_reg_lo, lower_32_bits(val)); 106 intel_uncore_posting_read_fw(uncore, fence_reg_lo); 107 } 108 } 109 110 static void i915_write_fence_reg(struct i915_fence_reg *fence) 111 { 112 u32 val; 113 114 val = 0; 115 if (fence->tiling) { 116 unsigned int stride = fence->stride; 117 unsigned int tiling = fence->tiling; 118 bool is_y_tiled = tiling == I915_TILING_Y; 119 120 if (is_y_tiled && HAS_128_BYTE_Y_TILING(fence_to_i915(fence))) 121 stride /= 128; 122 else 123 stride /= 512; 124 GEM_BUG_ON(!is_power_of_2(stride)); 125 126 val = fence->start; 127 if (is_y_tiled) 128 val |= BIT(I830_FENCE_TILING_Y_SHIFT); 129 val |= I915_FENCE_SIZE_BITS(fence->size); 130 val |= ilog2(stride) << I830_FENCE_PITCH_SHIFT; 131 132 val |= I830_FENCE_REG_VALID; 133 } 134 135 if (!pipelined) { 136 struct intel_uncore *uncore = fence_to_uncore(fence); 137 i915_reg_t reg = FENCE_REG(fence->id); 138 139 intel_uncore_write_fw(uncore, reg, val); 140 intel_uncore_posting_read_fw(uncore, reg); 141 } 142 } 143 144 static void i830_write_fence_reg(struct i915_fence_reg *fence) 145 { 146 u32 val; 147 148 val = 0; 149 if (fence->tiling) { 150 unsigned int stride = fence->stride; 151 152 val = fence->start; 153 if (fence->tiling == I915_TILING_Y) 154 val |= BIT(I830_FENCE_TILING_Y_SHIFT); 155 val |= I830_FENCE_SIZE_BITS(fence->size); 156 val |= ilog2(stride / 128) << I830_FENCE_PITCH_SHIFT; 157 val |= I830_FENCE_REG_VALID; 158 } 159 160 if (!pipelined) { 161 struct intel_uncore *uncore = fence_to_uncore(fence); 162 i915_reg_t reg = FENCE_REG(fence->id); 163 164 intel_uncore_write_fw(uncore, reg, val); 165 intel_uncore_posting_read_fw(uncore, reg); 166 } 167 } 168 169 static void fence_write(struct i915_fence_reg *fence) 170 { 171 struct drm_i915_private *i915 = fence_to_i915(fence); 172 173 /* 174 * Previous access through the fence register is marshalled by 175 * the mb() inside the fault handlers (i915_gem_release_mmaps) 176 * and explicitly managed for internal users. 177 */ 178 179 if (GRAPHICS_VER(i915) == 2) 180 i830_write_fence_reg(fence); 181 else if (GRAPHICS_VER(i915) == 3) 182 i915_write_fence_reg(fence); 183 else 184 i965_write_fence_reg(fence); 185 186 /* 187 * Access through the fenced region afterwards is 188 * ordered by the posting reads whilst writing the registers. 189 */ 190 } 191 192 static bool gpu_uses_fence_registers(struct i915_fence_reg *fence) 193 { 194 return GRAPHICS_VER(fence_to_i915(fence)) < 4; 195 } 196 197 static int fence_update(struct i915_fence_reg *fence, 198 struct i915_vma *vma) 199 { 200 struct i915_ggtt *ggtt = fence->ggtt; 201 struct intel_uncore *uncore = fence_to_uncore(fence); 202 intel_wakeref_t wakeref; 203 struct i915_vma *old; 204 int ret; 205 206 fence->tiling = 0; 207 if (vma) { 208 GEM_BUG_ON(!i915_gem_object_get_stride(vma->obj) || 209 !i915_gem_object_get_tiling(vma->obj)); 210 211 if (!i915_vma_is_map_and_fenceable(vma)) 212 return -EINVAL; 213 214 if (gpu_uses_fence_registers(fence)) { 215 /* implicit 'unfenced' GPU blits */ 216 ret = i915_vma_sync(vma); 217 if (ret) 218 return ret; 219 } 220 221 fence->start = vma->node.start; 222 fence->size = vma->fence_size; 223 fence->stride = i915_gem_object_get_stride(vma->obj); 224 fence->tiling = i915_gem_object_get_tiling(vma->obj); 225 } 226 WRITE_ONCE(fence->dirty, false); 227 228 old = xchg(&fence->vma, NULL); 229 if (old) { 230 /* XXX Ideally we would move the waiting to outside the mutex */ 231 ret = i915_active_wait(&fence->active); 232 if (ret) { 233 fence->vma = old; 234 return ret; 235 } 236 237 i915_vma_flush_writes(old); 238 239 /* 240 * Ensure that all userspace CPU access is completed before 241 * stealing the fence. 242 */ 243 if (old != vma) { 244 GEM_BUG_ON(old->fence != fence); 245 i915_vma_revoke_mmap(old); 246 old->fence = NULL; 247 } 248 249 list_move(&fence->link, &ggtt->fence_list); 250 } 251 252 /* 253 * We only need to update the register itself if the device is awake. 254 * If the device is currently powered down, we will defer the write 255 * to the runtime resume, see intel_ggtt_restore_fences(). 256 * 257 * This only works for removing the fence register, on acquisition 258 * the caller must hold the rpm wakeref. The fence register must 259 * be cleared before we can use any other fences to ensure that 260 * the new fences do not overlap the elided clears, confusing HW. 261 */ 262 wakeref = intel_runtime_pm_get_if_in_use(uncore->rpm); 263 if (!wakeref) { 264 GEM_BUG_ON(vma); 265 return 0; 266 } 267 268 WRITE_ONCE(fence->vma, vma); 269 fence_write(fence); 270 271 if (vma) { 272 vma->fence = fence; 273 list_move_tail(&fence->link, &ggtt->fence_list); 274 } 275 276 intel_runtime_pm_put(uncore->rpm, wakeref); 277 return 0; 278 } 279 280 /** 281 * i915_vma_revoke_fence - force-remove fence for a VMA 282 * @vma: vma to map linearly (not through a fence reg) 283 * 284 * This function force-removes any fence from the given object, which is useful 285 * if the kernel wants to do untiled GTT access. 286 */ 287 void i915_vma_revoke_fence(struct i915_vma *vma) 288 { 289 struct i915_fence_reg *fence = vma->fence; 290 intel_wakeref_t wakeref; 291 292 lockdep_assert_held(&vma->vm->mutex); 293 if (!fence) 294 return; 295 296 GEM_BUG_ON(fence->vma != vma); 297 GEM_BUG_ON(!i915_active_is_idle(&fence->active)); 298 GEM_BUG_ON(atomic_read(&fence->pin_count)); 299 300 fence->tiling = 0; 301 WRITE_ONCE(fence->vma, NULL); 302 vma->fence = NULL; 303 304 /* 305 * Skip the write to HW if and only if the device is currently 306 * suspended. 307 * 308 * If the driver does not currently hold a wakeref (if_in_use == 0), 309 * the device may currently be runtime suspended, or it may be woken 310 * up before the suspend takes place. If the device is not suspended 311 * (powered down) and we skip clearing the fence register, the HW is 312 * left in an undefined state where we may end up with multiple 313 * registers overlapping. 314 */ 315 with_intel_runtime_pm_if_active(fence_to_uncore(fence)->rpm, wakeref) 316 fence_write(fence); 317 } 318 319 static bool fence_is_active(const struct i915_fence_reg *fence) 320 { 321 return fence->vma && i915_vma_is_active(fence->vma); 322 } 323 324 static struct i915_fence_reg *fence_find(struct i915_ggtt *ggtt) 325 { 326 struct i915_fence_reg *active = NULL; 327 struct i915_fence_reg *fence, *fn; 328 329 list_for_each_entry_safe(fence, fn, &ggtt->fence_list, link) { 330 GEM_BUG_ON(fence->vma && fence->vma->fence != fence); 331 332 if (fence == active) /* now seen this fence twice */ 333 active = ERR_PTR(-EAGAIN); 334 335 /* Prefer idle fences so we do not have to wait on the GPU */ 336 if (active != ERR_PTR(-EAGAIN) && fence_is_active(fence)) { 337 if (!active) 338 active = fence; 339 340 list_move_tail(&fence->link, &ggtt->fence_list); 341 continue; 342 } 343 344 if (atomic_read(&fence->pin_count)) 345 continue; 346 347 return fence; 348 } 349 350 /* Wait for completion of pending flips which consume fences */ 351 if (intel_has_pending_fb_unpin(ggtt->vm.i915)) 352 return ERR_PTR(-EAGAIN); 353 354 return ERR_PTR(-ENOBUFS); 355 } 356 357 int __i915_vma_pin_fence(struct i915_vma *vma) 358 { 359 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vma->vm); 360 struct i915_fence_reg *fence; 361 struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL; 362 int err; 363 364 lockdep_assert_held(&vma->vm->mutex); 365 366 /* Just update our place in the LRU if our fence is getting reused. */ 367 if (vma->fence) { 368 fence = vma->fence; 369 GEM_BUG_ON(fence->vma != vma); 370 atomic_inc(&fence->pin_count); 371 if (!fence->dirty) { 372 list_move_tail(&fence->link, &ggtt->fence_list); 373 return 0; 374 } 375 } else if (set) { 376 fence = fence_find(ggtt); 377 if (IS_ERR(fence)) 378 return PTR_ERR(fence); 379 380 GEM_BUG_ON(atomic_read(&fence->pin_count)); 381 atomic_inc(&fence->pin_count); 382 } else { 383 return 0; 384 } 385 386 err = fence_update(fence, set); 387 if (err) 388 goto out_unpin; 389 390 GEM_BUG_ON(fence->vma != set); 391 GEM_BUG_ON(vma->fence != (set ? fence : NULL)); 392 393 if (set) 394 return 0; 395 396 out_unpin: 397 atomic_dec(&fence->pin_count); 398 return err; 399 } 400 401 /** 402 * i915_vma_pin_fence - set up fencing for a vma 403 * @vma: vma to map through a fence reg 404 * 405 * When mapping objects through the GTT, userspace wants to be able to write 406 * to them without having to worry about swizzling if the object is tiled. 407 * This function walks the fence regs looking for a free one for @obj, 408 * stealing one if it can't find any. 409 * 410 * It then sets up the reg based on the object's properties: address, pitch 411 * and tiling format. 412 * 413 * For an untiled surface, this removes any existing fence. 414 * 415 * Returns: 416 * 417 * 0 on success, negative error code on failure. 418 */ 419 int i915_vma_pin_fence(struct i915_vma *vma) 420 { 421 int err; 422 423 if (!vma->fence && !i915_gem_object_is_tiled(vma->obj)) 424 return 0; 425 426 /* 427 * Note that we revoke fences on runtime suspend. Therefore the user 428 * must keep the device awake whilst using the fence. 429 */ 430 assert_rpm_wakelock_held(vma->vm->gt->uncore->rpm); 431 GEM_BUG_ON(!i915_vma_is_ggtt(vma)); 432 433 err = mutex_lock_interruptible(&vma->vm->mutex); 434 if (err) 435 return err; 436 437 err = __i915_vma_pin_fence(vma); 438 mutex_unlock(&vma->vm->mutex); 439 440 return err; 441 } 442 443 /** 444 * i915_reserve_fence - Reserve a fence for vGPU 445 * @ggtt: Global GTT 446 * 447 * This function walks the fence regs looking for a free one and remove 448 * it from the fence_list. It is used to reserve fence for vGPU to use. 449 */ 450 struct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt) 451 { 452 struct i915_fence_reg *fence; 453 int count; 454 int ret; 455 456 lockdep_assert_held(&ggtt->vm.mutex); 457 458 /* Keep at least one fence available for the display engine. */ 459 count = 0; 460 list_for_each_entry(fence, &ggtt->fence_list, link) 461 count += !atomic_read(&fence->pin_count); 462 if (count <= 1) 463 return ERR_PTR(-ENOSPC); 464 465 fence = fence_find(ggtt); 466 if (IS_ERR(fence)) 467 return fence; 468 469 if (fence->vma) { 470 /* Force-remove fence from VMA */ 471 ret = fence_update(fence, NULL); 472 if (ret) 473 return ERR_PTR(ret); 474 } 475 476 list_del(&fence->link); 477 478 return fence; 479 } 480 481 /** 482 * i915_unreserve_fence - Reclaim a reserved fence 483 * @fence: the fence reg 484 * 485 * This function add a reserved fence register from vGPU to the fence_list. 486 */ 487 void i915_unreserve_fence(struct i915_fence_reg *fence) 488 { 489 struct i915_ggtt *ggtt = fence->ggtt; 490 491 lockdep_assert_held(&ggtt->vm.mutex); 492 493 list_add(&fence->link, &ggtt->fence_list); 494 } 495 496 /** 497 * intel_ggtt_restore_fences - restore fence state 498 * @ggtt: Global GTT 499 * 500 * Restore the hw fence state to match the software tracking again, to be called 501 * after a gpu reset and on resume. Note that on runtime suspend we only cancel 502 * the fences, to be reacquired by the user later. 503 */ 504 void intel_ggtt_restore_fences(struct i915_ggtt *ggtt) 505 { 506 int i; 507 508 for (i = 0; i < ggtt->num_fences; i++) 509 fence_write(&ggtt->fence_regs[i]); 510 } 511 512 /** 513 * DOC: tiling swizzling details 514 * 515 * The idea behind tiling is to increase cache hit rates by rearranging 516 * pixel data so that a group of pixel accesses are in the same cacheline. 517 * Performance improvement from doing this on the back/depth buffer are on 518 * the order of 30%. 519 * 520 * Intel architectures make this somewhat more complicated, though, by 521 * adjustments made to addressing of data when the memory is in interleaved 522 * mode (matched pairs of DIMMS) to improve memory bandwidth. 523 * For interleaved memory, the CPU sends every sequential 64 bytes 524 * to an alternate memory channel so it can get the bandwidth from both. 525 * 526 * The GPU also rearranges its accesses for increased bandwidth to interleaved 527 * memory, and it matches what the CPU does for non-tiled. However, when tiled 528 * it does it a little differently, since one walks addresses not just in the 529 * X direction but also Y. So, along with alternating channels when bit 530 * 6 of the address flips, it also alternates when other bits flip -- Bits 9 531 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) 532 * are common to both the 915 and 965-class hardware. 533 * 534 * The CPU also sometimes XORs in higher bits as well, to improve 535 * bandwidth doing strided access like we do so frequently in graphics. This 536 * is called "Channel XOR Randomization" in the MCH documentation. The result 537 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address 538 * decode. 539 * 540 * All of this bit 6 XORing has an effect on our memory management, 541 * as we need to make sure that the 3d driver can correctly address object 542 * contents. 543 * 544 * If we don't have interleaved memory, all tiling is safe and no swizzling is 545 * required. 546 * 547 * When bit 17 is XORed in, we simply refuse to tile at all. Bit 548 * 17 is not just a page offset, so as we page an object out and back in, 549 * individual pages in it will have different bit 17 addresses, resulting in 550 * each 64 bytes being swapped with its neighbor! 551 * 552 * Otherwise, if interleaved, we have to tell the 3d driver what the address 553 * swizzling it needs to do is, since it's writing with the CPU to the pages 554 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the 555 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling 556 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order 557 * to match what the GPU expects. 558 */ 559 560 /** 561 * detect_bit_6_swizzle - detect bit 6 swizzling pattern 562 * @ggtt: Global GGTT 563 * 564 * Detects bit 6 swizzling of address lookup between IGD access and CPU 565 * access through main memory. 566 */ 567 static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) 568 { 569 struct intel_uncore *uncore = ggtt->vm.gt->uncore; 570 struct drm_i915_private *i915 = ggtt->vm.i915; 571 u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; 572 u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 573 574 if (GRAPHICS_VER(i915) >= 8 || IS_VALLEYVIEW(i915)) { 575 /* 576 * On BDW+, swizzling is not used. We leave the CPU memory 577 * controller in charge of optimizing memory accesses without 578 * the extra address manipulation GPU side. 579 * 580 * VLV and CHV don't have GPU swizzling. 581 */ 582 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 583 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 584 } else if (GRAPHICS_VER(i915) >= 6) { 585 if (i915->preserve_bios_swizzle) { 586 if (intel_uncore_read(uncore, DISP_ARB_CTL) & 587 DISP_TILE_SURFACE_SWIZZLING) { 588 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 589 swizzle_y = I915_BIT_6_SWIZZLE_9; 590 } else { 591 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 592 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 593 } 594 } else { 595 u32 dimm_c0, dimm_c1; 596 597 dimm_c0 = intel_uncore_read(uncore, MAD_DIMM_C0); 598 dimm_c1 = intel_uncore_read(uncore, MAD_DIMM_C1); 599 dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; 600 dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; 601 /* 602 * Enable swizzling when the channels are populated 603 * with identically sized dimms. We don't need to check 604 * the 3rd channel because no cpu with gpu attached 605 * ships in that configuration. Also, swizzling only 606 * makes sense for 2 channels anyway. 607 */ 608 if (dimm_c0 == dimm_c1) { 609 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 610 swizzle_y = I915_BIT_6_SWIZZLE_9; 611 } else { 612 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 613 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 614 } 615 } 616 } else if (GRAPHICS_VER(i915) == 5) { 617 /* 618 * On Ironlake whatever DRAM config, GPU always do 619 * same swizzling setup. 620 */ 621 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 622 swizzle_y = I915_BIT_6_SWIZZLE_9; 623 } else if (GRAPHICS_VER(i915) == 2) { 624 /* 625 * As far as we know, the 865 doesn't have these bit 6 626 * swizzling issues. 627 */ 628 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 629 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 630 } else if (IS_G45(i915) || IS_I965G(i915) || IS_G33(i915)) { 631 /* 632 * The 965, G33, and newer, have a very flexible memory 633 * configuration. It will enable dual-channel mode 634 * (interleaving) on as much memory as it can, and the GPU 635 * will additionally sometimes enable different bit 6 636 * swizzling for tiled objects from the CPU. 637 * 638 * Here's what I found on the G965: 639 * slot fill memory size swizzling 640 * 0A 0B 1A 1B 1-ch 2-ch 641 * 512 0 0 0 512 0 O 642 * 512 0 512 0 16 1008 X 643 * 512 0 0 512 16 1008 X 644 * 0 512 0 512 16 1008 X 645 * 1024 1024 1024 0 2048 1024 O 646 * 647 * We could probably detect this based on either the DRB 648 * matching, which was the case for the swizzling required in 649 * the table above, or from the 1-ch value being less than 650 * the minimum size of a rank. 651 * 652 * Reports indicate that the swizzling actually 653 * varies depending upon page placement inside the 654 * channels, i.e. we see swizzled pages where the 655 * banks of memory are paired and unswizzled on the 656 * uneven portion, so leave that as unknown. 657 */ 658 if (intel_uncore_read16(uncore, C0DRB3_BW) == 659 intel_uncore_read16(uncore, C1DRB3_BW)) { 660 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 661 swizzle_y = I915_BIT_6_SWIZZLE_9; 662 } 663 } else { 664 u32 dcc = intel_uncore_read(uncore, DCC); 665 666 /* 667 * On 9xx chipsets, channel interleave by the CPU is 668 * determined by DCC. For single-channel, neither the CPU 669 * nor the GPU do swizzling. For dual channel interleaved, 670 * the GPU's interleave is bit 9 and 10 for X tiled, and bit 671 * 9 for Y tiled. The CPU's interleave is independent, and 672 * can be based on either bit 11 (haven't seen this yet) or 673 * bit 17 (common). 674 */ 675 switch (dcc & DCC_ADDRESSING_MODE_MASK) { 676 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL: 677 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC: 678 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 679 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 680 break; 681 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED: 682 if (dcc & DCC_CHANNEL_XOR_DISABLE) { 683 /* 684 * This is the base swizzling by the GPU for 685 * tiled buffers. 686 */ 687 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 688 swizzle_y = I915_BIT_6_SWIZZLE_9; 689 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { 690 /* Bit 11 swizzling by the CPU in addition. */ 691 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11; 692 swizzle_y = I915_BIT_6_SWIZZLE_9_11; 693 } else { 694 /* Bit 17 swizzling by the CPU in addition. */ 695 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; 696 swizzle_y = I915_BIT_6_SWIZZLE_9_17; 697 } 698 break; 699 } 700 701 /* check for L-shaped memory aka modified enhanced addressing */ 702 if (GRAPHICS_VER(i915) == 4 && 703 !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) { 704 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; 705 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 706 } 707 708 if (dcc == 0xffffffff) { 709 drm_err(&i915->drm, "Couldn't read from MCHBAR. " 710 "Disabling tiling.\n"); 711 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; 712 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 713 } 714 } 715 716 if (swizzle_x == I915_BIT_6_SWIZZLE_UNKNOWN || 717 swizzle_y == I915_BIT_6_SWIZZLE_UNKNOWN) { 718 /* 719 * Userspace likes to explode if it sees unknown swizzling, 720 * so lie. We will finish the lie when reporting through 721 * the get-tiling-ioctl by reporting the physical swizzle 722 * mode as unknown instead. 723 * 724 * As we don't strictly know what the swizzling is, it may be 725 * bit17 dependent, and so we need to also prevent the pages 726 * from being moved. 727 */ 728 i915->quirks |= QUIRK_PIN_SWIZZLED_PAGES; 729 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 730 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 731 } 732 733 to_gt(i915)->ggtt->bit_6_swizzle_x = swizzle_x; 734 to_gt(i915)->ggtt->bit_6_swizzle_y = swizzle_y; 735 } 736 737 /* 738 * Swap every 64 bytes of this page around, to account for it having a new 739 * bit 17 of its physical address and therefore being interpreted differently 740 * by the GPU. 741 */ 742 static void swizzle_page(struct page *page) 743 { 744 char temp[64]; 745 char *vaddr; 746 int i; 747 748 vaddr = kmap(page); 749 750 for (i = 0; i < PAGE_SIZE; i += 128) { 751 memcpy(temp, &vaddr[i], 64); 752 memcpy(&vaddr[i], &vaddr[i + 64], 64); 753 memcpy(&vaddr[i + 64], temp, 64); 754 } 755 756 kunmap(page); 757 } 758 759 /** 760 * i915_gem_object_do_bit_17_swizzle - fixup bit 17 swizzling 761 * @obj: i915 GEM buffer object 762 * @pages: the scattergather list of physical pages 763 * 764 * This function fixes up the swizzling in case any page frame number for this 765 * object has changed in bit 17 since that state has been saved with 766 * i915_gem_object_save_bit_17_swizzle(). 767 * 768 * This is called when pinning backing storage again, since the kernel is free 769 * to move unpinned backing storage around (either by directly moving pages or 770 * by swapping them out and back in again). 771 */ 772 void 773 i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, 774 struct sg_table *pages) 775 { 776 struct sgt_iter sgt_iter; 777 struct page *page; 778 int i; 779 780 if (obj->bit_17 == NULL) 781 return; 782 783 i = 0; 784 for_each_sgt_page(page, sgt_iter, pages) { 785 char new_bit_17 = page_to_phys(page) >> 17; 786 787 if ((new_bit_17 & 0x1) != (test_bit(i, obj->bit_17) != 0)) { 788 swizzle_page(page); 789 set_page_dirty(page); 790 } 791 792 i++; 793 } 794 } 795 796 /** 797 * i915_gem_object_save_bit_17_swizzle - save bit 17 swizzling 798 * @obj: i915 GEM buffer object 799 * @pages: the scattergather list of physical pages 800 * 801 * This function saves the bit 17 of each page frame number so that swizzling 802 * can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must 803 * be called before the backing storage can be unpinned. 804 */ 805 void 806 i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, 807 struct sg_table *pages) 808 { 809 const unsigned int page_count = obj->base.size >> PAGE_SHIFT; 810 struct sgt_iter sgt_iter; 811 struct page *page; 812 int i; 813 814 if (obj->bit_17 == NULL) { 815 obj->bit_17 = bitmap_zalloc(page_count, GFP_KERNEL); 816 if (obj->bit_17 == NULL) { 817 DRM_ERROR("Failed to allocate memory for bit 17 " 818 "record\n"); 819 return; 820 } 821 } 822 823 i = 0; 824 825 for_each_sgt_page(page, sgt_iter, pages) { 826 if (page_to_phys(page) & (1 << 17)) 827 __set_bit(i, obj->bit_17); 828 else 829 __clear_bit(i, obj->bit_17); 830 i++; 831 } 832 } 833 834 void intel_ggtt_init_fences(struct i915_ggtt *ggtt) 835 { 836 struct drm_i915_private *i915 = ggtt->vm.i915; 837 struct intel_uncore *uncore = ggtt->vm.gt->uncore; 838 int num_fences; 839 int i; 840 841 INIT_LIST_HEAD(&ggtt->fence_list); 842 INIT_LIST_HEAD(&ggtt->userfault_list); 843 intel_wakeref_auto_init(&ggtt->userfault_wakeref, uncore->rpm); 844 845 detect_bit_6_swizzle(ggtt); 846 847 if (!i915_ggtt_has_aperture(ggtt)) 848 num_fences = 0; 849 else if (GRAPHICS_VER(i915) >= 7 && 850 !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) 851 num_fences = 32; 852 else if (GRAPHICS_VER(i915) >= 4 || 853 IS_I945G(i915) || IS_I945GM(i915) || 854 IS_G33(i915) || IS_PINEVIEW(i915)) 855 num_fences = 16; 856 else 857 num_fences = 8; 858 859 if (intel_vgpu_active(i915)) 860 num_fences = intel_uncore_read(uncore, 861 vgtif_reg(avail_rs.fence_num)); 862 ggtt->fence_regs = kcalloc(num_fences, 863 sizeof(*ggtt->fence_regs), 864 GFP_KERNEL); 865 if (!ggtt->fence_regs) 866 num_fences = 0; 867 868 /* Initialize fence registers to zero */ 869 for (i = 0; i < num_fences; i++) { 870 struct i915_fence_reg *fence = &ggtt->fence_regs[i]; 871 872 i915_active_init(&fence->active, NULL, NULL, 0); 873 fence->ggtt = ggtt; 874 fence->id = i; 875 list_add_tail(&fence->link, &ggtt->fence_list); 876 } 877 ggtt->num_fences = num_fences; 878 879 intel_ggtt_restore_fences(ggtt); 880 } 881 882 void intel_ggtt_fini_fences(struct i915_ggtt *ggtt) 883 { 884 int i; 885 886 for (i = 0; i < ggtt->num_fences; i++) { 887 struct i915_fence_reg *fence = &ggtt->fence_regs[i]; 888 889 i915_active_fini(&fence->active); 890 } 891 892 kfree(ggtt->fence_regs); 893 } 894 895 void intel_gt_init_swizzling(struct intel_gt *gt) 896 { 897 struct drm_i915_private *i915 = gt->i915; 898 struct intel_uncore *uncore = gt->uncore; 899 900 if (GRAPHICS_VER(i915) < 5 || 901 to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) 902 return; 903 904 intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING); 905 906 if (GRAPHICS_VER(i915) == 5) 907 return; 908 909 intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL); 910 911 if (GRAPHICS_VER(i915) == 6) 912 intel_uncore_write(uncore, 913 ARB_MODE, 914 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); 915 else if (GRAPHICS_VER(i915) == 7) 916 intel_uncore_write(uncore, 917 ARB_MODE, 918 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); 919 else if (GRAPHICS_VER(i915) == 8) 920 intel_uncore_write(uncore, 921 GAMTARBMODE, 922 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); 923 else 924 MISSING_CASE(GRAPHICS_VER(i915)); 925 } 926