xref: /openbmc/linux/drivers/gpu/drm/i915/gt/intel_ggtt.c (revision 0b26ca68)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2020 Intel Corporation
4  */
5 
6 #include <linux/stop_machine.h>
7 
8 #include <asm/set_memory.h>
9 #include <asm/smp.h>
10 
11 #include <drm/i915_drm.h>
12 
13 #include "intel_gt.h"
14 #include "i915_drv.h"
15 #include "i915_scatterlist.h"
16 #include "i915_vgpu.h"
17 
18 #include "intel_gtt.h"
19 
20 static int
21 i915_get_ggtt_vma_pages(struct i915_vma *vma);
22 
23 static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
24 				   unsigned long color,
25 				   u64 *start,
26 				   u64 *end)
27 {
28 	if (i915_node_color_differs(node, color))
29 		*start += I915_GTT_PAGE_SIZE;
30 
31 	/*
32 	 * Also leave a space between the unallocated reserved node after the
33 	 * GTT and any objects within the GTT, i.e. we use the color adjustment
34 	 * to insert a guard page to prevent prefetches crossing over the
35 	 * GTT boundary.
36 	 */
37 	node = list_next_entry(node, node_list);
38 	if (node->color != color)
39 		*end -= I915_GTT_PAGE_SIZE;
40 }
41 
42 static int ggtt_init_hw(struct i915_ggtt *ggtt)
43 {
44 	struct drm_i915_private *i915 = ggtt->vm.i915;
45 
46 	i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
47 
48 	ggtt->vm.is_ggtt = true;
49 
50 	/* Only VLV supports read-only GGTT mappings */
51 	ggtt->vm.has_read_only = IS_VALLEYVIEW(i915);
52 
53 	if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
54 		ggtt->vm.mm.color_adjust = i915_ggtt_color_adjust;
55 
56 	if (ggtt->mappable_end) {
57 		if (!io_mapping_init_wc(&ggtt->iomap,
58 					ggtt->gmadr.start,
59 					ggtt->mappable_end)) {
60 			ggtt->vm.cleanup(&ggtt->vm);
61 			return -EIO;
62 		}
63 
64 		ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start,
65 					      ggtt->mappable_end);
66 	}
67 
68 	intel_ggtt_init_fences(ggtt);
69 
70 	return 0;
71 }
72 
73 /**
74  * i915_ggtt_init_hw - Initialize GGTT hardware
75  * @i915: i915 device
76  */
77 int i915_ggtt_init_hw(struct drm_i915_private *i915)
78 {
79 	int ret;
80 
81 	/*
82 	 * Note that we use page colouring to enforce a guard page at the
83 	 * end of the address space. This is required as the CS may prefetch
84 	 * beyond the end of the batch buffer, across the page boundary,
85 	 * and beyond the end of the GTT if we do not provide a guard.
86 	 */
87 	ret = ggtt_init_hw(&i915->ggtt);
88 	if (ret)
89 		return ret;
90 
91 	return 0;
92 }
93 
94 /*
95  * Certain Gen5 chipsets require require idling the GPU before
96  * unmapping anything from the GTT when VT-d is enabled.
97  */
98 static bool needs_idle_maps(struct drm_i915_private *i915)
99 {
100 	/*
101 	 * Query intel_iommu to see if we need the workaround. Presumably that
102 	 * was loaded first.
103 	 */
104 	if (!intel_vtd_active())
105 		return false;
106 
107 	if (IS_GEN(i915, 5) && IS_MOBILE(i915))
108 		return true;
109 
110 	if (IS_GEN(i915, 12))
111 		return true; /* XXX DMAR fault reason 7 */
112 
113 	return false;
114 }
115 
116 void i915_ggtt_suspend(struct i915_ggtt *ggtt)
117 {
118 	struct i915_vma *vma, *vn;
119 	int open;
120 
121 	mutex_lock(&ggtt->vm.mutex);
122 
123 	/* Skip rewriting PTE on VMA unbind. */
124 	open = atomic_xchg(&ggtt->vm.open, 0);
125 
126 	list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link) {
127 		GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
128 		i915_vma_wait_for_bind(vma);
129 
130 		if (i915_vma_is_pinned(vma))
131 			continue;
132 
133 		if (!i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND)) {
134 			__i915_vma_evict(vma);
135 			drm_mm_remove_node(&vma->node);
136 		}
137 	}
138 
139 	ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
140 	ggtt->invalidate(ggtt);
141 	atomic_set(&ggtt->vm.open, open);
142 
143 	mutex_unlock(&ggtt->vm.mutex);
144 
145 	intel_gt_check_and_clear_faults(ggtt->vm.gt);
146 }
147 
148 void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
149 {
150 	struct intel_uncore *uncore = ggtt->vm.gt->uncore;
151 
152 	spin_lock_irq(&uncore->lock);
153 	intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
154 	intel_uncore_read_fw(uncore, GFX_FLSH_CNTL_GEN6);
155 	spin_unlock_irq(&uncore->lock);
156 }
157 
158 static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
159 {
160 	struct intel_uncore *uncore = ggtt->vm.gt->uncore;
161 
162 	/*
163 	 * Note that as an uncached mmio write, this will flush the
164 	 * WCB of the writes into the GGTT before it triggers the invalidate.
165 	 */
166 	intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
167 }
168 
169 static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
170 {
171 	struct intel_uncore *uncore = ggtt->vm.gt->uncore;
172 	struct drm_i915_private *i915 = ggtt->vm.i915;
173 
174 	gen8_ggtt_invalidate(ggtt);
175 
176 	if (INTEL_GEN(i915) >= 12)
177 		intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
178 				      GEN12_GUC_TLB_INV_CR_INVALIDATE);
179 	else
180 		intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
181 }
182 
183 static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
184 {
185 	intel_gtt_chipset_flush();
186 }
187 
188 static u64 gen8_ggtt_pte_encode(dma_addr_t addr,
189 				enum i915_cache_level level,
190 				u32 flags)
191 {
192 	return addr | _PAGE_PRESENT;
193 }
194 
195 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
196 {
197 	writeq(pte, addr);
198 }
199 
200 static void gen8_ggtt_insert_page(struct i915_address_space *vm,
201 				  dma_addr_t addr,
202 				  u64 offset,
203 				  enum i915_cache_level level,
204 				  u32 unused)
205 {
206 	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
207 	gen8_pte_t __iomem *pte =
208 		(gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
209 
210 	gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, 0));
211 
212 	ggtt->invalidate(ggtt);
213 }
214 
215 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
216 				     struct i915_vma *vma,
217 				     enum i915_cache_level level,
218 				     u32 flags)
219 {
220 	const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, 0);
221 	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
222 	gen8_pte_t __iomem *gte;
223 	gen8_pte_t __iomem *end;
224 	struct sgt_iter iter;
225 	dma_addr_t addr;
226 
227 	/*
228 	 * Note that we ignore PTE_READ_ONLY here. The caller must be careful
229 	 * not to allow the user to override access to a read only page.
230 	 */
231 
232 	gte = (gen8_pte_t __iomem *)ggtt->gsm;
233 	gte += vma->node.start / I915_GTT_PAGE_SIZE;
234 	end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
235 
236 	for_each_sgt_daddr(addr, iter, vma->pages)
237 		gen8_set_pte(gte++, pte_encode | addr);
238 	GEM_BUG_ON(gte > end);
239 
240 	/* Fill the allocated but "unused" space beyond the end of the buffer */
241 	while (gte < end)
242 		gen8_set_pte(gte++, vm->scratch[0]->encode);
243 
244 	/*
245 	 * We want to flush the TLBs only after we're certain all the PTE
246 	 * updates have finished.
247 	 */
248 	ggtt->invalidate(ggtt);
249 }
250 
251 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
252 				  dma_addr_t addr,
253 				  u64 offset,
254 				  enum i915_cache_level level,
255 				  u32 flags)
256 {
257 	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
258 	gen6_pte_t __iomem *pte =
259 		(gen6_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
260 
261 	iowrite32(vm->pte_encode(addr, level, flags), pte);
262 
263 	ggtt->invalidate(ggtt);
264 }
265 
266 /*
267  * Binds an object into the global gtt with the specified cache level.
268  * The object will be accessible to the GPU via commands whose operands
269  * reference offsets within the global GTT as well as accessible by the GPU
270  * through the GMADR mapped BAR (i915->mm.gtt->gtt).
271  */
272 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
273 				     struct i915_vma *vma,
274 				     enum i915_cache_level level,
275 				     u32 flags)
276 {
277 	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
278 	gen6_pte_t __iomem *gte;
279 	gen6_pte_t __iomem *end;
280 	struct sgt_iter iter;
281 	dma_addr_t addr;
282 
283 	gte = (gen6_pte_t __iomem *)ggtt->gsm;
284 	gte += vma->node.start / I915_GTT_PAGE_SIZE;
285 	end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
286 
287 	for_each_sgt_daddr(addr, iter, vma->pages)
288 		iowrite32(vm->pte_encode(addr, level, flags), gte++);
289 	GEM_BUG_ON(gte > end);
290 
291 	/* Fill the allocated but "unused" space beyond the end of the buffer */
292 	while (gte < end)
293 		iowrite32(vm->scratch[0]->encode, gte++);
294 
295 	/*
296 	 * We want to flush the TLBs only after we're certain all the PTE
297 	 * updates have finished.
298 	 */
299 	ggtt->invalidate(ggtt);
300 }
301 
302 static void nop_clear_range(struct i915_address_space *vm,
303 			    u64 start, u64 length)
304 {
305 }
306 
307 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
308 				  u64 start, u64 length)
309 {
310 	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
311 	unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
312 	unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
313 	const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
314 	gen8_pte_t __iomem *gtt_base =
315 		(gen8_pte_t __iomem *)ggtt->gsm + first_entry;
316 	const int max_entries = ggtt_total_entries(ggtt) - first_entry;
317 	int i;
318 
319 	if (WARN(num_entries > max_entries,
320 		 "First entry = %d; Num entries = %d (max=%d)\n",
321 		 first_entry, num_entries, max_entries))
322 		num_entries = max_entries;
323 
324 	for (i = 0; i < num_entries; i++)
325 		gen8_set_pte(&gtt_base[i], scratch_pte);
326 }
327 
328 static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
329 {
330 	/*
331 	 * Make sure the internal GAM fifo has been cleared of all GTT
332 	 * writes before exiting stop_machine(). This guarantees that
333 	 * any aperture accesses waiting to start in another process
334 	 * cannot back up behind the GTT writes causing a hang.
335 	 * The register can be any arbitrary GAM register.
336 	 */
337 	intel_uncore_posting_read_fw(vm->gt->uncore, GFX_FLSH_CNTL_GEN6);
338 }
339 
340 struct insert_page {
341 	struct i915_address_space *vm;
342 	dma_addr_t addr;
343 	u64 offset;
344 	enum i915_cache_level level;
345 };
346 
347 static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
348 {
349 	struct insert_page *arg = _arg;
350 
351 	gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
352 	bxt_vtd_ggtt_wa(arg->vm);
353 
354 	return 0;
355 }
356 
357 static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
358 					  dma_addr_t addr,
359 					  u64 offset,
360 					  enum i915_cache_level level,
361 					  u32 unused)
362 {
363 	struct insert_page arg = { vm, addr, offset, level };
364 
365 	stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
366 }
367 
368 struct insert_entries {
369 	struct i915_address_space *vm;
370 	struct i915_vma *vma;
371 	enum i915_cache_level level;
372 	u32 flags;
373 };
374 
375 static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
376 {
377 	struct insert_entries *arg = _arg;
378 
379 	gen8_ggtt_insert_entries(arg->vm, arg->vma, arg->level, arg->flags);
380 	bxt_vtd_ggtt_wa(arg->vm);
381 
382 	return 0;
383 }
384 
385 static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
386 					     struct i915_vma *vma,
387 					     enum i915_cache_level level,
388 					     u32 flags)
389 {
390 	struct insert_entries arg = { vm, vma, level, flags };
391 
392 	stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
393 }
394 
395 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
396 				  u64 start, u64 length)
397 {
398 	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
399 	unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
400 	unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
401 	gen6_pte_t scratch_pte, __iomem *gtt_base =
402 		(gen6_pte_t __iomem *)ggtt->gsm + first_entry;
403 	const int max_entries = ggtt_total_entries(ggtt) - first_entry;
404 	int i;
405 
406 	if (WARN(num_entries > max_entries,
407 		 "First entry = %d; Num entries = %d (max=%d)\n",
408 		 first_entry, num_entries, max_entries))
409 		num_entries = max_entries;
410 
411 	scratch_pte = vm->scratch[0]->encode;
412 	for (i = 0; i < num_entries; i++)
413 		iowrite32(scratch_pte, &gtt_base[i]);
414 }
415 
416 static void i915_ggtt_insert_page(struct i915_address_space *vm,
417 				  dma_addr_t addr,
418 				  u64 offset,
419 				  enum i915_cache_level cache_level,
420 				  u32 unused)
421 {
422 	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
423 		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
424 
425 	intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
426 }
427 
428 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
429 				     struct i915_vma *vma,
430 				     enum i915_cache_level cache_level,
431 				     u32 unused)
432 {
433 	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
434 		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
435 
436 	intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT,
437 				    flags);
438 }
439 
440 static void i915_ggtt_clear_range(struct i915_address_space *vm,
441 				  u64 start, u64 length)
442 {
443 	intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
444 }
445 
446 static void ggtt_bind_vma(struct i915_address_space *vm,
447 			  struct i915_vm_pt_stash *stash,
448 			  struct i915_vma *vma,
449 			  enum i915_cache_level cache_level,
450 			  u32 flags)
451 {
452 	struct drm_i915_gem_object *obj = vma->obj;
453 	u32 pte_flags;
454 
455 	if (i915_vma_is_bound(vma, ~flags & I915_VMA_BIND_MASK))
456 		return;
457 
458 	/* Applicable to VLV (gen8+ do not support RO in the GGTT) */
459 	pte_flags = 0;
460 	if (i915_gem_object_is_readonly(obj))
461 		pte_flags |= PTE_READ_ONLY;
462 
463 	vm->insert_entries(vm, vma, cache_level, pte_flags);
464 	vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
465 }
466 
467 static void ggtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
468 {
469 	vm->clear_range(vm, vma->node.start, vma->size);
470 }
471 
472 static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
473 {
474 	u64 size;
475 	int ret;
476 
477 	if (!intel_uc_uses_guc(&ggtt->vm.gt->uc))
478 		return 0;
479 
480 	GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP);
481 	size = ggtt->vm.total - GUC_GGTT_TOP;
482 
483 	ret = i915_gem_gtt_reserve(&ggtt->vm, &ggtt->uc_fw, size,
484 				   GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,
485 				   PIN_NOEVICT);
486 	if (ret)
487 		drm_dbg(&ggtt->vm.i915->drm,
488 			"Failed to reserve top of GGTT for GuC\n");
489 
490 	return ret;
491 }
492 
493 static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
494 {
495 	if (drm_mm_node_allocated(&ggtt->uc_fw))
496 		drm_mm_remove_node(&ggtt->uc_fw);
497 }
498 
499 static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
500 {
501 	ggtt_release_guc_top(ggtt);
502 	if (drm_mm_node_allocated(&ggtt->error_capture))
503 		drm_mm_remove_node(&ggtt->error_capture);
504 	mutex_destroy(&ggtt->error_mutex);
505 }
506 
507 static int init_ggtt(struct i915_ggtt *ggtt)
508 {
509 	/*
510 	 * Let GEM Manage all of the aperture.
511 	 *
512 	 * However, leave one page at the end still bound to the scratch page.
513 	 * There are a number of places where the hardware apparently prefetches
514 	 * past the end of the object, and we've seen multiple hangs with the
515 	 * GPU head pointer stuck in a batchbuffer bound at the last page of the
516 	 * aperture.  One page should be enough to keep any prefetching inside
517 	 * of the aperture.
518 	 */
519 	unsigned long hole_start, hole_end;
520 	struct drm_mm_node *entry;
521 	int ret;
522 
523 	/*
524 	 * GuC requires all resources that we're sharing with it to be placed in
525 	 * non-WOPCM memory. If GuC is not present or not in use we still need a
526 	 * small bias as ring wraparound at offset 0 sometimes hangs. No idea
527 	 * why.
528 	 */
529 	ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
530 			       intel_wopcm_guc_size(&ggtt->vm.i915->wopcm));
531 
532 	ret = intel_vgt_balloon(ggtt);
533 	if (ret)
534 		return ret;
535 
536 	mutex_init(&ggtt->error_mutex);
537 	if (ggtt->mappable_end) {
538 		/* Reserve a mappable slot for our lockless error capture */
539 		ret = drm_mm_insert_node_in_range(&ggtt->vm.mm,
540 						  &ggtt->error_capture,
541 						  PAGE_SIZE, 0,
542 						  I915_COLOR_UNEVICTABLE,
543 						  0, ggtt->mappable_end,
544 						  DRM_MM_INSERT_LOW);
545 		if (ret)
546 			return ret;
547 	}
548 
549 	/*
550 	 * The upper portion of the GuC address space has a sizeable hole
551 	 * (several MB) that is inaccessible by GuC. Reserve this range within
552 	 * GGTT as it can comfortably hold GuC/HuC firmware images.
553 	 */
554 	ret = ggtt_reserve_guc_top(ggtt);
555 	if (ret)
556 		goto err;
557 
558 	/* Clear any non-preallocated blocks */
559 	drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
560 		drm_dbg_kms(&ggtt->vm.i915->drm,
561 			    "clearing unused GTT space: [%lx, %lx]\n",
562 			    hole_start, hole_end);
563 		ggtt->vm.clear_range(&ggtt->vm, hole_start,
564 				     hole_end - hole_start);
565 	}
566 
567 	/* And finally clear the reserved guard page */
568 	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
569 
570 	return 0;
571 
572 err:
573 	cleanup_init_ggtt(ggtt);
574 	return ret;
575 }
576 
577 static void aliasing_gtt_bind_vma(struct i915_address_space *vm,
578 				  struct i915_vm_pt_stash *stash,
579 				  struct i915_vma *vma,
580 				  enum i915_cache_level cache_level,
581 				  u32 flags)
582 {
583 	u32 pte_flags;
584 
585 	/* Currently applicable only to VLV */
586 	pte_flags = 0;
587 	if (i915_gem_object_is_readonly(vma->obj))
588 		pte_flags |= PTE_READ_ONLY;
589 
590 	if (flags & I915_VMA_LOCAL_BIND)
591 		ppgtt_bind_vma(&i915_vm_to_ggtt(vm)->alias->vm,
592 			       stash, vma, cache_level, flags);
593 
594 	if (flags & I915_VMA_GLOBAL_BIND)
595 		vm->insert_entries(vm, vma, cache_level, pte_flags);
596 }
597 
598 static void aliasing_gtt_unbind_vma(struct i915_address_space *vm,
599 				    struct i915_vma *vma)
600 {
601 	if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
602 		vm->clear_range(vm, vma->node.start, vma->size);
603 
604 	if (i915_vma_is_bound(vma, I915_VMA_LOCAL_BIND))
605 		ppgtt_unbind_vma(&i915_vm_to_ggtt(vm)->alias->vm, vma);
606 }
607 
608 static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
609 {
610 	struct i915_vm_pt_stash stash = {};
611 	struct i915_ppgtt *ppgtt;
612 	int err;
613 
614 	ppgtt = i915_ppgtt_create(ggtt->vm.gt);
615 	if (IS_ERR(ppgtt))
616 		return PTR_ERR(ppgtt);
617 
618 	if (GEM_WARN_ON(ppgtt->vm.total < ggtt->vm.total)) {
619 		err = -ENODEV;
620 		goto err_ppgtt;
621 	}
622 
623 	err = i915_vm_alloc_pt_stash(&ppgtt->vm, &stash, ggtt->vm.total);
624 	if (err)
625 		goto err_ppgtt;
626 
627 	err = i915_vm_pin_pt_stash(&ppgtt->vm, &stash);
628 	if (err)
629 		goto err_stash;
630 
631 	/*
632 	 * Note we only pre-allocate as far as the end of the global
633 	 * GTT. On 48b / 4-level page-tables, the difference is very,
634 	 * very significant! We have to preallocate as GVT/vgpu does
635 	 * not like the page directory disappearing.
636 	 */
637 	ppgtt->vm.allocate_va_range(&ppgtt->vm, &stash, 0, ggtt->vm.total);
638 
639 	ggtt->alias = ppgtt;
640 	ggtt->vm.bind_async_flags |= ppgtt->vm.bind_async_flags;
641 
642 	GEM_BUG_ON(ggtt->vm.vma_ops.bind_vma != ggtt_bind_vma);
643 	ggtt->vm.vma_ops.bind_vma = aliasing_gtt_bind_vma;
644 
645 	GEM_BUG_ON(ggtt->vm.vma_ops.unbind_vma != ggtt_unbind_vma);
646 	ggtt->vm.vma_ops.unbind_vma = aliasing_gtt_unbind_vma;
647 
648 	i915_vm_free_pt_stash(&ppgtt->vm, &stash);
649 	return 0;
650 
651 err_stash:
652 	i915_vm_free_pt_stash(&ppgtt->vm, &stash);
653 err_ppgtt:
654 	i915_vm_put(&ppgtt->vm);
655 	return err;
656 }
657 
658 static void fini_aliasing_ppgtt(struct i915_ggtt *ggtt)
659 {
660 	struct i915_ppgtt *ppgtt;
661 
662 	ppgtt = fetch_and_zero(&ggtt->alias);
663 	if (!ppgtt)
664 		return;
665 
666 	i915_vm_put(&ppgtt->vm);
667 
668 	ggtt->vm.vma_ops.bind_vma   = ggtt_bind_vma;
669 	ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
670 }
671 
672 int i915_init_ggtt(struct drm_i915_private *i915)
673 {
674 	int ret;
675 
676 	ret = init_ggtt(&i915->ggtt);
677 	if (ret)
678 		return ret;
679 
680 	if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
681 		ret = init_aliasing_ppgtt(&i915->ggtt);
682 		if (ret)
683 			cleanup_init_ggtt(&i915->ggtt);
684 	}
685 
686 	return 0;
687 }
688 
689 static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
690 {
691 	struct i915_vma *vma, *vn;
692 
693 	atomic_set(&ggtt->vm.open, 0);
694 
695 	rcu_barrier(); /* flush the RCU'ed__i915_vm_release */
696 	flush_workqueue(ggtt->vm.i915->wq);
697 
698 	mutex_lock(&ggtt->vm.mutex);
699 
700 	list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link)
701 		WARN_ON(__i915_vma_unbind(vma));
702 
703 	if (drm_mm_node_allocated(&ggtt->error_capture))
704 		drm_mm_remove_node(&ggtt->error_capture);
705 	mutex_destroy(&ggtt->error_mutex);
706 
707 	ggtt_release_guc_top(ggtt);
708 	intel_vgt_deballoon(ggtt);
709 
710 	ggtt->vm.cleanup(&ggtt->vm);
711 
712 	mutex_unlock(&ggtt->vm.mutex);
713 	i915_address_space_fini(&ggtt->vm);
714 
715 	arch_phys_wc_del(ggtt->mtrr);
716 
717 	if (ggtt->iomap.size)
718 		io_mapping_fini(&ggtt->iomap);
719 }
720 
721 /**
722  * i915_ggtt_driver_release - Clean up GGTT hardware initialization
723  * @i915: i915 device
724  */
725 void i915_ggtt_driver_release(struct drm_i915_private *i915)
726 {
727 	struct i915_ggtt *ggtt = &i915->ggtt;
728 
729 	fini_aliasing_ppgtt(ggtt);
730 
731 	intel_ggtt_fini_fences(ggtt);
732 	ggtt_cleanup_hw(ggtt);
733 }
734 
735 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
736 {
737 	snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
738 	snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
739 	return snb_gmch_ctl << 20;
740 }
741 
742 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
743 {
744 	bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
745 	bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
746 	if (bdw_gmch_ctl)
747 		bdw_gmch_ctl = 1 << bdw_gmch_ctl;
748 
749 #ifdef CONFIG_X86_32
750 	/* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * I915_GTT_PAGE_SIZE */
751 	if (bdw_gmch_ctl > 4)
752 		bdw_gmch_ctl = 4;
753 #endif
754 
755 	return bdw_gmch_ctl << 20;
756 }
757 
758 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
759 {
760 	gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
761 	gmch_ctrl &= SNB_GMCH_GGMS_MASK;
762 
763 	if (gmch_ctrl)
764 		return 1 << (20 + gmch_ctrl);
765 
766 	return 0;
767 }
768 
769 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
770 {
771 	struct drm_i915_private *i915 = ggtt->vm.i915;
772 	struct pci_dev *pdev = i915->drm.pdev;
773 	phys_addr_t phys_addr;
774 	int ret;
775 
776 	/* For Modern GENs the PTEs and register space are split in the BAR */
777 	phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
778 
779 	/*
780 	 * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range
781 	 * will be dropped. For WC mappings in general we have 64 byte burst
782 	 * writes when the WC buffer is flushed, so we can't use it, but have to
783 	 * resort to an uncached mapping. The WC issue is easily caught by the
784 	 * readback check when writing GTT PTE entries.
785 	 */
786 	if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
787 		ggtt->gsm = ioremap(phys_addr, size);
788 	else
789 		ggtt->gsm = ioremap_wc(phys_addr, size);
790 	if (!ggtt->gsm) {
791 		drm_err(&i915->drm, "Failed to map the ggtt page table\n");
792 		return -ENOMEM;
793 	}
794 
795 	ret = setup_scratch_page(&ggtt->vm);
796 	if (ret) {
797 		drm_err(&i915->drm, "Scratch setup failed\n");
798 		/* iounmap will also get called at remove, but meh */
799 		iounmap(ggtt->gsm);
800 		return ret;
801 	}
802 
803 	ggtt->vm.scratch[0]->encode =
804 		ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),
805 				    I915_CACHE_NONE, 0);
806 
807 	return 0;
808 }
809 
810 int ggtt_set_pages(struct i915_vma *vma)
811 {
812 	int ret;
813 
814 	GEM_BUG_ON(vma->pages);
815 
816 	ret = i915_get_ggtt_vma_pages(vma);
817 	if (ret)
818 		return ret;
819 
820 	vma->page_sizes = vma->obj->mm.page_sizes;
821 
822 	return 0;
823 }
824 
825 static void gen6_gmch_remove(struct i915_address_space *vm)
826 {
827 	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
828 
829 	iounmap(ggtt->gsm);
830 	free_scratch(vm);
831 }
832 
833 static struct resource pci_resource(struct pci_dev *pdev, int bar)
834 {
835 	return (struct resource)DEFINE_RES_MEM(pci_resource_start(pdev, bar),
836 					       pci_resource_len(pdev, bar));
837 }
838 
839 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
840 {
841 	struct drm_i915_private *i915 = ggtt->vm.i915;
842 	struct pci_dev *pdev = i915->drm.pdev;
843 	unsigned int size;
844 	u16 snb_gmch_ctl;
845 
846 	/* TODO: We're not aware of mappable constraints on gen8 yet */
847 	if (!HAS_LMEM(i915)) {
848 		ggtt->gmadr = pci_resource(pdev, 2);
849 		ggtt->mappable_end = resource_size(&ggtt->gmadr);
850 	}
851 
852 	pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
853 	if (IS_CHERRYVIEW(i915))
854 		size = chv_get_total_gtt_size(snb_gmch_ctl);
855 	else
856 		size = gen8_get_total_gtt_size(snb_gmch_ctl);
857 
858 	ggtt->vm.alloc_pt_dma = alloc_pt_dma;
859 
860 	ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
861 	ggtt->vm.cleanup = gen6_gmch_remove;
862 	ggtt->vm.insert_page = gen8_ggtt_insert_page;
863 	ggtt->vm.clear_range = nop_clear_range;
864 	if (intel_scanout_needs_vtd_wa(i915))
865 		ggtt->vm.clear_range = gen8_ggtt_clear_range;
866 
867 	ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
868 
869 	/* Serialize GTT updates with aperture access on BXT if VT-d is on. */
870 	if (intel_ggtt_update_needs_vtd_wa(i915) ||
871 	    IS_CHERRYVIEW(i915) /* fails with concurrent use/update */) {
872 		ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
873 		ggtt->vm.insert_page    = bxt_vtd_ggtt_insert_page__BKL;
874 		ggtt->vm.bind_async_flags =
875 			I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
876 	}
877 
878 	ggtt->invalidate = gen8_ggtt_invalidate;
879 
880 	ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
881 	ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
882 	ggtt->vm.vma_ops.set_pages   = ggtt_set_pages;
883 	ggtt->vm.vma_ops.clear_pages = clear_pages;
884 
885 	ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
886 
887 	setup_private_pat(ggtt->vm.gt->uncore);
888 
889 	return ggtt_probe_common(ggtt, size);
890 }
891 
892 static u64 snb_pte_encode(dma_addr_t addr,
893 			  enum i915_cache_level level,
894 			  u32 flags)
895 {
896 	gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
897 
898 	switch (level) {
899 	case I915_CACHE_L3_LLC:
900 	case I915_CACHE_LLC:
901 		pte |= GEN6_PTE_CACHE_LLC;
902 		break;
903 	case I915_CACHE_NONE:
904 		pte |= GEN6_PTE_UNCACHED;
905 		break;
906 	default:
907 		MISSING_CASE(level);
908 	}
909 
910 	return pte;
911 }
912 
913 static u64 ivb_pte_encode(dma_addr_t addr,
914 			  enum i915_cache_level level,
915 			  u32 flags)
916 {
917 	gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
918 
919 	switch (level) {
920 	case I915_CACHE_L3_LLC:
921 		pte |= GEN7_PTE_CACHE_L3_LLC;
922 		break;
923 	case I915_CACHE_LLC:
924 		pte |= GEN6_PTE_CACHE_LLC;
925 		break;
926 	case I915_CACHE_NONE:
927 		pte |= GEN6_PTE_UNCACHED;
928 		break;
929 	default:
930 		MISSING_CASE(level);
931 	}
932 
933 	return pte;
934 }
935 
936 static u64 byt_pte_encode(dma_addr_t addr,
937 			  enum i915_cache_level level,
938 			  u32 flags)
939 {
940 	gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
941 
942 	if (!(flags & PTE_READ_ONLY))
943 		pte |= BYT_PTE_WRITEABLE;
944 
945 	if (level != I915_CACHE_NONE)
946 		pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
947 
948 	return pte;
949 }
950 
951 static u64 hsw_pte_encode(dma_addr_t addr,
952 			  enum i915_cache_level level,
953 			  u32 flags)
954 {
955 	gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
956 
957 	if (level != I915_CACHE_NONE)
958 		pte |= HSW_WB_LLC_AGE3;
959 
960 	return pte;
961 }
962 
963 static u64 iris_pte_encode(dma_addr_t addr,
964 			   enum i915_cache_level level,
965 			   u32 flags)
966 {
967 	gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
968 
969 	switch (level) {
970 	case I915_CACHE_NONE:
971 		break;
972 	case I915_CACHE_WT:
973 		pte |= HSW_WT_ELLC_LLC_AGE3;
974 		break;
975 	default:
976 		pte |= HSW_WB_ELLC_LLC_AGE3;
977 		break;
978 	}
979 
980 	return pte;
981 }
982 
983 static int gen6_gmch_probe(struct i915_ggtt *ggtt)
984 {
985 	struct drm_i915_private *i915 = ggtt->vm.i915;
986 	struct pci_dev *pdev = i915->drm.pdev;
987 	unsigned int size;
988 	u16 snb_gmch_ctl;
989 
990 	ggtt->gmadr = pci_resource(pdev, 2);
991 	ggtt->mappable_end = resource_size(&ggtt->gmadr);
992 
993 	/*
994 	 * 64/512MB is the current min/max we actually know of, but this is
995 	 * just a coarse sanity check.
996 	 */
997 	if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
998 		drm_err(&i915->drm, "Unknown GMADR size (%pa)\n",
999 			&ggtt->mappable_end);
1000 		return -ENXIO;
1001 	}
1002 
1003 	pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1004 
1005 	size = gen6_get_total_gtt_size(snb_gmch_ctl);
1006 	ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
1007 
1008 	ggtt->vm.alloc_pt_dma = alloc_pt_dma;
1009 
1010 	ggtt->vm.clear_range = nop_clear_range;
1011 	if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
1012 		ggtt->vm.clear_range = gen6_ggtt_clear_range;
1013 	ggtt->vm.insert_page = gen6_ggtt_insert_page;
1014 	ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
1015 	ggtt->vm.cleanup = gen6_gmch_remove;
1016 
1017 	ggtt->invalidate = gen6_ggtt_invalidate;
1018 
1019 	if (HAS_EDRAM(i915))
1020 		ggtt->vm.pte_encode = iris_pte_encode;
1021 	else if (IS_HASWELL(i915))
1022 		ggtt->vm.pte_encode = hsw_pte_encode;
1023 	else if (IS_VALLEYVIEW(i915))
1024 		ggtt->vm.pte_encode = byt_pte_encode;
1025 	else if (INTEL_GEN(i915) >= 7)
1026 		ggtt->vm.pte_encode = ivb_pte_encode;
1027 	else
1028 		ggtt->vm.pte_encode = snb_pte_encode;
1029 
1030 	ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
1031 	ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
1032 	ggtt->vm.vma_ops.set_pages   = ggtt_set_pages;
1033 	ggtt->vm.vma_ops.clear_pages = clear_pages;
1034 
1035 	return ggtt_probe_common(ggtt, size);
1036 }
1037 
1038 static void i915_gmch_remove(struct i915_address_space *vm)
1039 {
1040 	intel_gmch_remove();
1041 }
1042 
1043 static int i915_gmch_probe(struct i915_ggtt *ggtt)
1044 {
1045 	struct drm_i915_private *i915 = ggtt->vm.i915;
1046 	phys_addr_t gmadr_base;
1047 	int ret;
1048 
1049 	ret = intel_gmch_probe(i915->bridge_dev, i915->drm.pdev, NULL);
1050 	if (!ret) {
1051 		drm_err(&i915->drm, "failed to set up gmch\n");
1052 		return -EIO;
1053 	}
1054 
1055 	intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
1056 
1057 	ggtt->gmadr =
1058 		(struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
1059 
1060 	ggtt->vm.alloc_pt_dma = alloc_pt_dma;
1061 
1062 	if (needs_idle_maps(i915)) {
1063 		drm_notice(&i915->drm,
1064 			   "Flushing DMA requests before IOMMU unmaps; performance may be degraded\n");
1065 		ggtt->do_idle_maps = true;
1066 	}
1067 
1068 	ggtt->vm.insert_page = i915_ggtt_insert_page;
1069 	ggtt->vm.insert_entries = i915_ggtt_insert_entries;
1070 	ggtt->vm.clear_range = i915_ggtt_clear_range;
1071 	ggtt->vm.cleanup = i915_gmch_remove;
1072 
1073 	ggtt->invalidate = gmch_ggtt_invalidate;
1074 
1075 	ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
1076 	ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
1077 	ggtt->vm.vma_ops.set_pages   = ggtt_set_pages;
1078 	ggtt->vm.vma_ops.clear_pages = clear_pages;
1079 
1080 	if (unlikely(ggtt->do_idle_maps))
1081 		drm_notice(&i915->drm,
1082 			   "Applying Ironlake quirks for intel_iommu\n");
1083 
1084 	return 0;
1085 }
1086 
1087 static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
1088 {
1089 	struct drm_i915_private *i915 = gt->i915;
1090 	int ret;
1091 
1092 	ggtt->vm.gt = gt;
1093 	ggtt->vm.i915 = i915;
1094 	ggtt->vm.dma = &i915->drm.pdev->dev;
1095 
1096 	if (INTEL_GEN(i915) <= 5)
1097 		ret = i915_gmch_probe(ggtt);
1098 	else if (INTEL_GEN(i915) < 8)
1099 		ret = gen6_gmch_probe(ggtt);
1100 	else
1101 		ret = gen8_gmch_probe(ggtt);
1102 	if (ret)
1103 		return ret;
1104 
1105 	if ((ggtt->vm.total - 1) >> 32) {
1106 		drm_err(&i915->drm,
1107 			"We never expected a Global GTT with more than 32bits"
1108 			" of address space! Found %lldM!\n",
1109 			ggtt->vm.total >> 20);
1110 		ggtt->vm.total = 1ULL << 32;
1111 		ggtt->mappable_end =
1112 			min_t(u64, ggtt->mappable_end, ggtt->vm.total);
1113 	}
1114 
1115 	if (ggtt->mappable_end > ggtt->vm.total) {
1116 		drm_err(&i915->drm,
1117 			"mappable aperture extends past end of GGTT,"
1118 			" aperture=%pa, total=%llx\n",
1119 			&ggtt->mappable_end, ggtt->vm.total);
1120 		ggtt->mappable_end = ggtt->vm.total;
1121 	}
1122 
1123 	/* GMADR is the PCI mmio aperture into the global GTT. */
1124 	drm_dbg(&i915->drm, "GGTT size = %lluM\n", ggtt->vm.total >> 20);
1125 	drm_dbg(&i915->drm, "GMADR size = %lluM\n",
1126 		(u64)ggtt->mappable_end >> 20);
1127 	drm_dbg(&i915->drm, "DSM size = %lluM\n",
1128 		(u64)resource_size(&intel_graphics_stolen_res) >> 20);
1129 
1130 	return 0;
1131 }
1132 
1133 /**
1134  * i915_ggtt_probe_hw - Probe GGTT hardware location
1135  * @i915: i915 device
1136  */
1137 int i915_ggtt_probe_hw(struct drm_i915_private *i915)
1138 {
1139 	int ret;
1140 
1141 	ret = ggtt_probe_hw(&i915->ggtt, &i915->gt);
1142 	if (ret)
1143 		return ret;
1144 
1145 	if (intel_vtd_active())
1146 		drm_info(&i915->drm, "VT-d active for gfx access\n");
1147 
1148 	return 0;
1149 }
1150 
1151 int i915_ggtt_enable_hw(struct drm_i915_private *i915)
1152 {
1153 	if (INTEL_GEN(i915) < 6 && !intel_enable_gtt())
1154 		return -EIO;
1155 
1156 	return 0;
1157 }
1158 
1159 void i915_ggtt_enable_guc(struct i915_ggtt *ggtt)
1160 {
1161 	GEM_BUG_ON(ggtt->invalidate != gen8_ggtt_invalidate);
1162 
1163 	ggtt->invalidate = guc_ggtt_invalidate;
1164 
1165 	ggtt->invalidate(ggtt);
1166 }
1167 
1168 void i915_ggtt_disable_guc(struct i915_ggtt *ggtt)
1169 {
1170 	/* XXX Temporary pardon for error unload */
1171 	if (ggtt->invalidate == gen8_ggtt_invalidate)
1172 		return;
1173 
1174 	/* We should only be called after i915_ggtt_enable_guc() */
1175 	GEM_BUG_ON(ggtt->invalidate != guc_ggtt_invalidate);
1176 
1177 	ggtt->invalidate = gen8_ggtt_invalidate;
1178 
1179 	ggtt->invalidate(ggtt);
1180 }
1181 
1182 void i915_ggtt_resume(struct i915_ggtt *ggtt)
1183 {
1184 	struct i915_vma *vma;
1185 	bool flush = false;
1186 	int open;
1187 
1188 	intel_gt_check_and_clear_faults(ggtt->vm.gt);
1189 
1190 	/* First fill our portion of the GTT with scratch pages */
1191 	ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
1192 
1193 	/* Skip rewriting PTE on VMA unbind. */
1194 	open = atomic_xchg(&ggtt->vm.open, 0);
1195 
1196 	/* clflush objects bound into the GGTT and rebind them. */
1197 	list_for_each_entry(vma, &ggtt->vm.bound_list, vm_link) {
1198 		struct drm_i915_gem_object *obj = vma->obj;
1199 		unsigned int was_bound =
1200 			atomic_read(&vma->flags) & I915_VMA_BIND_MASK;
1201 
1202 		GEM_BUG_ON(!was_bound);
1203 		vma->ops->bind_vma(&ggtt->vm, NULL, vma,
1204 				   obj ? obj->cache_level : 0,
1205 				   was_bound);
1206 		if (obj) { /* only used during resume => exclusive access */
1207 			flush |= fetch_and_zero(&obj->write_domain);
1208 			obj->read_domains |= I915_GEM_DOMAIN_GTT;
1209 		}
1210 	}
1211 
1212 	atomic_set(&ggtt->vm.open, open);
1213 	ggtt->invalidate(ggtt);
1214 
1215 	if (flush)
1216 		wbinvd_on_all_cpus();
1217 
1218 	if (INTEL_GEN(ggtt->vm.i915) >= 8)
1219 		setup_private_pat(ggtt->vm.gt->uncore);
1220 
1221 	intel_ggtt_restore_fences(ggtt);
1222 }
1223 
1224 static struct scatterlist *
1225 rotate_pages(struct drm_i915_gem_object *obj, unsigned int offset,
1226 	     unsigned int width, unsigned int height,
1227 	     unsigned int stride,
1228 	     struct sg_table *st, struct scatterlist *sg)
1229 {
1230 	unsigned int column, row;
1231 	unsigned int src_idx;
1232 
1233 	for (column = 0; column < width; column++) {
1234 		src_idx = stride * (height - 1) + column + offset;
1235 		for (row = 0; row < height; row++) {
1236 			st->nents++;
1237 			/*
1238 			 * We don't need the pages, but need to initialize
1239 			 * the entries so the sg list can be happily traversed.
1240 			 * The only thing we need are DMA addresses.
1241 			 */
1242 			sg_set_page(sg, NULL, I915_GTT_PAGE_SIZE, 0);
1243 			sg_dma_address(sg) =
1244 				i915_gem_object_get_dma_address(obj, src_idx);
1245 			sg_dma_len(sg) = I915_GTT_PAGE_SIZE;
1246 			sg = sg_next(sg);
1247 			src_idx -= stride;
1248 		}
1249 	}
1250 
1251 	return sg;
1252 }
1253 
1254 static noinline struct sg_table *
1255 intel_rotate_pages(struct intel_rotation_info *rot_info,
1256 		   struct drm_i915_gem_object *obj)
1257 {
1258 	unsigned int size = intel_rotation_info_size(rot_info);
1259 	struct drm_i915_private *i915 = to_i915(obj->base.dev);
1260 	struct sg_table *st;
1261 	struct scatterlist *sg;
1262 	int ret = -ENOMEM;
1263 	int i;
1264 
1265 	/* Allocate target SG list. */
1266 	st = kmalloc(sizeof(*st), GFP_KERNEL);
1267 	if (!st)
1268 		goto err_st_alloc;
1269 
1270 	ret = sg_alloc_table(st, size, GFP_KERNEL);
1271 	if (ret)
1272 		goto err_sg_alloc;
1273 
1274 	st->nents = 0;
1275 	sg = st->sgl;
1276 
1277 	for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) {
1278 		sg = rotate_pages(obj, rot_info->plane[i].offset,
1279 				  rot_info->plane[i].width, rot_info->plane[i].height,
1280 				  rot_info->plane[i].stride, st, sg);
1281 	}
1282 
1283 	return st;
1284 
1285 err_sg_alloc:
1286 	kfree(st);
1287 err_st_alloc:
1288 
1289 	drm_dbg(&i915->drm, "Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n",
1290 		obj->base.size, rot_info->plane[0].width,
1291 		rot_info->plane[0].height, size);
1292 
1293 	return ERR_PTR(ret);
1294 }
1295 
1296 static struct scatterlist *
1297 remap_pages(struct drm_i915_gem_object *obj, unsigned int offset,
1298 	    unsigned int width, unsigned int height,
1299 	    unsigned int stride,
1300 	    struct sg_table *st, struct scatterlist *sg)
1301 {
1302 	unsigned int row;
1303 
1304 	for (row = 0; row < height; row++) {
1305 		unsigned int left = width * I915_GTT_PAGE_SIZE;
1306 
1307 		while (left) {
1308 			dma_addr_t addr;
1309 			unsigned int length;
1310 
1311 			/*
1312 			 * We don't need the pages, but need to initialize
1313 			 * the entries so the sg list can be happily traversed.
1314 			 * The only thing we need are DMA addresses.
1315 			 */
1316 
1317 			addr = i915_gem_object_get_dma_address_len(obj, offset, &length);
1318 
1319 			length = min(left, length);
1320 
1321 			st->nents++;
1322 
1323 			sg_set_page(sg, NULL, length, 0);
1324 			sg_dma_address(sg) = addr;
1325 			sg_dma_len(sg) = length;
1326 			sg = sg_next(sg);
1327 
1328 			offset += length / I915_GTT_PAGE_SIZE;
1329 			left -= length;
1330 		}
1331 
1332 		offset += stride - width;
1333 	}
1334 
1335 	return sg;
1336 }
1337 
1338 static noinline struct sg_table *
1339 intel_remap_pages(struct intel_remapped_info *rem_info,
1340 		  struct drm_i915_gem_object *obj)
1341 {
1342 	unsigned int size = intel_remapped_info_size(rem_info);
1343 	struct drm_i915_private *i915 = to_i915(obj->base.dev);
1344 	struct sg_table *st;
1345 	struct scatterlist *sg;
1346 	int ret = -ENOMEM;
1347 	int i;
1348 
1349 	/* Allocate target SG list. */
1350 	st = kmalloc(sizeof(*st), GFP_KERNEL);
1351 	if (!st)
1352 		goto err_st_alloc;
1353 
1354 	ret = sg_alloc_table(st, size, GFP_KERNEL);
1355 	if (ret)
1356 		goto err_sg_alloc;
1357 
1358 	st->nents = 0;
1359 	sg = st->sgl;
1360 
1361 	for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
1362 		sg = remap_pages(obj, rem_info->plane[i].offset,
1363 				 rem_info->plane[i].width, rem_info->plane[i].height,
1364 				 rem_info->plane[i].stride, st, sg);
1365 	}
1366 
1367 	i915_sg_trim(st);
1368 
1369 	return st;
1370 
1371 err_sg_alloc:
1372 	kfree(st);
1373 err_st_alloc:
1374 
1375 	drm_dbg(&i915->drm, "Failed to create remapped mapping for object size %zu! (%ux%u tiles, %u pages)\n",
1376 		obj->base.size, rem_info->plane[0].width,
1377 		rem_info->plane[0].height, size);
1378 
1379 	return ERR_PTR(ret);
1380 }
1381 
1382 static noinline struct sg_table *
1383 intel_partial_pages(const struct i915_ggtt_view *view,
1384 		    struct drm_i915_gem_object *obj)
1385 {
1386 	struct sg_table *st;
1387 	struct scatterlist *sg, *iter;
1388 	unsigned int count = view->partial.size;
1389 	unsigned int offset;
1390 	int ret = -ENOMEM;
1391 
1392 	st = kmalloc(sizeof(*st), GFP_KERNEL);
1393 	if (!st)
1394 		goto err_st_alloc;
1395 
1396 	ret = sg_alloc_table(st, count, GFP_KERNEL);
1397 	if (ret)
1398 		goto err_sg_alloc;
1399 
1400 	iter = i915_gem_object_get_sg_dma(obj, view->partial.offset, &offset);
1401 	GEM_BUG_ON(!iter);
1402 
1403 	sg = st->sgl;
1404 	st->nents = 0;
1405 	do {
1406 		unsigned int len;
1407 
1408 		len = min(sg_dma_len(iter) - (offset << PAGE_SHIFT),
1409 			  count << PAGE_SHIFT);
1410 		sg_set_page(sg, NULL, len, 0);
1411 		sg_dma_address(sg) =
1412 			sg_dma_address(iter) + (offset << PAGE_SHIFT);
1413 		sg_dma_len(sg) = len;
1414 
1415 		st->nents++;
1416 		count -= len >> PAGE_SHIFT;
1417 		if (count == 0) {
1418 			sg_mark_end(sg);
1419 			i915_sg_trim(st); /* Drop any unused tail entries. */
1420 
1421 			return st;
1422 		}
1423 
1424 		sg = __sg_next(sg);
1425 		iter = __sg_next(iter);
1426 		offset = 0;
1427 	} while (1);
1428 
1429 err_sg_alloc:
1430 	kfree(st);
1431 err_st_alloc:
1432 	return ERR_PTR(ret);
1433 }
1434 
1435 static int
1436 i915_get_ggtt_vma_pages(struct i915_vma *vma)
1437 {
1438 	int ret;
1439 
1440 	/*
1441 	 * The vma->pages are only valid within the lifespan of the borrowed
1442 	 * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so
1443 	 * must be the vma->pages. A simple rule is that vma->pages must only
1444 	 * be accessed when the obj->mm.pages are pinned.
1445 	 */
1446 	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj));
1447 
1448 	switch (vma->ggtt_view.type) {
1449 	default:
1450 		GEM_BUG_ON(vma->ggtt_view.type);
1451 		fallthrough;
1452 	case I915_GGTT_VIEW_NORMAL:
1453 		vma->pages = vma->obj->mm.pages;
1454 		return 0;
1455 
1456 	case I915_GGTT_VIEW_ROTATED:
1457 		vma->pages =
1458 			intel_rotate_pages(&vma->ggtt_view.rotated, vma->obj);
1459 		break;
1460 
1461 	case I915_GGTT_VIEW_REMAPPED:
1462 		vma->pages =
1463 			intel_remap_pages(&vma->ggtt_view.remapped, vma->obj);
1464 		break;
1465 
1466 	case I915_GGTT_VIEW_PARTIAL:
1467 		vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj);
1468 		break;
1469 	}
1470 
1471 	ret = 0;
1472 	if (IS_ERR(vma->pages)) {
1473 		ret = PTR_ERR(vma->pages);
1474 		vma->pages = NULL;
1475 		drm_err(&vma->vm->i915->drm,
1476 			"Failed to get pages for VMA view type %u (%d)!\n",
1477 			vma->ggtt_view.type, ret);
1478 	}
1479 	return ret;
1480 }
1481