1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 8 #include "intel_breadcrumbs.h" 9 #include "intel_context.h" 10 #include "intel_engine.h" 11 #include "intel_engine_heartbeat.h" 12 #include "intel_engine_pm.h" 13 #include "intel_gt.h" 14 #include "intel_gt_pm.h" 15 #include "intel_rc6.h" 16 #include "intel_ring.h" 17 #include "shmem_utils.h" 18 19 static void dbg_poison_ce(struct intel_context *ce) 20 { 21 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 22 return; 23 24 if (ce->state) { 25 struct drm_i915_gem_object *obj = ce->state->obj; 26 int type = i915_coherent_map_type(ce->engine->i915, obj, true); 27 void *map; 28 29 if (!i915_gem_object_trylock(obj)) 30 return; 31 32 map = i915_gem_object_pin_map(obj, type); 33 if (!IS_ERR(map)) { 34 memset(map, CONTEXT_REDZONE, obj->base.size); 35 i915_gem_object_flush_map(obj); 36 i915_gem_object_unpin_map(obj); 37 } 38 i915_gem_object_unlock(obj); 39 } 40 } 41 42 static int __engine_unpark(struct intel_wakeref *wf) 43 { 44 struct intel_engine_cs *engine = 45 container_of(wf, typeof(*engine), wakeref); 46 struct intel_context *ce; 47 48 ENGINE_TRACE(engine, "\n"); 49 50 intel_gt_pm_get(engine->gt); 51 52 /* Discard stale context state from across idling */ 53 ce = engine->kernel_context; 54 if (ce) { 55 GEM_BUG_ON(test_bit(CONTEXT_VALID_BIT, &ce->flags)); 56 57 /* Flush all pending HW writes before we touch the context */ 58 while (unlikely(intel_context_inflight(ce))) 59 intel_engine_flush_submission(engine); 60 61 /* First poison the image to verify we never fully trust it */ 62 dbg_poison_ce(ce); 63 64 /* Scrub the context image after our loss of control */ 65 ce->ops->reset(ce); 66 67 CE_TRACE(ce, "reset { seqno:%x, *hwsp:%x, ring:%x }\n", 68 ce->timeline->seqno, 69 READ_ONCE(*ce->timeline->hwsp_seqno), 70 ce->ring->emit); 71 GEM_BUG_ON(ce->timeline->seqno != 72 READ_ONCE(*ce->timeline->hwsp_seqno)); 73 } 74 75 if (engine->unpark) 76 engine->unpark(engine); 77 78 intel_breadcrumbs_unpark(engine->breadcrumbs); 79 intel_engine_unpark_heartbeat(engine); 80 return 0; 81 } 82 83 #if IS_ENABLED(CONFIG_LOCKDEP) 84 85 static unsigned long __timeline_mark_lock(struct intel_context *ce) 86 { 87 unsigned long flags; 88 89 local_irq_save(flags); 90 mutex_acquire(&ce->timeline->mutex.dep_map, 2, 0, _THIS_IP_); 91 92 return flags; 93 } 94 95 static void __timeline_mark_unlock(struct intel_context *ce, 96 unsigned long flags) 97 { 98 mutex_release(&ce->timeline->mutex.dep_map, _THIS_IP_); 99 local_irq_restore(flags); 100 } 101 102 #else 103 104 static unsigned long __timeline_mark_lock(struct intel_context *ce) 105 { 106 return 0; 107 } 108 109 static void __timeline_mark_unlock(struct intel_context *ce, 110 unsigned long flags) 111 { 112 } 113 114 #endif /* !IS_ENABLED(CONFIG_LOCKDEP) */ 115 116 static void duration(struct dma_fence *fence, struct dma_fence_cb *cb) 117 { 118 struct i915_request *rq = to_request(fence); 119 120 ewma__engine_latency_add(&rq->engine->latency, 121 ktime_us_delta(rq->fence.timestamp, 122 rq->duration.emitted)); 123 } 124 125 static void 126 __queue_and_release_pm(struct i915_request *rq, 127 struct intel_timeline *tl, 128 struct intel_engine_cs *engine) 129 { 130 struct intel_gt_timelines *timelines = &engine->gt->timelines; 131 132 ENGINE_TRACE(engine, "parking\n"); 133 134 /* 135 * We have to serialise all potential retirement paths with our 136 * submission, as we don't want to underflow either the 137 * engine->wakeref.counter or our timeline->active_count. 138 * 139 * Equally, we cannot allow a new submission to start until 140 * after we finish queueing, nor could we allow that submitter 141 * to retire us before we are ready! 142 */ 143 spin_lock(&timelines->lock); 144 145 /* Let intel_gt_retire_requests() retire us (acquired under lock) */ 146 if (!atomic_fetch_inc(&tl->active_count)) 147 list_add_tail(&tl->link, &timelines->active_list); 148 149 /* Hand the request over to HW and so engine_retire() */ 150 __i915_request_queue_bh(rq); 151 152 /* Let new submissions commence (and maybe retire this timeline) */ 153 __intel_wakeref_defer_park(&engine->wakeref); 154 155 spin_unlock(&timelines->lock); 156 } 157 158 static bool switch_to_kernel_context(struct intel_engine_cs *engine) 159 { 160 struct intel_context *ce = engine->kernel_context; 161 struct i915_request *rq; 162 unsigned long flags; 163 bool result = true; 164 165 /* 166 * This is execlist specific behaviour intended to ensure the GPU is 167 * idle by switching to a known 'safe' context. With GuC submission, the 168 * same idle guarantee is achieved by other means (disabling 169 * scheduling). Further, switching to a 'safe' context has no effect 170 * with GuC submission as the scheduler can just switch back again. 171 * 172 * FIXME: Move this backend scheduler specific behaviour into the 173 * scheduler backend. 174 */ 175 if (intel_engine_uses_guc(engine)) 176 return true; 177 178 /* GPU is pointing to the void, as good as in the kernel context. */ 179 if (intel_gt_is_wedged(engine->gt)) 180 return true; 181 182 GEM_BUG_ON(!intel_context_is_barrier(ce)); 183 GEM_BUG_ON(ce->timeline->hwsp_ggtt != engine->status_page.vma); 184 185 /* Already inside the kernel context, safe to power down. */ 186 if (engine->wakeref_serial == engine->serial) 187 return true; 188 189 /* 190 * Note, we do this without taking the timeline->mutex. We cannot 191 * as we may be called while retiring the kernel context and so 192 * already underneath the timeline->mutex. Instead we rely on the 193 * exclusive property of the __engine_park that prevents anyone 194 * else from creating a request on this engine. This also requires 195 * that the ring is empty and we avoid any waits while constructing 196 * the context, as they assume protection by the timeline->mutex. 197 * This should hold true as we can only park the engine after 198 * retiring the last request, thus all rings should be empty and 199 * all timelines idle. 200 * 201 * For unlocking, there are 2 other parties and the GPU who have a 202 * stake here. 203 * 204 * A new gpu user will be waiting on the engine-pm to start their 205 * engine_unpark. New waiters are predicated on engine->wakeref.count 206 * and so intel_wakeref_defer_park() acts like a mutex_unlock of the 207 * engine->wakeref. 208 * 209 * The other party is intel_gt_retire_requests(), which is walking the 210 * list of active timelines looking for completions. Meanwhile as soon 211 * as we call __i915_request_queue(), the GPU may complete our request. 212 * Ergo, if we put ourselves on the timelines.active_list 213 * (se intel_timeline_enter()) before we increment the 214 * engine->wakeref.count, we may see the request completion and retire 215 * it causing an underflow of the engine->wakeref. 216 */ 217 flags = __timeline_mark_lock(ce); 218 GEM_BUG_ON(atomic_read(&ce->timeline->active_count) < 0); 219 220 rq = __i915_request_create(ce, GFP_NOWAIT); 221 if (IS_ERR(rq)) 222 /* Context switch failed, hope for the best! Maybe reset? */ 223 goto out_unlock; 224 225 /* Check again on the next retirement. */ 226 engine->wakeref_serial = engine->serial + 1; 227 i915_request_add_active_barriers(rq); 228 229 /* Install ourselves as a preemption barrier */ 230 rq->sched.attr.priority = I915_PRIORITY_BARRIER; 231 if (likely(!__i915_request_commit(rq))) { /* engine should be idle! */ 232 /* 233 * Use an interrupt for precise measurement of duration, 234 * otherwise we rely on someone else retiring all the requests 235 * which may delay the signaling (i.e. we will likely wait 236 * until the background request retirement running every 237 * second or two). 238 */ 239 BUILD_BUG_ON(sizeof(rq->duration) > sizeof(rq->submitq)); 240 dma_fence_add_callback(&rq->fence, &rq->duration.cb, duration); 241 rq->duration.emitted = ktime_get(); 242 } 243 244 /* Expose ourselves to the world */ 245 __queue_and_release_pm(rq, ce->timeline, engine); 246 247 result = false; 248 out_unlock: 249 __timeline_mark_unlock(ce, flags); 250 return result; 251 } 252 253 static void call_idle_barriers(struct intel_engine_cs *engine) 254 { 255 struct llist_node *node, *next; 256 257 llist_for_each_safe(node, next, llist_del_all(&engine->barrier_tasks)) { 258 struct dma_fence_cb *cb = 259 container_of((struct list_head *)node, 260 typeof(*cb), node); 261 262 cb->func(ERR_PTR(-EAGAIN), cb); 263 } 264 } 265 266 static int __engine_park(struct intel_wakeref *wf) 267 { 268 struct intel_engine_cs *engine = 269 container_of(wf, typeof(*engine), wakeref); 270 271 engine->saturated = 0; 272 273 /* 274 * If one and only one request is completed between pm events, 275 * we know that we are inside the kernel context and it is 276 * safe to power down. (We are paranoid in case that runtime 277 * suspend causes corruption to the active context image, and 278 * want to avoid that impacting userspace.) 279 */ 280 if (!switch_to_kernel_context(engine)) 281 return -EBUSY; 282 283 ENGINE_TRACE(engine, "parked\n"); 284 285 call_idle_barriers(engine); /* cleanup after wedging */ 286 287 intel_engine_park_heartbeat(engine); 288 intel_breadcrumbs_park(engine->breadcrumbs); 289 290 /* Must be reset upon idling, or we may miss the busy wakeup. */ 291 GEM_BUG_ON(engine->sched_engine->queue_priority_hint != INT_MIN); 292 293 if (engine->park) 294 engine->park(engine); 295 296 /* While gt calls i915_vma_parked(), we have to break the lock cycle */ 297 intel_gt_pm_put_async(engine->gt); 298 return 0; 299 } 300 301 static const struct intel_wakeref_ops wf_ops = { 302 .get = __engine_unpark, 303 .put = __engine_park, 304 }; 305 306 void intel_engine_init__pm(struct intel_engine_cs *engine) 307 { 308 struct intel_runtime_pm *rpm = engine->uncore->rpm; 309 310 intel_wakeref_init(&engine->wakeref, rpm, &wf_ops); 311 intel_engine_init_heartbeat(engine); 312 } 313 314 /** 315 * intel_engine_reset_pinned_contexts - Reset the pinned contexts of 316 * an engine. 317 * @engine: The engine whose pinned contexts we want to reset. 318 * 319 * Typically the pinned context LMEM images lose or get their content 320 * corrupted on suspend. This function resets their images. 321 */ 322 void intel_engine_reset_pinned_contexts(struct intel_engine_cs *engine) 323 { 324 struct intel_context *ce; 325 326 list_for_each_entry(ce, &engine->pinned_contexts_list, 327 pinned_contexts_link) { 328 /* kernel context gets reset at __engine_unpark() */ 329 if (ce == engine->kernel_context) 330 continue; 331 332 dbg_poison_ce(ce); 333 ce->ops->reset(ce); 334 } 335 } 336 337 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 338 #include "selftest_engine_pm.c" 339 #endif 340