1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 8 #include "intel_breadcrumbs.h" 9 #include "intel_context.h" 10 #include "intel_engine.h" 11 #include "intel_engine_heartbeat.h" 12 #include "intel_engine_pm.h" 13 #include "intel_gt.h" 14 #include "intel_gt_pm.h" 15 #include "intel_rc6.h" 16 #include "intel_ring.h" 17 #include "shmem_utils.h" 18 #include "intel_gt_regs.h" 19 20 static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine) 21 { 22 struct drm_i915_private *i915 = engine->i915; 23 24 if (IS_METEORLAKE(i915) && engine->id == GSC0) { 25 intel_uncore_write(engine->gt->uncore, 26 RC_PSMI_CTRL_GSCCS, 27 _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE)); 28 /* hysteresis 0xA=5us as recommended in spec*/ 29 intel_uncore_write(engine->gt->uncore, 30 PWRCTX_MAXCNT_GSCCS, 31 0xA); 32 } 33 } 34 35 static void dbg_poison_ce(struct intel_context *ce) 36 { 37 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 38 return; 39 40 if (ce->state) { 41 struct drm_i915_gem_object *obj = ce->state->obj; 42 int type = i915_coherent_map_type(ce->engine->i915, obj, true); 43 void *map; 44 45 if (!i915_gem_object_trylock(obj, NULL)) 46 return; 47 48 map = i915_gem_object_pin_map(obj, type); 49 if (!IS_ERR(map)) { 50 memset(map, CONTEXT_REDZONE, obj->base.size); 51 i915_gem_object_flush_map(obj); 52 i915_gem_object_unpin_map(obj); 53 } 54 i915_gem_object_unlock(obj); 55 } 56 } 57 58 static int __engine_unpark(struct intel_wakeref *wf) 59 { 60 struct intel_engine_cs *engine = 61 container_of(wf, typeof(*engine), wakeref); 62 struct intel_context *ce; 63 64 ENGINE_TRACE(engine, "\n"); 65 66 intel_gt_pm_get(engine->gt); 67 68 /* Discard stale context state from across idling */ 69 ce = engine->kernel_context; 70 if (ce) { 71 GEM_BUG_ON(test_bit(CONTEXT_VALID_BIT, &ce->flags)); 72 73 /* Flush all pending HW writes before we touch the context */ 74 while (unlikely(intel_context_inflight(ce))) 75 intel_engine_flush_submission(engine); 76 77 /* First poison the image to verify we never fully trust it */ 78 dbg_poison_ce(ce); 79 80 /* Scrub the context image after our loss of control */ 81 ce->ops->reset(ce); 82 83 CE_TRACE(ce, "reset { seqno:%x, *hwsp:%x, ring:%x }\n", 84 ce->timeline->seqno, 85 READ_ONCE(*ce->timeline->hwsp_seqno), 86 ce->ring->emit); 87 GEM_BUG_ON(ce->timeline->seqno != 88 READ_ONCE(*ce->timeline->hwsp_seqno)); 89 } 90 91 if (engine->unpark) 92 engine->unpark(engine); 93 94 intel_breadcrumbs_unpark(engine->breadcrumbs); 95 intel_engine_unpark_heartbeat(engine); 96 return 0; 97 } 98 99 static void duration(struct dma_fence *fence, struct dma_fence_cb *cb) 100 { 101 struct i915_request *rq = to_request(fence); 102 103 ewma__engine_latency_add(&rq->engine->latency, 104 ktime_us_delta(rq->fence.timestamp, 105 rq->duration.emitted)); 106 } 107 108 static void 109 __queue_and_release_pm(struct i915_request *rq, 110 struct intel_timeline *tl, 111 struct intel_engine_cs *engine) 112 { 113 struct intel_gt_timelines *timelines = &engine->gt->timelines; 114 115 ENGINE_TRACE(engine, "parking\n"); 116 117 /* 118 * We have to serialise all potential retirement paths with our 119 * submission, as we don't want to underflow either the 120 * engine->wakeref.counter or our timeline->active_count. 121 * 122 * Equally, we cannot allow a new submission to start until 123 * after we finish queueing, nor could we allow that submitter 124 * to retire us before we are ready! 125 */ 126 spin_lock(&timelines->lock); 127 128 /* Let intel_gt_retire_requests() retire us (acquired under lock) */ 129 if (!atomic_fetch_inc(&tl->active_count)) 130 list_add_tail(&tl->link, &timelines->active_list); 131 132 /* Hand the request over to HW and so engine_retire() */ 133 __i915_request_queue_bh(rq); 134 135 /* Let new submissions commence (and maybe retire this timeline) */ 136 __intel_wakeref_defer_park(&engine->wakeref); 137 138 spin_unlock(&timelines->lock); 139 } 140 141 static bool switch_to_kernel_context(struct intel_engine_cs *engine) 142 { 143 struct intel_context *ce = engine->kernel_context; 144 struct i915_request *rq; 145 bool result = true; 146 147 /* 148 * This is execlist specific behaviour intended to ensure the GPU is 149 * idle by switching to a known 'safe' context. With GuC submission, the 150 * same idle guarantee is achieved by other means (disabling 151 * scheduling). Further, switching to a 'safe' context has no effect 152 * with GuC submission as the scheduler can just switch back again. 153 * 154 * FIXME: Move this backend scheduler specific behaviour into the 155 * scheduler backend. 156 */ 157 if (intel_engine_uses_guc(engine)) 158 return true; 159 160 /* GPU is pointing to the void, as good as in the kernel context. */ 161 if (intel_gt_is_wedged(engine->gt)) 162 return true; 163 164 GEM_BUG_ON(!intel_context_is_barrier(ce)); 165 GEM_BUG_ON(ce->timeline->hwsp_ggtt != engine->status_page.vma); 166 167 /* Already inside the kernel context, safe to power down. */ 168 if (engine->wakeref_serial == engine->serial) 169 return true; 170 171 /* 172 * Note, we do this without taking the timeline->mutex. We cannot 173 * as we may be called while retiring the kernel context and so 174 * already underneath the timeline->mutex. Instead we rely on the 175 * exclusive property of the __engine_park that prevents anyone 176 * else from creating a request on this engine. This also requires 177 * that the ring is empty and we avoid any waits while constructing 178 * the context, as they assume protection by the timeline->mutex. 179 * This should hold true as we can only park the engine after 180 * retiring the last request, thus all rings should be empty and 181 * all timelines idle. 182 * 183 * For unlocking, there are 2 other parties and the GPU who have a 184 * stake here. 185 * 186 * A new gpu user will be waiting on the engine-pm to start their 187 * engine_unpark. New waiters are predicated on engine->wakeref.count 188 * and so intel_wakeref_defer_park() acts like a mutex_unlock of the 189 * engine->wakeref. 190 * 191 * The other party is intel_gt_retire_requests(), which is walking the 192 * list of active timelines looking for completions. Meanwhile as soon 193 * as we call __i915_request_queue(), the GPU may complete our request. 194 * Ergo, if we put ourselves on the timelines.active_list 195 * (se intel_timeline_enter()) before we increment the 196 * engine->wakeref.count, we may see the request completion and retire 197 * it causing an underflow of the engine->wakeref. 198 */ 199 set_bit(CONTEXT_IS_PARKING, &ce->flags); 200 GEM_BUG_ON(atomic_read(&ce->timeline->active_count) < 0); 201 202 rq = __i915_request_create(ce, GFP_NOWAIT); 203 if (IS_ERR(rq)) 204 /* Context switch failed, hope for the best! Maybe reset? */ 205 goto out_unlock; 206 207 /* Check again on the next retirement. */ 208 engine->wakeref_serial = engine->serial + 1; 209 i915_request_add_active_barriers(rq); 210 211 /* Install ourselves as a preemption barrier */ 212 rq->sched.attr.priority = I915_PRIORITY_BARRIER; 213 if (likely(!__i915_request_commit(rq))) { /* engine should be idle! */ 214 /* 215 * Use an interrupt for precise measurement of duration, 216 * otherwise we rely on someone else retiring all the requests 217 * which may delay the signaling (i.e. we will likely wait 218 * until the background request retirement running every 219 * second or two). 220 */ 221 BUILD_BUG_ON(sizeof(rq->duration) > sizeof(rq->submitq)); 222 dma_fence_add_callback(&rq->fence, &rq->duration.cb, duration); 223 rq->duration.emitted = ktime_get(); 224 } 225 226 /* Expose ourselves to the world */ 227 __queue_and_release_pm(rq, ce->timeline, engine); 228 229 result = false; 230 out_unlock: 231 clear_bit(CONTEXT_IS_PARKING, &ce->flags); 232 return result; 233 } 234 235 static void call_idle_barriers(struct intel_engine_cs *engine) 236 { 237 struct llist_node *node, *next; 238 239 llist_for_each_safe(node, next, llist_del_all(&engine->barrier_tasks)) { 240 struct dma_fence_cb *cb = 241 container_of((struct list_head *)node, 242 typeof(*cb), node); 243 244 cb->func(ERR_PTR(-EAGAIN), cb); 245 } 246 } 247 248 static int __engine_park(struct intel_wakeref *wf) 249 { 250 struct intel_engine_cs *engine = 251 container_of(wf, typeof(*engine), wakeref); 252 253 engine->saturated = 0; 254 255 /* 256 * If one and only one request is completed between pm events, 257 * we know that we are inside the kernel context and it is 258 * safe to power down. (We are paranoid in case that runtime 259 * suspend causes corruption to the active context image, and 260 * want to avoid that impacting userspace.) 261 */ 262 if (!switch_to_kernel_context(engine)) 263 return -EBUSY; 264 265 ENGINE_TRACE(engine, "parked\n"); 266 267 call_idle_barriers(engine); /* cleanup after wedging */ 268 269 intel_engine_park_heartbeat(engine); 270 intel_breadcrumbs_park(engine->breadcrumbs); 271 272 /* Must be reset upon idling, or we may miss the busy wakeup. */ 273 GEM_BUG_ON(engine->sched_engine->queue_priority_hint != INT_MIN); 274 275 if (engine->park) 276 engine->park(engine); 277 278 /* While gt calls i915_vma_parked(), we have to break the lock cycle */ 279 intel_gt_pm_put_async(engine->gt); 280 return 0; 281 } 282 283 static const struct intel_wakeref_ops wf_ops = { 284 .get = __engine_unpark, 285 .put = __engine_park, 286 }; 287 288 void intel_engine_init__pm(struct intel_engine_cs *engine) 289 { 290 struct intel_runtime_pm *rpm = engine->uncore->rpm; 291 292 intel_wakeref_init(&engine->wakeref, rpm, &wf_ops); 293 intel_engine_init_heartbeat(engine); 294 295 intel_gsc_idle_msg_enable(engine); 296 } 297 298 /** 299 * intel_engine_reset_pinned_contexts - Reset the pinned contexts of 300 * an engine. 301 * @engine: The engine whose pinned contexts we want to reset. 302 * 303 * Typically the pinned context LMEM images lose or get their content 304 * corrupted on suspend. This function resets their images. 305 */ 306 void intel_engine_reset_pinned_contexts(struct intel_engine_cs *engine) 307 { 308 struct intel_context *ce; 309 310 list_for_each_entry(ce, &engine->pinned_contexts_list, 311 pinned_contexts_link) { 312 /* kernel context gets reset at __engine_unpark() */ 313 if (ce == engine->kernel_context) 314 continue; 315 316 dbg_poison_ce(ce); 317 ce->ops->reset(ce); 318 } 319 } 320 321 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 322 #include "selftest_engine_pm.c" 323 #endif 324