1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2016 Intel Corporation 4 */ 5 6 #include <drm/drm_print.h> 7 8 #include "gem/i915_gem_context.h" 9 #include "gem/i915_gem_internal.h" 10 #include "gt/intel_gt_regs.h" 11 12 #include "i915_cmd_parser.h" 13 #include "i915_drv.h" 14 #include "intel_breadcrumbs.h" 15 #include "intel_context.h" 16 #include "intel_engine.h" 17 #include "intel_engine_pm.h" 18 #include "intel_engine_regs.h" 19 #include "intel_engine_user.h" 20 #include "intel_execlists_submission.h" 21 #include "intel_gt.h" 22 #include "intel_gt_requests.h" 23 #include "intel_gt_pm.h" 24 #include "intel_lrc.h" 25 #include "intel_lrc_reg.h" 26 #include "intel_reset.h" 27 #include "intel_ring.h" 28 #include "uc/intel_guc_submission.h" 29 30 /* Haswell does have the CXT_SIZE register however it does not appear to be 31 * valid. Now, docs explain in dwords what is in the context object. The full 32 * size is 70720 bytes, however, the power context and execlist context will 33 * never be saved (power context is stored elsewhere, and execlists don't work 34 * on HSW) - so the final size, including the extra state required for the 35 * Resource Streamer, is 66944 bytes, which rounds to 17 pages. 36 */ 37 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 38 39 #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 40 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) 41 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 42 #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE) 43 44 #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE) 45 46 #define MAX_MMIO_BASES 3 47 struct engine_info { 48 u8 class; 49 u8 instance; 50 /* mmio bases table *must* be sorted in reverse graphics_ver order */ 51 struct engine_mmio_base { 52 u32 graphics_ver : 8; 53 u32 base : 24; 54 } mmio_bases[MAX_MMIO_BASES]; 55 }; 56 57 static const struct engine_info intel_engines[] = { 58 [RCS0] = { 59 .class = RENDER_CLASS, 60 .instance = 0, 61 .mmio_bases = { 62 { .graphics_ver = 1, .base = RENDER_RING_BASE } 63 }, 64 }, 65 [BCS0] = { 66 .class = COPY_ENGINE_CLASS, 67 .instance = 0, 68 .mmio_bases = { 69 { .graphics_ver = 6, .base = BLT_RING_BASE } 70 }, 71 }, 72 [VCS0] = { 73 .class = VIDEO_DECODE_CLASS, 74 .instance = 0, 75 .mmio_bases = { 76 { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE }, 77 { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE }, 78 { .graphics_ver = 4, .base = BSD_RING_BASE } 79 }, 80 }, 81 [VCS1] = { 82 .class = VIDEO_DECODE_CLASS, 83 .instance = 1, 84 .mmio_bases = { 85 { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE }, 86 { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE } 87 }, 88 }, 89 [VCS2] = { 90 .class = VIDEO_DECODE_CLASS, 91 .instance = 2, 92 .mmio_bases = { 93 { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE } 94 }, 95 }, 96 [VCS3] = { 97 .class = VIDEO_DECODE_CLASS, 98 .instance = 3, 99 .mmio_bases = { 100 { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE } 101 }, 102 }, 103 [VCS4] = { 104 .class = VIDEO_DECODE_CLASS, 105 .instance = 4, 106 .mmio_bases = { 107 { .graphics_ver = 12, .base = XEHP_BSD5_RING_BASE } 108 }, 109 }, 110 [VCS5] = { 111 .class = VIDEO_DECODE_CLASS, 112 .instance = 5, 113 .mmio_bases = { 114 { .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE } 115 }, 116 }, 117 [VCS6] = { 118 .class = VIDEO_DECODE_CLASS, 119 .instance = 6, 120 .mmio_bases = { 121 { .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE } 122 }, 123 }, 124 [VCS7] = { 125 .class = VIDEO_DECODE_CLASS, 126 .instance = 7, 127 .mmio_bases = { 128 { .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE } 129 }, 130 }, 131 [VECS0] = { 132 .class = VIDEO_ENHANCEMENT_CLASS, 133 .instance = 0, 134 .mmio_bases = { 135 { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE }, 136 { .graphics_ver = 7, .base = VEBOX_RING_BASE } 137 }, 138 }, 139 [VECS1] = { 140 .class = VIDEO_ENHANCEMENT_CLASS, 141 .instance = 1, 142 .mmio_bases = { 143 { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE } 144 }, 145 }, 146 [VECS2] = { 147 .class = VIDEO_ENHANCEMENT_CLASS, 148 .instance = 2, 149 .mmio_bases = { 150 { .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE } 151 }, 152 }, 153 [VECS3] = { 154 .class = VIDEO_ENHANCEMENT_CLASS, 155 .instance = 3, 156 .mmio_bases = { 157 { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE } 158 }, 159 }, 160 [CCS0] = { 161 .class = COMPUTE_CLASS, 162 .instance = 0, 163 .mmio_bases = { 164 { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE } 165 } 166 }, 167 [CCS1] = { 168 .class = COMPUTE_CLASS, 169 .instance = 1, 170 .mmio_bases = { 171 { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE } 172 } 173 }, 174 [CCS2] = { 175 .class = COMPUTE_CLASS, 176 .instance = 2, 177 .mmio_bases = { 178 { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE } 179 } 180 }, 181 [CCS3] = { 182 .class = COMPUTE_CLASS, 183 .instance = 3, 184 .mmio_bases = { 185 { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE } 186 } 187 }, 188 }; 189 190 /** 191 * intel_engine_context_size() - return the size of the context for an engine 192 * @gt: the gt 193 * @class: engine class 194 * 195 * Each engine class may require a different amount of space for a context 196 * image. 197 * 198 * Return: size (in bytes) of an engine class specific context image 199 * 200 * Note: this size includes the HWSP, which is part of the context image 201 * in LRC mode, but does not include the "shared data page" used with 202 * GuC submission. The caller should account for this if using the GuC. 203 */ 204 u32 intel_engine_context_size(struct intel_gt *gt, u8 class) 205 { 206 struct intel_uncore *uncore = gt->uncore; 207 u32 cxt_size; 208 209 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE); 210 211 switch (class) { 212 case COMPUTE_CLASS: 213 fallthrough; 214 case RENDER_CLASS: 215 switch (GRAPHICS_VER(gt->i915)) { 216 default: 217 MISSING_CASE(GRAPHICS_VER(gt->i915)); 218 return DEFAULT_LR_CONTEXT_RENDER_SIZE; 219 case 12: 220 case 11: 221 return GEN11_LR_CONTEXT_RENDER_SIZE; 222 case 9: 223 return GEN9_LR_CONTEXT_RENDER_SIZE; 224 case 8: 225 return GEN8_LR_CONTEXT_RENDER_SIZE; 226 case 7: 227 if (IS_HASWELL(gt->i915)) 228 return HSW_CXT_TOTAL_SIZE; 229 230 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE); 231 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64, 232 PAGE_SIZE); 233 case 6: 234 cxt_size = intel_uncore_read(uncore, CXT_SIZE); 235 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64, 236 PAGE_SIZE); 237 case 5: 238 case 4: 239 /* 240 * There is a discrepancy here between the size reported 241 * by the register and the size of the context layout 242 * in the docs. Both are described as authorative! 243 * 244 * The discrepancy is on the order of a few cachelines, 245 * but the total is under one page (4k), which is our 246 * minimum allocation anyway so it should all come 247 * out in the wash. 248 */ 249 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1; 250 drm_dbg(>->i915->drm, 251 "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n", 252 GRAPHICS_VER(gt->i915), cxt_size * 64, 253 cxt_size - 1); 254 return round_up(cxt_size * 64, PAGE_SIZE); 255 case 3: 256 case 2: 257 /* For the special day when i810 gets merged. */ 258 case 1: 259 return 0; 260 } 261 break; 262 default: 263 MISSING_CASE(class); 264 fallthrough; 265 case VIDEO_DECODE_CLASS: 266 case VIDEO_ENHANCEMENT_CLASS: 267 case COPY_ENGINE_CLASS: 268 if (GRAPHICS_VER(gt->i915) < 8) 269 return 0; 270 return GEN8_LR_CONTEXT_OTHER_SIZE; 271 } 272 } 273 274 static u32 __engine_mmio_base(struct drm_i915_private *i915, 275 const struct engine_mmio_base *bases) 276 { 277 int i; 278 279 for (i = 0; i < MAX_MMIO_BASES; i++) 280 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver) 281 break; 282 283 GEM_BUG_ON(i == MAX_MMIO_BASES); 284 GEM_BUG_ON(!bases[i].base); 285 286 return bases[i].base; 287 } 288 289 static void __sprint_engine_name(struct intel_engine_cs *engine) 290 { 291 /* 292 * Before we know what the uABI name for this engine will be, 293 * we still would like to keep track of this engine in the debug logs. 294 * We throw in a ' here as a reminder that this isn't its final name. 295 */ 296 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u", 297 intel_engine_class_repr(engine->class), 298 engine->instance) >= sizeof(engine->name)); 299 } 300 301 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask) 302 { 303 /* 304 * Though they added more rings on g4x/ilk, they did not add 305 * per-engine HWSTAM until gen6. 306 */ 307 if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS) 308 return; 309 310 if (GRAPHICS_VER(engine->i915) >= 3) 311 ENGINE_WRITE(engine, RING_HWSTAM, mask); 312 else 313 ENGINE_WRITE16(engine, RING_HWSTAM, mask); 314 } 315 316 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine) 317 { 318 /* Mask off all writes into the unknown HWSP */ 319 intel_engine_set_hwsp_writemask(engine, ~0u); 320 } 321 322 static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir) 323 { 324 GEM_DEBUG_WARN_ON(iir); 325 } 326 327 static u32 get_reset_domain(u8 ver, enum intel_engine_id id) 328 { 329 u32 reset_domain; 330 331 if (ver >= 11) { 332 static const u32 engine_reset_domains[] = { 333 [RCS0] = GEN11_GRDOM_RENDER, 334 [BCS0] = GEN11_GRDOM_BLT, 335 [VCS0] = GEN11_GRDOM_MEDIA, 336 [VCS1] = GEN11_GRDOM_MEDIA2, 337 [VCS2] = GEN11_GRDOM_MEDIA3, 338 [VCS3] = GEN11_GRDOM_MEDIA4, 339 [VCS4] = GEN11_GRDOM_MEDIA5, 340 [VCS5] = GEN11_GRDOM_MEDIA6, 341 [VCS6] = GEN11_GRDOM_MEDIA7, 342 [VCS7] = GEN11_GRDOM_MEDIA8, 343 [VECS0] = GEN11_GRDOM_VECS, 344 [VECS1] = GEN11_GRDOM_VECS2, 345 [VECS2] = GEN11_GRDOM_VECS3, 346 [VECS3] = GEN11_GRDOM_VECS4, 347 [CCS0] = GEN11_GRDOM_RENDER, 348 [CCS1] = GEN11_GRDOM_RENDER, 349 [CCS2] = GEN11_GRDOM_RENDER, 350 [CCS3] = GEN11_GRDOM_RENDER, 351 }; 352 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || 353 !engine_reset_domains[id]); 354 reset_domain = engine_reset_domains[id]; 355 } else { 356 static const u32 engine_reset_domains[] = { 357 [RCS0] = GEN6_GRDOM_RENDER, 358 [BCS0] = GEN6_GRDOM_BLT, 359 [VCS0] = GEN6_GRDOM_MEDIA, 360 [VCS1] = GEN8_GRDOM_MEDIA2, 361 [VECS0] = GEN6_GRDOM_VECS, 362 }; 363 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || 364 !engine_reset_domains[id]); 365 reset_domain = engine_reset_domains[id]; 366 } 367 368 return reset_domain; 369 } 370 371 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, 372 u8 logical_instance) 373 { 374 const struct engine_info *info = &intel_engines[id]; 375 struct drm_i915_private *i915 = gt->i915; 376 struct intel_engine_cs *engine; 377 u8 guc_class; 378 379 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH)); 380 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH)); 381 BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1)); 382 BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1)); 383 384 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine))) 385 return -EINVAL; 386 387 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS)) 388 return -EINVAL; 389 390 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE)) 391 return -EINVAL; 392 393 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance])) 394 return -EINVAL; 395 396 engine = kzalloc(sizeof(*engine), GFP_KERNEL); 397 if (!engine) 398 return -ENOMEM; 399 400 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES); 401 402 INIT_LIST_HEAD(&engine->pinned_contexts_list); 403 engine->id = id; 404 engine->legacy_idx = INVALID_ENGINE; 405 engine->mask = BIT(id); 406 engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915), 407 id); 408 engine->i915 = i915; 409 engine->gt = gt; 410 engine->uncore = gt->uncore; 411 guc_class = engine_class_to_guc_class(info->class); 412 engine->guc_id = MAKE_GUC_ID(guc_class, info->instance); 413 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases); 414 415 engine->irq_handler = nop_irq_handler; 416 417 engine->class = info->class; 418 engine->instance = info->instance; 419 engine->logical_mask = BIT(logical_instance); 420 __sprint_engine_name(engine); 421 422 engine->props.heartbeat_interval_ms = 423 CONFIG_DRM_I915_HEARTBEAT_INTERVAL; 424 engine->props.max_busywait_duration_ns = 425 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT; 426 engine->props.preempt_timeout_ms = 427 CONFIG_DRM_I915_PREEMPT_TIMEOUT; 428 engine->props.stop_timeout_ms = 429 CONFIG_DRM_I915_STOP_TIMEOUT; 430 engine->props.timeslice_duration_ms = 431 CONFIG_DRM_I915_TIMESLICE_DURATION; 432 433 /* Override to uninterruptible for OpenCL workloads. */ 434 if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS) 435 engine->props.preempt_timeout_ms = 0; 436 437 /* features common between engines sharing EUs */ 438 if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) { 439 engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE; 440 engine->flags |= I915_ENGINE_HAS_EU_PRIORITY; 441 } 442 443 engine->defaults = engine->props; /* never to change again */ 444 445 engine->context_size = intel_engine_context_size(gt, engine->class); 446 if (WARN_ON(engine->context_size > BIT(20))) 447 engine->context_size = 0; 448 if (engine->context_size) 449 DRIVER_CAPS(i915)->has_logical_contexts = true; 450 451 ewma__engine_latency_init(&engine->latency); 452 seqcount_init(&engine->stats.execlists.lock); 453 454 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); 455 456 /* Scrub mmio state on takeover */ 457 intel_engine_sanitize_mmio(engine); 458 459 gt->engine_class[info->class][info->instance] = engine; 460 gt->engine[id] = engine; 461 462 return 0; 463 } 464 465 static void __setup_engine_capabilities(struct intel_engine_cs *engine) 466 { 467 struct drm_i915_private *i915 = engine->i915; 468 469 if (engine->class == VIDEO_DECODE_CLASS) { 470 /* 471 * HEVC support is present on first engine instance 472 * before Gen11 and on all instances afterwards. 473 */ 474 if (GRAPHICS_VER(i915) >= 11 || 475 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0)) 476 engine->uabi_capabilities |= 477 I915_VIDEO_CLASS_CAPABILITY_HEVC; 478 479 /* 480 * SFC block is present only on even logical engine 481 * instances. 482 */ 483 if ((GRAPHICS_VER(i915) >= 11 && 484 (engine->gt->info.vdbox_sfc_access & 485 BIT(engine->instance))) || 486 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0)) 487 engine->uabi_capabilities |= 488 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 489 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) { 490 if (GRAPHICS_VER(i915) >= 9 && 491 engine->gt->info.sfc_mask & BIT(engine->instance)) 492 engine->uabi_capabilities |= 493 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 494 } 495 } 496 497 static void intel_setup_engine_capabilities(struct intel_gt *gt) 498 { 499 struct intel_engine_cs *engine; 500 enum intel_engine_id id; 501 502 for_each_engine(engine, gt, id) 503 __setup_engine_capabilities(engine); 504 } 505 506 /** 507 * intel_engines_release() - free the resources allocated for Command Streamers 508 * @gt: pointer to struct intel_gt 509 */ 510 void intel_engines_release(struct intel_gt *gt) 511 { 512 struct intel_engine_cs *engine; 513 enum intel_engine_id id; 514 515 /* 516 * Before we release the resources held by engine, we must be certain 517 * that the HW is no longer accessing them -- having the GPU scribble 518 * to or read from a page being used for something else causes no end 519 * of fun. 520 * 521 * The GPU should be reset by this point, but assume the worst just 522 * in case we aborted before completely initialising the engines. 523 */ 524 GEM_BUG_ON(intel_gt_pm_is_awake(gt)); 525 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) 526 __intel_gt_reset(gt, ALL_ENGINES); 527 528 /* Decouple the backend; but keep the layout for late GPU resets */ 529 for_each_engine(engine, gt, id) { 530 if (!engine->release) 531 continue; 532 533 intel_wakeref_wait_for_idle(&engine->wakeref); 534 GEM_BUG_ON(intel_engine_pm_is_awake(engine)); 535 536 engine->release(engine); 537 engine->release = NULL; 538 539 memset(&engine->reset, 0, sizeof(engine->reset)); 540 } 541 } 542 543 void intel_engine_free_request_pool(struct intel_engine_cs *engine) 544 { 545 if (!engine->request_pool) 546 return; 547 548 kmem_cache_free(i915_request_slab_cache(), engine->request_pool); 549 } 550 551 void intel_engines_free(struct intel_gt *gt) 552 { 553 struct intel_engine_cs *engine; 554 enum intel_engine_id id; 555 556 /* Free the requests! dma-resv keeps fences around for an eternity */ 557 rcu_barrier(); 558 559 for_each_engine(engine, gt, id) { 560 intel_engine_free_request_pool(engine); 561 kfree(engine); 562 gt->engine[id] = NULL; 563 } 564 } 565 566 static 567 bool gen11_vdbox_has_sfc(struct intel_gt *gt, 568 unsigned int physical_vdbox, 569 unsigned int logical_vdbox, u16 vdbox_mask) 570 { 571 struct drm_i915_private *i915 = gt->i915; 572 573 /* 574 * In Gen11, only even numbered logical VDBOXes are hooked 575 * up to an SFC (Scaler & Format Converter) unit. 576 * In Gen12, Even numbered physical instance always are connected 577 * to an SFC. Odd numbered physical instances have SFC only if 578 * previous even instance is fused off. 579 * 580 * Starting with Xe_HP, there's also a dedicated SFC_ENABLE field 581 * in the fuse register that tells us whether a specific SFC is present. 582 */ 583 if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0) 584 return false; 585 else if (GRAPHICS_VER(i915) == 12) 586 return (physical_vdbox % 2 == 0) || 587 !(BIT(physical_vdbox - 1) & vdbox_mask); 588 else if (GRAPHICS_VER(i915) == 11) 589 return logical_vdbox % 2 == 0; 590 591 MISSING_CASE(GRAPHICS_VER(i915)); 592 return false; 593 } 594 595 static void engine_mask_apply_compute_fuses(struct intel_gt *gt) 596 { 597 struct drm_i915_private *i915 = gt->i915; 598 struct intel_gt_info *info = >->info; 599 int ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS; 600 unsigned long ccs_mask; 601 unsigned int i; 602 603 if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) 604 return; 605 606 ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu), 607 ss_per_ccs); 608 /* 609 * If all DSS in a quadrant are fused off, the corresponding CCS 610 * engine is not available for use. 611 */ 612 for_each_clear_bit(i, &ccs_mask, I915_MAX_CCS) { 613 info->engine_mask &= ~BIT(_CCS(i)); 614 drm_dbg(&i915->drm, "ccs%u fused off\n", i); 615 } 616 } 617 618 /* 619 * Determine which engines are fused off in our particular hardware. 620 * Note that we have a catch-22 situation where we need to be able to access 621 * the blitter forcewake domain to read the engine fuses, but at the same time 622 * we need to know which engines are available on the system to know which 623 * forcewake domains are present. We solve this by intializing the forcewake 624 * domains based on the full engine mask in the platform capabilities before 625 * calling this function and pruning the domains for fused-off engines 626 * afterwards. 627 */ 628 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) 629 { 630 struct drm_i915_private *i915 = gt->i915; 631 struct intel_gt_info *info = >->info; 632 struct intel_uncore *uncore = gt->uncore; 633 unsigned int logical_vdbox = 0; 634 unsigned int i; 635 u32 media_fuse, fuse1; 636 u16 vdbox_mask; 637 u16 vebox_mask; 638 639 info->engine_mask = INTEL_INFO(i915)->platform_engine_mask; 640 641 if (GRAPHICS_VER(i915) < 11) 642 return info->engine_mask; 643 644 /* 645 * On newer platforms the fusing register is called 'enable' and has 646 * enable semantics, while on older platforms it is called 'disable' 647 * and bits have disable semantices. 648 */ 649 media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); 650 if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) 651 media_fuse = ~media_fuse; 652 653 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; 654 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> 655 GEN11_GT_VEBOX_DISABLE_SHIFT; 656 657 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { 658 fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1); 659 gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1); 660 } else { 661 gt->info.sfc_mask = ~0; 662 } 663 664 for (i = 0; i < I915_MAX_VCS; i++) { 665 if (!HAS_ENGINE(gt, _VCS(i))) { 666 vdbox_mask &= ~BIT(i); 667 continue; 668 } 669 670 if (!(BIT(i) & vdbox_mask)) { 671 info->engine_mask &= ~BIT(_VCS(i)); 672 drm_dbg(&i915->drm, "vcs%u fused off\n", i); 673 continue; 674 } 675 676 if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask)) 677 gt->info.vdbox_sfc_access |= BIT(i); 678 logical_vdbox++; 679 } 680 drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n", 681 vdbox_mask, VDBOX_MASK(gt)); 682 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt)); 683 684 for (i = 0; i < I915_MAX_VECS; i++) { 685 if (!HAS_ENGINE(gt, _VECS(i))) { 686 vebox_mask &= ~BIT(i); 687 continue; 688 } 689 690 if (!(BIT(i) & vebox_mask)) { 691 info->engine_mask &= ~BIT(_VECS(i)); 692 drm_dbg(&i915->drm, "vecs%u fused off\n", i); 693 } 694 } 695 drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n", 696 vebox_mask, VEBOX_MASK(gt)); 697 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); 698 699 engine_mask_apply_compute_fuses(gt); 700 701 return info->engine_mask; 702 } 703 704 static void populate_logical_ids(struct intel_gt *gt, u8 *logical_ids, 705 u8 class, const u8 *map, u8 num_instances) 706 { 707 int i, j; 708 u8 current_logical_id = 0; 709 710 for (j = 0; j < num_instances; ++j) { 711 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) { 712 if (!HAS_ENGINE(gt, i) || 713 intel_engines[i].class != class) 714 continue; 715 716 if (intel_engines[i].instance == map[j]) { 717 logical_ids[intel_engines[i].instance] = 718 current_logical_id++; 719 break; 720 } 721 } 722 } 723 } 724 725 static void setup_logical_ids(struct intel_gt *gt, u8 *logical_ids, u8 class) 726 { 727 int i; 728 u8 map[MAX_ENGINE_INSTANCE + 1]; 729 730 for (i = 0; i < MAX_ENGINE_INSTANCE + 1; ++i) 731 map[i] = i; 732 populate_logical_ids(gt, logical_ids, class, map, ARRAY_SIZE(map)); 733 } 734 735 /** 736 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers 737 * @gt: pointer to struct intel_gt 738 * 739 * Return: non-zero if the initialization failed. 740 */ 741 int intel_engines_init_mmio(struct intel_gt *gt) 742 { 743 struct drm_i915_private *i915 = gt->i915; 744 const unsigned int engine_mask = init_engine_mask(gt); 745 unsigned int mask = 0; 746 unsigned int i, class; 747 u8 logical_ids[MAX_ENGINE_INSTANCE + 1]; 748 int err; 749 750 drm_WARN_ON(&i915->drm, engine_mask == 0); 751 drm_WARN_ON(&i915->drm, engine_mask & 752 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES)); 753 754 if (i915_inject_probe_failure(i915)) 755 return -ENODEV; 756 757 for (class = 0; class < MAX_ENGINE_CLASS + 1; ++class) { 758 setup_logical_ids(gt, logical_ids, class); 759 760 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) { 761 u8 instance = intel_engines[i].instance; 762 763 if (intel_engines[i].class != class || 764 !HAS_ENGINE(gt, i)) 765 continue; 766 767 err = intel_engine_setup(gt, i, 768 logical_ids[instance]); 769 if (err) 770 goto cleanup; 771 772 mask |= BIT(i); 773 } 774 } 775 776 /* 777 * Catch failures to update intel_engines table when the new engines 778 * are added to the driver by a warning and disabling the forgotten 779 * engines. 780 */ 781 if (drm_WARN_ON(&i915->drm, mask != engine_mask)) 782 gt->info.engine_mask = mask; 783 784 gt->info.num_engines = hweight32(mask); 785 786 intel_gt_check_and_clear_faults(gt); 787 788 intel_setup_engine_capabilities(gt); 789 790 intel_uncore_prune_engine_fw_domains(gt->uncore, gt); 791 792 return 0; 793 794 cleanup: 795 intel_engines_free(gt); 796 return err; 797 } 798 799 void intel_engine_init_execlists(struct intel_engine_cs *engine) 800 { 801 struct intel_engine_execlists * const execlists = &engine->execlists; 802 803 execlists->port_mask = 1; 804 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists))); 805 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS); 806 807 memset(execlists->pending, 0, sizeof(execlists->pending)); 808 execlists->active = 809 memset(execlists->inflight, 0, sizeof(execlists->inflight)); 810 } 811 812 static void cleanup_status_page(struct intel_engine_cs *engine) 813 { 814 struct i915_vma *vma; 815 816 /* Prevent writes into HWSP after returning the page to the system */ 817 intel_engine_set_hwsp_writemask(engine, ~0u); 818 819 vma = fetch_and_zero(&engine->status_page.vma); 820 if (!vma) 821 return; 822 823 if (!HWS_NEEDS_PHYSICAL(engine->i915)) 824 i915_vma_unpin(vma); 825 826 i915_gem_object_unpin_map(vma->obj); 827 i915_gem_object_put(vma->obj); 828 } 829 830 static int pin_ggtt_status_page(struct intel_engine_cs *engine, 831 struct i915_gem_ww_ctx *ww, 832 struct i915_vma *vma) 833 { 834 unsigned int flags; 835 836 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) 837 /* 838 * On g33, we cannot place HWS above 256MiB, so 839 * restrict its pinning to the low mappable arena. 840 * Though this restriction is not documented for 841 * gen4, gen5, or byt, they also behave similarly 842 * and hang if the HWS is placed at the top of the 843 * GTT. To generalise, it appears that all !llc 844 * platforms have issues with us placing the HWS 845 * above the mappable region (even though we never 846 * actually map it). 847 */ 848 flags = PIN_MAPPABLE; 849 else 850 flags = PIN_HIGH; 851 852 return i915_ggtt_pin(vma, ww, 0, flags); 853 } 854 855 static int init_status_page(struct intel_engine_cs *engine) 856 { 857 struct drm_i915_gem_object *obj; 858 struct i915_gem_ww_ctx ww; 859 struct i915_vma *vma; 860 void *vaddr; 861 int ret; 862 863 INIT_LIST_HEAD(&engine->status_page.timelines); 864 865 /* 866 * Though the HWS register does support 36bit addresses, historically 867 * we have had hangs and corruption reported due to wild writes if 868 * the HWS is placed above 4G. We only allow objects to be allocated 869 * in GFP_DMA32 for i965, and no earlier physical address users had 870 * access to more than 4G. 871 */ 872 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); 873 if (IS_ERR(obj)) { 874 drm_err(&engine->i915->drm, 875 "Failed to allocate status page\n"); 876 return PTR_ERR(obj); 877 } 878 879 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 880 881 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); 882 if (IS_ERR(vma)) { 883 ret = PTR_ERR(vma); 884 goto err_put; 885 } 886 887 i915_gem_ww_ctx_init(&ww, true); 888 retry: 889 ret = i915_gem_object_lock(obj, &ww); 890 if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915)) 891 ret = pin_ggtt_status_page(engine, &ww, vma); 892 if (ret) 893 goto err; 894 895 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); 896 if (IS_ERR(vaddr)) { 897 ret = PTR_ERR(vaddr); 898 goto err_unpin; 899 } 900 901 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE); 902 engine->status_page.vma = vma; 903 904 err_unpin: 905 if (ret) 906 i915_vma_unpin(vma); 907 err: 908 if (ret == -EDEADLK) { 909 ret = i915_gem_ww_ctx_backoff(&ww); 910 if (!ret) 911 goto retry; 912 } 913 i915_gem_ww_ctx_fini(&ww); 914 err_put: 915 if (ret) 916 i915_gem_object_put(obj); 917 return ret; 918 } 919 920 static int engine_setup_common(struct intel_engine_cs *engine) 921 { 922 int err; 923 924 init_llist_head(&engine->barrier_tasks); 925 926 err = init_status_page(engine); 927 if (err) 928 return err; 929 930 engine->breadcrumbs = intel_breadcrumbs_create(engine); 931 if (!engine->breadcrumbs) { 932 err = -ENOMEM; 933 goto err_status; 934 } 935 936 engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL); 937 if (!engine->sched_engine) { 938 err = -ENOMEM; 939 goto err_sched_engine; 940 } 941 engine->sched_engine->private_data = engine; 942 943 err = intel_engine_init_cmd_parser(engine); 944 if (err) 945 goto err_cmd_parser; 946 947 intel_engine_init_execlists(engine); 948 intel_engine_init__pm(engine); 949 intel_engine_init_retire(engine); 950 951 /* Use the whole device by default */ 952 engine->sseu = 953 intel_sseu_from_device_info(&engine->gt->info.sseu); 954 955 intel_engine_init_workarounds(engine); 956 intel_engine_init_whitelist(engine); 957 intel_engine_init_ctx_wa(engine); 958 959 if (GRAPHICS_VER(engine->i915) >= 12) 960 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO; 961 962 return 0; 963 964 err_cmd_parser: 965 i915_sched_engine_put(engine->sched_engine); 966 err_sched_engine: 967 intel_breadcrumbs_put(engine->breadcrumbs); 968 err_status: 969 cleanup_status_page(engine); 970 return err; 971 } 972 973 struct measure_breadcrumb { 974 struct i915_request rq; 975 struct intel_ring ring; 976 u32 cs[2048]; 977 }; 978 979 static int measure_breadcrumb_dw(struct intel_context *ce) 980 { 981 struct intel_engine_cs *engine = ce->engine; 982 struct measure_breadcrumb *frame; 983 int dw; 984 985 GEM_BUG_ON(!engine->gt->scratch); 986 987 frame = kzalloc(sizeof(*frame), GFP_KERNEL); 988 if (!frame) 989 return -ENOMEM; 990 991 frame->rq.engine = engine; 992 frame->rq.context = ce; 993 rcu_assign_pointer(frame->rq.timeline, ce->timeline); 994 frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno; 995 996 frame->ring.vaddr = frame->cs; 997 frame->ring.size = sizeof(frame->cs); 998 frame->ring.wrap = 999 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size); 1000 frame->ring.effective_size = frame->ring.size; 1001 intel_ring_update_space(&frame->ring); 1002 frame->rq.ring = &frame->ring; 1003 1004 mutex_lock(&ce->timeline->mutex); 1005 spin_lock_irq(&engine->sched_engine->lock); 1006 1007 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs; 1008 1009 spin_unlock_irq(&engine->sched_engine->lock); 1010 mutex_unlock(&ce->timeline->mutex); 1011 1012 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */ 1013 1014 kfree(frame); 1015 return dw; 1016 } 1017 1018 struct intel_context * 1019 intel_engine_create_pinned_context(struct intel_engine_cs *engine, 1020 struct i915_address_space *vm, 1021 unsigned int ring_size, 1022 unsigned int hwsp, 1023 struct lock_class_key *key, 1024 const char *name) 1025 { 1026 struct intel_context *ce; 1027 int err; 1028 1029 ce = intel_context_create(engine); 1030 if (IS_ERR(ce)) 1031 return ce; 1032 1033 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags); 1034 ce->timeline = page_pack_bits(NULL, hwsp); 1035 ce->ring = NULL; 1036 ce->ring_size = ring_size; 1037 1038 i915_vm_put(ce->vm); 1039 ce->vm = i915_vm_get(vm); 1040 1041 err = intel_context_pin(ce); /* perma-pin so it is always available */ 1042 if (err) { 1043 intel_context_put(ce); 1044 return ERR_PTR(err); 1045 } 1046 1047 list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list); 1048 1049 /* 1050 * Give our perma-pinned kernel timelines a separate lockdep class, 1051 * so that we can use them from within the normal user timelines 1052 * should we need to inject GPU operations during their request 1053 * construction. 1054 */ 1055 lockdep_set_class_and_name(&ce->timeline->mutex, key, name); 1056 1057 return ce; 1058 } 1059 1060 void intel_engine_destroy_pinned_context(struct intel_context *ce) 1061 { 1062 struct intel_engine_cs *engine = ce->engine; 1063 struct i915_vma *hwsp = engine->status_page.vma; 1064 1065 GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp); 1066 1067 mutex_lock(&hwsp->vm->mutex); 1068 list_del(&ce->timeline->engine_link); 1069 mutex_unlock(&hwsp->vm->mutex); 1070 1071 list_del(&ce->pinned_contexts_link); 1072 intel_context_unpin(ce); 1073 intel_context_put(ce); 1074 } 1075 1076 static struct intel_context * 1077 create_kernel_context(struct intel_engine_cs *engine) 1078 { 1079 static struct lock_class_key kernel; 1080 1081 return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K, 1082 I915_GEM_HWS_SEQNO_ADDR, 1083 &kernel, "kernel_context"); 1084 } 1085 1086 /** 1087 * intel_engines_init_common - initialize cengine state which might require hw access 1088 * @engine: Engine to initialize. 1089 * 1090 * Initializes @engine@ structure members shared between legacy and execlists 1091 * submission modes which do require hardware access. 1092 * 1093 * Typcally done at later stages of submission mode specific engine setup. 1094 * 1095 * Returns zero on success or an error code on failure. 1096 */ 1097 static int engine_init_common(struct intel_engine_cs *engine) 1098 { 1099 struct intel_context *ce; 1100 int ret; 1101 1102 engine->set_default_submission(engine); 1103 1104 /* 1105 * We may need to do things with the shrinker which 1106 * require us to immediately switch back to the default 1107 * context. This can cause a problem as pinning the 1108 * default context also requires GTT space which may not 1109 * be available. To avoid this we always pin the default 1110 * context. 1111 */ 1112 ce = create_kernel_context(engine); 1113 if (IS_ERR(ce)) 1114 return PTR_ERR(ce); 1115 1116 ret = measure_breadcrumb_dw(ce); 1117 if (ret < 0) 1118 goto err_context; 1119 1120 engine->emit_fini_breadcrumb_dw = ret; 1121 engine->kernel_context = ce; 1122 1123 return 0; 1124 1125 err_context: 1126 intel_engine_destroy_pinned_context(ce); 1127 return ret; 1128 } 1129 1130 int intel_engines_init(struct intel_gt *gt) 1131 { 1132 int (*setup)(struct intel_engine_cs *engine); 1133 struct intel_engine_cs *engine; 1134 enum intel_engine_id id; 1135 int err; 1136 1137 if (intel_uc_uses_guc_submission(>->uc)) { 1138 gt->submission_method = INTEL_SUBMISSION_GUC; 1139 setup = intel_guc_submission_setup; 1140 } else if (HAS_EXECLISTS(gt->i915)) { 1141 gt->submission_method = INTEL_SUBMISSION_ELSP; 1142 setup = intel_execlists_submission_setup; 1143 } else { 1144 gt->submission_method = INTEL_SUBMISSION_RING; 1145 setup = intel_ring_submission_setup; 1146 } 1147 1148 for_each_engine(engine, gt, id) { 1149 err = engine_setup_common(engine); 1150 if (err) 1151 return err; 1152 1153 err = setup(engine); 1154 if (err) 1155 return err; 1156 1157 err = engine_init_common(engine); 1158 if (err) 1159 return err; 1160 1161 intel_engine_add_user(engine); 1162 } 1163 1164 return 0; 1165 } 1166 1167 /** 1168 * intel_engines_cleanup_common - cleans up the engine state created by 1169 * the common initiailizers. 1170 * @engine: Engine to cleanup. 1171 * 1172 * This cleans up everything created by the common helpers. 1173 */ 1174 void intel_engine_cleanup_common(struct intel_engine_cs *engine) 1175 { 1176 GEM_BUG_ON(!list_empty(&engine->sched_engine->requests)); 1177 1178 i915_sched_engine_put(engine->sched_engine); 1179 intel_breadcrumbs_put(engine->breadcrumbs); 1180 1181 intel_engine_fini_retire(engine); 1182 intel_engine_cleanup_cmd_parser(engine); 1183 1184 if (engine->default_state) 1185 fput(engine->default_state); 1186 1187 if (engine->kernel_context) 1188 intel_engine_destroy_pinned_context(engine->kernel_context); 1189 1190 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks)); 1191 cleanup_status_page(engine); 1192 1193 intel_wa_list_free(&engine->ctx_wa_list); 1194 intel_wa_list_free(&engine->wa_list); 1195 intel_wa_list_free(&engine->whitelist); 1196 } 1197 1198 /** 1199 * intel_engine_resume - re-initializes the HW state of the engine 1200 * @engine: Engine to resume. 1201 * 1202 * Returns zero on success or an error code on failure. 1203 */ 1204 int intel_engine_resume(struct intel_engine_cs *engine) 1205 { 1206 intel_engine_apply_workarounds(engine); 1207 intel_engine_apply_whitelist(engine); 1208 1209 return engine->resume(engine); 1210 } 1211 1212 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine) 1213 { 1214 struct drm_i915_private *i915 = engine->i915; 1215 1216 u64 acthd; 1217 1218 if (GRAPHICS_VER(i915) >= 8) 1219 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW); 1220 else if (GRAPHICS_VER(i915) >= 4) 1221 acthd = ENGINE_READ(engine, RING_ACTHD); 1222 else 1223 acthd = ENGINE_READ(engine, ACTHD); 1224 1225 return acthd; 1226 } 1227 1228 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine) 1229 { 1230 u64 bbaddr; 1231 1232 if (GRAPHICS_VER(engine->i915) >= 8) 1233 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW); 1234 else 1235 bbaddr = ENGINE_READ(engine, RING_BBADDR); 1236 1237 return bbaddr; 1238 } 1239 1240 static unsigned long stop_timeout(const struct intel_engine_cs *engine) 1241 { 1242 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */ 1243 return 0; 1244 1245 /* 1246 * If we are doing a normal GPU reset, we can take our time and allow 1247 * the engine to quiesce. We've stopped submission to the engine, and 1248 * if we wait long enough an innocent context should complete and 1249 * leave the engine idle. So they should not be caught unaware by 1250 * the forthcoming GPU reset (which usually follows the stop_cs)! 1251 */ 1252 return READ_ONCE(engine->props.stop_timeout_ms); 1253 } 1254 1255 static int __intel_engine_stop_cs(struct intel_engine_cs *engine, 1256 int fast_timeout_us, 1257 int slow_timeout_ms) 1258 { 1259 struct intel_uncore *uncore = engine->uncore; 1260 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); 1261 int err; 1262 1263 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); 1264 err = __intel_wait_for_register_fw(engine->uncore, mode, 1265 MODE_IDLE, MODE_IDLE, 1266 fast_timeout_us, 1267 slow_timeout_ms, 1268 NULL); 1269 1270 /* A final mmio read to let GPU writes be hopefully flushed to memory */ 1271 intel_uncore_posting_read_fw(uncore, mode); 1272 return err; 1273 } 1274 1275 int intel_engine_stop_cs(struct intel_engine_cs *engine) 1276 { 1277 int err = 0; 1278 1279 if (GRAPHICS_VER(engine->i915) < 3) 1280 return -ENODEV; 1281 1282 ENGINE_TRACE(engine, "\n"); 1283 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { 1284 ENGINE_TRACE(engine, 1285 "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n", 1286 ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR, 1287 ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR); 1288 1289 /* 1290 * Sometimes we observe that the idle flag is not 1291 * set even though the ring is empty. So double 1292 * check before giving up. 1293 */ 1294 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) != 1295 (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR)) 1296 err = -ETIMEDOUT; 1297 } 1298 1299 return err; 1300 } 1301 1302 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) 1303 { 1304 ENGINE_TRACE(engine, "\n"); 1305 1306 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); 1307 } 1308 1309 static u32 1310 read_subslice_reg(const struct intel_engine_cs *engine, 1311 int slice, int subslice, i915_reg_t reg) 1312 { 1313 return intel_uncore_read_with_mcr_steering(engine->uncore, reg, 1314 slice, subslice); 1315 } 1316 1317 /* NB: please notice the memset */ 1318 void intel_engine_get_instdone(const struct intel_engine_cs *engine, 1319 struct intel_instdone *instdone) 1320 { 1321 struct drm_i915_private *i915 = engine->i915; 1322 const struct sseu_dev_info *sseu = &engine->gt->info.sseu; 1323 struct intel_uncore *uncore = engine->uncore; 1324 u32 mmio_base = engine->mmio_base; 1325 int slice; 1326 int subslice; 1327 int iter; 1328 1329 memset(instdone, 0, sizeof(*instdone)); 1330 1331 if (GRAPHICS_VER(i915) >= 8) { 1332 instdone->instdone = 1333 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1334 1335 if (engine->id != RCS0) 1336 return; 1337 1338 instdone->slice_common = 1339 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1340 if (GRAPHICS_VER(i915) >= 12) { 1341 instdone->slice_common_extra[0] = 1342 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA); 1343 instdone->slice_common_extra[1] = 1344 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2); 1345 } 1346 1347 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { 1348 for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) { 1349 instdone->sampler[slice][subslice] = 1350 read_subslice_reg(engine, slice, subslice, 1351 GEN7_SAMPLER_INSTDONE); 1352 instdone->row[slice][subslice] = 1353 read_subslice_reg(engine, slice, subslice, 1354 GEN7_ROW_INSTDONE); 1355 } 1356 } else { 1357 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) { 1358 instdone->sampler[slice][subslice] = 1359 read_subslice_reg(engine, slice, subslice, 1360 GEN7_SAMPLER_INSTDONE); 1361 instdone->row[slice][subslice] = 1362 read_subslice_reg(engine, slice, subslice, 1363 GEN7_ROW_INSTDONE); 1364 } 1365 } 1366 1367 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { 1368 for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) 1369 instdone->geom_svg[slice][subslice] = 1370 read_subslice_reg(engine, slice, subslice, 1371 XEHPG_INSTDONE_GEOM_SVG); 1372 } 1373 } else if (GRAPHICS_VER(i915) >= 7) { 1374 instdone->instdone = 1375 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1376 1377 if (engine->id != RCS0) 1378 return; 1379 1380 instdone->slice_common = 1381 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1382 instdone->sampler[0][0] = 1383 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE); 1384 instdone->row[0][0] = 1385 intel_uncore_read(uncore, GEN7_ROW_INSTDONE); 1386 } else if (GRAPHICS_VER(i915) >= 4) { 1387 instdone->instdone = 1388 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1389 if (engine->id == RCS0) 1390 /* HACK: Using the wrong struct member */ 1391 instdone->slice_common = 1392 intel_uncore_read(uncore, GEN4_INSTDONE1); 1393 } else { 1394 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE); 1395 } 1396 } 1397 1398 static bool ring_is_idle(struct intel_engine_cs *engine) 1399 { 1400 bool idle = true; 1401 1402 if (I915_SELFTEST_ONLY(!engine->mmio_base)) 1403 return true; 1404 1405 if (!intel_engine_pm_get_if_awake(engine)) 1406 return true; 1407 1408 /* First check that no commands are left in the ring */ 1409 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) != 1410 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR)) 1411 idle = false; 1412 1413 /* No bit for gen2, so assume the CS parser is idle */ 1414 if (GRAPHICS_VER(engine->i915) > 2 && 1415 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE)) 1416 idle = false; 1417 1418 intel_engine_pm_put(engine); 1419 1420 return idle; 1421 } 1422 1423 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync) 1424 { 1425 struct tasklet_struct *t = &engine->sched_engine->tasklet; 1426 1427 if (!t->callback) 1428 return; 1429 1430 local_bh_disable(); 1431 if (tasklet_trylock(t)) { 1432 /* Must wait for any GPU reset in progress. */ 1433 if (__tasklet_is_enabled(t)) 1434 t->callback(t); 1435 tasklet_unlock(t); 1436 } 1437 local_bh_enable(); 1438 1439 /* Synchronise and wait for the tasklet on another CPU */ 1440 if (sync) 1441 tasklet_unlock_wait(t); 1442 } 1443 1444 /** 1445 * intel_engine_is_idle() - Report if the engine has finished process all work 1446 * @engine: the intel_engine_cs 1447 * 1448 * Return true if there are no requests pending, nothing left to be submitted 1449 * to hardware, and that the engine is idle. 1450 */ 1451 bool intel_engine_is_idle(struct intel_engine_cs *engine) 1452 { 1453 /* More white lies, if wedged, hw state is inconsistent */ 1454 if (intel_gt_is_wedged(engine->gt)) 1455 return true; 1456 1457 if (!intel_engine_pm_is_awake(engine)) 1458 return true; 1459 1460 /* Waiting to drain ELSP? */ 1461 intel_synchronize_hardirq(engine->i915); 1462 intel_engine_flush_submission(engine); 1463 1464 /* ELSP is empty, but there are ready requests? E.g. after reset */ 1465 if (!i915_sched_engine_is_empty(engine->sched_engine)) 1466 return false; 1467 1468 /* Ring stopped? */ 1469 return ring_is_idle(engine); 1470 } 1471 1472 bool intel_engines_are_idle(struct intel_gt *gt) 1473 { 1474 struct intel_engine_cs *engine; 1475 enum intel_engine_id id; 1476 1477 /* 1478 * If the driver is wedged, HW state may be very inconsistent and 1479 * report that it is still busy, even though we have stopped using it. 1480 */ 1481 if (intel_gt_is_wedged(gt)) 1482 return true; 1483 1484 /* Already parked (and passed an idleness test); must still be idle */ 1485 if (!READ_ONCE(gt->awake)) 1486 return true; 1487 1488 for_each_engine(engine, gt, id) { 1489 if (!intel_engine_is_idle(engine)) 1490 return false; 1491 } 1492 1493 return true; 1494 } 1495 1496 bool intel_engine_irq_enable(struct intel_engine_cs *engine) 1497 { 1498 if (!engine->irq_enable) 1499 return false; 1500 1501 /* Caller disables interrupts */ 1502 spin_lock(&engine->gt->irq_lock); 1503 engine->irq_enable(engine); 1504 spin_unlock(&engine->gt->irq_lock); 1505 1506 return true; 1507 } 1508 1509 void intel_engine_irq_disable(struct intel_engine_cs *engine) 1510 { 1511 if (!engine->irq_disable) 1512 return; 1513 1514 /* Caller disables interrupts */ 1515 spin_lock(&engine->gt->irq_lock); 1516 engine->irq_disable(engine); 1517 spin_unlock(&engine->gt->irq_lock); 1518 } 1519 1520 void intel_engines_reset_default_submission(struct intel_gt *gt) 1521 { 1522 struct intel_engine_cs *engine; 1523 enum intel_engine_id id; 1524 1525 for_each_engine(engine, gt, id) { 1526 if (engine->sanitize) 1527 engine->sanitize(engine); 1528 1529 engine->set_default_submission(engine); 1530 } 1531 } 1532 1533 bool intel_engine_can_store_dword(struct intel_engine_cs *engine) 1534 { 1535 switch (GRAPHICS_VER(engine->i915)) { 1536 case 2: 1537 return false; /* uses physical not virtual addresses */ 1538 case 3: 1539 /* maybe only uses physical not virtual addresses */ 1540 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); 1541 case 4: 1542 return !IS_I965G(engine->i915); /* who knows! */ 1543 case 6: 1544 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ 1545 default: 1546 return true; 1547 } 1548 } 1549 1550 static struct intel_timeline *get_timeline(struct i915_request *rq) 1551 { 1552 struct intel_timeline *tl; 1553 1554 /* 1555 * Even though we are holding the engine->sched_engine->lock here, there 1556 * is no control over the submission queue per-se and we are 1557 * inspecting the active state at a random point in time, with an 1558 * unknown queue. Play safe and make sure the timeline remains valid. 1559 * (Only being used for pretty printing, one extra kref shouldn't 1560 * cause a camel stampede!) 1561 */ 1562 rcu_read_lock(); 1563 tl = rcu_dereference(rq->timeline); 1564 if (!kref_get_unless_zero(&tl->kref)) 1565 tl = NULL; 1566 rcu_read_unlock(); 1567 1568 return tl; 1569 } 1570 1571 static int print_ring(char *buf, int sz, struct i915_request *rq) 1572 { 1573 int len = 0; 1574 1575 if (!i915_request_signaled(rq)) { 1576 struct intel_timeline *tl = get_timeline(rq); 1577 1578 len = scnprintf(buf, sz, 1579 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ", 1580 i915_ggtt_offset(rq->ring->vma), 1581 tl ? tl->hwsp_offset : 0, 1582 hwsp_seqno(rq), 1583 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context), 1584 1000 * 1000)); 1585 1586 if (tl) 1587 intel_timeline_put(tl); 1588 } 1589 1590 return len; 1591 } 1592 1593 static void hexdump(struct drm_printer *m, const void *buf, size_t len) 1594 { 1595 const size_t rowsize = 8 * sizeof(u32); 1596 const void *prev = NULL; 1597 bool skip = false; 1598 size_t pos; 1599 1600 for (pos = 0; pos < len; pos += rowsize) { 1601 char line[128]; 1602 1603 if (prev && !memcmp(prev, buf + pos, rowsize)) { 1604 if (!skip) { 1605 drm_printf(m, "*\n"); 1606 skip = true; 1607 } 1608 continue; 1609 } 1610 1611 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos, 1612 rowsize, sizeof(u32), 1613 line, sizeof(line), 1614 false) >= sizeof(line)); 1615 drm_printf(m, "[%04zx] %s\n", pos, line); 1616 1617 prev = buf + pos; 1618 skip = false; 1619 } 1620 } 1621 1622 static const char *repr_timer(const struct timer_list *t) 1623 { 1624 if (!READ_ONCE(t->expires)) 1625 return "inactive"; 1626 1627 if (timer_pending(t)) 1628 return "active"; 1629 1630 return "expired"; 1631 } 1632 1633 static void intel_engine_print_registers(struct intel_engine_cs *engine, 1634 struct drm_printer *m) 1635 { 1636 struct drm_i915_private *dev_priv = engine->i915; 1637 struct intel_engine_execlists * const execlists = &engine->execlists; 1638 u64 addr; 1639 1640 if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7)) 1641 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID)); 1642 if (HAS_EXECLISTS(dev_priv)) { 1643 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n", 1644 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI)); 1645 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n", 1646 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO)); 1647 } 1648 drm_printf(m, "\tRING_START: 0x%08x\n", 1649 ENGINE_READ(engine, RING_START)); 1650 drm_printf(m, "\tRING_HEAD: 0x%08x\n", 1651 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR); 1652 drm_printf(m, "\tRING_TAIL: 0x%08x\n", 1653 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR); 1654 drm_printf(m, "\tRING_CTL: 0x%08x%s\n", 1655 ENGINE_READ(engine, RING_CTL), 1656 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : ""); 1657 if (GRAPHICS_VER(engine->i915) > 2) { 1658 drm_printf(m, "\tRING_MODE: 0x%08x%s\n", 1659 ENGINE_READ(engine, RING_MI_MODE), 1660 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : ""); 1661 } 1662 1663 if (GRAPHICS_VER(dev_priv) >= 6) { 1664 drm_printf(m, "\tRING_IMR: 0x%08x\n", 1665 ENGINE_READ(engine, RING_IMR)); 1666 drm_printf(m, "\tRING_ESR: 0x%08x\n", 1667 ENGINE_READ(engine, RING_ESR)); 1668 drm_printf(m, "\tRING_EMR: 0x%08x\n", 1669 ENGINE_READ(engine, RING_EMR)); 1670 drm_printf(m, "\tRING_EIR: 0x%08x\n", 1671 ENGINE_READ(engine, RING_EIR)); 1672 } 1673 1674 addr = intel_engine_get_active_head(engine); 1675 drm_printf(m, "\tACTHD: 0x%08x_%08x\n", 1676 upper_32_bits(addr), lower_32_bits(addr)); 1677 addr = intel_engine_get_last_batch_head(engine); 1678 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n", 1679 upper_32_bits(addr), lower_32_bits(addr)); 1680 if (GRAPHICS_VER(dev_priv) >= 8) 1681 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW); 1682 else if (GRAPHICS_VER(dev_priv) >= 4) 1683 addr = ENGINE_READ(engine, RING_DMA_FADD); 1684 else 1685 addr = ENGINE_READ(engine, DMA_FADD_I8XX); 1686 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n", 1687 upper_32_bits(addr), lower_32_bits(addr)); 1688 if (GRAPHICS_VER(dev_priv) >= 4) { 1689 drm_printf(m, "\tIPEIR: 0x%08x\n", 1690 ENGINE_READ(engine, RING_IPEIR)); 1691 drm_printf(m, "\tIPEHR: 0x%08x\n", 1692 ENGINE_READ(engine, RING_IPEHR)); 1693 } else { 1694 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR)); 1695 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR)); 1696 } 1697 1698 if (intel_engine_uses_guc(engine)) { 1699 /* nothing to print yet */ 1700 } else if (HAS_EXECLISTS(dev_priv)) { 1701 struct i915_request * const *port, *rq; 1702 const u32 *hws = 1703 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; 1704 const u8 num_entries = execlists->csb_size; 1705 unsigned int idx; 1706 u8 read, write; 1707 1708 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n", 1709 yesno(test_bit(TASKLET_STATE_SCHED, 1710 &engine->sched_engine->tasklet.state)), 1711 enableddisabled(!atomic_read(&engine->sched_engine->tasklet.count)), 1712 repr_timer(&engine->execlists.preempt), 1713 repr_timer(&engine->execlists.timer)); 1714 1715 read = execlists->csb_head; 1716 write = READ_ONCE(*execlists->csb_write); 1717 1718 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n", 1719 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO), 1720 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI), 1721 read, write, num_entries); 1722 1723 if (read >= num_entries) 1724 read = 0; 1725 if (write >= num_entries) 1726 write = 0; 1727 if (read > write) 1728 write += num_entries; 1729 while (read < write) { 1730 idx = ++read % num_entries; 1731 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", 1732 idx, hws[idx * 2], hws[idx * 2 + 1]); 1733 } 1734 1735 i915_sched_engine_active_lock_bh(engine->sched_engine); 1736 rcu_read_lock(); 1737 for (port = execlists->active; (rq = *port); port++) { 1738 char hdr[160]; 1739 int len; 1740 1741 len = scnprintf(hdr, sizeof(hdr), 1742 "\t\tActive[%d]: ccid:%08x%s%s, ", 1743 (int)(port - execlists->active), 1744 rq->context->lrc.ccid, 1745 intel_context_is_closed(rq->context) ? "!" : "", 1746 intel_context_is_banned(rq->context) ? "*" : ""); 1747 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1748 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1749 i915_request_show(m, rq, hdr, 0); 1750 } 1751 for (port = execlists->pending; (rq = *port); port++) { 1752 char hdr[160]; 1753 int len; 1754 1755 len = scnprintf(hdr, sizeof(hdr), 1756 "\t\tPending[%d]: ccid:%08x%s%s, ", 1757 (int)(port - execlists->pending), 1758 rq->context->lrc.ccid, 1759 intel_context_is_closed(rq->context) ? "!" : "", 1760 intel_context_is_banned(rq->context) ? "*" : ""); 1761 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1762 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1763 i915_request_show(m, rq, hdr, 0); 1764 } 1765 rcu_read_unlock(); 1766 i915_sched_engine_active_unlock_bh(engine->sched_engine); 1767 } else if (GRAPHICS_VER(dev_priv) > 6) { 1768 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n", 1769 ENGINE_READ(engine, RING_PP_DIR_BASE)); 1770 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", 1771 ENGINE_READ(engine, RING_PP_DIR_BASE_READ)); 1772 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", 1773 ENGINE_READ(engine, RING_PP_DIR_DCLV)); 1774 } 1775 } 1776 1777 static void print_request_ring(struct drm_printer *m, struct i915_request *rq) 1778 { 1779 struct i915_vma_resource *vma_res = rq->batch_res; 1780 void *ring; 1781 int size; 1782 1783 drm_printf(m, 1784 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n", 1785 rq->head, rq->postfix, rq->tail, 1786 vma_res ? upper_32_bits(vma_res->start) : ~0u, 1787 vma_res ? lower_32_bits(vma_res->start) : ~0u); 1788 1789 size = rq->tail - rq->head; 1790 if (rq->tail < rq->head) 1791 size += rq->ring->size; 1792 1793 ring = kmalloc(size, GFP_ATOMIC); 1794 if (ring) { 1795 const void *vaddr = rq->ring->vaddr; 1796 unsigned int head = rq->head; 1797 unsigned int len = 0; 1798 1799 if (rq->tail < head) { 1800 len = rq->ring->size - head; 1801 memcpy(ring, vaddr + head, len); 1802 head = 0; 1803 } 1804 memcpy(ring + len, vaddr + head, size - len); 1805 1806 hexdump(m, ring, size); 1807 kfree(ring); 1808 } 1809 } 1810 1811 static unsigned long list_count(struct list_head *list) 1812 { 1813 struct list_head *pos; 1814 unsigned long count = 0; 1815 1816 list_for_each(pos, list) 1817 count++; 1818 1819 return count; 1820 } 1821 1822 static unsigned long read_ul(void *p, size_t x) 1823 { 1824 return *(unsigned long *)(p + x); 1825 } 1826 1827 static void print_properties(struct intel_engine_cs *engine, 1828 struct drm_printer *m) 1829 { 1830 static const struct pmap { 1831 size_t offset; 1832 const char *name; 1833 } props[] = { 1834 #define P(x) { \ 1835 .offset = offsetof(typeof(engine->props), x), \ 1836 .name = #x \ 1837 } 1838 P(heartbeat_interval_ms), 1839 P(max_busywait_duration_ns), 1840 P(preempt_timeout_ms), 1841 P(stop_timeout_ms), 1842 P(timeslice_duration_ms), 1843 1844 {}, 1845 #undef P 1846 }; 1847 const struct pmap *p; 1848 1849 drm_printf(m, "\tProperties:\n"); 1850 for (p = props; p->name; p++) 1851 drm_printf(m, "\t\t%s: %lu [default %lu]\n", 1852 p->name, 1853 read_ul(&engine->props, p->offset), 1854 read_ul(&engine->defaults, p->offset)); 1855 } 1856 1857 static void engine_dump_request(struct i915_request *rq, struct drm_printer *m, const char *msg) 1858 { 1859 struct intel_timeline *tl = get_timeline(rq); 1860 1861 i915_request_show(m, rq, msg, 0); 1862 1863 drm_printf(m, "\t\tring->start: 0x%08x\n", 1864 i915_ggtt_offset(rq->ring->vma)); 1865 drm_printf(m, "\t\tring->head: 0x%08x\n", 1866 rq->ring->head); 1867 drm_printf(m, "\t\tring->tail: 0x%08x\n", 1868 rq->ring->tail); 1869 drm_printf(m, "\t\tring->emit: 0x%08x\n", 1870 rq->ring->emit); 1871 drm_printf(m, "\t\tring->space: 0x%08x\n", 1872 rq->ring->space); 1873 1874 if (tl) { 1875 drm_printf(m, "\t\tring->hwsp: 0x%08x\n", 1876 tl->hwsp_offset); 1877 intel_timeline_put(tl); 1878 } 1879 1880 print_request_ring(m, rq); 1881 1882 if (rq->context->lrc_reg_state) { 1883 drm_printf(m, "Logical Ring Context:\n"); 1884 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE); 1885 } 1886 } 1887 1888 void intel_engine_dump_active_requests(struct list_head *requests, 1889 struct i915_request *hung_rq, 1890 struct drm_printer *m) 1891 { 1892 struct i915_request *rq; 1893 const char *msg; 1894 enum i915_request_state state; 1895 1896 list_for_each_entry(rq, requests, sched.link) { 1897 if (rq == hung_rq) 1898 continue; 1899 1900 state = i915_test_request_state(rq); 1901 if (state < I915_REQUEST_QUEUED) 1902 continue; 1903 1904 if (state == I915_REQUEST_ACTIVE) 1905 msg = "\t\tactive on engine"; 1906 else 1907 msg = "\t\tactive in queue"; 1908 1909 engine_dump_request(rq, m, msg); 1910 } 1911 } 1912 1913 static void engine_dump_active_requests(struct intel_engine_cs *engine, struct drm_printer *m) 1914 { 1915 struct i915_request *hung_rq = NULL; 1916 struct intel_context *ce; 1917 bool guc; 1918 1919 /* 1920 * No need for an engine->irq_seqno_barrier() before the seqno reads. 1921 * The GPU is still running so requests are still executing and any 1922 * hardware reads will be out of date by the time they are reported. 1923 * But the intention here is just to report an instantaneous snapshot 1924 * so that's fine. 1925 */ 1926 lockdep_assert_held(&engine->sched_engine->lock); 1927 1928 drm_printf(m, "\tRequests:\n"); 1929 1930 guc = intel_uc_uses_guc_submission(&engine->gt->uc); 1931 if (guc) { 1932 ce = intel_engine_get_hung_context(engine); 1933 if (ce) 1934 hung_rq = intel_context_find_active_request(ce); 1935 } else { 1936 hung_rq = intel_engine_execlist_find_hung_request(engine); 1937 } 1938 1939 if (hung_rq) 1940 engine_dump_request(hung_rq, m, "\t\thung"); 1941 1942 if (guc) 1943 intel_guc_dump_active_requests(engine, hung_rq, m); 1944 else 1945 intel_engine_dump_active_requests(&engine->sched_engine->requests, 1946 hung_rq, m); 1947 } 1948 1949 void intel_engine_dump(struct intel_engine_cs *engine, 1950 struct drm_printer *m, 1951 const char *header, ...) 1952 { 1953 struct i915_gpu_error * const error = &engine->i915->gpu_error; 1954 struct i915_request *rq; 1955 intel_wakeref_t wakeref; 1956 unsigned long flags; 1957 ktime_t dummy; 1958 1959 if (header) { 1960 va_list ap; 1961 1962 va_start(ap, header); 1963 drm_vprintf(m, header, &ap); 1964 va_end(ap); 1965 } 1966 1967 if (intel_gt_is_wedged(engine->gt)) 1968 drm_printf(m, "*** WEDGED ***\n"); 1969 1970 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count)); 1971 drm_printf(m, "\tBarriers?: %s\n", 1972 yesno(!llist_empty(&engine->barrier_tasks))); 1973 drm_printf(m, "\tLatency: %luus\n", 1974 ewma__engine_latency_read(&engine->latency)); 1975 if (intel_engine_supports_stats(engine)) 1976 drm_printf(m, "\tRuntime: %llums\n", 1977 ktime_to_ms(intel_engine_get_busy_time(engine, 1978 &dummy))); 1979 drm_printf(m, "\tForcewake: %x domains, %d active\n", 1980 engine->fw_domain, READ_ONCE(engine->fw_active)); 1981 1982 rcu_read_lock(); 1983 rq = READ_ONCE(engine->heartbeat.systole); 1984 if (rq) 1985 drm_printf(m, "\tHeartbeat: %d ms ago\n", 1986 jiffies_to_msecs(jiffies - rq->emitted_jiffies)); 1987 rcu_read_unlock(); 1988 drm_printf(m, "\tReset count: %d (global %d)\n", 1989 i915_reset_engine_count(error, engine), 1990 i915_reset_count(error)); 1991 print_properties(engine, m); 1992 1993 spin_lock_irqsave(&engine->sched_engine->lock, flags); 1994 engine_dump_active_requests(engine, m); 1995 1996 drm_printf(m, "\tOn hold?: %lu\n", 1997 list_count(&engine->sched_engine->hold)); 1998 spin_unlock_irqrestore(&engine->sched_engine->lock, flags); 1999 2000 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base); 2001 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm); 2002 if (wakeref) { 2003 intel_engine_print_registers(engine, m); 2004 intel_runtime_pm_put(engine->uncore->rpm, wakeref); 2005 } else { 2006 drm_printf(m, "\tDevice is asleep; skipping register dump\n"); 2007 } 2008 2009 intel_execlists_show_requests(engine, m, i915_request_show, 8); 2010 2011 drm_printf(m, "HWSP:\n"); 2012 hexdump(m, engine->status_page.addr, PAGE_SIZE); 2013 2014 drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine))); 2015 2016 intel_engine_print_breadcrumbs(engine, m); 2017 } 2018 2019 /** 2020 * intel_engine_get_busy_time() - Return current accumulated engine busyness 2021 * @engine: engine to report on 2022 * @now: monotonic timestamp of sampling 2023 * 2024 * Returns accumulated time @engine was busy since engine stats were enabled. 2025 */ 2026 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) 2027 { 2028 return engine->busyness(engine, now); 2029 } 2030 2031 struct intel_context * 2032 intel_engine_create_virtual(struct intel_engine_cs **siblings, 2033 unsigned int count, unsigned long flags) 2034 { 2035 if (count == 0) 2036 return ERR_PTR(-EINVAL); 2037 2038 if (count == 1 && !(flags & FORCE_VIRTUAL)) 2039 return intel_context_create(siblings[0]); 2040 2041 GEM_BUG_ON(!siblings[0]->cops->create_virtual); 2042 return siblings[0]->cops->create_virtual(siblings, count, flags); 2043 } 2044 2045 struct i915_request * 2046 intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine) 2047 { 2048 struct i915_request *request, *active = NULL; 2049 2050 /* 2051 * This search does not work in GuC submission mode. However, the GuC 2052 * will report the hanging context directly to the driver itself. So 2053 * the driver should never get here when in GuC mode. 2054 */ 2055 GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc)); 2056 2057 /* 2058 * We are called by the error capture, reset and to dump engine 2059 * state at random points in time. In particular, note that neither is 2060 * crucially ordered with an interrupt. After a hang, the GPU is dead 2061 * and we assume that no more writes can happen (we waited long enough 2062 * for all writes that were in transaction to be flushed) - adding an 2063 * extra delay for a recent interrupt is pointless. Hence, we do 2064 * not need an engine->irq_seqno_barrier() before the seqno reads. 2065 * At all other times, we must assume the GPU is still running, but 2066 * we only care about the snapshot of this moment. 2067 */ 2068 lockdep_assert_held(&engine->sched_engine->lock); 2069 2070 rcu_read_lock(); 2071 request = execlists_active(&engine->execlists); 2072 if (request) { 2073 struct intel_timeline *tl = request->context->timeline; 2074 2075 list_for_each_entry_from_reverse(request, &tl->requests, link) { 2076 if (__i915_request_is_complete(request)) 2077 break; 2078 2079 active = request; 2080 } 2081 } 2082 rcu_read_unlock(); 2083 if (active) 2084 return active; 2085 2086 list_for_each_entry(request, &engine->sched_engine->requests, 2087 sched.link) { 2088 if (i915_test_request_state(request) != I915_REQUEST_ACTIVE) 2089 continue; 2090 2091 active = request; 2092 break; 2093 } 2094 2095 return active; 2096 } 2097 2098 void xehp_enable_ccs_engines(struct intel_engine_cs *engine) 2099 { 2100 /* 2101 * If there are any non-fused-off CCS engines, we need to enable CCS 2102 * support in the RCU_MODE register. This only needs to be done once, 2103 * so for simplicity we'll take care of this in the RCS engine's 2104 * resume handler; since the RCS and all CCS engines belong to the 2105 * same reset domain and are reset together, this will also take care 2106 * of re-applying the setting after i915-triggered resets. 2107 */ 2108 if (!CCS_MASK(engine->gt)) 2109 return; 2110 2111 intel_uncore_write(engine->uncore, GEN12_RCU_MODE, 2112 _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE)); 2113 } 2114 2115 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2116 #include "mock_engine.c" 2117 #include "selftest_engine.c" 2118 #include "selftest_engine_cs.c" 2119 #endif 2120