1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2016 Intel Corporation 4 */ 5 6 #include <drm/drm_print.h> 7 8 #include "gem/i915_gem_context.h" 9 10 #include "i915_drv.h" 11 12 #include "intel_breadcrumbs.h" 13 #include "intel_context.h" 14 #include "intel_engine.h" 15 #include "intel_engine_pm.h" 16 #include "intel_engine_user.h" 17 #include "intel_execlists_submission.h" 18 #include "intel_gt.h" 19 #include "intel_gt_requests.h" 20 #include "intel_gt_pm.h" 21 #include "intel_lrc_reg.h" 22 #include "intel_reset.h" 23 #include "intel_ring.h" 24 #include "uc/intel_guc_submission.h" 25 26 /* Haswell does have the CXT_SIZE register however it does not appear to be 27 * valid. Now, docs explain in dwords what is in the context object. The full 28 * size is 70720 bytes, however, the power context and execlist context will 29 * never be saved (power context is stored elsewhere, and execlists don't work 30 * on HSW) - so the final size, including the extra state required for the 31 * Resource Streamer, is 66944 bytes, which rounds to 17 pages. 32 */ 33 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 34 35 #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 36 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) 37 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 38 #define GEN10_LR_CONTEXT_RENDER_SIZE (18 * PAGE_SIZE) 39 #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE) 40 41 #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE) 42 43 #define MAX_MMIO_BASES 3 44 struct engine_info { 45 unsigned int hw_id; 46 u8 class; 47 u8 instance; 48 /* mmio bases table *must* be sorted in reverse graphics_ver order */ 49 struct engine_mmio_base { 50 u32 graphics_ver : 8; 51 u32 base : 24; 52 } mmio_bases[MAX_MMIO_BASES]; 53 }; 54 55 static const struct engine_info intel_engines[] = { 56 [RCS0] = { 57 .hw_id = RCS0_HW, 58 .class = RENDER_CLASS, 59 .instance = 0, 60 .mmio_bases = { 61 { .graphics_ver = 1, .base = RENDER_RING_BASE } 62 }, 63 }, 64 [BCS0] = { 65 .hw_id = BCS0_HW, 66 .class = COPY_ENGINE_CLASS, 67 .instance = 0, 68 .mmio_bases = { 69 { .graphics_ver = 6, .base = BLT_RING_BASE } 70 }, 71 }, 72 [VCS0] = { 73 .hw_id = VCS0_HW, 74 .class = VIDEO_DECODE_CLASS, 75 .instance = 0, 76 .mmio_bases = { 77 { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE }, 78 { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE }, 79 { .graphics_ver = 4, .base = BSD_RING_BASE } 80 }, 81 }, 82 [VCS1] = { 83 .hw_id = VCS1_HW, 84 .class = VIDEO_DECODE_CLASS, 85 .instance = 1, 86 .mmio_bases = { 87 { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE }, 88 { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE } 89 }, 90 }, 91 [VCS2] = { 92 .hw_id = VCS2_HW, 93 .class = VIDEO_DECODE_CLASS, 94 .instance = 2, 95 .mmio_bases = { 96 { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE } 97 }, 98 }, 99 [VCS3] = { 100 .hw_id = VCS3_HW, 101 .class = VIDEO_DECODE_CLASS, 102 .instance = 3, 103 .mmio_bases = { 104 { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE } 105 }, 106 }, 107 [VECS0] = { 108 .hw_id = VECS0_HW, 109 .class = VIDEO_ENHANCEMENT_CLASS, 110 .instance = 0, 111 .mmio_bases = { 112 { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE }, 113 { .graphics_ver = 7, .base = VEBOX_RING_BASE } 114 }, 115 }, 116 [VECS1] = { 117 .hw_id = VECS1_HW, 118 .class = VIDEO_ENHANCEMENT_CLASS, 119 .instance = 1, 120 .mmio_bases = { 121 { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE } 122 }, 123 }, 124 }; 125 126 /** 127 * intel_engine_context_size() - return the size of the context for an engine 128 * @gt: the gt 129 * @class: engine class 130 * 131 * Each engine class may require a different amount of space for a context 132 * image. 133 * 134 * Return: size (in bytes) of an engine class specific context image 135 * 136 * Note: this size includes the HWSP, which is part of the context image 137 * in LRC mode, but does not include the "shared data page" used with 138 * GuC submission. The caller should account for this if using the GuC. 139 */ 140 u32 intel_engine_context_size(struct intel_gt *gt, u8 class) 141 { 142 struct intel_uncore *uncore = gt->uncore; 143 u32 cxt_size; 144 145 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE); 146 147 switch (class) { 148 case RENDER_CLASS: 149 switch (GRAPHICS_VER(gt->i915)) { 150 default: 151 MISSING_CASE(GRAPHICS_VER(gt->i915)); 152 return DEFAULT_LR_CONTEXT_RENDER_SIZE; 153 case 12: 154 case 11: 155 return GEN11_LR_CONTEXT_RENDER_SIZE; 156 case 10: 157 return GEN10_LR_CONTEXT_RENDER_SIZE; 158 case 9: 159 return GEN9_LR_CONTEXT_RENDER_SIZE; 160 case 8: 161 return GEN8_LR_CONTEXT_RENDER_SIZE; 162 case 7: 163 if (IS_HASWELL(gt->i915)) 164 return HSW_CXT_TOTAL_SIZE; 165 166 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE); 167 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64, 168 PAGE_SIZE); 169 case 6: 170 cxt_size = intel_uncore_read(uncore, CXT_SIZE); 171 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64, 172 PAGE_SIZE); 173 case 5: 174 case 4: 175 /* 176 * There is a discrepancy here between the size reported 177 * by the register and the size of the context layout 178 * in the docs. Both are described as authorative! 179 * 180 * The discrepancy is on the order of a few cachelines, 181 * but the total is under one page (4k), which is our 182 * minimum allocation anyway so it should all come 183 * out in the wash. 184 */ 185 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1; 186 drm_dbg(>->i915->drm, 187 "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n", 188 GRAPHICS_VER(gt->i915), cxt_size * 64, 189 cxt_size - 1); 190 return round_up(cxt_size * 64, PAGE_SIZE); 191 case 3: 192 case 2: 193 /* For the special day when i810 gets merged. */ 194 case 1: 195 return 0; 196 } 197 break; 198 default: 199 MISSING_CASE(class); 200 fallthrough; 201 case VIDEO_DECODE_CLASS: 202 case VIDEO_ENHANCEMENT_CLASS: 203 case COPY_ENGINE_CLASS: 204 if (GRAPHICS_VER(gt->i915) < 8) 205 return 0; 206 return GEN8_LR_CONTEXT_OTHER_SIZE; 207 } 208 } 209 210 static u32 __engine_mmio_base(struct drm_i915_private *i915, 211 const struct engine_mmio_base *bases) 212 { 213 int i; 214 215 for (i = 0; i < MAX_MMIO_BASES; i++) 216 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver) 217 break; 218 219 GEM_BUG_ON(i == MAX_MMIO_BASES); 220 GEM_BUG_ON(!bases[i].base); 221 222 return bases[i].base; 223 } 224 225 static void __sprint_engine_name(struct intel_engine_cs *engine) 226 { 227 /* 228 * Before we know what the uABI name for this engine will be, 229 * we still would like to keep track of this engine in the debug logs. 230 * We throw in a ' here as a reminder that this isn't its final name. 231 */ 232 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u", 233 intel_engine_class_repr(engine->class), 234 engine->instance) >= sizeof(engine->name)); 235 } 236 237 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask) 238 { 239 /* 240 * Though they added more rings on g4x/ilk, they did not add 241 * per-engine HWSTAM until gen6. 242 */ 243 if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS) 244 return; 245 246 if (INTEL_GEN(engine->i915) >= 3) 247 ENGINE_WRITE(engine, RING_HWSTAM, mask); 248 else 249 ENGINE_WRITE16(engine, RING_HWSTAM, mask); 250 } 251 252 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine) 253 { 254 /* Mask off all writes into the unknown HWSP */ 255 intel_engine_set_hwsp_writemask(engine, ~0u); 256 } 257 258 static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir) 259 { 260 GEM_DEBUG_WARN_ON(iir); 261 } 262 263 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) 264 { 265 const struct engine_info *info = &intel_engines[id]; 266 struct drm_i915_private *i915 = gt->i915; 267 struct intel_engine_cs *engine; 268 269 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH)); 270 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH)); 271 272 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine))) 273 return -EINVAL; 274 275 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS)) 276 return -EINVAL; 277 278 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE)) 279 return -EINVAL; 280 281 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance])) 282 return -EINVAL; 283 284 engine = kzalloc(sizeof(*engine), GFP_KERNEL); 285 if (!engine) 286 return -ENOMEM; 287 288 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES); 289 290 engine->id = id; 291 engine->legacy_idx = INVALID_ENGINE; 292 engine->mask = BIT(id); 293 engine->i915 = i915; 294 engine->gt = gt; 295 engine->uncore = gt->uncore; 296 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases); 297 engine->hw_id = info->hw_id; 298 engine->guc_id = MAKE_GUC_ID(info->class, info->instance); 299 300 engine->irq_handler = nop_irq_handler; 301 302 engine->class = info->class; 303 engine->instance = info->instance; 304 __sprint_engine_name(engine); 305 306 engine->props.heartbeat_interval_ms = 307 CONFIG_DRM_I915_HEARTBEAT_INTERVAL; 308 engine->props.max_busywait_duration_ns = 309 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT; 310 engine->props.preempt_timeout_ms = 311 CONFIG_DRM_I915_PREEMPT_TIMEOUT; 312 engine->props.stop_timeout_ms = 313 CONFIG_DRM_I915_STOP_TIMEOUT; 314 engine->props.timeslice_duration_ms = 315 CONFIG_DRM_I915_TIMESLICE_DURATION; 316 317 /* Override to uninterruptible for OpenCL workloads. */ 318 if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS) 319 engine->props.preempt_timeout_ms = 0; 320 321 engine->defaults = engine->props; /* never to change again */ 322 323 engine->context_size = intel_engine_context_size(gt, engine->class); 324 if (WARN_ON(engine->context_size > BIT(20))) 325 engine->context_size = 0; 326 if (engine->context_size) 327 DRIVER_CAPS(i915)->has_logical_contexts = true; 328 329 /* Nothing to do here, execute in order of dependencies */ 330 engine->schedule = NULL; 331 332 ewma__engine_latency_init(&engine->latency); 333 seqcount_init(&engine->stats.lock); 334 335 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); 336 337 /* Scrub mmio state on takeover */ 338 intel_engine_sanitize_mmio(engine); 339 340 gt->engine_class[info->class][info->instance] = engine; 341 gt->engine[id] = engine; 342 343 return 0; 344 } 345 346 static void __setup_engine_capabilities(struct intel_engine_cs *engine) 347 { 348 struct drm_i915_private *i915 = engine->i915; 349 350 if (engine->class == VIDEO_DECODE_CLASS) { 351 /* 352 * HEVC support is present on first engine instance 353 * before Gen11 and on all instances afterwards. 354 */ 355 if (INTEL_GEN(i915) >= 11 || 356 (INTEL_GEN(i915) >= 9 && engine->instance == 0)) 357 engine->uabi_capabilities |= 358 I915_VIDEO_CLASS_CAPABILITY_HEVC; 359 360 /* 361 * SFC block is present only on even logical engine 362 * instances. 363 */ 364 if ((INTEL_GEN(i915) >= 11 && 365 (engine->gt->info.vdbox_sfc_access & 366 BIT(engine->instance))) || 367 (INTEL_GEN(i915) >= 9 && engine->instance == 0)) 368 engine->uabi_capabilities |= 369 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 370 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) { 371 if (INTEL_GEN(i915) >= 9) 372 engine->uabi_capabilities |= 373 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 374 } 375 } 376 377 static void intel_setup_engine_capabilities(struct intel_gt *gt) 378 { 379 struct intel_engine_cs *engine; 380 enum intel_engine_id id; 381 382 for_each_engine(engine, gt, id) 383 __setup_engine_capabilities(engine); 384 } 385 386 /** 387 * intel_engines_release() - free the resources allocated for Command Streamers 388 * @gt: pointer to struct intel_gt 389 */ 390 void intel_engines_release(struct intel_gt *gt) 391 { 392 struct intel_engine_cs *engine; 393 enum intel_engine_id id; 394 395 /* 396 * Before we release the resources held by engine, we must be certain 397 * that the HW is no longer accessing them -- having the GPU scribble 398 * to or read from a page being used for something else causes no end 399 * of fun. 400 * 401 * The GPU should be reset by this point, but assume the worst just 402 * in case we aborted before completely initialising the engines. 403 */ 404 GEM_BUG_ON(intel_gt_pm_is_awake(gt)); 405 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) 406 __intel_gt_reset(gt, ALL_ENGINES); 407 408 /* Decouple the backend; but keep the layout for late GPU resets */ 409 for_each_engine(engine, gt, id) { 410 if (!engine->release) 411 continue; 412 413 intel_wakeref_wait_for_idle(&engine->wakeref); 414 GEM_BUG_ON(intel_engine_pm_is_awake(engine)); 415 416 engine->release(engine); 417 engine->release = NULL; 418 419 memset(&engine->reset, 0, sizeof(engine->reset)); 420 } 421 } 422 423 void intel_engine_free_request_pool(struct intel_engine_cs *engine) 424 { 425 if (!engine->request_pool) 426 return; 427 428 kmem_cache_free(i915_request_slab_cache(), engine->request_pool); 429 } 430 431 void intel_engines_free(struct intel_gt *gt) 432 { 433 struct intel_engine_cs *engine; 434 enum intel_engine_id id; 435 436 /* Free the requests! dma-resv keeps fences around for an eternity */ 437 rcu_barrier(); 438 439 for_each_engine(engine, gt, id) { 440 intel_engine_free_request_pool(engine); 441 kfree(engine); 442 gt->engine[id] = NULL; 443 } 444 } 445 446 /* 447 * Determine which engines are fused off in our particular hardware. 448 * Note that we have a catch-22 situation where we need to be able to access 449 * the blitter forcewake domain to read the engine fuses, but at the same time 450 * we need to know which engines are available on the system to know which 451 * forcewake domains are present. We solve this by intializing the forcewake 452 * domains based on the full engine mask in the platform capabilities before 453 * calling this function and pruning the domains for fused-off engines 454 * afterwards. 455 */ 456 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) 457 { 458 struct drm_i915_private *i915 = gt->i915; 459 struct intel_gt_info *info = >->info; 460 struct intel_uncore *uncore = gt->uncore; 461 unsigned int logical_vdbox = 0; 462 unsigned int i; 463 u32 media_fuse; 464 u16 vdbox_mask; 465 u16 vebox_mask; 466 467 info->engine_mask = INTEL_INFO(i915)->platform_engine_mask; 468 469 if (INTEL_GEN(i915) < 11) 470 return info->engine_mask; 471 472 media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); 473 474 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; 475 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> 476 GEN11_GT_VEBOX_DISABLE_SHIFT; 477 478 for (i = 0; i < I915_MAX_VCS; i++) { 479 if (!HAS_ENGINE(gt, _VCS(i))) { 480 vdbox_mask &= ~BIT(i); 481 continue; 482 } 483 484 if (!(BIT(i) & vdbox_mask)) { 485 info->engine_mask &= ~BIT(_VCS(i)); 486 drm_dbg(&i915->drm, "vcs%u fused off\n", i); 487 continue; 488 } 489 490 /* 491 * In Gen11, only even numbered logical VDBOXes are 492 * hooked up to an SFC (Scaler & Format Converter) unit. 493 * In TGL each VDBOX has access to an SFC. 494 */ 495 if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0) 496 gt->info.vdbox_sfc_access |= BIT(i); 497 } 498 drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n", 499 vdbox_mask, VDBOX_MASK(gt)); 500 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt)); 501 502 for (i = 0; i < I915_MAX_VECS; i++) { 503 if (!HAS_ENGINE(gt, _VECS(i))) { 504 vebox_mask &= ~BIT(i); 505 continue; 506 } 507 508 if (!(BIT(i) & vebox_mask)) { 509 info->engine_mask &= ~BIT(_VECS(i)); 510 drm_dbg(&i915->drm, "vecs%u fused off\n", i); 511 } 512 } 513 drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n", 514 vebox_mask, VEBOX_MASK(gt)); 515 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); 516 517 return info->engine_mask; 518 } 519 520 /** 521 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers 522 * @gt: pointer to struct intel_gt 523 * 524 * Return: non-zero if the initialization failed. 525 */ 526 int intel_engines_init_mmio(struct intel_gt *gt) 527 { 528 struct drm_i915_private *i915 = gt->i915; 529 const unsigned int engine_mask = init_engine_mask(gt); 530 unsigned int mask = 0; 531 unsigned int i; 532 int err; 533 534 drm_WARN_ON(&i915->drm, engine_mask == 0); 535 drm_WARN_ON(&i915->drm, engine_mask & 536 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES)); 537 538 if (i915_inject_probe_failure(i915)) 539 return -ENODEV; 540 541 for (i = 0; i < ARRAY_SIZE(intel_engines); i++) { 542 if (!HAS_ENGINE(gt, i)) 543 continue; 544 545 err = intel_engine_setup(gt, i); 546 if (err) 547 goto cleanup; 548 549 mask |= BIT(i); 550 } 551 552 /* 553 * Catch failures to update intel_engines table when the new engines 554 * are added to the driver by a warning and disabling the forgotten 555 * engines. 556 */ 557 if (drm_WARN_ON(&i915->drm, mask != engine_mask)) 558 gt->info.engine_mask = mask; 559 560 gt->info.num_engines = hweight32(mask); 561 562 intel_gt_check_and_clear_faults(gt); 563 564 intel_setup_engine_capabilities(gt); 565 566 intel_uncore_prune_engine_fw_domains(gt->uncore, gt); 567 568 return 0; 569 570 cleanup: 571 intel_engines_free(gt); 572 return err; 573 } 574 575 void intel_engine_init_execlists(struct intel_engine_cs *engine) 576 { 577 struct intel_engine_execlists * const execlists = &engine->execlists; 578 579 execlists->port_mask = 1; 580 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists))); 581 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS); 582 583 memset(execlists->pending, 0, sizeof(execlists->pending)); 584 execlists->active = 585 memset(execlists->inflight, 0, sizeof(execlists->inflight)); 586 587 execlists->queue_priority_hint = INT_MIN; 588 execlists->queue = RB_ROOT_CACHED; 589 } 590 591 static void cleanup_status_page(struct intel_engine_cs *engine) 592 { 593 struct i915_vma *vma; 594 595 /* Prevent writes into HWSP after returning the page to the system */ 596 intel_engine_set_hwsp_writemask(engine, ~0u); 597 598 vma = fetch_and_zero(&engine->status_page.vma); 599 if (!vma) 600 return; 601 602 if (!HWS_NEEDS_PHYSICAL(engine->i915)) 603 i915_vma_unpin(vma); 604 605 i915_gem_object_unpin_map(vma->obj); 606 i915_gem_object_put(vma->obj); 607 } 608 609 static int pin_ggtt_status_page(struct intel_engine_cs *engine, 610 struct i915_gem_ww_ctx *ww, 611 struct i915_vma *vma) 612 { 613 unsigned int flags; 614 615 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) 616 /* 617 * On g33, we cannot place HWS above 256MiB, so 618 * restrict its pinning to the low mappable arena. 619 * Though this restriction is not documented for 620 * gen4, gen5, or byt, they also behave similarly 621 * and hang if the HWS is placed at the top of the 622 * GTT. To generalise, it appears that all !llc 623 * platforms have issues with us placing the HWS 624 * above the mappable region (even though we never 625 * actually map it). 626 */ 627 flags = PIN_MAPPABLE; 628 else 629 flags = PIN_HIGH; 630 631 return i915_ggtt_pin(vma, ww, 0, flags); 632 } 633 634 static int init_status_page(struct intel_engine_cs *engine) 635 { 636 struct drm_i915_gem_object *obj; 637 struct i915_gem_ww_ctx ww; 638 struct i915_vma *vma; 639 void *vaddr; 640 int ret; 641 642 INIT_LIST_HEAD(&engine->status_page.timelines); 643 644 /* 645 * Though the HWS register does support 36bit addresses, historically 646 * we have had hangs and corruption reported due to wild writes if 647 * the HWS is placed above 4G. We only allow objects to be allocated 648 * in GFP_DMA32 for i965, and no earlier physical address users had 649 * access to more than 4G. 650 */ 651 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); 652 if (IS_ERR(obj)) { 653 drm_err(&engine->i915->drm, 654 "Failed to allocate status page\n"); 655 return PTR_ERR(obj); 656 } 657 658 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 659 660 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); 661 if (IS_ERR(vma)) { 662 ret = PTR_ERR(vma); 663 goto err_put; 664 } 665 666 i915_gem_ww_ctx_init(&ww, true); 667 retry: 668 ret = i915_gem_object_lock(obj, &ww); 669 if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915)) 670 ret = pin_ggtt_status_page(engine, &ww, vma); 671 if (ret) 672 goto err; 673 674 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); 675 if (IS_ERR(vaddr)) { 676 ret = PTR_ERR(vaddr); 677 goto err_unpin; 678 } 679 680 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE); 681 engine->status_page.vma = vma; 682 683 err_unpin: 684 if (ret) 685 i915_vma_unpin(vma); 686 err: 687 if (ret == -EDEADLK) { 688 ret = i915_gem_ww_ctx_backoff(&ww); 689 if (!ret) 690 goto retry; 691 } 692 i915_gem_ww_ctx_fini(&ww); 693 err_put: 694 if (ret) 695 i915_gem_object_put(obj); 696 return ret; 697 } 698 699 static int engine_setup_common(struct intel_engine_cs *engine) 700 { 701 int err; 702 703 init_llist_head(&engine->barrier_tasks); 704 705 err = init_status_page(engine); 706 if (err) 707 return err; 708 709 engine->breadcrumbs = intel_breadcrumbs_create(engine); 710 if (!engine->breadcrumbs) { 711 err = -ENOMEM; 712 goto err_status; 713 } 714 715 err = intel_engine_init_cmd_parser(engine); 716 if (err) 717 goto err_cmd_parser; 718 719 intel_engine_init_active(engine, ENGINE_PHYSICAL); 720 intel_engine_init_execlists(engine); 721 intel_engine_init__pm(engine); 722 intel_engine_init_retire(engine); 723 724 /* Use the whole device by default */ 725 engine->sseu = 726 intel_sseu_from_device_info(&engine->gt->info.sseu); 727 728 intel_engine_init_workarounds(engine); 729 intel_engine_init_whitelist(engine); 730 intel_engine_init_ctx_wa(engine); 731 732 if (INTEL_GEN(engine->i915) >= 12) 733 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO; 734 735 return 0; 736 737 err_cmd_parser: 738 intel_breadcrumbs_free(engine->breadcrumbs); 739 err_status: 740 cleanup_status_page(engine); 741 return err; 742 } 743 744 struct measure_breadcrumb { 745 struct i915_request rq; 746 struct intel_ring ring; 747 u32 cs[2048]; 748 }; 749 750 static int measure_breadcrumb_dw(struct intel_context *ce) 751 { 752 struct intel_engine_cs *engine = ce->engine; 753 struct measure_breadcrumb *frame; 754 int dw; 755 756 GEM_BUG_ON(!engine->gt->scratch); 757 758 frame = kzalloc(sizeof(*frame), GFP_KERNEL); 759 if (!frame) 760 return -ENOMEM; 761 762 frame->rq.engine = engine; 763 frame->rq.context = ce; 764 rcu_assign_pointer(frame->rq.timeline, ce->timeline); 765 frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno; 766 767 frame->ring.vaddr = frame->cs; 768 frame->ring.size = sizeof(frame->cs); 769 frame->ring.wrap = 770 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size); 771 frame->ring.effective_size = frame->ring.size; 772 intel_ring_update_space(&frame->ring); 773 frame->rq.ring = &frame->ring; 774 775 mutex_lock(&ce->timeline->mutex); 776 spin_lock_irq(&engine->active.lock); 777 778 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs; 779 780 spin_unlock_irq(&engine->active.lock); 781 mutex_unlock(&ce->timeline->mutex); 782 783 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */ 784 785 kfree(frame); 786 return dw; 787 } 788 789 void 790 intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass) 791 { 792 INIT_LIST_HEAD(&engine->active.requests); 793 INIT_LIST_HEAD(&engine->active.hold); 794 795 spin_lock_init(&engine->active.lock); 796 lockdep_set_subclass(&engine->active.lock, subclass); 797 798 /* 799 * Due to an interesting quirk in lockdep's internal debug tracking, 800 * after setting a subclass we must ensure the lock is used. Otherwise, 801 * nr_unused_locks is incremented once too often. 802 */ 803 #ifdef CONFIG_DEBUG_LOCK_ALLOC 804 local_irq_disable(); 805 lock_map_acquire(&engine->active.lock.dep_map); 806 lock_map_release(&engine->active.lock.dep_map); 807 local_irq_enable(); 808 #endif 809 } 810 811 static struct intel_context * 812 create_pinned_context(struct intel_engine_cs *engine, 813 unsigned int hwsp, 814 struct lock_class_key *key, 815 const char *name) 816 { 817 struct intel_context *ce; 818 int err; 819 820 ce = intel_context_create(engine); 821 if (IS_ERR(ce)) 822 return ce; 823 824 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags); 825 ce->timeline = page_pack_bits(NULL, hwsp); 826 827 err = intel_context_pin(ce); /* perma-pin so it is always available */ 828 if (err) { 829 intel_context_put(ce); 830 return ERR_PTR(err); 831 } 832 833 /* 834 * Give our perma-pinned kernel timelines a separate lockdep class, 835 * so that we can use them from within the normal user timelines 836 * should we need to inject GPU operations during their request 837 * construction. 838 */ 839 lockdep_set_class_and_name(&ce->timeline->mutex, key, name); 840 841 return ce; 842 } 843 844 static void destroy_pinned_context(struct intel_context *ce) 845 { 846 struct intel_engine_cs *engine = ce->engine; 847 struct i915_vma *hwsp = engine->status_page.vma; 848 849 GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp); 850 851 mutex_lock(&hwsp->vm->mutex); 852 list_del(&ce->timeline->engine_link); 853 mutex_unlock(&hwsp->vm->mutex); 854 855 intel_context_unpin(ce); 856 intel_context_put(ce); 857 } 858 859 static struct intel_context * 860 create_kernel_context(struct intel_engine_cs *engine) 861 { 862 static struct lock_class_key kernel; 863 864 return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR, 865 &kernel, "kernel_context"); 866 } 867 868 /** 869 * intel_engines_init_common - initialize cengine state which might require hw access 870 * @engine: Engine to initialize. 871 * 872 * Initializes @engine@ structure members shared between legacy and execlists 873 * submission modes which do require hardware access. 874 * 875 * Typcally done at later stages of submission mode specific engine setup. 876 * 877 * Returns zero on success or an error code on failure. 878 */ 879 static int engine_init_common(struct intel_engine_cs *engine) 880 { 881 struct intel_context *ce; 882 int ret; 883 884 engine->set_default_submission(engine); 885 886 /* 887 * We may need to do things with the shrinker which 888 * require us to immediately switch back to the default 889 * context. This can cause a problem as pinning the 890 * default context also requires GTT space which may not 891 * be available. To avoid this we always pin the default 892 * context. 893 */ 894 ce = create_kernel_context(engine); 895 if (IS_ERR(ce)) 896 return PTR_ERR(ce); 897 898 ret = measure_breadcrumb_dw(ce); 899 if (ret < 0) 900 goto err_context; 901 902 engine->emit_fini_breadcrumb_dw = ret; 903 engine->kernel_context = ce; 904 905 return 0; 906 907 err_context: 908 destroy_pinned_context(ce); 909 return ret; 910 } 911 912 int intel_engines_init(struct intel_gt *gt) 913 { 914 int (*setup)(struct intel_engine_cs *engine); 915 struct intel_engine_cs *engine; 916 enum intel_engine_id id; 917 int err; 918 919 if (intel_uc_uses_guc_submission(>->uc)) { 920 gt->submission_method = INTEL_SUBMISSION_GUC; 921 setup = intel_guc_submission_setup; 922 } else if (HAS_EXECLISTS(gt->i915)) { 923 gt->submission_method = INTEL_SUBMISSION_ELSP; 924 setup = intel_execlists_submission_setup; 925 } else { 926 gt->submission_method = INTEL_SUBMISSION_RING; 927 setup = intel_ring_submission_setup; 928 } 929 930 for_each_engine(engine, gt, id) { 931 err = engine_setup_common(engine); 932 if (err) 933 return err; 934 935 err = setup(engine); 936 if (err) 937 return err; 938 939 err = engine_init_common(engine); 940 if (err) 941 return err; 942 943 intel_engine_add_user(engine); 944 } 945 946 return 0; 947 } 948 949 /** 950 * intel_engines_cleanup_common - cleans up the engine state created by 951 * the common initiailizers. 952 * @engine: Engine to cleanup. 953 * 954 * This cleans up everything created by the common helpers. 955 */ 956 void intel_engine_cleanup_common(struct intel_engine_cs *engine) 957 { 958 GEM_BUG_ON(!list_empty(&engine->active.requests)); 959 tasklet_kill(&engine->execlists.tasklet); /* flush the callback */ 960 961 intel_breadcrumbs_free(engine->breadcrumbs); 962 963 intel_engine_fini_retire(engine); 964 intel_engine_cleanup_cmd_parser(engine); 965 966 if (engine->default_state) 967 fput(engine->default_state); 968 969 if (engine->kernel_context) 970 destroy_pinned_context(engine->kernel_context); 971 972 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks)); 973 cleanup_status_page(engine); 974 975 intel_wa_list_free(&engine->ctx_wa_list); 976 intel_wa_list_free(&engine->wa_list); 977 intel_wa_list_free(&engine->whitelist); 978 } 979 980 /** 981 * intel_engine_resume - re-initializes the HW state of the engine 982 * @engine: Engine to resume. 983 * 984 * Returns zero on success or an error code on failure. 985 */ 986 int intel_engine_resume(struct intel_engine_cs *engine) 987 { 988 intel_engine_apply_workarounds(engine); 989 intel_engine_apply_whitelist(engine); 990 991 return engine->resume(engine); 992 } 993 994 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine) 995 { 996 struct drm_i915_private *i915 = engine->i915; 997 998 u64 acthd; 999 1000 if (INTEL_GEN(i915) >= 8) 1001 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW); 1002 else if (INTEL_GEN(i915) >= 4) 1003 acthd = ENGINE_READ(engine, RING_ACTHD); 1004 else 1005 acthd = ENGINE_READ(engine, ACTHD); 1006 1007 return acthd; 1008 } 1009 1010 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine) 1011 { 1012 u64 bbaddr; 1013 1014 if (INTEL_GEN(engine->i915) >= 8) 1015 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW); 1016 else 1017 bbaddr = ENGINE_READ(engine, RING_BBADDR); 1018 1019 return bbaddr; 1020 } 1021 1022 static unsigned long stop_timeout(const struct intel_engine_cs *engine) 1023 { 1024 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */ 1025 return 0; 1026 1027 /* 1028 * If we are doing a normal GPU reset, we can take our time and allow 1029 * the engine to quiesce. We've stopped submission to the engine, and 1030 * if we wait long enough an innocent context should complete and 1031 * leave the engine idle. So they should not be caught unaware by 1032 * the forthcoming GPU reset (which usually follows the stop_cs)! 1033 */ 1034 return READ_ONCE(engine->props.stop_timeout_ms); 1035 } 1036 1037 static int __intel_engine_stop_cs(struct intel_engine_cs *engine, 1038 int fast_timeout_us, 1039 int slow_timeout_ms) 1040 { 1041 struct intel_uncore *uncore = engine->uncore; 1042 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); 1043 int err; 1044 1045 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); 1046 err = __intel_wait_for_register_fw(engine->uncore, mode, 1047 MODE_IDLE, MODE_IDLE, 1048 fast_timeout_us, 1049 slow_timeout_ms, 1050 NULL); 1051 1052 /* A final mmio read to let GPU writes be hopefully flushed to memory */ 1053 intel_uncore_posting_read_fw(uncore, mode); 1054 return err; 1055 } 1056 1057 int intel_engine_stop_cs(struct intel_engine_cs *engine) 1058 { 1059 int err = 0; 1060 1061 if (INTEL_GEN(engine->i915) < 3) 1062 return -ENODEV; 1063 1064 ENGINE_TRACE(engine, "\n"); 1065 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { 1066 ENGINE_TRACE(engine, 1067 "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n", 1068 ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR, 1069 ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR); 1070 1071 /* 1072 * Sometimes we observe that the idle flag is not 1073 * set even though the ring is empty. So double 1074 * check before giving up. 1075 */ 1076 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) != 1077 (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR)) 1078 err = -ETIMEDOUT; 1079 } 1080 1081 return err; 1082 } 1083 1084 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) 1085 { 1086 ENGINE_TRACE(engine, "\n"); 1087 1088 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); 1089 } 1090 1091 const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 1092 { 1093 switch (type) { 1094 case I915_CACHE_NONE: return " uncached"; 1095 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 1096 case I915_CACHE_L3_LLC: return " L3+LLC"; 1097 case I915_CACHE_WT: return " WT"; 1098 default: return ""; 1099 } 1100 } 1101 1102 static u32 1103 read_subslice_reg(const struct intel_engine_cs *engine, 1104 int slice, int subslice, i915_reg_t reg) 1105 { 1106 struct drm_i915_private *i915 = engine->i915; 1107 struct intel_uncore *uncore = engine->uncore; 1108 u32 mcr_mask, mcr_ss, mcr, old_mcr, val; 1109 enum forcewake_domains fw_domains; 1110 1111 if (INTEL_GEN(i915) >= 11) { 1112 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1113 mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1114 } else { 1115 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1116 mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1117 } 1118 1119 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, 1120 FW_REG_READ); 1121 fw_domains |= intel_uncore_forcewake_for_reg(uncore, 1122 GEN8_MCR_SELECTOR, 1123 FW_REG_READ | FW_REG_WRITE); 1124 1125 spin_lock_irq(&uncore->lock); 1126 intel_uncore_forcewake_get__locked(uncore, fw_domains); 1127 1128 old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); 1129 1130 mcr &= ~mcr_mask; 1131 mcr |= mcr_ss; 1132 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); 1133 1134 val = intel_uncore_read_fw(uncore, reg); 1135 1136 mcr &= ~mcr_mask; 1137 mcr |= old_mcr & mcr_mask; 1138 1139 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); 1140 1141 intel_uncore_forcewake_put__locked(uncore, fw_domains); 1142 spin_unlock_irq(&uncore->lock); 1143 1144 return val; 1145 } 1146 1147 /* NB: please notice the memset */ 1148 void intel_engine_get_instdone(const struct intel_engine_cs *engine, 1149 struct intel_instdone *instdone) 1150 { 1151 struct drm_i915_private *i915 = engine->i915; 1152 const struct sseu_dev_info *sseu = &engine->gt->info.sseu; 1153 struct intel_uncore *uncore = engine->uncore; 1154 u32 mmio_base = engine->mmio_base; 1155 int slice; 1156 int subslice; 1157 1158 memset(instdone, 0, sizeof(*instdone)); 1159 1160 switch (INTEL_GEN(i915)) { 1161 default: 1162 instdone->instdone = 1163 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1164 1165 if (engine->id != RCS0) 1166 break; 1167 1168 instdone->slice_common = 1169 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1170 if (INTEL_GEN(i915) >= 12) { 1171 instdone->slice_common_extra[0] = 1172 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA); 1173 instdone->slice_common_extra[1] = 1174 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2); 1175 } 1176 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) { 1177 instdone->sampler[slice][subslice] = 1178 read_subslice_reg(engine, slice, subslice, 1179 GEN7_SAMPLER_INSTDONE); 1180 instdone->row[slice][subslice] = 1181 read_subslice_reg(engine, slice, subslice, 1182 GEN7_ROW_INSTDONE); 1183 } 1184 break; 1185 case 7: 1186 instdone->instdone = 1187 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1188 1189 if (engine->id != RCS0) 1190 break; 1191 1192 instdone->slice_common = 1193 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1194 instdone->sampler[0][0] = 1195 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE); 1196 instdone->row[0][0] = 1197 intel_uncore_read(uncore, GEN7_ROW_INSTDONE); 1198 1199 break; 1200 case 6: 1201 case 5: 1202 case 4: 1203 instdone->instdone = 1204 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1205 if (engine->id == RCS0) 1206 /* HACK: Using the wrong struct member */ 1207 instdone->slice_common = 1208 intel_uncore_read(uncore, GEN4_INSTDONE1); 1209 break; 1210 case 3: 1211 case 2: 1212 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE); 1213 break; 1214 } 1215 } 1216 1217 static bool ring_is_idle(struct intel_engine_cs *engine) 1218 { 1219 bool idle = true; 1220 1221 if (I915_SELFTEST_ONLY(!engine->mmio_base)) 1222 return true; 1223 1224 if (!intel_engine_pm_get_if_awake(engine)) 1225 return true; 1226 1227 /* First check that no commands are left in the ring */ 1228 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) != 1229 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR)) 1230 idle = false; 1231 1232 /* No bit for gen2, so assume the CS parser is idle */ 1233 if (INTEL_GEN(engine->i915) > 2 && 1234 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE)) 1235 idle = false; 1236 1237 intel_engine_pm_put(engine); 1238 1239 return idle; 1240 } 1241 1242 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync) 1243 { 1244 struct tasklet_struct *t = &engine->execlists.tasklet; 1245 1246 if (!t->callback) 1247 return; 1248 1249 local_bh_disable(); 1250 if (tasklet_trylock(t)) { 1251 /* Must wait for any GPU reset in progress. */ 1252 if (__tasklet_is_enabled(t)) 1253 t->callback(t); 1254 tasklet_unlock(t); 1255 } 1256 local_bh_enable(); 1257 1258 /* Synchronise and wait for the tasklet on another CPU */ 1259 if (sync) 1260 tasklet_unlock_wait(t); 1261 } 1262 1263 /** 1264 * intel_engine_is_idle() - Report if the engine has finished process all work 1265 * @engine: the intel_engine_cs 1266 * 1267 * Return true if there are no requests pending, nothing left to be submitted 1268 * to hardware, and that the engine is idle. 1269 */ 1270 bool intel_engine_is_idle(struct intel_engine_cs *engine) 1271 { 1272 /* More white lies, if wedged, hw state is inconsistent */ 1273 if (intel_gt_is_wedged(engine->gt)) 1274 return true; 1275 1276 if (!intel_engine_pm_is_awake(engine)) 1277 return true; 1278 1279 /* Waiting to drain ELSP? */ 1280 synchronize_hardirq(to_pci_dev(engine->i915->drm.dev)->irq); 1281 intel_engine_flush_submission(engine); 1282 1283 /* ELSP is empty, but there are ready requests? E.g. after reset */ 1284 if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)) 1285 return false; 1286 1287 /* Ring stopped? */ 1288 return ring_is_idle(engine); 1289 } 1290 1291 bool intel_engines_are_idle(struct intel_gt *gt) 1292 { 1293 struct intel_engine_cs *engine; 1294 enum intel_engine_id id; 1295 1296 /* 1297 * If the driver is wedged, HW state may be very inconsistent and 1298 * report that it is still busy, even though we have stopped using it. 1299 */ 1300 if (intel_gt_is_wedged(gt)) 1301 return true; 1302 1303 /* Already parked (and passed an idleness test); must still be idle */ 1304 if (!READ_ONCE(gt->awake)) 1305 return true; 1306 1307 for_each_engine(engine, gt, id) { 1308 if (!intel_engine_is_idle(engine)) 1309 return false; 1310 } 1311 1312 return true; 1313 } 1314 1315 void intel_engines_reset_default_submission(struct intel_gt *gt) 1316 { 1317 struct intel_engine_cs *engine; 1318 enum intel_engine_id id; 1319 1320 for_each_engine(engine, gt, id) { 1321 if (engine->sanitize) 1322 engine->sanitize(engine); 1323 1324 engine->set_default_submission(engine); 1325 } 1326 } 1327 1328 bool intel_engine_can_store_dword(struct intel_engine_cs *engine) 1329 { 1330 switch (INTEL_GEN(engine->i915)) { 1331 case 2: 1332 return false; /* uses physical not virtual addresses */ 1333 case 3: 1334 /* maybe only uses physical not virtual addresses */ 1335 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); 1336 case 4: 1337 return !IS_I965G(engine->i915); /* who knows! */ 1338 case 6: 1339 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ 1340 default: 1341 return true; 1342 } 1343 } 1344 1345 static struct intel_timeline *get_timeline(struct i915_request *rq) 1346 { 1347 struct intel_timeline *tl; 1348 1349 /* 1350 * Even though we are holding the engine->active.lock here, there 1351 * is no control over the submission queue per-se and we are 1352 * inspecting the active state at a random point in time, with an 1353 * unknown queue. Play safe and make sure the timeline remains valid. 1354 * (Only being used for pretty printing, one extra kref shouldn't 1355 * cause a camel stampede!) 1356 */ 1357 rcu_read_lock(); 1358 tl = rcu_dereference(rq->timeline); 1359 if (!kref_get_unless_zero(&tl->kref)) 1360 tl = NULL; 1361 rcu_read_unlock(); 1362 1363 return tl; 1364 } 1365 1366 static int print_ring(char *buf, int sz, struct i915_request *rq) 1367 { 1368 int len = 0; 1369 1370 if (!i915_request_signaled(rq)) { 1371 struct intel_timeline *tl = get_timeline(rq); 1372 1373 len = scnprintf(buf, sz, 1374 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ", 1375 i915_ggtt_offset(rq->ring->vma), 1376 tl ? tl->hwsp_offset : 0, 1377 hwsp_seqno(rq), 1378 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context), 1379 1000 * 1000)); 1380 1381 if (tl) 1382 intel_timeline_put(tl); 1383 } 1384 1385 return len; 1386 } 1387 1388 static void hexdump(struct drm_printer *m, const void *buf, size_t len) 1389 { 1390 const size_t rowsize = 8 * sizeof(u32); 1391 const void *prev = NULL; 1392 bool skip = false; 1393 size_t pos; 1394 1395 for (pos = 0; pos < len; pos += rowsize) { 1396 char line[128]; 1397 1398 if (prev && !memcmp(prev, buf + pos, rowsize)) { 1399 if (!skip) { 1400 drm_printf(m, "*\n"); 1401 skip = true; 1402 } 1403 continue; 1404 } 1405 1406 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos, 1407 rowsize, sizeof(u32), 1408 line, sizeof(line), 1409 false) >= sizeof(line)); 1410 drm_printf(m, "[%04zx] %s\n", pos, line); 1411 1412 prev = buf + pos; 1413 skip = false; 1414 } 1415 } 1416 1417 static const char *repr_timer(const struct timer_list *t) 1418 { 1419 if (!READ_ONCE(t->expires)) 1420 return "inactive"; 1421 1422 if (timer_pending(t)) 1423 return "active"; 1424 1425 return "expired"; 1426 } 1427 1428 static void intel_engine_print_registers(struct intel_engine_cs *engine, 1429 struct drm_printer *m) 1430 { 1431 struct drm_i915_private *dev_priv = engine->i915; 1432 struct intel_engine_execlists * const execlists = &engine->execlists; 1433 u64 addr; 1434 1435 if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7)) 1436 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID)); 1437 if (HAS_EXECLISTS(dev_priv)) { 1438 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n", 1439 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI)); 1440 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n", 1441 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO)); 1442 } 1443 drm_printf(m, "\tRING_START: 0x%08x\n", 1444 ENGINE_READ(engine, RING_START)); 1445 drm_printf(m, "\tRING_HEAD: 0x%08x\n", 1446 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR); 1447 drm_printf(m, "\tRING_TAIL: 0x%08x\n", 1448 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR); 1449 drm_printf(m, "\tRING_CTL: 0x%08x%s\n", 1450 ENGINE_READ(engine, RING_CTL), 1451 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : ""); 1452 if (INTEL_GEN(engine->i915) > 2) { 1453 drm_printf(m, "\tRING_MODE: 0x%08x%s\n", 1454 ENGINE_READ(engine, RING_MI_MODE), 1455 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : ""); 1456 } 1457 1458 if (INTEL_GEN(dev_priv) >= 6) { 1459 drm_printf(m, "\tRING_IMR: 0x%08x\n", 1460 ENGINE_READ(engine, RING_IMR)); 1461 drm_printf(m, "\tRING_ESR: 0x%08x\n", 1462 ENGINE_READ(engine, RING_ESR)); 1463 drm_printf(m, "\tRING_EMR: 0x%08x\n", 1464 ENGINE_READ(engine, RING_EMR)); 1465 drm_printf(m, "\tRING_EIR: 0x%08x\n", 1466 ENGINE_READ(engine, RING_EIR)); 1467 } 1468 1469 addr = intel_engine_get_active_head(engine); 1470 drm_printf(m, "\tACTHD: 0x%08x_%08x\n", 1471 upper_32_bits(addr), lower_32_bits(addr)); 1472 addr = intel_engine_get_last_batch_head(engine); 1473 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n", 1474 upper_32_bits(addr), lower_32_bits(addr)); 1475 if (INTEL_GEN(dev_priv) >= 8) 1476 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW); 1477 else if (INTEL_GEN(dev_priv) >= 4) 1478 addr = ENGINE_READ(engine, RING_DMA_FADD); 1479 else 1480 addr = ENGINE_READ(engine, DMA_FADD_I8XX); 1481 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n", 1482 upper_32_bits(addr), lower_32_bits(addr)); 1483 if (INTEL_GEN(dev_priv) >= 4) { 1484 drm_printf(m, "\tIPEIR: 0x%08x\n", 1485 ENGINE_READ(engine, RING_IPEIR)); 1486 drm_printf(m, "\tIPEHR: 0x%08x\n", 1487 ENGINE_READ(engine, RING_IPEHR)); 1488 } else { 1489 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR)); 1490 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR)); 1491 } 1492 1493 if (intel_engine_uses_guc(engine)) { 1494 /* nothing to print yet */ 1495 } else if (HAS_EXECLISTS(dev_priv)) { 1496 struct i915_request * const *port, *rq; 1497 const u32 *hws = 1498 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; 1499 const u8 num_entries = execlists->csb_size; 1500 unsigned int idx; 1501 u8 read, write; 1502 1503 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n", 1504 yesno(test_bit(TASKLET_STATE_SCHED, 1505 &engine->execlists.tasklet.state)), 1506 enableddisabled(!atomic_read(&engine->execlists.tasklet.count)), 1507 repr_timer(&engine->execlists.preempt), 1508 repr_timer(&engine->execlists.timer)); 1509 1510 read = execlists->csb_head; 1511 write = READ_ONCE(*execlists->csb_write); 1512 1513 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n", 1514 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO), 1515 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI), 1516 read, write, num_entries); 1517 1518 if (read >= num_entries) 1519 read = 0; 1520 if (write >= num_entries) 1521 write = 0; 1522 if (read > write) 1523 write += num_entries; 1524 while (read < write) { 1525 idx = ++read % num_entries; 1526 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", 1527 idx, hws[idx * 2], hws[idx * 2 + 1]); 1528 } 1529 1530 execlists_active_lock_bh(execlists); 1531 rcu_read_lock(); 1532 for (port = execlists->active; (rq = *port); port++) { 1533 char hdr[160]; 1534 int len; 1535 1536 len = scnprintf(hdr, sizeof(hdr), 1537 "\t\tActive[%d]: ccid:%08x%s%s, ", 1538 (int)(port - execlists->active), 1539 rq->context->lrc.ccid, 1540 intel_context_is_closed(rq->context) ? "!" : "", 1541 intel_context_is_banned(rq->context) ? "*" : ""); 1542 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1543 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1544 i915_request_show(m, rq, hdr, 0); 1545 } 1546 for (port = execlists->pending; (rq = *port); port++) { 1547 char hdr[160]; 1548 int len; 1549 1550 len = scnprintf(hdr, sizeof(hdr), 1551 "\t\tPending[%d]: ccid:%08x%s%s, ", 1552 (int)(port - execlists->pending), 1553 rq->context->lrc.ccid, 1554 intel_context_is_closed(rq->context) ? "!" : "", 1555 intel_context_is_banned(rq->context) ? "*" : ""); 1556 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1557 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1558 i915_request_show(m, rq, hdr, 0); 1559 } 1560 rcu_read_unlock(); 1561 execlists_active_unlock_bh(execlists); 1562 } else if (INTEL_GEN(dev_priv) > 6) { 1563 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n", 1564 ENGINE_READ(engine, RING_PP_DIR_BASE)); 1565 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", 1566 ENGINE_READ(engine, RING_PP_DIR_BASE_READ)); 1567 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", 1568 ENGINE_READ(engine, RING_PP_DIR_DCLV)); 1569 } 1570 } 1571 1572 static void print_request_ring(struct drm_printer *m, struct i915_request *rq) 1573 { 1574 void *ring; 1575 int size; 1576 1577 drm_printf(m, 1578 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n", 1579 rq->head, rq->postfix, rq->tail, 1580 rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, 1581 rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); 1582 1583 size = rq->tail - rq->head; 1584 if (rq->tail < rq->head) 1585 size += rq->ring->size; 1586 1587 ring = kmalloc(size, GFP_ATOMIC); 1588 if (ring) { 1589 const void *vaddr = rq->ring->vaddr; 1590 unsigned int head = rq->head; 1591 unsigned int len = 0; 1592 1593 if (rq->tail < head) { 1594 len = rq->ring->size - head; 1595 memcpy(ring, vaddr + head, len); 1596 head = 0; 1597 } 1598 memcpy(ring + len, vaddr + head, size - len); 1599 1600 hexdump(m, ring, size); 1601 kfree(ring); 1602 } 1603 } 1604 1605 static unsigned long list_count(struct list_head *list) 1606 { 1607 struct list_head *pos; 1608 unsigned long count = 0; 1609 1610 list_for_each(pos, list) 1611 count++; 1612 1613 return count; 1614 } 1615 1616 static unsigned long read_ul(void *p, size_t x) 1617 { 1618 return *(unsigned long *)(p + x); 1619 } 1620 1621 static void print_properties(struct intel_engine_cs *engine, 1622 struct drm_printer *m) 1623 { 1624 static const struct pmap { 1625 size_t offset; 1626 const char *name; 1627 } props[] = { 1628 #define P(x) { \ 1629 .offset = offsetof(typeof(engine->props), x), \ 1630 .name = #x \ 1631 } 1632 P(heartbeat_interval_ms), 1633 P(max_busywait_duration_ns), 1634 P(preempt_timeout_ms), 1635 P(stop_timeout_ms), 1636 P(timeslice_duration_ms), 1637 1638 {}, 1639 #undef P 1640 }; 1641 const struct pmap *p; 1642 1643 drm_printf(m, "\tProperties:\n"); 1644 for (p = props; p->name; p++) 1645 drm_printf(m, "\t\t%s: %lu [default %lu]\n", 1646 p->name, 1647 read_ul(&engine->props, p->offset), 1648 read_ul(&engine->defaults, p->offset)); 1649 } 1650 1651 void intel_engine_dump(struct intel_engine_cs *engine, 1652 struct drm_printer *m, 1653 const char *header, ...) 1654 { 1655 struct i915_gpu_error * const error = &engine->i915->gpu_error; 1656 struct i915_request *rq; 1657 intel_wakeref_t wakeref; 1658 unsigned long flags; 1659 ktime_t dummy; 1660 1661 if (header) { 1662 va_list ap; 1663 1664 va_start(ap, header); 1665 drm_vprintf(m, header, &ap); 1666 va_end(ap); 1667 } 1668 1669 if (intel_gt_is_wedged(engine->gt)) 1670 drm_printf(m, "*** WEDGED ***\n"); 1671 1672 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count)); 1673 drm_printf(m, "\tBarriers?: %s\n", 1674 yesno(!llist_empty(&engine->barrier_tasks))); 1675 drm_printf(m, "\tLatency: %luus\n", 1676 ewma__engine_latency_read(&engine->latency)); 1677 if (intel_engine_supports_stats(engine)) 1678 drm_printf(m, "\tRuntime: %llums\n", 1679 ktime_to_ms(intel_engine_get_busy_time(engine, 1680 &dummy))); 1681 drm_printf(m, "\tForcewake: %x domains, %d active\n", 1682 engine->fw_domain, READ_ONCE(engine->fw_active)); 1683 1684 rcu_read_lock(); 1685 rq = READ_ONCE(engine->heartbeat.systole); 1686 if (rq) 1687 drm_printf(m, "\tHeartbeat: %d ms ago\n", 1688 jiffies_to_msecs(jiffies - rq->emitted_jiffies)); 1689 rcu_read_unlock(); 1690 drm_printf(m, "\tReset count: %d (global %d)\n", 1691 i915_reset_engine_count(error, engine), 1692 i915_reset_count(error)); 1693 print_properties(engine, m); 1694 1695 drm_printf(m, "\tRequests:\n"); 1696 1697 spin_lock_irqsave(&engine->active.lock, flags); 1698 rq = intel_engine_find_active_request(engine); 1699 if (rq) { 1700 struct intel_timeline *tl = get_timeline(rq); 1701 1702 i915_request_show(m, rq, "\t\tactive ", 0); 1703 1704 drm_printf(m, "\t\tring->start: 0x%08x\n", 1705 i915_ggtt_offset(rq->ring->vma)); 1706 drm_printf(m, "\t\tring->head: 0x%08x\n", 1707 rq->ring->head); 1708 drm_printf(m, "\t\tring->tail: 0x%08x\n", 1709 rq->ring->tail); 1710 drm_printf(m, "\t\tring->emit: 0x%08x\n", 1711 rq->ring->emit); 1712 drm_printf(m, "\t\tring->space: 0x%08x\n", 1713 rq->ring->space); 1714 1715 if (tl) { 1716 drm_printf(m, "\t\tring->hwsp: 0x%08x\n", 1717 tl->hwsp_offset); 1718 intel_timeline_put(tl); 1719 } 1720 1721 print_request_ring(m, rq); 1722 1723 if (rq->context->lrc_reg_state) { 1724 drm_printf(m, "Logical Ring Context:\n"); 1725 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE); 1726 } 1727 } 1728 drm_printf(m, "\tOn hold?: %lu\n", list_count(&engine->active.hold)); 1729 spin_unlock_irqrestore(&engine->active.lock, flags); 1730 1731 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base); 1732 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm); 1733 if (wakeref) { 1734 intel_engine_print_registers(engine, m); 1735 intel_runtime_pm_put(engine->uncore->rpm, wakeref); 1736 } else { 1737 drm_printf(m, "\tDevice is asleep; skipping register dump\n"); 1738 } 1739 1740 intel_execlists_show_requests(engine, m, i915_request_show, 8); 1741 1742 drm_printf(m, "HWSP:\n"); 1743 hexdump(m, engine->status_page.addr, PAGE_SIZE); 1744 1745 drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine))); 1746 1747 intel_engine_print_breadcrumbs(engine, m); 1748 } 1749 1750 static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine, 1751 ktime_t *now) 1752 { 1753 ktime_t total = engine->stats.total; 1754 1755 /* 1756 * If the engine is executing something at the moment 1757 * add it to the total. 1758 */ 1759 *now = ktime_get(); 1760 if (READ_ONCE(engine->stats.active)) 1761 total = ktime_add(total, ktime_sub(*now, engine->stats.start)); 1762 1763 return total; 1764 } 1765 1766 /** 1767 * intel_engine_get_busy_time() - Return current accumulated engine busyness 1768 * @engine: engine to report on 1769 * @now: monotonic timestamp of sampling 1770 * 1771 * Returns accumulated time @engine was busy since engine stats were enabled. 1772 */ 1773 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) 1774 { 1775 unsigned int seq; 1776 ktime_t total; 1777 1778 do { 1779 seq = read_seqcount_begin(&engine->stats.lock); 1780 total = __intel_engine_get_busy_time(engine, now); 1781 } while (read_seqcount_retry(&engine->stats.lock, seq)); 1782 1783 return total; 1784 } 1785 1786 static bool match_ring(struct i915_request *rq) 1787 { 1788 u32 ring = ENGINE_READ(rq->engine, RING_START); 1789 1790 return ring == i915_ggtt_offset(rq->ring->vma); 1791 } 1792 1793 struct i915_request * 1794 intel_engine_find_active_request(struct intel_engine_cs *engine) 1795 { 1796 struct i915_request *request, *active = NULL; 1797 1798 /* 1799 * We are called by the error capture, reset and to dump engine 1800 * state at random points in time. In particular, note that neither is 1801 * crucially ordered with an interrupt. After a hang, the GPU is dead 1802 * and we assume that no more writes can happen (we waited long enough 1803 * for all writes that were in transaction to be flushed) - adding an 1804 * extra delay for a recent interrupt is pointless. Hence, we do 1805 * not need an engine->irq_seqno_barrier() before the seqno reads. 1806 * At all other times, we must assume the GPU is still running, but 1807 * we only care about the snapshot of this moment. 1808 */ 1809 lockdep_assert_held(&engine->active.lock); 1810 1811 rcu_read_lock(); 1812 request = execlists_active(&engine->execlists); 1813 if (request) { 1814 struct intel_timeline *tl = request->context->timeline; 1815 1816 list_for_each_entry_from_reverse(request, &tl->requests, link) { 1817 if (__i915_request_is_complete(request)) 1818 break; 1819 1820 active = request; 1821 } 1822 } 1823 rcu_read_unlock(); 1824 if (active) 1825 return active; 1826 1827 list_for_each_entry(request, &engine->active.requests, sched.link) { 1828 if (__i915_request_is_complete(request)) 1829 continue; 1830 1831 if (!__i915_request_has_started(request)) 1832 continue; 1833 1834 /* More than one preemptible request may match! */ 1835 if (!match_ring(request)) 1836 continue; 1837 1838 active = request; 1839 break; 1840 } 1841 1842 return active; 1843 } 1844 1845 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 1846 #include "mock_engine.c" 1847 #include "selftest_engine.c" 1848 #include "selftest_engine_cs.c" 1849 #endif 1850