1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_print.h> 26 27 #include "gem/i915_gem_context.h" 28 29 #include "i915_drv.h" 30 31 #include "intel_context.h" 32 #include "intel_engine.h" 33 #include "intel_engine_pm.h" 34 #include "intel_engine_user.h" 35 #include "intel_gt.h" 36 #include "intel_gt_requests.h" 37 #include "intel_gt_pm.h" 38 #include "intel_lrc.h" 39 #include "intel_reset.h" 40 #include "intel_ring.h" 41 42 /* Haswell does have the CXT_SIZE register however it does not appear to be 43 * valid. Now, docs explain in dwords what is in the context object. The full 44 * size is 70720 bytes, however, the power context and execlist context will 45 * never be saved (power context is stored elsewhere, and execlists don't work 46 * on HSW) - so the final size, including the extra state required for the 47 * Resource Streamer, is 66944 bytes, which rounds to 17 pages. 48 */ 49 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 50 51 #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 52 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) 53 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 54 #define GEN10_LR_CONTEXT_RENDER_SIZE (18 * PAGE_SIZE) 55 #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE) 56 57 #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE) 58 59 #define MAX_MMIO_BASES 3 60 struct engine_info { 61 unsigned int hw_id; 62 u8 class; 63 u8 instance; 64 /* mmio bases table *must* be sorted in reverse gen order */ 65 struct engine_mmio_base { 66 u32 gen : 8; 67 u32 base : 24; 68 } mmio_bases[MAX_MMIO_BASES]; 69 }; 70 71 static const struct engine_info intel_engines[] = { 72 [RCS0] = { 73 .hw_id = RCS0_HW, 74 .class = RENDER_CLASS, 75 .instance = 0, 76 .mmio_bases = { 77 { .gen = 1, .base = RENDER_RING_BASE } 78 }, 79 }, 80 [BCS0] = { 81 .hw_id = BCS0_HW, 82 .class = COPY_ENGINE_CLASS, 83 .instance = 0, 84 .mmio_bases = { 85 { .gen = 6, .base = BLT_RING_BASE } 86 }, 87 }, 88 [VCS0] = { 89 .hw_id = VCS0_HW, 90 .class = VIDEO_DECODE_CLASS, 91 .instance = 0, 92 .mmio_bases = { 93 { .gen = 11, .base = GEN11_BSD_RING_BASE }, 94 { .gen = 6, .base = GEN6_BSD_RING_BASE }, 95 { .gen = 4, .base = BSD_RING_BASE } 96 }, 97 }, 98 [VCS1] = { 99 .hw_id = VCS1_HW, 100 .class = VIDEO_DECODE_CLASS, 101 .instance = 1, 102 .mmio_bases = { 103 { .gen = 11, .base = GEN11_BSD2_RING_BASE }, 104 { .gen = 8, .base = GEN8_BSD2_RING_BASE } 105 }, 106 }, 107 [VCS2] = { 108 .hw_id = VCS2_HW, 109 .class = VIDEO_DECODE_CLASS, 110 .instance = 2, 111 .mmio_bases = { 112 { .gen = 11, .base = GEN11_BSD3_RING_BASE } 113 }, 114 }, 115 [VCS3] = { 116 .hw_id = VCS3_HW, 117 .class = VIDEO_DECODE_CLASS, 118 .instance = 3, 119 .mmio_bases = { 120 { .gen = 11, .base = GEN11_BSD4_RING_BASE } 121 }, 122 }, 123 [VECS0] = { 124 .hw_id = VECS0_HW, 125 .class = VIDEO_ENHANCEMENT_CLASS, 126 .instance = 0, 127 .mmio_bases = { 128 { .gen = 11, .base = GEN11_VEBOX_RING_BASE }, 129 { .gen = 7, .base = VEBOX_RING_BASE } 130 }, 131 }, 132 [VECS1] = { 133 .hw_id = VECS1_HW, 134 .class = VIDEO_ENHANCEMENT_CLASS, 135 .instance = 1, 136 .mmio_bases = { 137 { .gen = 11, .base = GEN11_VEBOX2_RING_BASE } 138 }, 139 }, 140 }; 141 142 /** 143 * intel_engine_context_size() - return the size of the context for an engine 144 * @gt: the gt 145 * @class: engine class 146 * 147 * Each engine class may require a different amount of space for a context 148 * image. 149 * 150 * Return: size (in bytes) of an engine class specific context image 151 * 152 * Note: this size includes the HWSP, which is part of the context image 153 * in LRC mode, but does not include the "shared data page" used with 154 * GuC submission. The caller should account for this if using the GuC. 155 */ 156 u32 intel_engine_context_size(struct intel_gt *gt, u8 class) 157 { 158 struct intel_uncore *uncore = gt->uncore; 159 u32 cxt_size; 160 161 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE); 162 163 switch (class) { 164 case RENDER_CLASS: 165 switch (INTEL_GEN(gt->i915)) { 166 default: 167 MISSING_CASE(INTEL_GEN(gt->i915)); 168 return DEFAULT_LR_CONTEXT_RENDER_SIZE; 169 case 12: 170 case 11: 171 return GEN11_LR_CONTEXT_RENDER_SIZE; 172 case 10: 173 return GEN10_LR_CONTEXT_RENDER_SIZE; 174 case 9: 175 return GEN9_LR_CONTEXT_RENDER_SIZE; 176 case 8: 177 return GEN8_LR_CONTEXT_RENDER_SIZE; 178 case 7: 179 if (IS_HASWELL(gt->i915)) 180 return HSW_CXT_TOTAL_SIZE; 181 182 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE); 183 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64, 184 PAGE_SIZE); 185 case 6: 186 cxt_size = intel_uncore_read(uncore, CXT_SIZE); 187 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64, 188 PAGE_SIZE); 189 case 5: 190 case 4: 191 /* 192 * There is a discrepancy here between the size reported 193 * by the register and the size of the context layout 194 * in the docs. Both are described as authorative! 195 * 196 * The discrepancy is on the order of a few cachelines, 197 * but the total is under one page (4k), which is our 198 * minimum allocation anyway so it should all come 199 * out in the wash. 200 */ 201 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1; 202 drm_dbg(>->i915->drm, 203 "gen%d CXT_SIZE = %d bytes [0x%08x]\n", 204 INTEL_GEN(gt->i915), cxt_size * 64, 205 cxt_size - 1); 206 return round_up(cxt_size * 64, PAGE_SIZE); 207 case 3: 208 case 2: 209 /* For the special day when i810 gets merged. */ 210 case 1: 211 return 0; 212 } 213 break; 214 default: 215 MISSING_CASE(class); 216 /* fall through */ 217 case VIDEO_DECODE_CLASS: 218 case VIDEO_ENHANCEMENT_CLASS: 219 case COPY_ENGINE_CLASS: 220 if (INTEL_GEN(gt->i915) < 8) 221 return 0; 222 return GEN8_LR_CONTEXT_OTHER_SIZE; 223 } 224 } 225 226 static u32 __engine_mmio_base(struct drm_i915_private *i915, 227 const struct engine_mmio_base *bases) 228 { 229 int i; 230 231 for (i = 0; i < MAX_MMIO_BASES; i++) 232 if (INTEL_GEN(i915) >= bases[i].gen) 233 break; 234 235 GEM_BUG_ON(i == MAX_MMIO_BASES); 236 GEM_BUG_ON(!bases[i].base); 237 238 return bases[i].base; 239 } 240 241 static void __sprint_engine_name(struct intel_engine_cs *engine) 242 { 243 /* 244 * Before we know what the uABI name for this engine will be, 245 * we still would like to keep track of this engine in the debug logs. 246 * We throw in a ' here as a reminder that this isn't its final name. 247 */ 248 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u", 249 intel_engine_class_repr(engine->class), 250 engine->instance) >= sizeof(engine->name)); 251 } 252 253 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask) 254 { 255 /* 256 * Though they added more rings on g4x/ilk, they did not add 257 * per-engine HWSTAM until gen6. 258 */ 259 if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS) 260 return; 261 262 if (INTEL_GEN(engine->i915) >= 3) 263 ENGINE_WRITE(engine, RING_HWSTAM, mask); 264 else 265 ENGINE_WRITE16(engine, RING_HWSTAM, mask); 266 } 267 268 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine) 269 { 270 /* Mask off all writes into the unknown HWSP */ 271 intel_engine_set_hwsp_writemask(engine, ~0u); 272 } 273 274 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) 275 { 276 const struct engine_info *info = &intel_engines[id]; 277 struct drm_i915_private *i915 = gt->i915; 278 struct intel_engine_cs *engine; 279 280 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH)); 281 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH)); 282 283 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine))) 284 return -EINVAL; 285 286 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS)) 287 return -EINVAL; 288 289 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE)) 290 return -EINVAL; 291 292 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance])) 293 return -EINVAL; 294 295 engine = kzalloc(sizeof(*engine), GFP_KERNEL); 296 if (!engine) 297 return -ENOMEM; 298 299 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES); 300 301 engine->id = id; 302 engine->legacy_idx = INVALID_ENGINE; 303 engine->mask = BIT(id); 304 engine->i915 = i915; 305 engine->gt = gt; 306 engine->uncore = gt->uncore; 307 engine->hw_id = engine->guc_id = info->hw_id; 308 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases); 309 310 engine->class = info->class; 311 engine->instance = info->instance; 312 __sprint_engine_name(engine); 313 314 engine->props.heartbeat_interval_ms = 315 CONFIG_DRM_I915_HEARTBEAT_INTERVAL; 316 engine->props.max_busywait_duration_ns = 317 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT; 318 engine->props.preempt_timeout_ms = 319 CONFIG_DRM_I915_PREEMPT_TIMEOUT; 320 engine->props.stop_timeout_ms = 321 CONFIG_DRM_I915_STOP_TIMEOUT; 322 engine->props.timeslice_duration_ms = 323 CONFIG_DRM_I915_TIMESLICE_DURATION; 324 325 /* Override to uninterruptible for OpenCL workloads. */ 326 if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS) 327 engine->props.preempt_timeout_ms = 0; 328 329 engine->defaults = engine->props; /* never to change again */ 330 331 engine->context_size = intel_engine_context_size(gt, engine->class); 332 if (WARN_ON(engine->context_size > BIT(20))) 333 engine->context_size = 0; 334 if (engine->context_size) 335 DRIVER_CAPS(i915)->has_logical_contexts = true; 336 337 /* Nothing to do here, execute in order of dependencies */ 338 engine->schedule = NULL; 339 340 ewma__engine_latency_init(&engine->latency); 341 seqlock_init(&engine->stats.lock); 342 343 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); 344 345 /* Scrub mmio state on takeover */ 346 intel_engine_sanitize_mmio(engine); 347 348 gt->engine_class[info->class][info->instance] = engine; 349 gt->engine[id] = engine; 350 351 return 0; 352 } 353 354 static void __setup_engine_capabilities(struct intel_engine_cs *engine) 355 { 356 struct drm_i915_private *i915 = engine->i915; 357 358 if (engine->class == VIDEO_DECODE_CLASS) { 359 /* 360 * HEVC support is present on first engine instance 361 * before Gen11 and on all instances afterwards. 362 */ 363 if (INTEL_GEN(i915) >= 11 || 364 (INTEL_GEN(i915) >= 9 && engine->instance == 0)) 365 engine->uabi_capabilities |= 366 I915_VIDEO_CLASS_CAPABILITY_HEVC; 367 368 /* 369 * SFC block is present only on even logical engine 370 * instances. 371 */ 372 if ((INTEL_GEN(i915) >= 11 && 373 RUNTIME_INFO(i915)->vdbox_sfc_access & engine->mask) || 374 (INTEL_GEN(i915) >= 9 && engine->instance == 0)) 375 engine->uabi_capabilities |= 376 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 377 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) { 378 if (INTEL_GEN(i915) >= 9) 379 engine->uabi_capabilities |= 380 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 381 } 382 } 383 384 static void intel_setup_engine_capabilities(struct intel_gt *gt) 385 { 386 struct intel_engine_cs *engine; 387 enum intel_engine_id id; 388 389 for_each_engine(engine, gt, id) 390 __setup_engine_capabilities(engine); 391 } 392 393 /** 394 * intel_engines_release() - free the resources allocated for Command Streamers 395 * @gt: pointer to struct intel_gt 396 */ 397 void intel_engines_release(struct intel_gt *gt) 398 { 399 struct intel_engine_cs *engine; 400 enum intel_engine_id id; 401 402 /* 403 * Before we release the resources held by engine, we must be certain 404 * that the HW is no longer accessing them -- having the GPU scribble 405 * to or read from a page being used for something else causes no end 406 * of fun. 407 * 408 * The GPU should be reset by this point, but assume the worst just 409 * in case we aborted before completely initialising the engines. 410 */ 411 GEM_BUG_ON(intel_gt_pm_is_awake(gt)); 412 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) 413 __intel_gt_reset(gt, ALL_ENGINES); 414 415 /* Decouple the backend; but keep the layout for late GPU resets */ 416 for_each_engine(engine, gt, id) { 417 intel_wakeref_wait_for_idle(&engine->wakeref); 418 GEM_BUG_ON(intel_engine_pm_is_awake(engine)); 419 420 if (!engine->release) 421 continue; 422 423 engine->release(engine); 424 engine->release = NULL; 425 426 memset(&engine->reset, 0, sizeof(engine->reset)); 427 } 428 } 429 430 void intel_engine_free_request_pool(struct intel_engine_cs *engine) 431 { 432 if (!engine->request_pool) 433 return; 434 435 kmem_cache_free(i915_request_slab_cache(), engine->request_pool); 436 } 437 438 void intel_engines_free(struct intel_gt *gt) 439 { 440 struct intel_engine_cs *engine; 441 enum intel_engine_id id; 442 443 /* Free the requests! dma-resv keeps fences around for an eternity */ 444 rcu_barrier(); 445 446 for_each_engine(engine, gt, id) { 447 intel_engine_free_request_pool(engine); 448 kfree(engine); 449 gt->engine[id] = NULL; 450 } 451 } 452 453 /** 454 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers 455 * @gt: pointer to struct intel_gt 456 * 457 * Return: non-zero if the initialization failed. 458 */ 459 int intel_engines_init_mmio(struct intel_gt *gt) 460 { 461 struct drm_i915_private *i915 = gt->i915; 462 struct intel_device_info *device_info = mkwrite_device_info(i915); 463 const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask; 464 unsigned int mask = 0; 465 unsigned int i; 466 int err; 467 468 drm_WARN_ON(&i915->drm, engine_mask == 0); 469 drm_WARN_ON(&i915->drm, engine_mask & 470 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES)); 471 472 if (i915_inject_probe_failure(i915)) 473 return -ENODEV; 474 475 for (i = 0; i < ARRAY_SIZE(intel_engines); i++) { 476 if (!HAS_ENGINE(i915, i)) 477 continue; 478 479 err = intel_engine_setup(gt, i); 480 if (err) 481 goto cleanup; 482 483 mask |= BIT(i); 484 } 485 486 /* 487 * Catch failures to update intel_engines table when the new engines 488 * are added to the driver by a warning and disabling the forgotten 489 * engines. 490 */ 491 if (drm_WARN_ON(&i915->drm, mask != engine_mask)) 492 device_info->engine_mask = mask; 493 494 RUNTIME_INFO(i915)->num_engines = hweight32(mask); 495 496 intel_gt_check_and_clear_faults(gt); 497 498 intel_setup_engine_capabilities(gt); 499 500 return 0; 501 502 cleanup: 503 intel_engines_free(gt); 504 return err; 505 } 506 507 void intel_engine_init_execlists(struct intel_engine_cs *engine) 508 { 509 struct intel_engine_execlists * const execlists = &engine->execlists; 510 511 execlists->port_mask = 1; 512 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists))); 513 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS); 514 515 memset(execlists->pending, 0, sizeof(execlists->pending)); 516 execlists->active = 517 memset(execlists->inflight, 0, sizeof(execlists->inflight)); 518 519 execlists->queue_priority_hint = INT_MIN; 520 execlists->queue = RB_ROOT_CACHED; 521 } 522 523 static void cleanup_status_page(struct intel_engine_cs *engine) 524 { 525 struct i915_vma *vma; 526 527 /* Prevent writes into HWSP after returning the page to the system */ 528 intel_engine_set_hwsp_writemask(engine, ~0u); 529 530 vma = fetch_and_zero(&engine->status_page.vma); 531 if (!vma) 532 return; 533 534 if (!HWS_NEEDS_PHYSICAL(engine->i915)) 535 i915_vma_unpin(vma); 536 537 i915_gem_object_unpin_map(vma->obj); 538 i915_gem_object_put(vma->obj); 539 } 540 541 static int pin_ggtt_status_page(struct intel_engine_cs *engine, 542 struct i915_vma *vma) 543 { 544 unsigned int flags; 545 546 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) 547 /* 548 * On g33, we cannot place HWS above 256MiB, so 549 * restrict its pinning to the low mappable arena. 550 * Though this restriction is not documented for 551 * gen4, gen5, or byt, they also behave similarly 552 * and hang if the HWS is placed at the top of the 553 * GTT. To generalise, it appears that all !llc 554 * platforms have issues with us placing the HWS 555 * above the mappable region (even though we never 556 * actually map it). 557 */ 558 flags = PIN_MAPPABLE; 559 else 560 flags = PIN_HIGH; 561 562 return i915_ggtt_pin(vma, 0, flags); 563 } 564 565 static int init_status_page(struct intel_engine_cs *engine) 566 { 567 struct drm_i915_gem_object *obj; 568 struct i915_vma *vma; 569 void *vaddr; 570 int ret; 571 572 /* 573 * Though the HWS register does support 36bit addresses, historically 574 * we have had hangs and corruption reported due to wild writes if 575 * the HWS is placed above 4G. We only allow objects to be allocated 576 * in GFP_DMA32 for i965, and no earlier physical address users had 577 * access to more than 4G. 578 */ 579 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); 580 if (IS_ERR(obj)) { 581 drm_err(&engine->i915->drm, 582 "Failed to allocate status page\n"); 583 return PTR_ERR(obj); 584 } 585 586 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 587 588 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); 589 if (IS_ERR(vma)) { 590 ret = PTR_ERR(vma); 591 goto err; 592 } 593 594 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); 595 if (IS_ERR(vaddr)) { 596 ret = PTR_ERR(vaddr); 597 goto err; 598 } 599 600 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE); 601 engine->status_page.vma = vma; 602 603 if (!HWS_NEEDS_PHYSICAL(engine->i915)) { 604 ret = pin_ggtt_status_page(engine, vma); 605 if (ret) 606 goto err_unpin; 607 } 608 609 return 0; 610 611 err_unpin: 612 i915_gem_object_unpin_map(obj); 613 err: 614 i915_gem_object_put(obj); 615 return ret; 616 } 617 618 static int engine_setup_common(struct intel_engine_cs *engine) 619 { 620 int err; 621 622 init_llist_head(&engine->barrier_tasks); 623 624 err = init_status_page(engine); 625 if (err) 626 return err; 627 628 intel_engine_init_active(engine, ENGINE_PHYSICAL); 629 intel_engine_init_breadcrumbs(engine); 630 intel_engine_init_execlists(engine); 631 intel_engine_init_cmd_parser(engine); 632 intel_engine_init__pm(engine); 633 intel_engine_init_retire(engine); 634 635 /* Use the whole device by default */ 636 engine->sseu = 637 intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu); 638 639 intel_engine_init_workarounds(engine); 640 intel_engine_init_whitelist(engine); 641 intel_engine_init_ctx_wa(engine); 642 643 return 0; 644 } 645 646 struct measure_breadcrumb { 647 struct i915_request rq; 648 struct intel_ring ring; 649 u32 cs[1024]; 650 }; 651 652 static int measure_breadcrumb_dw(struct intel_context *ce) 653 { 654 struct intel_engine_cs *engine = ce->engine; 655 struct measure_breadcrumb *frame; 656 int dw; 657 658 GEM_BUG_ON(!engine->gt->scratch); 659 660 frame = kzalloc(sizeof(*frame), GFP_KERNEL); 661 if (!frame) 662 return -ENOMEM; 663 664 frame->rq.i915 = engine->i915; 665 frame->rq.engine = engine; 666 frame->rq.context = ce; 667 rcu_assign_pointer(frame->rq.timeline, ce->timeline); 668 669 frame->ring.vaddr = frame->cs; 670 frame->ring.size = sizeof(frame->cs); 671 frame->ring.effective_size = frame->ring.size; 672 intel_ring_update_space(&frame->ring); 673 frame->rq.ring = &frame->ring; 674 675 mutex_lock(&ce->timeline->mutex); 676 spin_lock_irq(&engine->active.lock); 677 678 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs; 679 680 spin_unlock_irq(&engine->active.lock); 681 mutex_unlock(&ce->timeline->mutex); 682 683 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */ 684 685 kfree(frame); 686 return dw; 687 } 688 689 void 690 intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass) 691 { 692 INIT_LIST_HEAD(&engine->active.requests); 693 INIT_LIST_HEAD(&engine->active.hold); 694 695 spin_lock_init(&engine->active.lock); 696 lockdep_set_subclass(&engine->active.lock, subclass); 697 698 /* 699 * Due to an interesting quirk in lockdep's internal debug tracking, 700 * after setting a subclass we must ensure the lock is used. Otherwise, 701 * nr_unused_locks is incremented once too often. 702 */ 703 #ifdef CONFIG_DEBUG_LOCK_ALLOC 704 local_irq_disable(); 705 lock_map_acquire(&engine->active.lock.dep_map); 706 lock_map_release(&engine->active.lock.dep_map); 707 local_irq_enable(); 708 #endif 709 } 710 711 static struct intel_context * 712 create_kernel_context(struct intel_engine_cs *engine) 713 { 714 static struct lock_class_key kernel; 715 struct intel_context *ce; 716 int err; 717 718 ce = intel_context_create(engine); 719 if (IS_ERR(ce)) 720 return ce; 721 722 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags); 723 724 err = intel_context_pin(ce); /* perma-pin so it is always available */ 725 if (err) { 726 intel_context_put(ce); 727 return ERR_PTR(err); 728 } 729 730 /* 731 * Give our perma-pinned kernel timelines a separate lockdep class, 732 * so that we can use them from within the normal user timelines 733 * should we need to inject GPU operations during their request 734 * construction. 735 */ 736 lockdep_set_class(&ce->timeline->mutex, &kernel); 737 738 return ce; 739 } 740 741 /** 742 * intel_engines_init_common - initialize cengine state which might require hw access 743 * @engine: Engine to initialize. 744 * 745 * Initializes @engine@ structure members shared between legacy and execlists 746 * submission modes which do require hardware access. 747 * 748 * Typcally done at later stages of submission mode specific engine setup. 749 * 750 * Returns zero on success or an error code on failure. 751 */ 752 static int engine_init_common(struct intel_engine_cs *engine) 753 { 754 struct intel_context *ce; 755 int ret; 756 757 engine->set_default_submission(engine); 758 759 /* 760 * We may need to do things with the shrinker which 761 * require us to immediately switch back to the default 762 * context. This can cause a problem as pinning the 763 * default context also requires GTT space which may not 764 * be available. To avoid this we always pin the default 765 * context. 766 */ 767 ce = create_kernel_context(engine); 768 if (IS_ERR(ce)) 769 return PTR_ERR(ce); 770 771 ret = measure_breadcrumb_dw(ce); 772 if (ret < 0) 773 goto err_context; 774 775 engine->emit_fini_breadcrumb_dw = ret; 776 engine->kernel_context = ce; 777 778 return 0; 779 780 err_context: 781 intel_context_put(ce); 782 return ret; 783 } 784 785 int intel_engines_init(struct intel_gt *gt) 786 { 787 int (*setup)(struct intel_engine_cs *engine); 788 struct intel_engine_cs *engine; 789 enum intel_engine_id id; 790 int err; 791 792 if (HAS_EXECLISTS(gt->i915)) 793 setup = intel_execlists_submission_setup; 794 else 795 setup = intel_ring_submission_setup; 796 797 for_each_engine(engine, gt, id) { 798 err = engine_setup_common(engine); 799 if (err) 800 return err; 801 802 err = setup(engine); 803 if (err) 804 return err; 805 806 err = engine_init_common(engine); 807 if (err) 808 return err; 809 810 intel_engine_add_user(engine); 811 } 812 813 return 0; 814 } 815 816 /** 817 * intel_engines_cleanup_common - cleans up the engine state created by 818 * the common initiailizers. 819 * @engine: Engine to cleanup. 820 * 821 * This cleans up everything created by the common helpers. 822 */ 823 void intel_engine_cleanup_common(struct intel_engine_cs *engine) 824 { 825 GEM_BUG_ON(!list_empty(&engine->active.requests)); 826 tasklet_kill(&engine->execlists.tasklet); /* flush the callback */ 827 828 cleanup_status_page(engine); 829 830 intel_engine_fini_retire(engine); 831 intel_engine_fini_breadcrumbs(engine); 832 intel_engine_cleanup_cmd_parser(engine); 833 834 if (engine->default_state) 835 fput(engine->default_state); 836 837 if (engine->kernel_context) { 838 intel_context_unpin(engine->kernel_context); 839 intel_context_put(engine->kernel_context); 840 } 841 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks)); 842 843 intel_wa_list_free(&engine->ctx_wa_list); 844 intel_wa_list_free(&engine->wa_list); 845 intel_wa_list_free(&engine->whitelist); 846 } 847 848 /** 849 * intel_engine_resume - re-initializes the HW state of the engine 850 * @engine: Engine to resume. 851 * 852 * Returns zero on success or an error code on failure. 853 */ 854 int intel_engine_resume(struct intel_engine_cs *engine) 855 { 856 intel_engine_apply_workarounds(engine); 857 intel_engine_apply_whitelist(engine); 858 859 return engine->resume(engine); 860 } 861 862 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine) 863 { 864 struct drm_i915_private *i915 = engine->i915; 865 866 u64 acthd; 867 868 if (INTEL_GEN(i915) >= 8) 869 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW); 870 else if (INTEL_GEN(i915) >= 4) 871 acthd = ENGINE_READ(engine, RING_ACTHD); 872 else 873 acthd = ENGINE_READ(engine, ACTHD); 874 875 return acthd; 876 } 877 878 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine) 879 { 880 u64 bbaddr; 881 882 if (INTEL_GEN(engine->i915) >= 8) 883 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW); 884 else 885 bbaddr = ENGINE_READ(engine, RING_BBADDR); 886 887 return bbaddr; 888 } 889 890 static unsigned long stop_timeout(const struct intel_engine_cs *engine) 891 { 892 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */ 893 return 0; 894 895 /* 896 * If we are doing a normal GPU reset, we can take our time and allow 897 * the engine to quiesce. We've stopped submission to the engine, and 898 * if we wait long enough an innocent context should complete and 899 * leave the engine idle. So they should not be caught unaware by 900 * the forthcoming GPU reset (which usually follows the stop_cs)! 901 */ 902 return READ_ONCE(engine->props.stop_timeout_ms); 903 } 904 905 int intel_engine_stop_cs(struct intel_engine_cs *engine) 906 { 907 struct intel_uncore *uncore = engine->uncore; 908 const u32 base = engine->mmio_base; 909 const i915_reg_t mode = RING_MI_MODE(base); 910 int err; 911 912 if (INTEL_GEN(engine->i915) < 3) 913 return -ENODEV; 914 915 ENGINE_TRACE(engine, "\n"); 916 917 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); 918 919 err = 0; 920 if (__intel_wait_for_register_fw(uncore, 921 mode, MODE_IDLE, MODE_IDLE, 922 1000, stop_timeout(engine), 923 NULL)) { 924 ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n"); 925 err = -ETIMEDOUT; 926 } 927 928 /* A final mmio read to let GPU writes be hopefully flushed to memory */ 929 intel_uncore_posting_read_fw(uncore, mode); 930 931 return err; 932 } 933 934 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) 935 { 936 ENGINE_TRACE(engine, "\n"); 937 938 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); 939 } 940 941 const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 942 { 943 switch (type) { 944 case I915_CACHE_NONE: return " uncached"; 945 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 946 case I915_CACHE_L3_LLC: return " L3+LLC"; 947 case I915_CACHE_WT: return " WT"; 948 default: return ""; 949 } 950 } 951 952 static u32 953 read_subslice_reg(const struct intel_engine_cs *engine, 954 int slice, int subslice, i915_reg_t reg) 955 { 956 struct drm_i915_private *i915 = engine->i915; 957 struct intel_uncore *uncore = engine->uncore; 958 u32 mcr_mask, mcr_ss, mcr, old_mcr, val; 959 enum forcewake_domains fw_domains; 960 961 if (INTEL_GEN(i915) >= 11) { 962 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 963 mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 964 } else { 965 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 966 mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 967 } 968 969 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, 970 FW_REG_READ); 971 fw_domains |= intel_uncore_forcewake_for_reg(uncore, 972 GEN8_MCR_SELECTOR, 973 FW_REG_READ | FW_REG_WRITE); 974 975 spin_lock_irq(&uncore->lock); 976 intel_uncore_forcewake_get__locked(uncore, fw_domains); 977 978 old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); 979 980 mcr &= ~mcr_mask; 981 mcr |= mcr_ss; 982 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); 983 984 val = intel_uncore_read_fw(uncore, reg); 985 986 mcr &= ~mcr_mask; 987 mcr |= old_mcr & mcr_mask; 988 989 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); 990 991 intel_uncore_forcewake_put__locked(uncore, fw_domains); 992 spin_unlock_irq(&uncore->lock); 993 994 return val; 995 } 996 997 /* NB: please notice the memset */ 998 void intel_engine_get_instdone(const struct intel_engine_cs *engine, 999 struct intel_instdone *instdone) 1000 { 1001 struct drm_i915_private *i915 = engine->i915; 1002 const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; 1003 struct intel_uncore *uncore = engine->uncore; 1004 u32 mmio_base = engine->mmio_base; 1005 int slice; 1006 int subslice; 1007 1008 memset(instdone, 0, sizeof(*instdone)); 1009 1010 switch (INTEL_GEN(i915)) { 1011 default: 1012 instdone->instdone = 1013 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1014 1015 if (engine->id != RCS0) 1016 break; 1017 1018 instdone->slice_common = 1019 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1020 if (INTEL_GEN(i915) >= 12) { 1021 instdone->slice_common_extra[0] = 1022 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA); 1023 instdone->slice_common_extra[1] = 1024 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2); 1025 } 1026 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) { 1027 instdone->sampler[slice][subslice] = 1028 read_subslice_reg(engine, slice, subslice, 1029 GEN7_SAMPLER_INSTDONE); 1030 instdone->row[slice][subslice] = 1031 read_subslice_reg(engine, slice, subslice, 1032 GEN7_ROW_INSTDONE); 1033 } 1034 break; 1035 case 7: 1036 instdone->instdone = 1037 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1038 1039 if (engine->id != RCS0) 1040 break; 1041 1042 instdone->slice_common = 1043 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1044 instdone->sampler[0][0] = 1045 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE); 1046 instdone->row[0][0] = 1047 intel_uncore_read(uncore, GEN7_ROW_INSTDONE); 1048 1049 break; 1050 case 6: 1051 case 5: 1052 case 4: 1053 instdone->instdone = 1054 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1055 if (engine->id == RCS0) 1056 /* HACK: Using the wrong struct member */ 1057 instdone->slice_common = 1058 intel_uncore_read(uncore, GEN4_INSTDONE1); 1059 break; 1060 case 3: 1061 case 2: 1062 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE); 1063 break; 1064 } 1065 } 1066 1067 static bool ring_is_idle(struct intel_engine_cs *engine) 1068 { 1069 bool idle = true; 1070 1071 if (I915_SELFTEST_ONLY(!engine->mmio_base)) 1072 return true; 1073 1074 if (!intel_engine_pm_get_if_awake(engine)) 1075 return true; 1076 1077 /* First check that no commands are left in the ring */ 1078 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) != 1079 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR)) 1080 idle = false; 1081 1082 /* No bit for gen2, so assume the CS parser is idle */ 1083 if (INTEL_GEN(engine->i915) > 2 && 1084 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE)) 1085 idle = false; 1086 1087 intel_engine_pm_put(engine); 1088 1089 return idle; 1090 } 1091 1092 void intel_engine_flush_submission(struct intel_engine_cs *engine) 1093 { 1094 struct tasklet_struct *t = &engine->execlists.tasklet; 1095 1096 if (__tasklet_is_scheduled(t)) { 1097 local_bh_disable(); 1098 if (tasklet_trylock(t)) { 1099 /* Must wait for any GPU reset in progress. */ 1100 if (__tasklet_is_enabled(t)) 1101 t->func(t->data); 1102 tasklet_unlock(t); 1103 } 1104 local_bh_enable(); 1105 } 1106 1107 /* Otherwise flush the tasklet if it was running on another cpu */ 1108 tasklet_unlock_wait(t); 1109 } 1110 1111 /** 1112 * intel_engine_is_idle() - Report if the engine has finished process all work 1113 * @engine: the intel_engine_cs 1114 * 1115 * Return true if there are no requests pending, nothing left to be submitted 1116 * to hardware, and that the engine is idle. 1117 */ 1118 bool intel_engine_is_idle(struct intel_engine_cs *engine) 1119 { 1120 /* More white lies, if wedged, hw state is inconsistent */ 1121 if (intel_gt_is_wedged(engine->gt)) 1122 return true; 1123 1124 if (!intel_engine_pm_is_awake(engine)) 1125 return true; 1126 1127 /* Waiting to drain ELSP? */ 1128 if (execlists_active(&engine->execlists)) { 1129 synchronize_hardirq(engine->i915->drm.pdev->irq); 1130 1131 intel_engine_flush_submission(engine); 1132 1133 if (execlists_active(&engine->execlists)) 1134 return false; 1135 } 1136 1137 /* ELSP is empty, but there are ready requests? E.g. after reset */ 1138 if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)) 1139 return false; 1140 1141 /* Ring stopped? */ 1142 return ring_is_idle(engine); 1143 } 1144 1145 bool intel_engines_are_idle(struct intel_gt *gt) 1146 { 1147 struct intel_engine_cs *engine; 1148 enum intel_engine_id id; 1149 1150 /* 1151 * If the driver is wedged, HW state may be very inconsistent and 1152 * report that it is still busy, even though we have stopped using it. 1153 */ 1154 if (intel_gt_is_wedged(gt)) 1155 return true; 1156 1157 /* Already parked (and passed an idleness test); must still be idle */ 1158 if (!READ_ONCE(gt->awake)) 1159 return true; 1160 1161 for_each_engine(engine, gt, id) { 1162 if (!intel_engine_is_idle(engine)) 1163 return false; 1164 } 1165 1166 return true; 1167 } 1168 1169 void intel_engines_reset_default_submission(struct intel_gt *gt) 1170 { 1171 struct intel_engine_cs *engine; 1172 enum intel_engine_id id; 1173 1174 for_each_engine(engine, gt, id) 1175 engine->set_default_submission(engine); 1176 } 1177 1178 bool intel_engine_can_store_dword(struct intel_engine_cs *engine) 1179 { 1180 switch (INTEL_GEN(engine->i915)) { 1181 case 2: 1182 return false; /* uses physical not virtual addresses */ 1183 case 3: 1184 /* maybe only uses physical not virtual addresses */ 1185 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); 1186 case 4: 1187 return !IS_I965G(engine->i915); /* who knows! */ 1188 case 6: 1189 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ 1190 default: 1191 return true; 1192 } 1193 } 1194 1195 static int print_sched_attr(struct drm_i915_private *i915, 1196 const struct i915_sched_attr *attr, 1197 char *buf, int x, int len) 1198 { 1199 if (attr->priority == I915_PRIORITY_INVALID) 1200 return x; 1201 1202 x += snprintf(buf + x, len - x, 1203 " prio=%d", attr->priority); 1204 1205 return x; 1206 } 1207 1208 static void print_request(struct drm_printer *m, 1209 struct i915_request *rq, 1210 const char *prefix) 1211 { 1212 const char *name = rq->fence.ops->get_timeline_name(&rq->fence); 1213 char buf[80] = ""; 1214 int x = 0; 1215 1216 x = print_sched_attr(rq->i915, &rq->sched.attr, buf, x, sizeof(buf)); 1217 1218 drm_printf(m, "%s %llx:%llx%s%s %s @ %dms: %s\n", 1219 prefix, 1220 rq->fence.context, rq->fence.seqno, 1221 i915_request_completed(rq) ? "!" : 1222 i915_request_started(rq) ? "*" : 1223 "", 1224 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 1225 &rq->fence.flags) ? "+" : 1226 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 1227 &rq->fence.flags) ? "-" : 1228 "", 1229 buf, 1230 jiffies_to_msecs(jiffies - rq->emitted_jiffies), 1231 name); 1232 } 1233 1234 static struct intel_timeline *get_timeline(struct i915_request *rq) 1235 { 1236 struct intel_timeline *tl; 1237 1238 /* 1239 * Even though we are holding the engine->active.lock here, there 1240 * is no control over the submission queue per-se and we are 1241 * inspecting the active state at a random point in time, with an 1242 * unknown queue. Play safe and make sure the timeline remains valid. 1243 * (Only being used for pretty printing, one extra kref shouldn't 1244 * cause a camel stampede!) 1245 */ 1246 rcu_read_lock(); 1247 tl = rcu_dereference(rq->timeline); 1248 if (!kref_get_unless_zero(&tl->kref)) 1249 tl = NULL; 1250 rcu_read_unlock(); 1251 1252 return tl; 1253 } 1254 1255 static int print_ring(char *buf, int sz, struct i915_request *rq) 1256 { 1257 int len = 0; 1258 1259 if (!i915_request_signaled(rq)) { 1260 struct intel_timeline *tl = get_timeline(rq); 1261 1262 len = scnprintf(buf, sz, 1263 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ", 1264 i915_ggtt_offset(rq->ring->vma), 1265 tl ? tl->hwsp_offset : 0, 1266 hwsp_seqno(rq), 1267 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context), 1268 1000 * 1000)); 1269 1270 if (tl) 1271 intel_timeline_put(tl); 1272 } 1273 1274 return len; 1275 } 1276 1277 static void hexdump(struct drm_printer *m, const void *buf, size_t len) 1278 { 1279 const size_t rowsize = 8 * sizeof(u32); 1280 const void *prev = NULL; 1281 bool skip = false; 1282 size_t pos; 1283 1284 for (pos = 0; pos < len; pos += rowsize) { 1285 char line[128]; 1286 1287 if (prev && !memcmp(prev, buf + pos, rowsize)) { 1288 if (!skip) { 1289 drm_printf(m, "*\n"); 1290 skip = true; 1291 } 1292 continue; 1293 } 1294 1295 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos, 1296 rowsize, sizeof(u32), 1297 line, sizeof(line), 1298 false) >= sizeof(line)); 1299 drm_printf(m, "[%04zx] %s\n", pos, line); 1300 1301 prev = buf + pos; 1302 skip = false; 1303 } 1304 } 1305 1306 static const char *repr_timer(const struct timer_list *t) 1307 { 1308 if (!READ_ONCE(t->expires)) 1309 return "inactive"; 1310 1311 if (timer_pending(t)) 1312 return "active"; 1313 1314 return "expired"; 1315 } 1316 1317 static void intel_engine_print_registers(struct intel_engine_cs *engine, 1318 struct drm_printer *m) 1319 { 1320 struct drm_i915_private *dev_priv = engine->i915; 1321 struct intel_engine_execlists * const execlists = &engine->execlists; 1322 u64 addr; 1323 1324 if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7)) 1325 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID)); 1326 if (HAS_EXECLISTS(dev_priv)) { 1327 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n", 1328 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI)); 1329 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n", 1330 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO)); 1331 } 1332 drm_printf(m, "\tRING_START: 0x%08x\n", 1333 ENGINE_READ(engine, RING_START)); 1334 drm_printf(m, "\tRING_HEAD: 0x%08x\n", 1335 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR); 1336 drm_printf(m, "\tRING_TAIL: 0x%08x\n", 1337 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR); 1338 drm_printf(m, "\tRING_CTL: 0x%08x%s\n", 1339 ENGINE_READ(engine, RING_CTL), 1340 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : ""); 1341 if (INTEL_GEN(engine->i915) > 2) { 1342 drm_printf(m, "\tRING_MODE: 0x%08x%s\n", 1343 ENGINE_READ(engine, RING_MI_MODE), 1344 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : ""); 1345 } 1346 1347 if (INTEL_GEN(dev_priv) >= 6) { 1348 drm_printf(m, "\tRING_IMR: 0x%08x\n", 1349 ENGINE_READ(engine, RING_IMR)); 1350 drm_printf(m, "\tRING_ESR: 0x%08x\n", 1351 ENGINE_READ(engine, RING_ESR)); 1352 drm_printf(m, "\tRING_EMR: 0x%08x\n", 1353 ENGINE_READ(engine, RING_EMR)); 1354 drm_printf(m, "\tRING_EIR: 0x%08x\n", 1355 ENGINE_READ(engine, RING_EIR)); 1356 } 1357 1358 addr = intel_engine_get_active_head(engine); 1359 drm_printf(m, "\tACTHD: 0x%08x_%08x\n", 1360 upper_32_bits(addr), lower_32_bits(addr)); 1361 addr = intel_engine_get_last_batch_head(engine); 1362 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n", 1363 upper_32_bits(addr), lower_32_bits(addr)); 1364 if (INTEL_GEN(dev_priv) >= 8) 1365 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW); 1366 else if (INTEL_GEN(dev_priv) >= 4) 1367 addr = ENGINE_READ(engine, RING_DMA_FADD); 1368 else 1369 addr = ENGINE_READ(engine, DMA_FADD_I8XX); 1370 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n", 1371 upper_32_bits(addr), lower_32_bits(addr)); 1372 if (INTEL_GEN(dev_priv) >= 4) { 1373 drm_printf(m, "\tIPEIR: 0x%08x\n", 1374 ENGINE_READ(engine, RING_IPEIR)); 1375 drm_printf(m, "\tIPEHR: 0x%08x\n", 1376 ENGINE_READ(engine, RING_IPEHR)); 1377 } else { 1378 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR)); 1379 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR)); 1380 } 1381 1382 if (HAS_EXECLISTS(dev_priv)) { 1383 struct i915_request * const *port, *rq; 1384 const u32 *hws = 1385 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; 1386 const u8 num_entries = execlists->csb_size; 1387 unsigned int idx; 1388 u8 read, write; 1389 1390 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n", 1391 yesno(test_bit(TASKLET_STATE_SCHED, 1392 &engine->execlists.tasklet.state)), 1393 enableddisabled(!atomic_read(&engine->execlists.tasklet.count)), 1394 repr_timer(&engine->execlists.preempt), 1395 repr_timer(&engine->execlists.timer)); 1396 1397 read = execlists->csb_head; 1398 write = READ_ONCE(*execlists->csb_write); 1399 1400 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n", 1401 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO), 1402 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI), 1403 read, write, num_entries); 1404 1405 if (read >= num_entries) 1406 read = 0; 1407 if (write >= num_entries) 1408 write = 0; 1409 if (read > write) 1410 write += num_entries; 1411 while (read < write) { 1412 idx = ++read % num_entries; 1413 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", 1414 idx, hws[idx * 2], hws[idx * 2 + 1]); 1415 } 1416 1417 execlists_active_lock_bh(execlists); 1418 rcu_read_lock(); 1419 for (port = execlists->active; (rq = *port); port++) { 1420 char hdr[160]; 1421 int len; 1422 1423 len = scnprintf(hdr, sizeof(hdr), 1424 "\t\tActive[%d]: ccid:%08x, ", 1425 (int)(port - execlists->active), 1426 rq->context->lrc.ccid); 1427 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1428 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1429 print_request(m, rq, hdr); 1430 } 1431 for (port = execlists->pending; (rq = *port); port++) { 1432 char hdr[160]; 1433 int len; 1434 1435 len = scnprintf(hdr, sizeof(hdr), 1436 "\t\tPending[%d]: ccid:%08x, ", 1437 (int)(port - execlists->pending), 1438 rq->context->lrc.ccid); 1439 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1440 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1441 print_request(m, rq, hdr); 1442 } 1443 rcu_read_unlock(); 1444 execlists_active_unlock_bh(execlists); 1445 } else if (INTEL_GEN(dev_priv) > 6) { 1446 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n", 1447 ENGINE_READ(engine, RING_PP_DIR_BASE)); 1448 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", 1449 ENGINE_READ(engine, RING_PP_DIR_BASE_READ)); 1450 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", 1451 ENGINE_READ(engine, RING_PP_DIR_DCLV)); 1452 } 1453 } 1454 1455 static void print_request_ring(struct drm_printer *m, struct i915_request *rq) 1456 { 1457 void *ring; 1458 int size; 1459 1460 drm_printf(m, 1461 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n", 1462 rq->head, rq->postfix, rq->tail, 1463 rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, 1464 rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); 1465 1466 size = rq->tail - rq->head; 1467 if (rq->tail < rq->head) 1468 size += rq->ring->size; 1469 1470 ring = kmalloc(size, GFP_ATOMIC); 1471 if (ring) { 1472 const void *vaddr = rq->ring->vaddr; 1473 unsigned int head = rq->head; 1474 unsigned int len = 0; 1475 1476 if (rq->tail < head) { 1477 len = rq->ring->size - head; 1478 memcpy(ring, vaddr + head, len); 1479 head = 0; 1480 } 1481 memcpy(ring + len, vaddr + head, size - len); 1482 1483 hexdump(m, ring, size); 1484 kfree(ring); 1485 } 1486 } 1487 1488 static unsigned long list_count(struct list_head *list) 1489 { 1490 struct list_head *pos; 1491 unsigned long count = 0; 1492 1493 list_for_each(pos, list) 1494 count++; 1495 1496 return count; 1497 } 1498 1499 void intel_engine_dump(struct intel_engine_cs *engine, 1500 struct drm_printer *m, 1501 const char *header, ...) 1502 { 1503 struct i915_gpu_error * const error = &engine->i915->gpu_error; 1504 struct i915_request *rq; 1505 intel_wakeref_t wakeref; 1506 unsigned long flags; 1507 1508 if (header) { 1509 va_list ap; 1510 1511 va_start(ap, header); 1512 drm_vprintf(m, header, &ap); 1513 va_end(ap); 1514 } 1515 1516 if (intel_gt_is_wedged(engine->gt)) 1517 drm_printf(m, "*** WEDGED ***\n"); 1518 1519 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count)); 1520 drm_printf(m, "\tBarriers?: %s\n", 1521 yesno(!llist_empty(&engine->barrier_tasks))); 1522 drm_printf(m, "\tLatency: %luus\n", 1523 ewma__engine_latency_read(&engine->latency)); 1524 1525 rcu_read_lock(); 1526 rq = READ_ONCE(engine->heartbeat.systole); 1527 if (rq) 1528 drm_printf(m, "\tHeartbeat: %d ms ago\n", 1529 jiffies_to_msecs(jiffies - rq->emitted_jiffies)); 1530 rcu_read_unlock(); 1531 drm_printf(m, "\tReset count: %d (global %d)\n", 1532 i915_reset_engine_count(error, engine), 1533 i915_reset_count(error)); 1534 1535 drm_printf(m, "\tRequests:\n"); 1536 1537 spin_lock_irqsave(&engine->active.lock, flags); 1538 rq = intel_engine_find_active_request(engine); 1539 if (rq) { 1540 struct intel_timeline *tl = get_timeline(rq); 1541 1542 print_request(m, rq, "\t\tactive "); 1543 1544 drm_printf(m, "\t\tring->start: 0x%08x\n", 1545 i915_ggtt_offset(rq->ring->vma)); 1546 drm_printf(m, "\t\tring->head: 0x%08x\n", 1547 rq->ring->head); 1548 drm_printf(m, "\t\tring->tail: 0x%08x\n", 1549 rq->ring->tail); 1550 drm_printf(m, "\t\tring->emit: 0x%08x\n", 1551 rq->ring->emit); 1552 drm_printf(m, "\t\tring->space: 0x%08x\n", 1553 rq->ring->space); 1554 1555 if (tl) { 1556 drm_printf(m, "\t\tring->hwsp: 0x%08x\n", 1557 tl->hwsp_offset); 1558 intel_timeline_put(tl); 1559 } 1560 1561 print_request_ring(m, rq); 1562 1563 if (rq->context->lrc_reg_state) { 1564 drm_printf(m, "Logical Ring Context:\n"); 1565 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE); 1566 } 1567 } 1568 drm_printf(m, "\tOn hold?: %lu\n", list_count(&engine->active.hold)); 1569 spin_unlock_irqrestore(&engine->active.lock, flags); 1570 1571 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base); 1572 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm); 1573 if (wakeref) { 1574 intel_engine_print_registers(engine, m); 1575 intel_runtime_pm_put(engine->uncore->rpm, wakeref); 1576 } else { 1577 drm_printf(m, "\tDevice is asleep; skipping register dump\n"); 1578 } 1579 1580 intel_execlists_show_requests(engine, m, print_request, 8); 1581 1582 drm_printf(m, "HWSP:\n"); 1583 hexdump(m, engine->status_page.addr, PAGE_SIZE); 1584 1585 drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine))); 1586 1587 intel_engine_print_breadcrumbs(engine, m); 1588 } 1589 1590 static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine) 1591 { 1592 ktime_t total = engine->stats.total; 1593 1594 /* 1595 * If the engine is executing something at the moment 1596 * add it to the total. 1597 */ 1598 if (atomic_read(&engine->stats.active)) 1599 total = ktime_add(total, 1600 ktime_sub(ktime_get(), engine->stats.start)); 1601 1602 return total; 1603 } 1604 1605 /** 1606 * intel_engine_get_busy_time() - Return current accumulated engine busyness 1607 * @engine: engine to report on 1608 * 1609 * Returns accumulated time @engine was busy since engine stats were enabled. 1610 */ 1611 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine) 1612 { 1613 unsigned int seq; 1614 ktime_t total; 1615 1616 do { 1617 seq = read_seqbegin(&engine->stats.lock); 1618 total = __intel_engine_get_busy_time(engine); 1619 } while (read_seqretry(&engine->stats.lock, seq)); 1620 1621 return total; 1622 } 1623 1624 static bool match_ring(struct i915_request *rq) 1625 { 1626 u32 ring = ENGINE_READ(rq->engine, RING_START); 1627 1628 return ring == i915_ggtt_offset(rq->ring->vma); 1629 } 1630 1631 struct i915_request * 1632 intel_engine_find_active_request(struct intel_engine_cs *engine) 1633 { 1634 struct i915_request *request, *active = NULL; 1635 1636 /* 1637 * We are called by the error capture, reset and to dump engine 1638 * state at random points in time. In particular, note that neither is 1639 * crucially ordered with an interrupt. After a hang, the GPU is dead 1640 * and we assume that no more writes can happen (we waited long enough 1641 * for all writes that were in transaction to be flushed) - adding an 1642 * extra delay for a recent interrupt is pointless. Hence, we do 1643 * not need an engine->irq_seqno_barrier() before the seqno reads. 1644 * At all other times, we must assume the GPU is still running, but 1645 * we only care about the snapshot of this moment. 1646 */ 1647 lockdep_assert_held(&engine->active.lock); 1648 1649 rcu_read_lock(); 1650 request = execlists_active(&engine->execlists); 1651 if (request) { 1652 struct intel_timeline *tl = request->context->timeline; 1653 1654 list_for_each_entry_from_reverse(request, &tl->requests, link) { 1655 if (i915_request_completed(request)) 1656 break; 1657 1658 active = request; 1659 } 1660 } 1661 rcu_read_unlock(); 1662 if (active) 1663 return active; 1664 1665 list_for_each_entry(request, &engine->active.requests, sched.link) { 1666 if (i915_request_completed(request)) 1667 continue; 1668 1669 if (!i915_request_started(request)) 1670 continue; 1671 1672 /* More than one preemptible request may match! */ 1673 if (!match_ring(request)) 1674 continue; 1675 1676 active = request; 1677 break; 1678 } 1679 1680 return active; 1681 } 1682 1683 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 1684 #include "mock_engine.c" 1685 #include "selftest_engine.c" 1686 #include "selftest_engine_cs.c" 1687 #endif 1688