1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2016 Intel Corporation
4  */
5 
6 #include <linux/string_helpers.h>
7 
8 #include <drm/drm_print.h>
9 
10 #include "gem/i915_gem_context.h"
11 #include "gem/i915_gem_internal.h"
12 #include "gt/intel_gt_regs.h"
13 
14 #include "i915_cmd_parser.h"
15 #include "i915_drv.h"
16 #include "intel_breadcrumbs.h"
17 #include "intel_context.h"
18 #include "intel_engine.h"
19 #include "intel_engine_pm.h"
20 #include "intel_engine_regs.h"
21 #include "intel_engine_user.h"
22 #include "intel_execlists_submission.h"
23 #include "intel_gt.h"
24 #include "intel_gt_mcr.h"
25 #include "intel_gt_pm.h"
26 #include "intel_gt_requests.h"
27 #include "intel_lrc.h"
28 #include "intel_lrc_reg.h"
29 #include "intel_reset.h"
30 #include "intel_ring.h"
31 #include "uc/intel_guc_submission.h"
32 
33 /* Haswell does have the CXT_SIZE register however it does not appear to be
34  * valid. Now, docs explain in dwords what is in the context object. The full
35  * size is 70720 bytes, however, the power context and execlist context will
36  * never be saved (power context is stored elsewhere, and execlists don't work
37  * on HSW) - so the final size, including the extra state required for the
38  * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
39  */
40 #define HSW_CXT_TOTAL_SIZE		(17 * PAGE_SIZE)
41 
42 #define DEFAULT_LR_CONTEXT_RENDER_SIZE	(22 * PAGE_SIZE)
43 #define GEN8_LR_CONTEXT_RENDER_SIZE	(20 * PAGE_SIZE)
44 #define GEN9_LR_CONTEXT_RENDER_SIZE	(22 * PAGE_SIZE)
45 #define GEN11_LR_CONTEXT_RENDER_SIZE	(14 * PAGE_SIZE)
46 
47 #define GEN8_LR_CONTEXT_OTHER_SIZE	( 2 * PAGE_SIZE)
48 
49 #define MAX_MMIO_BASES 3
50 struct engine_info {
51 	u8 class;
52 	u8 instance;
53 	/* mmio bases table *must* be sorted in reverse graphics_ver order */
54 	struct engine_mmio_base {
55 		u32 graphics_ver : 8;
56 		u32 base : 24;
57 	} mmio_bases[MAX_MMIO_BASES];
58 };
59 
60 static const struct engine_info intel_engines[] = {
61 	[RCS0] = {
62 		.class = RENDER_CLASS,
63 		.instance = 0,
64 		.mmio_bases = {
65 			{ .graphics_ver = 1, .base = RENDER_RING_BASE }
66 		},
67 	},
68 	[BCS0] = {
69 		.class = COPY_ENGINE_CLASS,
70 		.instance = 0,
71 		.mmio_bases = {
72 			{ .graphics_ver = 6, .base = BLT_RING_BASE }
73 		},
74 	},
75 	[BCS1] = {
76 		.class = COPY_ENGINE_CLASS,
77 		.instance = 1,
78 		.mmio_bases = {
79 			{ .graphics_ver = 12, .base = XEHPC_BCS1_RING_BASE }
80 		},
81 	},
82 	[BCS2] = {
83 		.class = COPY_ENGINE_CLASS,
84 		.instance = 2,
85 		.mmio_bases = {
86 			{ .graphics_ver = 12, .base = XEHPC_BCS2_RING_BASE }
87 		},
88 	},
89 	[BCS3] = {
90 		.class = COPY_ENGINE_CLASS,
91 		.instance = 3,
92 		.mmio_bases = {
93 			{ .graphics_ver = 12, .base = XEHPC_BCS3_RING_BASE }
94 		},
95 	},
96 	[BCS4] = {
97 		.class = COPY_ENGINE_CLASS,
98 		.instance = 4,
99 		.mmio_bases = {
100 			{ .graphics_ver = 12, .base = XEHPC_BCS4_RING_BASE }
101 		},
102 	},
103 	[BCS5] = {
104 		.class = COPY_ENGINE_CLASS,
105 		.instance = 5,
106 		.mmio_bases = {
107 			{ .graphics_ver = 12, .base = XEHPC_BCS5_RING_BASE }
108 		},
109 	},
110 	[BCS6] = {
111 		.class = COPY_ENGINE_CLASS,
112 		.instance = 6,
113 		.mmio_bases = {
114 			{ .graphics_ver = 12, .base = XEHPC_BCS6_RING_BASE }
115 		},
116 	},
117 	[BCS7] = {
118 		.class = COPY_ENGINE_CLASS,
119 		.instance = 7,
120 		.mmio_bases = {
121 			{ .graphics_ver = 12, .base = XEHPC_BCS7_RING_BASE }
122 		},
123 	},
124 	[BCS8] = {
125 		.class = COPY_ENGINE_CLASS,
126 		.instance = 8,
127 		.mmio_bases = {
128 			{ .graphics_ver = 12, .base = XEHPC_BCS8_RING_BASE }
129 		},
130 	},
131 	[VCS0] = {
132 		.class = VIDEO_DECODE_CLASS,
133 		.instance = 0,
134 		.mmio_bases = {
135 			{ .graphics_ver = 11, .base = GEN11_BSD_RING_BASE },
136 			{ .graphics_ver = 6, .base = GEN6_BSD_RING_BASE },
137 			{ .graphics_ver = 4, .base = BSD_RING_BASE }
138 		},
139 	},
140 	[VCS1] = {
141 		.class = VIDEO_DECODE_CLASS,
142 		.instance = 1,
143 		.mmio_bases = {
144 			{ .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE },
145 			{ .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE }
146 		},
147 	},
148 	[VCS2] = {
149 		.class = VIDEO_DECODE_CLASS,
150 		.instance = 2,
151 		.mmio_bases = {
152 			{ .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE }
153 		},
154 	},
155 	[VCS3] = {
156 		.class = VIDEO_DECODE_CLASS,
157 		.instance = 3,
158 		.mmio_bases = {
159 			{ .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
160 		},
161 	},
162 	[VCS4] = {
163 		.class = VIDEO_DECODE_CLASS,
164 		.instance = 4,
165 		.mmio_bases = {
166 			{ .graphics_ver = 12, .base = XEHP_BSD5_RING_BASE }
167 		},
168 	},
169 	[VCS5] = {
170 		.class = VIDEO_DECODE_CLASS,
171 		.instance = 5,
172 		.mmio_bases = {
173 			{ .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE }
174 		},
175 	},
176 	[VCS6] = {
177 		.class = VIDEO_DECODE_CLASS,
178 		.instance = 6,
179 		.mmio_bases = {
180 			{ .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE }
181 		},
182 	},
183 	[VCS7] = {
184 		.class = VIDEO_DECODE_CLASS,
185 		.instance = 7,
186 		.mmio_bases = {
187 			{ .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE }
188 		},
189 	},
190 	[VECS0] = {
191 		.class = VIDEO_ENHANCEMENT_CLASS,
192 		.instance = 0,
193 		.mmio_bases = {
194 			{ .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE },
195 			{ .graphics_ver = 7, .base = VEBOX_RING_BASE }
196 		},
197 	},
198 	[VECS1] = {
199 		.class = VIDEO_ENHANCEMENT_CLASS,
200 		.instance = 1,
201 		.mmio_bases = {
202 			{ .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE }
203 		},
204 	},
205 	[VECS2] = {
206 		.class = VIDEO_ENHANCEMENT_CLASS,
207 		.instance = 2,
208 		.mmio_bases = {
209 			{ .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE }
210 		},
211 	},
212 	[VECS3] = {
213 		.class = VIDEO_ENHANCEMENT_CLASS,
214 		.instance = 3,
215 		.mmio_bases = {
216 			{ .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
217 		},
218 	},
219 	[CCS0] = {
220 		.class = COMPUTE_CLASS,
221 		.instance = 0,
222 		.mmio_bases = {
223 			{ .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }
224 		}
225 	},
226 	[CCS1] = {
227 		.class = COMPUTE_CLASS,
228 		.instance = 1,
229 		.mmio_bases = {
230 			{ .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }
231 		}
232 	},
233 	[CCS2] = {
234 		.class = COMPUTE_CLASS,
235 		.instance = 2,
236 		.mmio_bases = {
237 			{ .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }
238 		}
239 	},
240 	[CCS3] = {
241 		.class = COMPUTE_CLASS,
242 		.instance = 3,
243 		.mmio_bases = {
244 			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
245 		}
246 	},
247 };
248 
249 /**
250  * intel_engine_context_size() - return the size of the context for an engine
251  * @gt: the gt
252  * @class: engine class
253  *
254  * Each engine class may require a different amount of space for a context
255  * image.
256  *
257  * Return: size (in bytes) of an engine class specific context image
258  *
259  * Note: this size includes the HWSP, which is part of the context image
260  * in LRC mode, but does not include the "shared data page" used with
261  * GuC submission. The caller should account for this if using the GuC.
262  */
263 u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
264 {
265 	struct intel_uncore *uncore = gt->uncore;
266 	u32 cxt_size;
267 
268 	BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
269 
270 	switch (class) {
271 	case COMPUTE_CLASS:
272 		fallthrough;
273 	case RENDER_CLASS:
274 		switch (GRAPHICS_VER(gt->i915)) {
275 		default:
276 			MISSING_CASE(GRAPHICS_VER(gt->i915));
277 			return DEFAULT_LR_CONTEXT_RENDER_SIZE;
278 		case 12:
279 		case 11:
280 			return GEN11_LR_CONTEXT_RENDER_SIZE;
281 		case 9:
282 			return GEN9_LR_CONTEXT_RENDER_SIZE;
283 		case 8:
284 			return GEN8_LR_CONTEXT_RENDER_SIZE;
285 		case 7:
286 			if (IS_HASWELL(gt->i915))
287 				return HSW_CXT_TOTAL_SIZE;
288 
289 			cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
290 			return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
291 					PAGE_SIZE);
292 		case 6:
293 			cxt_size = intel_uncore_read(uncore, CXT_SIZE);
294 			return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
295 					PAGE_SIZE);
296 		case 5:
297 		case 4:
298 			/*
299 			 * There is a discrepancy here between the size reported
300 			 * by the register and the size of the context layout
301 			 * in the docs. Both are described as authorative!
302 			 *
303 			 * The discrepancy is on the order of a few cachelines,
304 			 * but the total is under one page (4k), which is our
305 			 * minimum allocation anyway so it should all come
306 			 * out in the wash.
307 			 */
308 			cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
309 			drm_dbg(&gt->i915->drm,
310 				"graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",
311 				GRAPHICS_VER(gt->i915), cxt_size * 64,
312 				cxt_size - 1);
313 			return round_up(cxt_size * 64, PAGE_SIZE);
314 		case 3:
315 		case 2:
316 		/* For the special day when i810 gets merged. */
317 		case 1:
318 			return 0;
319 		}
320 		break;
321 	default:
322 		MISSING_CASE(class);
323 		fallthrough;
324 	case VIDEO_DECODE_CLASS:
325 	case VIDEO_ENHANCEMENT_CLASS:
326 	case COPY_ENGINE_CLASS:
327 		if (GRAPHICS_VER(gt->i915) < 8)
328 			return 0;
329 		return GEN8_LR_CONTEXT_OTHER_SIZE;
330 	}
331 }
332 
333 static u32 __engine_mmio_base(struct drm_i915_private *i915,
334 			      const struct engine_mmio_base *bases)
335 {
336 	int i;
337 
338 	for (i = 0; i < MAX_MMIO_BASES; i++)
339 		if (GRAPHICS_VER(i915) >= bases[i].graphics_ver)
340 			break;
341 
342 	GEM_BUG_ON(i == MAX_MMIO_BASES);
343 	GEM_BUG_ON(!bases[i].base);
344 
345 	return bases[i].base;
346 }
347 
348 static void __sprint_engine_name(struct intel_engine_cs *engine)
349 {
350 	/*
351 	 * Before we know what the uABI name for this engine will be,
352 	 * we still would like to keep track of this engine in the debug logs.
353 	 * We throw in a ' here as a reminder that this isn't its final name.
354 	 */
355 	GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",
356 			     intel_engine_class_repr(engine->class),
357 			     engine->instance) >= sizeof(engine->name));
358 }
359 
360 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
361 {
362 	/*
363 	 * Though they added more rings on g4x/ilk, they did not add
364 	 * per-engine HWSTAM until gen6.
365 	 */
366 	if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)
367 		return;
368 
369 	if (GRAPHICS_VER(engine->i915) >= 3)
370 		ENGINE_WRITE(engine, RING_HWSTAM, mask);
371 	else
372 		ENGINE_WRITE16(engine, RING_HWSTAM, mask);
373 }
374 
375 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
376 {
377 	/* Mask off all writes into the unknown HWSP */
378 	intel_engine_set_hwsp_writemask(engine, ~0u);
379 }
380 
381 static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir)
382 {
383 	GEM_DEBUG_WARN_ON(iir);
384 }
385 
386 static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
387 {
388 	u32 reset_domain;
389 
390 	if (ver >= 11) {
391 		static const u32 engine_reset_domains[] = {
392 			[RCS0]  = GEN11_GRDOM_RENDER,
393 			[BCS0]  = GEN11_GRDOM_BLT,
394 			[BCS1]  = XEHPC_GRDOM_BLT1,
395 			[BCS2]  = XEHPC_GRDOM_BLT2,
396 			[BCS3]  = XEHPC_GRDOM_BLT3,
397 			[BCS4]  = XEHPC_GRDOM_BLT4,
398 			[BCS5]  = XEHPC_GRDOM_BLT5,
399 			[BCS6]  = XEHPC_GRDOM_BLT6,
400 			[BCS7]  = XEHPC_GRDOM_BLT7,
401 			[BCS8]  = XEHPC_GRDOM_BLT8,
402 			[VCS0]  = GEN11_GRDOM_MEDIA,
403 			[VCS1]  = GEN11_GRDOM_MEDIA2,
404 			[VCS2]  = GEN11_GRDOM_MEDIA3,
405 			[VCS3]  = GEN11_GRDOM_MEDIA4,
406 			[VCS4]  = GEN11_GRDOM_MEDIA5,
407 			[VCS5]  = GEN11_GRDOM_MEDIA6,
408 			[VCS6]  = GEN11_GRDOM_MEDIA7,
409 			[VCS7]  = GEN11_GRDOM_MEDIA8,
410 			[VECS0] = GEN11_GRDOM_VECS,
411 			[VECS1] = GEN11_GRDOM_VECS2,
412 			[VECS2] = GEN11_GRDOM_VECS3,
413 			[VECS3] = GEN11_GRDOM_VECS4,
414 			[CCS0]  = GEN11_GRDOM_RENDER,
415 			[CCS1]  = GEN11_GRDOM_RENDER,
416 			[CCS2]  = GEN11_GRDOM_RENDER,
417 			[CCS3]  = GEN11_GRDOM_RENDER,
418 		};
419 		GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
420 			   !engine_reset_domains[id]);
421 		reset_domain = engine_reset_domains[id];
422 	} else {
423 		static const u32 engine_reset_domains[] = {
424 			[RCS0]  = GEN6_GRDOM_RENDER,
425 			[BCS0]  = GEN6_GRDOM_BLT,
426 			[VCS0]  = GEN6_GRDOM_MEDIA,
427 			[VCS1]  = GEN8_GRDOM_MEDIA2,
428 			[VECS0] = GEN6_GRDOM_VECS,
429 		};
430 		GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
431 			   !engine_reset_domains[id]);
432 		reset_domain = engine_reset_domains[id];
433 	}
434 
435 	return reset_domain;
436 }
437 
438 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
439 			      u8 logical_instance)
440 {
441 	const struct engine_info *info = &intel_engines[id];
442 	struct drm_i915_private *i915 = gt->i915;
443 	struct intel_engine_cs *engine;
444 	u8 guc_class;
445 
446 	BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
447 	BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
448 	BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1));
449 	BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1));
450 
451 	if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
452 		return -EINVAL;
453 
454 	if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
455 		return -EINVAL;
456 
457 	if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
458 		return -EINVAL;
459 
460 	if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))
461 		return -EINVAL;
462 
463 	engine = kzalloc(sizeof(*engine), GFP_KERNEL);
464 	if (!engine)
465 		return -ENOMEM;
466 
467 	BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
468 
469 	INIT_LIST_HEAD(&engine->pinned_contexts_list);
470 	engine->id = id;
471 	engine->legacy_idx = INVALID_ENGINE;
472 	engine->mask = BIT(id);
473 	engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915),
474 						id);
475 	engine->i915 = i915;
476 	engine->gt = gt;
477 	engine->uncore = gt->uncore;
478 	guc_class = engine_class_to_guc_class(info->class);
479 	engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);
480 	engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
481 
482 	engine->irq_handler = nop_irq_handler;
483 
484 	engine->class = info->class;
485 	engine->instance = info->instance;
486 	engine->logical_mask = BIT(logical_instance);
487 	__sprint_engine_name(engine);
488 
489 	if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) &&
490 	     __ffs(CCS_MASK(engine->gt)) == engine->instance) ||
491 	     engine->class == RENDER_CLASS)
492 		engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE;
493 
494 	/* features common between engines sharing EUs */
495 	if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
496 		engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
497 		engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
498 	}
499 
500 	engine->props.heartbeat_interval_ms =
501 		CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
502 	engine->props.max_busywait_duration_ns =
503 		CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT;
504 	engine->props.preempt_timeout_ms =
505 		CONFIG_DRM_I915_PREEMPT_TIMEOUT;
506 	engine->props.stop_timeout_ms =
507 		CONFIG_DRM_I915_STOP_TIMEOUT;
508 	engine->props.timeslice_duration_ms =
509 		CONFIG_DRM_I915_TIMESLICE_DURATION;
510 
511 	/*
512 	 * Mid-thread pre-emption is not available in Gen12. Unfortunately,
513 	 * some compute workloads run quite long threads. That means they get
514 	 * reset due to not pre-empting in a timely manner. So, bump the
515 	 * pre-emption timeout value to be much higher for compute engines.
516 	 */
517 	if (GRAPHICS_VER(i915) == 12 && (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
518 		engine->props.preempt_timeout_ms = CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE;
519 
520 	/* Cap properties according to any system limits */
521 #define CLAMP_PROP(field) \
522 	do { \
523 		u64 clamp = intel_clamp_##field(engine, engine->props.field); \
524 		if (clamp != engine->props.field) { \
525 			drm_notice(&engine->i915->drm, \
526 				   "Warning, clamping %s to %lld to prevent overflow\n", \
527 				   #field, clamp); \
528 			engine->props.field = clamp; \
529 		} \
530 	} while (0)
531 
532 	CLAMP_PROP(heartbeat_interval_ms);
533 	CLAMP_PROP(max_busywait_duration_ns);
534 	CLAMP_PROP(preempt_timeout_ms);
535 	CLAMP_PROP(stop_timeout_ms);
536 	CLAMP_PROP(timeslice_duration_ms);
537 
538 #undef CLAMP_PROP
539 
540 	engine->defaults = engine->props; /* never to change again */
541 
542 	engine->context_size = intel_engine_context_size(gt, engine->class);
543 	if (WARN_ON(engine->context_size > BIT(20)))
544 		engine->context_size = 0;
545 	if (engine->context_size)
546 		DRIVER_CAPS(i915)->has_logical_contexts = true;
547 
548 	ewma__engine_latency_init(&engine->latency);
549 	seqcount_init(&engine->stats.execlists.lock);
550 
551 	ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
552 
553 	/* Scrub mmio state on takeover */
554 	intel_engine_sanitize_mmio(engine);
555 
556 	gt->engine_class[info->class][info->instance] = engine;
557 	gt->engine[id] = engine;
558 
559 	return 0;
560 }
561 
562 u64 intel_clamp_heartbeat_interval_ms(struct intel_engine_cs *engine, u64 value)
563 {
564 	value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
565 
566 	return value;
567 }
568 
569 u64 intel_clamp_max_busywait_duration_ns(struct intel_engine_cs *engine, u64 value)
570 {
571 	value = min(value, jiffies_to_nsecs(2));
572 
573 	return value;
574 }
575 
576 u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value)
577 {
578 	/*
579 	 * NB: The GuC API only supports 32bit values. However, the limit is further
580 	 * reduced due to internal calculations which would otherwise overflow.
581 	 */
582 	if (intel_guc_submission_is_wanted(&engine->gt->uc.guc))
583 		value = min_t(u64, value, guc_policy_max_preempt_timeout_ms());
584 
585 	value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
586 
587 	return value;
588 }
589 
590 u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value)
591 {
592 	value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
593 
594 	return value;
595 }
596 
597 u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value)
598 {
599 	/*
600 	 * NB: The GuC API only supports 32bit values. However, the limit is further
601 	 * reduced due to internal calculations which would otherwise overflow.
602 	 */
603 	if (intel_guc_submission_is_wanted(&engine->gt->uc.guc))
604 		value = min_t(u64, value, guc_policy_max_exec_quantum_ms());
605 
606 	value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
607 
608 	return value;
609 }
610 
611 static void __setup_engine_capabilities(struct intel_engine_cs *engine)
612 {
613 	struct drm_i915_private *i915 = engine->i915;
614 
615 	if (engine->class == VIDEO_DECODE_CLASS) {
616 		/*
617 		 * HEVC support is present on first engine instance
618 		 * before Gen11 and on all instances afterwards.
619 		 */
620 		if (GRAPHICS_VER(i915) >= 11 ||
621 		    (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
622 			engine->uabi_capabilities |=
623 				I915_VIDEO_CLASS_CAPABILITY_HEVC;
624 
625 		/*
626 		 * SFC block is present only on even logical engine
627 		 * instances.
628 		 */
629 		if ((GRAPHICS_VER(i915) >= 11 &&
630 		     (engine->gt->info.vdbox_sfc_access &
631 		      BIT(engine->instance))) ||
632 		    (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
633 			engine->uabi_capabilities |=
634 				I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
635 	} else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
636 		if (GRAPHICS_VER(i915) >= 9 &&
637 		    engine->gt->info.sfc_mask & BIT(engine->instance))
638 			engine->uabi_capabilities |=
639 				I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
640 	}
641 }
642 
643 static void intel_setup_engine_capabilities(struct intel_gt *gt)
644 {
645 	struct intel_engine_cs *engine;
646 	enum intel_engine_id id;
647 
648 	for_each_engine(engine, gt, id)
649 		__setup_engine_capabilities(engine);
650 }
651 
652 /**
653  * intel_engines_release() - free the resources allocated for Command Streamers
654  * @gt: pointer to struct intel_gt
655  */
656 void intel_engines_release(struct intel_gt *gt)
657 {
658 	struct intel_engine_cs *engine;
659 	enum intel_engine_id id;
660 
661 	/*
662 	 * Before we release the resources held by engine, we must be certain
663 	 * that the HW is no longer accessing them -- having the GPU scribble
664 	 * to or read from a page being used for something else causes no end
665 	 * of fun.
666 	 *
667 	 * The GPU should be reset by this point, but assume the worst just
668 	 * in case we aborted before completely initialising the engines.
669 	 */
670 	GEM_BUG_ON(intel_gt_pm_is_awake(gt));
671 	if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
672 		__intel_gt_reset(gt, ALL_ENGINES);
673 
674 	/* Decouple the backend; but keep the layout for late GPU resets */
675 	for_each_engine(engine, gt, id) {
676 		if (!engine->release)
677 			continue;
678 
679 		intel_wakeref_wait_for_idle(&engine->wakeref);
680 		GEM_BUG_ON(intel_engine_pm_is_awake(engine));
681 
682 		engine->release(engine);
683 		engine->release = NULL;
684 
685 		memset(&engine->reset, 0, sizeof(engine->reset));
686 	}
687 }
688 
689 void intel_engine_free_request_pool(struct intel_engine_cs *engine)
690 {
691 	if (!engine->request_pool)
692 		return;
693 
694 	kmem_cache_free(i915_request_slab_cache(), engine->request_pool);
695 }
696 
697 void intel_engines_free(struct intel_gt *gt)
698 {
699 	struct intel_engine_cs *engine;
700 	enum intel_engine_id id;
701 
702 	/* Free the requests! dma-resv keeps fences around for an eternity */
703 	rcu_barrier();
704 
705 	for_each_engine(engine, gt, id) {
706 		intel_engine_free_request_pool(engine);
707 		kfree(engine);
708 		gt->engine[id] = NULL;
709 	}
710 }
711 
712 static
713 bool gen11_vdbox_has_sfc(struct intel_gt *gt,
714 			 unsigned int physical_vdbox,
715 			 unsigned int logical_vdbox, u16 vdbox_mask)
716 {
717 	struct drm_i915_private *i915 = gt->i915;
718 
719 	/*
720 	 * In Gen11, only even numbered logical VDBOXes are hooked
721 	 * up to an SFC (Scaler & Format Converter) unit.
722 	 * In Gen12, Even numbered physical instance always are connected
723 	 * to an SFC. Odd numbered physical instances have SFC only if
724 	 * previous even instance is fused off.
725 	 *
726 	 * Starting with Xe_HP, there's also a dedicated SFC_ENABLE field
727 	 * in the fuse register that tells us whether a specific SFC is present.
728 	 */
729 	if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
730 		return false;
731 	else if (MEDIA_VER(i915) >= 12)
732 		return (physical_vdbox % 2 == 0) ||
733 			!(BIT(physical_vdbox - 1) & vdbox_mask);
734 	else if (MEDIA_VER(i915) == 11)
735 		return logical_vdbox % 2 == 0;
736 
737 	return false;
738 }
739 
740 static void engine_mask_apply_media_fuses(struct intel_gt *gt)
741 {
742 	struct drm_i915_private *i915 = gt->i915;
743 	unsigned int logical_vdbox = 0;
744 	unsigned int i;
745 	u32 media_fuse, fuse1;
746 	u16 vdbox_mask;
747 	u16 vebox_mask;
748 
749 	if (MEDIA_VER(gt->i915) < 11)
750 		return;
751 
752 	/*
753 	 * On newer platforms the fusing register is called 'enable' and has
754 	 * enable semantics, while on older platforms it is called 'disable'
755 	 * and bits have disable semantices.
756 	 */
757 	media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
758 	if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
759 		media_fuse = ~media_fuse;
760 
761 	vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
762 	vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
763 		      GEN11_GT_VEBOX_DISABLE_SHIFT;
764 
765 	if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
766 		fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
767 		gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
768 	} else {
769 		gt->info.sfc_mask = ~0;
770 	}
771 
772 	for (i = 0; i < I915_MAX_VCS; i++) {
773 		if (!HAS_ENGINE(gt, _VCS(i))) {
774 			vdbox_mask &= ~BIT(i);
775 			continue;
776 		}
777 
778 		if (!(BIT(i) & vdbox_mask)) {
779 			gt->info.engine_mask &= ~BIT(_VCS(i));
780 			drm_dbg(&i915->drm, "vcs%u fused off\n", i);
781 			continue;
782 		}
783 
784 		if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
785 			gt->info.vdbox_sfc_access |= BIT(i);
786 		logical_vdbox++;
787 	}
788 	drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
789 		vdbox_mask, VDBOX_MASK(gt));
790 	GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
791 
792 	for (i = 0; i < I915_MAX_VECS; i++) {
793 		if (!HAS_ENGINE(gt, _VECS(i))) {
794 			vebox_mask &= ~BIT(i);
795 			continue;
796 		}
797 
798 		if (!(BIT(i) & vebox_mask)) {
799 			gt->info.engine_mask &= ~BIT(_VECS(i));
800 			drm_dbg(&i915->drm, "vecs%u fused off\n", i);
801 		}
802 	}
803 	drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
804 		vebox_mask, VEBOX_MASK(gt));
805 	GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
806 }
807 
808 static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
809 {
810 	struct drm_i915_private *i915 = gt->i915;
811 	struct intel_gt_info *info = &gt->info;
812 	int ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS;
813 	unsigned long ccs_mask;
814 	unsigned int i;
815 
816 	if (GRAPHICS_VER(i915) < 11)
817 		return;
818 
819 	if (hweight32(CCS_MASK(gt)) <= 1)
820 		return;
821 
822 	ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
823 						     ss_per_ccs);
824 	/*
825 	 * If all DSS in a quadrant are fused off, the corresponding CCS
826 	 * engine is not available for use.
827 	 */
828 	for_each_clear_bit(i, &ccs_mask, I915_MAX_CCS) {
829 		info->engine_mask &= ~BIT(_CCS(i));
830 		drm_dbg(&i915->drm, "ccs%u fused off\n", i);
831 	}
832 }
833 
834 static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
835 {
836 	struct drm_i915_private *i915 = gt->i915;
837 	struct intel_gt_info *info = &gt->info;
838 	unsigned long meml3_mask;
839 	unsigned long quad;
840 
841 	if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
842 	      GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
843 		return;
844 
845 	meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
846 	meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
847 
848 	/*
849 	 * Link Copy engines may be fused off according to meml3_mask. Each
850 	 * bit is a quad that houses 2 Link Copy and two Sub Copy engines.
851 	 */
852 	for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
853 		unsigned int instance = quad * 2 + 1;
854 		intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
855 						   _BCS(instance));
856 
857 		if (mask & info->engine_mask) {
858 			drm_dbg(&i915->drm, "bcs%u fused off\n", instance);
859 			drm_dbg(&i915->drm, "bcs%u fused off\n", instance + 1);
860 
861 			info->engine_mask &= ~mask;
862 		}
863 	}
864 }
865 
866 /*
867  * Determine which engines are fused off in our particular hardware.
868  * Note that we have a catch-22 situation where we need to be able to access
869  * the blitter forcewake domain to read the engine fuses, but at the same time
870  * we need to know which engines are available on the system to know which
871  * forcewake domains are present. We solve this by intializing the forcewake
872  * domains based on the full engine mask in the platform capabilities before
873  * calling this function and pruning the domains for fused-off engines
874  * afterwards.
875  */
876 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
877 {
878 	struct intel_gt_info *info = &gt->info;
879 
880 	GEM_BUG_ON(!info->engine_mask);
881 
882 	engine_mask_apply_media_fuses(gt);
883 	engine_mask_apply_compute_fuses(gt);
884 	engine_mask_apply_copy_fuses(gt);
885 
886 	return info->engine_mask;
887 }
888 
889 static void populate_logical_ids(struct intel_gt *gt, u8 *logical_ids,
890 				 u8 class, const u8 *map, u8 num_instances)
891 {
892 	int i, j;
893 	u8 current_logical_id = 0;
894 
895 	for (j = 0; j < num_instances; ++j) {
896 		for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) {
897 			if (!HAS_ENGINE(gt, i) ||
898 			    intel_engines[i].class != class)
899 				continue;
900 
901 			if (intel_engines[i].instance == map[j]) {
902 				logical_ids[intel_engines[i].instance] =
903 					current_logical_id++;
904 				break;
905 			}
906 		}
907 	}
908 }
909 
910 static void setup_logical_ids(struct intel_gt *gt, u8 *logical_ids, u8 class)
911 {
912 	/*
913 	 * Logical to physical mapping is needed for proper support
914 	 * to split-frame feature.
915 	 */
916 	if (MEDIA_VER(gt->i915) >= 11 && class == VIDEO_DECODE_CLASS) {
917 		const u8 map[] = { 0, 2, 4, 6, 1, 3, 5, 7 };
918 
919 		populate_logical_ids(gt, logical_ids, class,
920 				     map, ARRAY_SIZE(map));
921 	} else {
922 		int i;
923 		u8 map[MAX_ENGINE_INSTANCE + 1];
924 
925 		for (i = 0; i < MAX_ENGINE_INSTANCE + 1; ++i)
926 			map[i] = i;
927 		populate_logical_ids(gt, logical_ids, class,
928 				     map, ARRAY_SIZE(map));
929 	}
930 }
931 
932 /**
933  * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
934  * @gt: pointer to struct intel_gt
935  *
936  * Return: non-zero if the initialization failed.
937  */
938 int intel_engines_init_mmio(struct intel_gt *gt)
939 {
940 	struct drm_i915_private *i915 = gt->i915;
941 	const unsigned int engine_mask = init_engine_mask(gt);
942 	unsigned int mask = 0;
943 	unsigned int i, class;
944 	u8 logical_ids[MAX_ENGINE_INSTANCE + 1];
945 	int err;
946 
947 	drm_WARN_ON(&i915->drm, engine_mask == 0);
948 	drm_WARN_ON(&i915->drm, engine_mask &
949 		    GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
950 
951 	if (i915_inject_probe_failure(i915))
952 		return -ENODEV;
953 
954 	for (class = 0; class < MAX_ENGINE_CLASS + 1; ++class) {
955 		setup_logical_ids(gt, logical_ids, class);
956 
957 		for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) {
958 			u8 instance = intel_engines[i].instance;
959 
960 			if (intel_engines[i].class != class ||
961 			    !HAS_ENGINE(gt, i))
962 				continue;
963 
964 			err = intel_engine_setup(gt, i,
965 						 logical_ids[instance]);
966 			if (err)
967 				goto cleanup;
968 
969 			mask |= BIT(i);
970 		}
971 	}
972 
973 	/*
974 	 * Catch failures to update intel_engines table when the new engines
975 	 * are added to the driver by a warning and disabling the forgotten
976 	 * engines.
977 	 */
978 	if (drm_WARN_ON(&i915->drm, mask != engine_mask))
979 		gt->info.engine_mask = mask;
980 
981 	gt->info.num_engines = hweight32(mask);
982 
983 	intel_gt_check_and_clear_faults(gt);
984 
985 	intel_setup_engine_capabilities(gt);
986 
987 	intel_uncore_prune_engine_fw_domains(gt->uncore, gt);
988 
989 	return 0;
990 
991 cleanup:
992 	intel_engines_free(gt);
993 	return err;
994 }
995 
996 void intel_engine_init_execlists(struct intel_engine_cs *engine)
997 {
998 	struct intel_engine_execlists * const execlists = &engine->execlists;
999 
1000 	execlists->port_mask = 1;
1001 	GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
1002 	GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
1003 
1004 	memset(execlists->pending, 0, sizeof(execlists->pending));
1005 	execlists->active =
1006 		memset(execlists->inflight, 0, sizeof(execlists->inflight));
1007 }
1008 
1009 static void cleanup_status_page(struct intel_engine_cs *engine)
1010 {
1011 	struct i915_vma *vma;
1012 
1013 	/* Prevent writes into HWSP after returning the page to the system */
1014 	intel_engine_set_hwsp_writemask(engine, ~0u);
1015 
1016 	vma = fetch_and_zero(&engine->status_page.vma);
1017 	if (!vma)
1018 		return;
1019 
1020 	if (!HWS_NEEDS_PHYSICAL(engine->i915))
1021 		i915_vma_unpin(vma);
1022 
1023 	i915_gem_object_unpin_map(vma->obj);
1024 	i915_gem_object_put(vma->obj);
1025 }
1026 
1027 static int pin_ggtt_status_page(struct intel_engine_cs *engine,
1028 				struct i915_gem_ww_ctx *ww,
1029 				struct i915_vma *vma)
1030 {
1031 	unsigned int flags;
1032 
1033 	if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))
1034 		/*
1035 		 * On g33, we cannot place HWS above 256MiB, so
1036 		 * restrict its pinning to the low mappable arena.
1037 		 * Though this restriction is not documented for
1038 		 * gen4, gen5, or byt, they also behave similarly
1039 		 * and hang if the HWS is placed at the top of the
1040 		 * GTT. To generalise, it appears that all !llc
1041 		 * platforms have issues with us placing the HWS
1042 		 * above the mappable region (even though we never
1043 		 * actually map it).
1044 		 */
1045 		flags = PIN_MAPPABLE;
1046 	else
1047 		flags = PIN_HIGH;
1048 
1049 	return i915_ggtt_pin(vma, ww, 0, flags);
1050 }
1051 
1052 static int init_status_page(struct intel_engine_cs *engine)
1053 {
1054 	struct drm_i915_gem_object *obj;
1055 	struct i915_gem_ww_ctx ww;
1056 	struct i915_vma *vma;
1057 	void *vaddr;
1058 	int ret;
1059 
1060 	INIT_LIST_HEAD(&engine->status_page.timelines);
1061 
1062 	/*
1063 	 * Though the HWS register does support 36bit addresses, historically
1064 	 * we have had hangs and corruption reported due to wild writes if
1065 	 * the HWS is placed above 4G. We only allow objects to be allocated
1066 	 * in GFP_DMA32 for i965, and no earlier physical address users had
1067 	 * access to more than 4G.
1068 	 */
1069 	obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
1070 	if (IS_ERR(obj)) {
1071 		drm_err(&engine->i915->drm,
1072 			"Failed to allocate status page\n");
1073 		return PTR_ERR(obj);
1074 	}
1075 
1076 	i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
1077 
1078 	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
1079 	if (IS_ERR(vma)) {
1080 		ret = PTR_ERR(vma);
1081 		goto err_put;
1082 	}
1083 
1084 	i915_gem_ww_ctx_init(&ww, true);
1085 retry:
1086 	ret = i915_gem_object_lock(obj, &ww);
1087 	if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915))
1088 		ret = pin_ggtt_status_page(engine, &ww, vma);
1089 	if (ret)
1090 		goto err;
1091 
1092 	vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1093 	if (IS_ERR(vaddr)) {
1094 		ret = PTR_ERR(vaddr);
1095 		goto err_unpin;
1096 	}
1097 
1098 	engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
1099 	engine->status_page.vma = vma;
1100 
1101 err_unpin:
1102 	if (ret)
1103 		i915_vma_unpin(vma);
1104 err:
1105 	if (ret == -EDEADLK) {
1106 		ret = i915_gem_ww_ctx_backoff(&ww);
1107 		if (!ret)
1108 			goto retry;
1109 	}
1110 	i915_gem_ww_ctx_fini(&ww);
1111 err_put:
1112 	if (ret)
1113 		i915_gem_object_put(obj);
1114 	return ret;
1115 }
1116 
1117 static int engine_setup_common(struct intel_engine_cs *engine)
1118 {
1119 	int err;
1120 
1121 	init_llist_head(&engine->barrier_tasks);
1122 
1123 	err = init_status_page(engine);
1124 	if (err)
1125 		return err;
1126 
1127 	engine->breadcrumbs = intel_breadcrumbs_create(engine);
1128 	if (!engine->breadcrumbs) {
1129 		err = -ENOMEM;
1130 		goto err_status;
1131 	}
1132 
1133 	engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL);
1134 	if (!engine->sched_engine) {
1135 		err = -ENOMEM;
1136 		goto err_sched_engine;
1137 	}
1138 	engine->sched_engine->private_data = engine;
1139 
1140 	err = intel_engine_init_cmd_parser(engine);
1141 	if (err)
1142 		goto err_cmd_parser;
1143 
1144 	intel_engine_init_execlists(engine);
1145 	intel_engine_init__pm(engine);
1146 	intel_engine_init_retire(engine);
1147 
1148 	/* Use the whole device by default */
1149 	engine->sseu =
1150 		intel_sseu_from_device_info(&engine->gt->info.sseu);
1151 
1152 	intel_engine_init_workarounds(engine);
1153 	intel_engine_init_whitelist(engine);
1154 	intel_engine_init_ctx_wa(engine);
1155 
1156 	if (GRAPHICS_VER(engine->i915) >= 12)
1157 		engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
1158 
1159 	return 0;
1160 
1161 err_cmd_parser:
1162 	i915_sched_engine_put(engine->sched_engine);
1163 err_sched_engine:
1164 	intel_breadcrumbs_put(engine->breadcrumbs);
1165 err_status:
1166 	cleanup_status_page(engine);
1167 	return err;
1168 }
1169 
1170 struct measure_breadcrumb {
1171 	struct i915_request rq;
1172 	struct intel_ring ring;
1173 	u32 cs[2048];
1174 };
1175 
1176 static int measure_breadcrumb_dw(struct intel_context *ce)
1177 {
1178 	struct intel_engine_cs *engine = ce->engine;
1179 	struct measure_breadcrumb *frame;
1180 	int dw;
1181 
1182 	GEM_BUG_ON(!engine->gt->scratch);
1183 
1184 	frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1185 	if (!frame)
1186 		return -ENOMEM;
1187 
1188 	frame->rq.engine = engine;
1189 	frame->rq.context = ce;
1190 	rcu_assign_pointer(frame->rq.timeline, ce->timeline);
1191 	frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno;
1192 
1193 	frame->ring.vaddr = frame->cs;
1194 	frame->ring.size = sizeof(frame->cs);
1195 	frame->ring.wrap =
1196 		BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size);
1197 	frame->ring.effective_size = frame->ring.size;
1198 	intel_ring_update_space(&frame->ring);
1199 	frame->rq.ring = &frame->ring;
1200 
1201 	mutex_lock(&ce->timeline->mutex);
1202 	spin_lock_irq(&engine->sched_engine->lock);
1203 
1204 	dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
1205 
1206 	spin_unlock_irq(&engine->sched_engine->lock);
1207 	mutex_unlock(&ce->timeline->mutex);
1208 
1209 	GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
1210 
1211 	kfree(frame);
1212 	return dw;
1213 }
1214 
1215 struct intel_context *
1216 intel_engine_create_pinned_context(struct intel_engine_cs *engine,
1217 				   struct i915_address_space *vm,
1218 				   unsigned int ring_size,
1219 				   unsigned int hwsp,
1220 				   struct lock_class_key *key,
1221 				   const char *name)
1222 {
1223 	struct intel_context *ce;
1224 	int err;
1225 
1226 	ce = intel_context_create(engine);
1227 	if (IS_ERR(ce))
1228 		return ce;
1229 
1230 	__set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
1231 	ce->timeline = page_pack_bits(NULL, hwsp);
1232 	ce->ring = NULL;
1233 	ce->ring_size = ring_size;
1234 
1235 	i915_vm_put(ce->vm);
1236 	ce->vm = i915_vm_get(vm);
1237 
1238 	err = intel_context_pin(ce); /* perma-pin so it is always available */
1239 	if (err) {
1240 		intel_context_put(ce);
1241 		return ERR_PTR(err);
1242 	}
1243 
1244 	list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list);
1245 
1246 	/*
1247 	 * Give our perma-pinned kernel timelines a separate lockdep class,
1248 	 * so that we can use them from within the normal user timelines
1249 	 * should we need to inject GPU operations during their request
1250 	 * construction.
1251 	 */
1252 	lockdep_set_class_and_name(&ce->timeline->mutex, key, name);
1253 
1254 	return ce;
1255 }
1256 
1257 void intel_engine_destroy_pinned_context(struct intel_context *ce)
1258 {
1259 	struct intel_engine_cs *engine = ce->engine;
1260 	struct i915_vma *hwsp = engine->status_page.vma;
1261 
1262 	GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp);
1263 
1264 	mutex_lock(&hwsp->vm->mutex);
1265 	list_del(&ce->timeline->engine_link);
1266 	mutex_unlock(&hwsp->vm->mutex);
1267 
1268 	list_del(&ce->pinned_contexts_link);
1269 	intel_context_unpin(ce);
1270 	intel_context_put(ce);
1271 }
1272 
1273 static struct intel_context *
1274 create_kernel_context(struct intel_engine_cs *engine)
1275 {
1276 	static struct lock_class_key kernel;
1277 
1278 	return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,
1279 						  I915_GEM_HWS_SEQNO_ADDR,
1280 						  &kernel, "kernel_context");
1281 }
1282 
1283 /**
1284  * intel_engines_init_common - initialize cengine state which might require hw access
1285  * @engine: Engine to initialize.
1286  *
1287  * Initializes @engine@ structure members shared between legacy and execlists
1288  * submission modes which do require hardware access.
1289  *
1290  * Typcally done at later stages of submission mode specific engine setup.
1291  *
1292  * Returns zero on success or an error code on failure.
1293  */
1294 static int engine_init_common(struct intel_engine_cs *engine)
1295 {
1296 	struct intel_context *ce;
1297 	int ret;
1298 
1299 	engine->set_default_submission(engine);
1300 
1301 	/*
1302 	 * We may need to do things with the shrinker which
1303 	 * require us to immediately switch back to the default
1304 	 * context. This can cause a problem as pinning the
1305 	 * default context also requires GTT space which may not
1306 	 * be available. To avoid this we always pin the default
1307 	 * context.
1308 	 */
1309 	ce = create_kernel_context(engine);
1310 	if (IS_ERR(ce))
1311 		return PTR_ERR(ce);
1312 
1313 	ret = measure_breadcrumb_dw(ce);
1314 	if (ret < 0)
1315 		goto err_context;
1316 
1317 	engine->emit_fini_breadcrumb_dw = ret;
1318 	engine->kernel_context = ce;
1319 
1320 	return 0;
1321 
1322 err_context:
1323 	intel_engine_destroy_pinned_context(ce);
1324 	return ret;
1325 }
1326 
1327 int intel_engines_init(struct intel_gt *gt)
1328 {
1329 	int (*setup)(struct intel_engine_cs *engine);
1330 	struct intel_engine_cs *engine;
1331 	enum intel_engine_id id;
1332 	int err;
1333 
1334 	if (intel_uc_uses_guc_submission(&gt->uc)) {
1335 		gt->submission_method = INTEL_SUBMISSION_GUC;
1336 		setup = intel_guc_submission_setup;
1337 	} else if (HAS_EXECLISTS(gt->i915)) {
1338 		gt->submission_method = INTEL_SUBMISSION_ELSP;
1339 		setup = intel_execlists_submission_setup;
1340 	} else {
1341 		gt->submission_method = INTEL_SUBMISSION_RING;
1342 		setup = intel_ring_submission_setup;
1343 	}
1344 
1345 	for_each_engine(engine, gt, id) {
1346 		err = engine_setup_common(engine);
1347 		if (err)
1348 			return err;
1349 
1350 		err = setup(engine);
1351 		if (err) {
1352 			intel_engine_cleanup_common(engine);
1353 			return err;
1354 		}
1355 
1356 		/* The backend should now be responsible for cleanup */
1357 		GEM_BUG_ON(engine->release == NULL);
1358 
1359 		err = engine_init_common(engine);
1360 		if (err)
1361 			return err;
1362 
1363 		intel_engine_add_user(engine);
1364 	}
1365 
1366 	return 0;
1367 }
1368 
1369 /**
1370  * intel_engines_cleanup_common - cleans up the engine state created by
1371  *                                the common initiailizers.
1372  * @engine: Engine to cleanup.
1373  *
1374  * This cleans up everything created by the common helpers.
1375  */
1376 void intel_engine_cleanup_common(struct intel_engine_cs *engine)
1377 {
1378 	GEM_BUG_ON(!list_empty(&engine->sched_engine->requests));
1379 
1380 	i915_sched_engine_put(engine->sched_engine);
1381 	intel_breadcrumbs_put(engine->breadcrumbs);
1382 
1383 	intel_engine_fini_retire(engine);
1384 	intel_engine_cleanup_cmd_parser(engine);
1385 
1386 	if (engine->default_state)
1387 		fput(engine->default_state);
1388 
1389 	if (engine->kernel_context)
1390 		intel_engine_destroy_pinned_context(engine->kernel_context);
1391 
1392 	GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
1393 	cleanup_status_page(engine);
1394 
1395 	intel_wa_list_free(&engine->ctx_wa_list);
1396 	intel_wa_list_free(&engine->wa_list);
1397 	intel_wa_list_free(&engine->whitelist);
1398 }
1399 
1400 /**
1401  * intel_engine_resume - re-initializes the HW state of the engine
1402  * @engine: Engine to resume.
1403  *
1404  * Returns zero on success or an error code on failure.
1405  */
1406 int intel_engine_resume(struct intel_engine_cs *engine)
1407 {
1408 	intel_engine_apply_workarounds(engine);
1409 	intel_engine_apply_whitelist(engine);
1410 
1411 	return engine->resume(engine);
1412 }
1413 
1414 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
1415 {
1416 	struct drm_i915_private *i915 = engine->i915;
1417 
1418 	u64 acthd;
1419 
1420 	if (GRAPHICS_VER(i915) >= 8)
1421 		acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
1422 	else if (GRAPHICS_VER(i915) >= 4)
1423 		acthd = ENGINE_READ(engine, RING_ACTHD);
1424 	else
1425 		acthd = ENGINE_READ(engine, ACTHD);
1426 
1427 	return acthd;
1428 }
1429 
1430 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
1431 {
1432 	u64 bbaddr;
1433 
1434 	if (GRAPHICS_VER(engine->i915) >= 8)
1435 		bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
1436 	else
1437 		bbaddr = ENGINE_READ(engine, RING_BBADDR);
1438 
1439 	return bbaddr;
1440 }
1441 
1442 static unsigned long stop_timeout(const struct intel_engine_cs *engine)
1443 {
1444 	if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */
1445 		return 0;
1446 
1447 	/*
1448 	 * If we are doing a normal GPU reset, we can take our time and allow
1449 	 * the engine to quiesce. We've stopped submission to the engine, and
1450 	 * if we wait long enough an innocent context should complete and
1451 	 * leave the engine idle. So they should not be caught unaware by
1452 	 * the forthcoming GPU reset (which usually follows the stop_cs)!
1453 	 */
1454 	return READ_ONCE(engine->props.stop_timeout_ms);
1455 }
1456 
1457 static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
1458 				  int fast_timeout_us,
1459 				  int slow_timeout_ms)
1460 {
1461 	struct intel_uncore *uncore = engine->uncore;
1462 	const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);
1463 	int err;
1464 
1465 	intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
1466 
1467 	/*
1468 	 * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
1469 	 * stopped, set ring stop bit and prefetch disable bit to halt CS
1470 	 */
1471 	if (IS_GRAPHICS_VER(engine->i915, 11, 12))
1472 		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
1473 				      _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
1474 
1475 	err = __intel_wait_for_register_fw(engine->uncore, mode,
1476 					   MODE_IDLE, MODE_IDLE,
1477 					   fast_timeout_us,
1478 					   slow_timeout_ms,
1479 					   NULL);
1480 
1481 	/* A final mmio read to let GPU writes be hopefully flushed to memory */
1482 	intel_uncore_posting_read_fw(uncore, mode);
1483 	return err;
1484 }
1485 
1486 int intel_engine_stop_cs(struct intel_engine_cs *engine)
1487 {
1488 	int err = 0;
1489 
1490 	if (GRAPHICS_VER(engine->i915) < 3)
1491 		return -ENODEV;
1492 
1493 	ENGINE_TRACE(engine, "\n");
1494 	/*
1495 	 * TODO: Find out why occasionally stopping the CS times out. Seen
1496 	 * especially with gem_eio tests.
1497 	 *
1498 	 * Occasionally trying to stop the cs times out, but does not adversely
1499 	 * affect functionality. The timeout is set as a config parameter that
1500 	 * defaults to 100ms. In most cases the follow up operation is to wait
1501 	 * for pending MI_FORCE_WAKES. The assumption is that this timeout is
1502 	 * sufficient for any pending MI_FORCEWAKEs to complete. Once root
1503 	 * caused, the caller must check and handle the return from this
1504 	 * function.
1505 	 */
1506 	if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
1507 		ENGINE_TRACE(engine,
1508 			     "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n",
1509 			     ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR,
1510 			     ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR);
1511 
1512 		/*
1513 		 * Sometimes we observe that the idle flag is not
1514 		 * set even though the ring is empty. So double
1515 		 * check before giving up.
1516 		 */
1517 		if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) !=
1518 		    (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR))
1519 			err = -ETIMEDOUT;
1520 	}
1521 
1522 	return err;
1523 }
1524 
1525 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
1526 {
1527 	ENGINE_TRACE(engine, "\n");
1528 
1529 	ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1530 }
1531 
1532 static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
1533 {
1534 	static const i915_reg_t _reg[I915_NUM_ENGINES] = {
1535 		[RCS0] = MSG_IDLE_CS,
1536 		[BCS0] = MSG_IDLE_BCS,
1537 		[VCS0] = MSG_IDLE_VCS0,
1538 		[VCS1] = MSG_IDLE_VCS1,
1539 		[VCS2] = MSG_IDLE_VCS2,
1540 		[VCS3] = MSG_IDLE_VCS3,
1541 		[VCS4] = MSG_IDLE_VCS4,
1542 		[VCS5] = MSG_IDLE_VCS5,
1543 		[VCS6] = MSG_IDLE_VCS6,
1544 		[VCS7] = MSG_IDLE_VCS7,
1545 		[VECS0] = MSG_IDLE_VECS0,
1546 		[VECS1] = MSG_IDLE_VECS1,
1547 		[VECS2] = MSG_IDLE_VECS2,
1548 		[VECS3] = MSG_IDLE_VECS3,
1549 		[CCS0] = MSG_IDLE_CS,
1550 		[CCS1] = MSG_IDLE_CS,
1551 		[CCS2] = MSG_IDLE_CS,
1552 		[CCS3] = MSG_IDLE_CS,
1553 	};
1554 	u32 val;
1555 
1556 	if (!_reg[engine->id].reg) {
1557 		drm_err(&engine->i915->drm,
1558 			"MSG IDLE undefined for engine id %u\n", engine->id);
1559 		return 0;
1560 	}
1561 
1562 	val = intel_uncore_read(engine->uncore, _reg[engine->id]);
1563 
1564 	/* bits[29:25] & bits[13:9] >> shift */
1565 	return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
1566 }
1567 
1568 static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
1569 {
1570 	int ret;
1571 
1572 	/* Ensure GPM receives fw up/down after CS is stopped */
1573 	udelay(1);
1574 
1575 	/* Wait for forcewake request to complete in GPM */
1576 	ret =  __intel_wait_for_register_fw(gt->uncore,
1577 					    GEN9_PWRGT_DOMAIN_STATUS,
1578 					    fw_mask, fw_mask, 5000, 0, NULL);
1579 
1580 	/* Ensure CS receives fw ack from GPM */
1581 	udelay(1);
1582 
1583 	if (ret)
1584 		GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
1585 }
1586 
1587 /*
1588  * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
1589  * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
1590  * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the
1591  * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
1592  * are concerned only with the gt reset here, we use a logical OR of pending
1593  * forcewakeups from all reset domains and then wait for them to complete by
1594  * querying PWRGT_DOMAIN_STATUS.
1595  */
1596 void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine)
1597 {
1598 	u32 fw_pending = __cs_pending_mi_force_wakes(engine);
1599 
1600 	if (fw_pending)
1601 		__gpm_wait_for_fw_complete(engine->gt, fw_pending);
1602 }
1603 
1604 /* NB: please notice the memset */
1605 void intel_engine_get_instdone(const struct intel_engine_cs *engine,
1606 			       struct intel_instdone *instdone)
1607 {
1608 	struct drm_i915_private *i915 = engine->i915;
1609 	struct intel_uncore *uncore = engine->uncore;
1610 	u32 mmio_base = engine->mmio_base;
1611 	int slice;
1612 	int subslice;
1613 	int iter;
1614 
1615 	memset(instdone, 0, sizeof(*instdone));
1616 
1617 	if (GRAPHICS_VER(i915) >= 8) {
1618 		instdone->instdone =
1619 			intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1620 
1621 		if (engine->id != RCS0)
1622 			return;
1623 
1624 		instdone->slice_common =
1625 			intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1626 		if (GRAPHICS_VER(i915) >= 12) {
1627 			instdone->slice_common_extra[0] =
1628 				intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
1629 			instdone->slice_common_extra[1] =
1630 				intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2);
1631 		}
1632 
1633 		for_each_ss_steering(iter, engine->gt, slice, subslice) {
1634 			instdone->sampler[slice][subslice] =
1635 				intel_gt_mcr_read(engine->gt,
1636 						  GEN8_SAMPLER_INSTDONE,
1637 						  slice, subslice);
1638 			instdone->row[slice][subslice] =
1639 				intel_gt_mcr_read(engine->gt,
1640 						  GEN8_ROW_INSTDONE,
1641 						  slice, subslice);
1642 		}
1643 
1644 		if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
1645 			for_each_ss_steering(iter, engine->gt, slice, subslice)
1646 				instdone->geom_svg[slice][subslice] =
1647 					intel_gt_mcr_read(engine->gt,
1648 							  XEHPG_INSTDONE_GEOM_SVG,
1649 							  slice, subslice);
1650 		}
1651 	} else if (GRAPHICS_VER(i915) >= 7) {
1652 		instdone->instdone =
1653 			intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1654 
1655 		if (engine->id != RCS0)
1656 			return;
1657 
1658 		instdone->slice_common =
1659 			intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1660 		instdone->sampler[0][0] =
1661 			intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
1662 		instdone->row[0][0] =
1663 			intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
1664 	} else if (GRAPHICS_VER(i915) >= 4) {
1665 		instdone->instdone =
1666 			intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1667 		if (engine->id == RCS0)
1668 			/* HACK: Using the wrong struct member */
1669 			instdone->slice_common =
1670 				intel_uncore_read(uncore, GEN4_INSTDONE1);
1671 	} else {
1672 		instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
1673 	}
1674 }
1675 
1676 static bool ring_is_idle(struct intel_engine_cs *engine)
1677 {
1678 	bool idle = true;
1679 
1680 	if (I915_SELFTEST_ONLY(!engine->mmio_base))
1681 		return true;
1682 
1683 	if (!intel_engine_pm_get_if_awake(engine))
1684 		return true;
1685 
1686 	/* First check that no commands are left in the ring */
1687 	if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
1688 	    (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
1689 		idle = false;
1690 
1691 	/* No bit for gen2, so assume the CS parser is idle */
1692 	if (GRAPHICS_VER(engine->i915) > 2 &&
1693 	    !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
1694 		idle = false;
1695 
1696 	intel_engine_pm_put(engine);
1697 
1698 	return idle;
1699 }
1700 
1701 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync)
1702 {
1703 	struct tasklet_struct *t = &engine->sched_engine->tasklet;
1704 
1705 	if (!t->callback)
1706 		return;
1707 
1708 	local_bh_disable();
1709 	if (tasklet_trylock(t)) {
1710 		/* Must wait for any GPU reset in progress. */
1711 		if (__tasklet_is_enabled(t))
1712 			t->callback(t);
1713 		tasklet_unlock(t);
1714 	}
1715 	local_bh_enable();
1716 
1717 	/* Synchronise and wait for the tasklet on another CPU */
1718 	if (sync)
1719 		tasklet_unlock_wait(t);
1720 }
1721 
1722 /**
1723  * intel_engine_is_idle() - Report if the engine has finished process all work
1724  * @engine: the intel_engine_cs
1725  *
1726  * Return true if there are no requests pending, nothing left to be submitted
1727  * to hardware, and that the engine is idle.
1728  */
1729 bool intel_engine_is_idle(struct intel_engine_cs *engine)
1730 {
1731 	/* More white lies, if wedged, hw state is inconsistent */
1732 	if (intel_gt_is_wedged(engine->gt))
1733 		return true;
1734 
1735 	if (!intel_engine_pm_is_awake(engine))
1736 		return true;
1737 
1738 	/* Waiting to drain ELSP? */
1739 	intel_synchronize_hardirq(engine->i915);
1740 	intel_engine_flush_submission(engine);
1741 
1742 	/* ELSP is empty, but there are ready requests? E.g. after reset */
1743 	if (!i915_sched_engine_is_empty(engine->sched_engine))
1744 		return false;
1745 
1746 	/* Ring stopped? */
1747 	return ring_is_idle(engine);
1748 }
1749 
1750 bool intel_engines_are_idle(struct intel_gt *gt)
1751 {
1752 	struct intel_engine_cs *engine;
1753 	enum intel_engine_id id;
1754 
1755 	/*
1756 	 * If the driver is wedged, HW state may be very inconsistent and
1757 	 * report that it is still busy, even though we have stopped using it.
1758 	 */
1759 	if (intel_gt_is_wedged(gt))
1760 		return true;
1761 
1762 	/* Already parked (and passed an idleness test); must still be idle */
1763 	if (!READ_ONCE(gt->awake))
1764 		return true;
1765 
1766 	for_each_engine(engine, gt, id) {
1767 		if (!intel_engine_is_idle(engine))
1768 			return false;
1769 	}
1770 
1771 	return true;
1772 }
1773 
1774 bool intel_engine_irq_enable(struct intel_engine_cs *engine)
1775 {
1776 	if (!engine->irq_enable)
1777 		return false;
1778 
1779 	/* Caller disables interrupts */
1780 	spin_lock(engine->gt->irq_lock);
1781 	engine->irq_enable(engine);
1782 	spin_unlock(engine->gt->irq_lock);
1783 
1784 	return true;
1785 }
1786 
1787 void intel_engine_irq_disable(struct intel_engine_cs *engine)
1788 {
1789 	if (!engine->irq_disable)
1790 		return;
1791 
1792 	/* Caller disables interrupts */
1793 	spin_lock(engine->gt->irq_lock);
1794 	engine->irq_disable(engine);
1795 	spin_unlock(engine->gt->irq_lock);
1796 }
1797 
1798 void intel_engines_reset_default_submission(struct intel_gt *gt)
1799 {
1800 	struct intel_engine_cs *engine;
1801 	enum intel_engine_id id;
1802 
1803 	for_each_engine(engine, gt, id) {
1804 		if (engine->sanitize)
1805 			engine->sanitize(engine);
1806 
1807 		engine->set_default_submission(engine);
1808 	}
1809 }
1810 
1811 bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
1812 {
1813 	switch (GRAPHICS_VER(engine->i915)) {
1814 	case 2:
1815 		return false; /* uses physical not virtual addresses */
1816 	case 3:
1817 		/* maybe only uses physical not virtual addresses */
1818 		return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
1819 	case 4:
1820 		return !IS_I965G(engine->i915); /* who knows! */
1821 	case 6:
1822 		return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
1823 	default:
1824 		return true;
1825 	}
1826 }
1827 
1828 static struct intel_timeline *get_timeline(struct i915_request *rq)
1829 {
1830 	struct intel_timeline *tl;
1831 
1832 	/*
1833 	 * Even though we are holding the engine->sched_engine->lock here, there
1834 	 * is no control over the submission queue per-se and we are
1835 	 * inspecting the active state at a random point in time, with an
1836 	 * unknown queue. Play safe and make sure the timeline remains valid.
1837 	 * (Only being used for pretty printing, one extra kref shouldn't
1838 	 * cause a camel stampede!)
1839 	 */
1840 	rcu_read_lock();
1841 	tl = rcu_dereference(rq->timeline);
1842 	if (!kref_get_unless_zero(&tl->kref))
1843 		tl = NULL;
1844 	rcu_read_unlock();
1845 
1846 	return tl;
1847 }
1848 
1849 static int print_ring(char *buf, int sz, struct i915_request *rq)
1850 {
1851 	int len = 0;
1852 
1853 	if (!i915_request_signaled(rq)) {
1854 		struct intel_timeline *tl = get_timeline(rq);
1855 
1856 		len = scnprintf(buf, sz,
1857 				"ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ",
1858 				i915_ggtt_offset(rq->ring->vma),
1859 				tl ? tl->hwsp_offset : 0,
1860 				hwsp_seqno(rq),
1861 				DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
1862 						      1000 * 1000));
1863 
1864 		if (tl)
1865 			intel_timeline_put(tl);
1866 	}
1867 
1868 	return len;
1869 }
1870 
1871 static void hexdump(struct drm_printer *m, const void *buf, size_t len)
1872 {
1873 	const size_t rowsize = 8 * sizeof(u32);
1874 	const void *prev = NULL;
1875 	bool skip = false;
1876 	size_t pos;
1877 
1878 	for (pos = 0; pos < len; pos += rowsize) {
1879 		char line[128];
1880 
1881 		if (prev && !memcmp(prev, buf + pos, rowsize)) {
1882 			if (!skip) {
1883 				drm_printf(m, "*\n");
1884 				skip = true;
1885 			}
1886 			continue;
1887 		}
1888 
1889 		WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
1890 						rowsize, sizeof(u32),
1891 						line, sizeof(line),
1892 						false) >= sizeof(line));
1893 		drm_printf(m, "[%04zx] %s\n", pos, line);
1894 
1895 		prev = buf + pos;
1896 		skip = false;
1897 	}
1898 }
1899 
1900 static const char *repr_timer(const struct timer_list *t)
1901 {
1902 	if (!READ_ONCE(t->expires))
1903 		return "inactive";
1904 
1905 	if (timer_pending(t))
1906 		return "active";
1907 
1908 	return "expired";
1909 }
1910 
1911 static void intel_engine_print_registers(struct intel_engine_cs *engine,
1912 					 struct drm_printer *m)
1913 {
1914 	struct drm_i915_private *dev_priv = engine->i915;
1915 	struct intel_engine_execlists * const execlists = &engine->execlists;
1916 	u64 addr;
1917 
1918 	if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7))
1919 		drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
1920 	if (HAS_EXECLISTS(dev_priv)) {
1921 		drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
1922 			   ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
1923 		drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
1924 			   ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
1925 	}
1926 	drm_printf(m, "\tRING_START: 0x%08x\n",
1927 		   ENGINE_READ(engine, RING_START));
1928 	drm_printf(m, "\tRING_HEAD:  0x%08x\n",
1929 		   ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
1930 	drm_printf(m, "\tRING_TAIL:  0x%08x\n",
1931 		   ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
1932 	drm_printf(m, "\tRING_CTL:   0x%08x%s\n",
1933 		   ENGINE_READ(engine, RING_CTL),
1934 		   ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
1935 	if (GRAPHICS_VER(engine->i915) > 2) {
1936 		drm_printf(m, "\tRING_MODE:  0x%08x%s\n",
1937 			   ENGINE_READ(engine, RING_MI_MODE),
1938 			   ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
1939 	}
1940 
1941 	if (GRAPHICS_VER(dev_priv) >= 6) {
1942 		drm_printf(m, "\tRING_IMR:   0x%08x\n",
1943 			   ENGINE_READ(engine, RING_IMR));
1944 		drm_printf(m, "\tRING_ESR:   0x%08x\n",
1945 			   ENGINE_READ(engine, RING_ESR));
1946 		drm_printf(m, "\tRING_EMR:   0x%08x\n",
1947 			   ENGINE_READ(engine, RING_EMR));
1948 		drm_printf(m, "\tRING_EIR:   0x%08x\n",
1949 			   ENGINE_READ(engine, RING_EIR));
1950 	}
1951 
1952 	addr = intel_engine_get_active_head(engine);
1953 	drm_printf(m, "\tACTHD:  0x%08x_%08x\n",
1954 		   upper_32_bits(addr), lower_32_bits(addr));
1955 	addr = intel_engine_get_last_batch_head(engine);
1956 	drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
1957 		   upper_32_bits(addr), lower_32_bits(addr));
1958 	if (GRAPHICS_VER(dev_priv) >= 8)
1959 		addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
1960 	else if (GRAPHICS_VER(dev_priv) >= 4)
1961 		addr = ENGINE_READ(engine, RING_DMA_FADD);
1962 	else
1963 		addr = ENGINE_READ(engine, DMA_FADD_I8XX);
1964 	drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
1965 		   upper_32_bits(addr), lower_32_bits(addr));
1966 	if (GRAPHICS_VER(dev_priv) >= 4) {
1967 		drm_printf(m, "\tIPEIR: 0x%08x\n",
1968 			   ENGINE_READ(engine, RING_IPEIR));
1969 		drm_printf(m, "\tIPEHR: 0x%08x\n",
1970 			   ENGINE_READ(engine, RING_IPEHR));
1971 	} else {
1972 		drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
1973 		drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
1974 	}
1975 
1976 	if (HAS_EXECLISTS(dev_priv) && !intel_engine_uses_guc(engine)) {
1977 		struct i915_request * const *port, *rq;
1978 		const u32 *hws =
1979 			&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
1980 		const u8 num_entries = execlists->csb_size;
1981 		unsigned int idx;
1982 		u8 read, write;
1983 
1984 		drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",
1985 			   str_yes_no(test_bit(TASKLET_STATE_SCHED, &engine->sched_engine->tasklet.state)),
1986 			   str_enabled_disabled(!atomic_read(&engine->sched_engine->tasklet.count)),
1987 			   repr_timer(&engine->execlists.preempt),
1988 			   repr_timer(&engine->execlists.timer));
1989 
1990 		read = execlists->csb_head;
1991 		write = READ_ONCE(*execlists->csb_write);
1992 
1993 		drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n",
1994 			   ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
1995 			   ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
1996 			   read, write, num_entries);
1997 
1998 		if (read >= num_entries)
1999 			read = 0;
2000 		if (write >= num_entries)
2001 			write = 0;
2002 		if (read > write)
2003 			write += num_entries;
2004 		while (read < write) {
2005 			idx = ++read % num_entries;
2006 			drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
2007 				   idx, hws[idx * 2], hws[idx * 2 + 1]);
2008 		}
2009 
2010 		i915_sched_engine_active_lock_bh(engine->sched_engine);
2011 		rcu_read_lock();
2012 		for (port = execlists->active; (rq = *port); port++) {
2013 			char hdr[160];
2014 			int len;
2015 
2016 			len = scnprintf(hdr, sizeof(hdr),
2017 					"\t\tActive[%d]:  ccid:%08x%s%s, ",
2018 					(int)(port - execlists->active),
2019 					rq->context->lrc.ccid,
2020 					intel_context_is_closed(rq->context) ? "!" : "",
2021 					intel_context_is_banned(rq->context) ? "*" : "");
2022 			len += print_ring(hdr + len, sizeof(hdr) - len, rq);
2023 			scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
2024 			i915_request_show(m, rq, hdr, 0);
2025 		}
2026 		for (port = execlists->pending; (rq = *port); port++) {
2027 			char hdr[160];
2028 			int len;
2029 
2030 			len = scnprintf(hdr, sizeof(hdr),
2031 					"\t\tPending[%d]: ccid:%08x%s%s, ",
2032 					(int)(port - execlists->pending),
2033 					rq->context->lrc.ccid,
2034 					intel_context_is_closed(rq->context) ? "!" : "",
2035 					intel_context_is_banned(rq->context) ? "*" : "");
2036 			len += print_ring(hdr + len, sizeof(hdr) - len, rq);
2037 			scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
2038 			i915_request_show(m, rq, hdr, 0);
2039 		}
2040 		rcu_read_unlock();
2041 		i915_sched_engine_active_unlock_bh(engine->sched_engine);
2042 	} else if (GRAPHICS_VER(dev_priv) > 6) {
2043 		drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
2044 			   ENGINE_READ(engine, RING_PP_DIR_BASE));
2045 		drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
2046 			   ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
2047 		drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
2048 			   ENGINE_READ(engine, RING_PP_DIR_DCLV));
2049 	}
2050 }
2051 
2052 static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
2053 {
2054 	struct i915_vma_resource *vma_res = rq->batch_res;
2055 	void *ring;
2056 	int size;
2057 
2058 	drm_printf(m,
2059 		   "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
2060 		   rq->head, rq->postfix, rq->tail,
2061 		   vma_res ? upper_32_bits(vma_res->start) : ~0u,
2062 		   vma_res ? lower_32_bits(vma_res->start) : ~0u);
2063 
2064 	size = rq->tail - rq->head;
2065 	if (rq->tail < rq->head)
2066 		size += rq->ring->size;
2067 
2068 	ring = kmalloc(size, GFP_ATOMIC);
2069 	if (ring) {
2070 		const void *vaddr = rq->ring->vaddr;
2071 		unsigned int head = rq->head;
2072 		unsigned int len = 0;
2073 
2074 		if (rq->tail < head) {
2075 			len = rq->ring->size - head;
2076 			memcpy(ring, vaddr + head, len);
2077 			head = 0;
2078 		}
2079 		memcpy(ring + len, vaddr + head, size - len);
2080 
2081 		hexdump(m, ring, size);
2082 		kfree(ring);
2083 	}
2084 }
2085 
2086 static unsigned long list_count(struct list_head *list)
2087 {
2088 	struct list_head *pos;
2089 	unsigned long count = 0;
2090 
2091 	list_for_each(pos, list)
2092 		count++;
2093 
2094 	return count;
2095 }
2096 
2097 static unsigned long read_ul(void *p, size_t x)
2098 {
2099 	return *(unsigned long *)(p + x);
2100 }
2101 
2102 static void print_properties(struct intel_engine_cs *engine,
2103 			     struct drm_printer *m)
2104 {
2105 	static const struct pmap {
2106 		size_t offset;
2107 		const char *name;
2108 	} props[] = {
2109 #define P(x) { \
2110 	.offset = offsetof(typeof(engine->props), x), \
2111 	.name = #x \
2112 }
2113 		P(heartbeat_interval_ms),
2114 		P(max_busywait_duration_ns),
2115 		P(preempt_timeout_ms),
2116 		P(stop_timeout_ms),
2117 		P(timeslice_duration_ms),
2118 
2119 		{},
2120 #undef P
2121 	};
2122 	const struct pmap *p;
2123 
2124 	drm_printf(m, "\tProperties:\n");
2125 	for (p = props; p->name; p++)
2126 		drm_printf(m, "\t\t%s: %lu [default %lu]\n",
2127 			   p->name,
2128 			   read_ul(&engine->props, p->offset),
2129 			   read_ul(&engine->defaults, p->offset));
2130 }
2131 
2132 static void engine_dump_request(struct i915_request *rq, struct drm_printer *m, const char *msg)
2133 {
2134 	struct intel_timeline *tl = get_timeline(rq);
2135 
2136 	i915_request_show(m, rq, msg, 0);
2137 
2138 	drm_printf(m, "\t\tring->start:  0x%08x\n",
2139 		   i915_ggtt_offset(rq->ring->vma));
2140 	drm_printf(m, "\t\tring->head:   0x%08x\n",
2141 		   rq->ring->head);
2142 	drm_printf(m, "\t\tring->tail:   0x%08x\n",
2143 		   rq->ring->tail);
2144 	drm_printf(m, "\t\tring->emit:   0x%08x\n",
2145 		   rq->ring->emit);
2146 	drm_printf(m, "\t\tring->space:  0x%08x\n",
2147 		   rq->ring->space);
2148 
2149 	if (tl) {
2150 		drm_printf(m, "\t\tring->hwsp:   0x%08x\n",
2151 			   tl->hwsp_offset);
2152 		intel_timeline_put(tl);
2153 	}
2154 
2155 	print_request_ring(m, rq);
2156 
2157 	if (rq->context->lrc_reg_state) {
2158 		drm_printf(m, "Logical Ring Context:\n");
2159 		hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE);
2160 	}
2161 }
2162 
2163 void intel_engine_dump_active_requests(struct list_head *requests,
2164 				       struct i915_request *hung_rq,
2165 				       struct drm_printer *m)
2166 {
2167 	struct i915_request *rq;
2168 	const char *msg;
2169 	enum i915_request_state state;
2170 
2171 	list_for_each_entry(rq, requests, sched.link) {
2172 		if (rq == hung_rq)
2173 			continue;
2174 
2175 		state = i915_test_request_state(rq);
2176 		if (state < I915_REQUEST_QUEUED)
2177 			continue;
2178 
2179 		if (state == I915_REQUEST_ACTIVE)
2180 			msg = "\t\tactive on engine";
2181 		else
2182 			msg = "\t\tactive in queue";
2183 
2184 		engine_dump_request(rq, m, msg);
2185 	}
2186 }
2187 
2188 static void engine_dump_active_requests(struct intel_engine_cs *engine, struct drm_printer *m)
2189 {
2190 	struct i915_request *hung_rq = NULL;
2191 	struct intel_context *ce;
2192 	bool guc;
2193 
2194 	/*
2195 	 * No need for an engine->irq_seqno_barrier() before the seqno reads.
2196 	 * The GPU is still running so requests are still executing and any
2197 	 * hardware reads will be out of date by the time they are reported.
2198 	 * But the intention here is just to report an instantaneous snapshot
2199 	 * so that's fine.
2200 	 */
2201 	lockdep_assert_held(&engine->sched_engine->lock);
2202 
2203 	drm_printf(m, "\tRequests:\n");
2204 
2205 	guc = intel_uc_uses_guc_submission(&engine->gt->uc);
2206 	if (guc) {
2207 		ce = intel_engine_get_hung_context(engine);
2208 		if (ce)
2209 			hung_rq = intel_context_find_active_request(ce);
2210 	} else {
2211 		hung_rq = intel_engine_execlist_find_hung_request(engine);
2212 	}
2213 
2214 	if (hung_rq)
2215 		engine_dump_request(hung_rq, m, "\t\thung");
2216 
2217 	if (guc)
2218 		intel_guc_dump_active_requests(engine, hung_rq, m);
2219 	else
2220 		intel_engine_dump_active_requests(&engine->sched_engine->requests,
2221 						  hung_rq, m);
2222 }
2223 
2224 void intel_engine_dump(struct intel_engine_cs *engine,
2225 		       struct drm_printer *m,
2226 		       const char *header, ...)
2227 {
2228 	struct i915_gpu_error * const error = &engine->i915->gpu_error;
2229 	struct i915_request *rq;
2230 	intel_wakeref_t wakeref;
2231 	unsigned long flags;
2232 	ktime_t dummy;
2233 
2234 	if (header) {
2235 		va_list ap;
2236 
2237 		va_start(ap, header);
2238 		drm_vprintf(m, header, &ap);
2239 		va_end(ap);
2240 	}
2241 
2242 	if (intel_gt_is_wedged(engine->gt))
2243 		drm_printf(m, "*** WEDGED ***\n");
2244 
2245 	drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
2246 	drm_printf(m, "\tBarriers?: %s\n",
2247 		   str_yes_no(!llist_empty(&engine->barrier_tasks)));
2248 	drm_printf(m, "\tLatency: %luus\n",
2249 		   ewma__engine_latency_read(&engine->latency));
2250 	if (intel_engine_supports_stats(engine))
2251 		drm_printf(m, "\tRuntime: %llums\n",
2252 			   ktime_to_ms(intel_engine_get_busy_time(engine,
2253 								  &dummy)));
2254 	drm_printf(m, "\tForcewake: %x domains, %d active\n",
2255 		   engine->fw_domain, READ_ONCE(engine->fw_active));
2256 
2257 	rcu_read_lock();
2258 	rq = READ_ONCE(engine->heartbeat.systole);
2259 	if (rq)
2260 		drm_printf(m, "\tHeartbeat: %d ms ago\n",
2261 			   jiffies_to_msecs(jiffies - rq->emitted_jiffies));
2262 	rcu_read_unlock();
2263 	drm_printf(m, "\tReset count: %d (global %d)\n",
2264 		   i915_reset_engine_count(error, engine),
2265 		   i915_reset_count(error));
2266 	print_properties(engine, m);
2267 
2268 	spin_lock_irqsave(&engine->sched_engine->lock, flags);
2269 	engine_dump_active_requests(engine, m);
2270 
2271 	drm_printf(m, "\tOn hold?: %lu\n",
2272 		   list_count(&engine->sched_engine->hold));
2273 	spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
2274 
2275 	drm_printf(m, "\tMMIO base:  0x%08x\n", engine->mmio_base);
2276 	wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
2277 	if (wakeref) {
2278 		intel_engine_print_registers(engine, m);
2279 		intel_runtime_pm_put(engine->uncore->rpm, wakeref);
2280 	} else {
2281 		drm_printf(m, "\tDevice is asleep; skipping register dump\n");
2282 	}
2283 
2284 	intel_execlists_show_requests(engine, m, i915_request_show, 8);
2285 
2286 	drm_printf(m, "HWSP:\n");
2287 	hexdump(m, engine->status_page.addr, PAGE_SIZE);
2288 
2289 	drm_printf(m, "Idle? %s\n", str_yes_no(intel_engine_is_idle(engine)));
2290 
2291 	intel_engine_print_breadcrumbs(engine, m);
2292 }
2293 
2294 /**
2295  * intel_engine_get_busy_time() - Return current accumulated engine busyness
2296  * @engine: engine to report on
2297  * @now: monotonic timestamp of sampling
2298  *
2299  * Returns accumulated time @engine was busy since engine stats were enabled.
2300  */
2301 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now)
2302 {
2303 	return engine->busyness(engine, now);
2304 }
2305 
2306 struct intel_context *
2307 intel_engine_create_virtual(struct intel_engine_cs **siblings,
2308 			    unsigned int count, unsigned long flags)
2309 {
2310 	if (count == 0)
2311 		return ERR_PTR(-EINVAL);
2312 
2313 	if (count == 1 && !(flags & FORCE_VIRTUAL))
2314 		return intel_context_create(siblings[0]);
2315 
2316 	GEM_BUG_ON(!siblings[0]->cops->create_virtual);
2317 	return siblings[0]->cops->create_virtual(siblings, count, flags);
2318 }
2319 
2320 struct i915_request *
2321 intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine)
2322 {
2323 	struct i915_request *request, *active = NULL;
2324 
2325 	/*
2326 	 * This search does not work in GuC submission mode. However, the GuC
2327 	 * will report the hanging context directly to the driver itself. So
2328 	 * the driver should never get here when in GuC mode.
2329 	 */
2330 	GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc));
2331 
2332 	/*
2333 	 * We are called by the error capture, reset and to dump engine
2334 	 * state at random points in time. In particular, note that neither is
2335 	 * crucially ordered with an interrupt. After a hang, the GPU is dead
2336 	 * and we assume that no more writes can happen (we waited long enough
2337 	 * for all writes that were in transaction to be flushed) - adding an
2338 	 * extra delay for a recent interrupt is pointless. Hence, we do
2339 	 * not need an engine->irq_seqno_barrier() before the seqno reads.
2340 	 * At all other times, we must assume the GPU is still running, but
2341 	 * we only care about the snapshot of this moment.
2342 	 */
2343 	lockdep_assert_held(&engine->sched_engine->lock);
2344 
2345 	rcu_read_lock();
2346 	request = execlists_active(&engine->execlists);
2347 	if (request) {
2348 		struct intel_timeline *tl = request->context->timeline;
2349 
2350 		list_for_each_entry_from_reverse(request, &tl->requests, link) {
2351 			if (__i915_request_is_complete(request))
2352 				break;
2353 
2354 			active = request;
2355 		}
2356 	}
2357 	rcu_read_unlock();
2358 	if (active)
2359 		return active;
2360 
2361 	list_for_each_entry(request, &engine->sched_engine->requests,
2362 			    sched.link) {
2363 		if (i915_test_request_state(request) != I915_REQUEST_ACTIVE)
2364 			continue;
2365 
2366 		active = request;
2367 		break;
2368 	}
2369 
2370 	return active;
2371 }
2372 
2373 void xehp_enable_ccs_engines(struct intel_engine_cs *engine)
2374 {
2375 	/*
2376 	 * If there are any non-fused-off CCS engines, we need to enable CCS
2377 	 * support in the RCU_MODE register.  This only needs to be done once,
2378 	 * so for simplicity we'll take care of this in the RCS engine's
2379 	 * resume handler; since the RCS and all CCS engines belong to the
2380 	 * same reset domain and are reset together, this will also take care
2381 	 * of re-applying the setting after i915-triggered resets.
2382 	 */
2383 	if (!CCS_MASK(engine->gt))
2384 		return;
2385 
2386 	intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
2387 			   _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
2388 }
2389 
2390 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2391 #include "mock_engine.c"
2392 #include "selftest_engine.c"
2393 #include "selftest_engine_cs.c"
2394 #endif
2395