1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_print.h> 26 27 #include "gem/i915_gem_context.h" 28 29 #include "i915_drv.h" 30 31 #include "intel_breadcrumbs.h" 32 #include "intel_context.h" 33 #include "intel_engine.h" 34 #include "intel_engine_pm.h" 35 #include "intel_engine_user.h" 36 #include "intel_gt.h" 37 #include "intel_gt_requests.h" 38 #include "intel_gt_pm.h" 39 #include "intel_lrc.h" 40 #include "intel_reset.h" 41 #include "intel_ring.h" 42 43 /* Haswell does have the CXT_SIZE register however it does not appear to be 44 * valid. Now, docs explain in dwords what is in the context object. The full 45 * size is 70720 bytes, however, the power context and execlist context will 46 * never be saved (power context is stored elsewhere, and execlists don't work 47 * on HSW) - so the final size, including the extra state required for the 48 * Resource Streamer, is 66944 bytes, which rounds to 17 pages. 49 */ 50 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 51 52 #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 53 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) 54 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 55 #define GEN10_LR_CONTEXT_RENDER_SIZE (18 * PAGE_SIZE) 56 #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE) 57 58 #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE) 59 60 #define MAX_MMIO_BASES 3 61 struct engine_info { 62 unsigned int hw_id; 63 u8 class; 64 u8 instance; 65 /* mmio bases table *must* be sorted in reverse gen order */ 66 struct engine_mmio_base { 67 u32 gen : 8; 68 u32 base : 24; 69 } mmio_bases[MAX_MMIO_BASES]; 70 }; 71 72 static const struct engine_info intel_engines[] = { 73 [RCS0] = { 74 .hw_id = RCS0_HW, 75 .class = RENDER_CLASS, 76 .instance = 0, 77 .mmio_bases = { 78 { .gen = 1, .base = RENDER_RING_BASE } 79 }, 80 }, 81 [BCS0] = { 82 .hw_id = BCS0_HW, 83 .class = COPY_ENGINE_CLASS, 84 .instance = 0, 85 .mmio_bases = { 86 { .gen = 6, .base = BLT_RING_BASE } 87 }, 88 }, 89 [VCS0] = { 90 .hw_id = VCS0_HW, 91 .class = VIDEO_DECODE_CLASS, 92 .instance = 0, 93 .mmio_bases = { 94 { .gen = 11, .base = GEN11_BSD_RING_BASE }, 95 { .gen = 6, .base = GEN6_BSD_RING_BASE }, 96 { .gen = 4, .base = BSD_RING_BASE } 97 }, 98 }, 99 [VCS1] = { 100 .hw_id = VCS1_HW, 101 .class = VIDEO_DECODE_CLASS, 102 .instance = 1, 103 .mmio_bases = { 104 { .gen = 11, .base = GEN11_BSD2_RING_BASE }, 105 { .gen = 8, .base = GEN8_BSD2_RING_BASE } 106 }, 107 }, 108 [VCS2] = { 109 .hw_id = VCS2_HW, 110 .class = VIDEO_DECODE_CLASS, 111 .instance = 2, 112 .mmio_bases = { 113 { .gen = 11, .base = GEN11_BSD3_RING_BASE } 114 }, 115 }, 116 [VCS3] = { 117 .hw_id = VCS3_HW, 118 .class = VIDEO_DECODE_CLASS, 119 .instance = 3, 120 .mmio_bases = { 121 { .gen = 11, .base = GEN11_BSD4_RING_BASE } 122 }, 123 }, 124 [VECS0] = { 125 .hw_id = VECS0_HW, 126 .class = VIDEO_ENHANCEMENT_CLASS, 127 .instance = 0, 128 .mmio_bases = { 129 { .gen = 11, .base = GEN11_VEBOX_RING_BASE }, 130 { .gen = 7, .base = VEBOX_RING_BASE } 131 }, 132 }, 133 [VECS1] = { 134 .hw_id = VECS1_HW, 135 .class = VIDEO_ENHANCEMENT_CLASS, 136 .instance = 1, 137 .mmio_bases = { 138 { .gen = 11, .base = GEN11_VEBOX2_RING_BASE } 139 }, 140 }, 141 }; 142 143 /** 144 * intel_engine_context_size() - return the size of the context for an engine 145 * @gt: the gt 146 * @class: engine class 147 * 148 * Each engine class may require a different amount of space for a context 149 * image. 150 * 151 * Return: size (in bytes) of an engine class specific context image 152 * 153 * Note: this size includes the HWSP, which is part of the context image 154 * in LRC mode, but does not include the "shared data page" used with 155 * GuC submission. The caller should account for this if using the GuC. 156 */ 157 u32 intel_engine_context_size(struct intel_gt *gt, u8 class) 158 { 159 struct intel_uncore *uncore = gt->uncore; 160 u32 cxt_size; 161 162 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE); 163 164 switch (class) { 165 case RENDER_CLASS: 166 switch (INTEL_GEN(gt->i915)) { 167 default: 168 MISSING_CASE(INTEL_GEN(gt->i915)); 169 return DEFAULT_LR_CONTEXT_RENDER_SIZE; 170 case 12: 171 case 11: 172 return GEN11_LR_CONTEXT_RENDER_SIZE; 173 case 10: 174 return GEN10_LR_CONTEXT_RENDER_SIZE; 175 case 9: 176 return GEN9_LR_CONTEXT_RENDER_SIZE; 177 case 8: 178 return GEN8_LR_CONTEXT_RENDER_SIZE; 179 case 7: 180 if (IS_HASWELL(gt->i915)) 181 return HSW_CXT_TOTAL_SIZE; 182 183 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE); 184 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64, 185 PAGE_SIZE); 186 case 6: 187 cxt_size = intel_uncore_read(uncore, CXT_SIZE); 188 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64, 189 PAGE_SIZE); 190 case 5: 191 case 4: 192 /* 193 * There is a discrepancy here between the size reported 194 * by the register and the size of the context layout 195 * in the docs. Both are described as authorative! 196 * 197 * The discrepancy is on the order of a few cachelines, 198 * but the total is under one page (4k), which is our 199 * minimum allocation anyway so it should all come 200 * out in the wash. 201 */ 202 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1; 203 drm_dbg(>->i915->drm, 204 "gen%d CXT_SIZE = %d bytes [0x%08x]\n", 205 INTEL_GEN(gt->i915), cxt_size * 64, 206 cxt_size - 1); 207 return round_up(cxt_size * 64, PAGE_SIZE); 208 case 3: 209 case 2: 210 /* For the special day when i810 gets merged. */ 211 case 1: 212 return 0; 213 } 214 break; 215 default: 216 MISSING_CASE(class); 217 fallthrough; 218 case VIDEO_DECODE_CLASS: 219 case VIDEO_ENHANCEMENT_CLASS: 220 case COPY_ENGINE_CLASS: 221 if (INTEL_GEN(gt->i915) < 8) 222 return 0; 223 return GEN8_LR_CONTEXT_OTHER_SIZE; 224 } 225 } 226 227 static u32 __engine_mmio_base(struct drm_i915_private *i915, 228 const struct engine_mmio_base *bases) 229 { 230 int i; 231 232 for (i = 0; i < MAX_MMIO_BASES; i++) 233 if (INTEL_GEN(i915) >= bases[i].gen) 234 break; 235 236 GEM_BUG_ON(i == MAX_MMIO_BASES); 237 GEM_BUG_ON(!bases[i].base); 238 239 return bases[i].base; 240 } 241 242 static void __sprint_engine_name(struct intel_engine_cs *engine) 243 { 244 /* 245 * Before we know what the uABI name for this engine will be, 246 * we still would like to keep track of this engine in the debug logs. 247 * We throw in a ' here as a reminder that this isn't its final name. 248 */ 249 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u", 250 intel_engine_class_repr(engine->class), 251 engine->instance) >= sizeof(engine->name)); 252 } 253 254 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask) 255 { 256 /* 257 * Though they added more rings on g4x/ilk, they did not add 258 * per-engine HWSTAM until gen6. 259 */ 260 if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS) 261 return; 262 263 if (INTEL_GEN(engine->i915) >= 3) 264 ENGINE_WRITE(engine, RING_HWSTAM, mask); 265 else 266 ENGINE_WRITE16(engine, RING_HWSTAM, mask); 267 } 268 269 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine) 270 { 271 /* Mask off all writes into the unknown HWSP */ 272 intel_engine_set_hwsp_writemask(engine, ~0u); 273 } 274 275 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) 276 { 277 const struct engine_info *info = &intel_engines[id]; 278 struct drm_i915_private *i915 = gt->i915; 279 struct intel_engine_cs *engine; 280 281 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH)); 282 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH)); 283 284 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine))) 285 return -EINVAL; 286 287 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS)) 288 return -EINVAL; 289 290 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE)) 291 return -EINVAL; 292 293 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance])) 294 return -EINVAL; 295 296 engine = kzalloc(sizeof(*engine), GFP_KERNEL); 297 if (!engine) 298 return -ENOMEM; 299 300 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES); 301 302 engine->id = id; 303 engine->legacy_idx = INVALID_ENGINE; 304 engine->mask = BIT(id); 305 engine->i915 = i915; 306 engine->gt = gt; 307 engine->uncore = gt->uncore; 308 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases); 309 engine->hw_id = info->hw_id; 310 engine->guc_id = MAKE_GUC_ID(info->class, info->instance); 311 312 engine->class = info->class; 313 engine->instance = info->instance; 314 __sprint_engine_name(engine); 315 316 engine->props.heartbeat_interval_ms = 317 CONFIG_DRM_I915_HEARTBEAT_INTERVAL; 318 engine->props.max_busywait_duration_ns = 319 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT; 320 engine->props.preempt_timeout_ms = 321 CONFIG_DRM_I915_PREEMPT_TIMEOUT; 322 engine->props.stop_timeout_ms = 323 CONFIG_DRM_I915_STOP_TIMEOUT; 324 engine->props.timeslice_duration_ms = 325 CONFIG_DRM_I915_TIMESLICE_DURATION; 326 327 /* Override to uninterruptible for OpenCL workloads. */ 328 if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS) 329 engine->props.preempt_timeout_ms = 0; 330 331 engine->defaults = engine->props; /* never to change again */ 332 333 engine->context_size = intel_engine_context_size(gt, engine->class); 334 if (WARN_ON(engine->context_size > BIT(20))) 335 engine->context_size = 0; 336 if (engine->context_size) 337 DRIVER_CAPS(i915)->has_logical_contexts = true; 338 339 /* Nothing to do here, execute in order of dependencies */ 340 engine->schedule = NULL; 341 342 ewma__engine_latency_init(&engine->latency); 343 seqlock_init(&engine->stats.lock); 344 345 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); 346 347 /* Scrub mmio state on takeover */ 348 intel_engine_sanitize_mmio(engine); 349 350 gt->engine_class[info->class][info->instance] = engine; 351 gt->engine[id] = engine; 352 353 return 0; 354 } 355 356 static void __setup_engine_capabilities(struct intel_engine_cs *engine) 357 { 358 struct drm_i915_private *i915 = engine->i915; 359 360 if (engine->class == VIDEO_DECODE_CLASS) { 361 /* 362 * HEVC support is present on first engine instance 363 * before Gen11 and on all instances afterwards. 364 */ 365 if (INTEL_GEN(i915) >= 11 || 366 (INTEL_GEN(i915) >= 9 && engine->instance == 0)) 367 engine->uabi_capabilities |= 368 I915_VIDEO_CLASS_CAPABILITY_HEVC; 369 370 /* 371 * SFC block is present only on even logical engine 372 * instances. 373 */ 374 if ((INTEL_GEN(i915) >= 11 && 375 (engine->gt->info.vdbox_sfc_access & 376 BIT(engine->instance))) || 377 (INTEL_GEN(i915) >= 9 && engine->instance == 0)) 378 engine->uabi_capabilities |= 379 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 380 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) { 381 if (INTEL_GEN(i915) >= 9) 382 engine->uabi_capabilities |= 383 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 384 } 385 } 386 387 static void intel_setup_engine_capabilities(struct intel_gt *gt) 388 { 389 struct intel_engine_cs *engine; 390 enum intel_engine_id id; 391 392 for_each_engine(engine, gt, id) 393 __setup_engine_capabilities(engine); 394 } 395 396 /** 397 * intel_engines_release() - free the resources allocated for Command Streamers 398 * @gt: pointer to struct intel_gt 399 */ 400 void intel_engines_release(struct intel_gt *gt) 401 { 402 struct intel_engine_cs *engine; 403 enum intel_engine_id id; 404 405 /* 406 * Before we release the resources held by engine, we must be certain 407 * that the HW is no longer accessing them -- having the GPU scribble 408 * to or read from a page being used for something else causes no end 409 * of fun. 410 * 411 * The GPU should be reset by this point, but assume the worst just 412 * in case we aborted before completely initialising the engines. 413 */ 414 GEM_BUG_ON(intel_gt_pm_is_awake(gt)); 415 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) 416 __intel_gt_reset(gt, ALL_ENGINES); 417 418 /* Decouple the backend; but keep the layout for late GPU resets */ 419 for_each_engine(engine, gt, id) { 420 if (!engine->release) 421 continue; 422 423 intel_wakeref_wait_for_idle(&engine->wakeref); 424 GEM_BUG_ON(intel_engine_pm_is_awake(engine)); 425 426 engine->release(engine); 427 engine->release = NULL; 428 429 memset(&engine->reset, 0, sizeof(engine->reset)); 430 } 431 } 432 433 void intel_engine_free_request_pool(struct intel_engine_cs *engine) 434 { 435 if (!engine->request_pool) 436 return; 437 438 kmem_cache_free(i915_request_slab_cache(), engine->request_pool); 439 } 440 441 void intel_engines_free(struct intel_gt *gt) 442 { 443 struct intel_engine_cs *engine; 444 enum intel_engine_id id; 445 446 /* Free the requests! dma-resv keeps fences around for an eternity */ 447 rcu_barrier(); 448 449 for_each_engine(engine, gt, id) { 450 intel_engine_free_request_pool(engine); 451 kfree(engine); 452 gt->engine[id] = NULL; 453 } 454 } 455 456 /* 457 * Determine which engines are fused off in our particular hardware. 458 * Note that we have a catch-22 situation where we need to be able to access 459 * the blitter forcewake domain to read the engine fuses, but at the same time 460 * we need to know which engines are available on the system to know which 461 * forcewake domains are present. We solve this by intializing the forcewake 462 * domains based on the full engine mask in the platform capabilities before 463 * calling this function and pruning the domains for fused-off engines 464 * afterwards. 465 */ 466 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) 467 { 468 struct drm_i915_private *i915 = gt->i915; 469 struct intel_gt_info *info = >->info; 470 struct intel_uncore *uncore = gt->uncore; 471 unsigned int logical_vdbox = 0; 472 unsigned int i; 473 u32 media_fuse; 474 u16 vdbox_mask; 475 u16 vebox_mask; 476 477 info->engine_mask = INTEL_INFO(i915)->platform_engine_mask; 478 479 if (INTEL_GEN(i915) < 11) 480 return info->engine_mask; 481 482 media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); 483 484 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; 485 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> 486 GEN11_GT_VEBOX_DISABLE_SHIFT; 487 488 for (i = 0; i < I915_MAX_VCS; i++) { 489 if (!HAS_ENGINE(gt, _VCS(i))) { 490 vdbox_mask &= ~BIT(i); 491 continue; 492 } 493 494 if (!(BIT(i) & vdbox_mask)) { 495 info->engine_mask &= ~BIT(_VCS(i)); 496 drm_dbg(&i915->drm, "vcs%u fused off\n", i); 497 continue; 498 } 499 500 /* 501 * In Gen11, only even numbered logical VDBOXes are 502 * hooked up to an SFC (Scaler & Format Converter) unit. 503 * In TGL each VDBOX has access to an SFC. 504 */ 505 if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0) 506 gt->info.vdbox_sfc_access |= BIT(i); 507 } 508 drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n", 509 vdbox_mask, VDBOX_MASK(gt)); 510 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt)); 511 512 for (i = 0; i < I915_MAX_VECS; i++) { 513 if (!HAS_ENGINE(gt, _VECS(i))) { 514 vebox_mask &= ~BIT(i); 515 continue; 516 } 517 518 if (!(BIT(i) & vebox_mask)) { 519 info->engine_mask &= ~BIT(_VECS(i)); 520 drm_dbg(&i915->drm, "vecs%u fused off\n", i); 521 } 522 } 523 drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n", 524 vebox_mask, VEBOX_MASK(gt)); 525 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); 526 527 return info->engine_mask; 528 } 529 530 /** 531 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers 532 * @gt: pointer to struct intel_gt 533 * 534 * Return: non-zero if the initialization failed. 535 */ 536 int intel_engines_init_mmio(struct intel_gt *gt) 537 { 538 struct drm_i915_private *i915 = gt->i915; 539 const unsigned int engine_mask = init_engine_mask(gt); 540 unsigned int mask = 0; 541 unsigned int i; 542 int err; 543 544 drm_WARN_ON(&i915->drm, engine_mask == 0); 545 drm_WARN_ON(&i915->drm, engine_mask & 546 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES)); 547 548 if (i915_inject_probe_failure(i915)) 549 return -ENODEV; 550 551 for (i = 0; i < ARRAY_SIZE(intel_engines); i++) { 552 if (!HAS_ENGINE(gt, i)) 553 continue; 554 555 err = intel_engine_setup(gt, i); 556 if (err) 557 goto cleanup; 558 559 mask |= BIT(i); 560 } 561 562 /* 563 * Catch failures to update intel_engines table when the new engines 564 * are added to the driver by a warning and disabling the forgotten 565 * engines. 566 */ 567 if (drm_WARN_ON(&i915->drm, mask != engine_mask)) 568 gt->info.engine_mask = mask; 569 570 gt->info.num_engines = hweight32(mask); 571 572 intel_gt_check_and_clear_faults(gt); 573 574 intel_setup_engine_capabilities(gt); 575 576 intel_uncore_prune_engine_fw_domains(gt->uncore, gt); 577 578 return 0; 579 580 cleanup: 581 intel_engines_free(gt); 582 return err; 583 } 584 585 void intel_engine_init_execlists(struct intel_engine_cs *engine) 586 { 587 struct intel_engine_execlists * const execlists = &engine->execlists; 588 589 execlists->port_mask = 1; 590 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists))); 591 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS); 592 593 memset(execlists->pending, 0, sizeof(execlists->pending)); 594 execlists->active = 595 memset(execlists->inflight, 0, sizeof(execlists->inflight)); 596 597 execlists->queue_priority_hint = INT_MIN; 598 execlists->queue = RB_ROOT_CACHED; 599 } 600 601 static void cleanup_status_page(struct intel_engine_cs *engine) 602 { 603 struct i915_vma *vma; 604 605 /* Prevent writes into HWSP after returning the page to the system */ 606 intel_engine_set_hwsp_writemask(engine, ~0u); 607 608 vma = fetch_and_zero(&engine->status_page.vma); 609 if (!vma) 610 return; 611 612 if (!HWS_NEEDS_PHYSICAL(engine->i915)) 613 i915_vma_unpin(vma); 614 615 i915_gem_object_unpin_map(vma->obj); 616 i915_gem_object_put(vma->obj); 617 } 618 619 static int pin_ggtt_status_page(struct intel_engine_cs *engine, 620 struct i915_vma *vma) 621 { 622 unsigned int flags; 623 624 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) 625 /* 626 * On g33, we cannot place HWS above 256MiB, so 627 * restrict its pinning to the low mappable arena. 628 * Though this restriction is not documented for 629 * gen4, gen5, or byt, they also behave similarly 630 * and hang if the HWS is placed at the top of the 631 * GTT. To generalise, it appears that all !llc 632 * platforms have issues with us placing the HWS 633 * above the mappable region (even though we never 634 * actually map it). 635 */ 636 flags = PIN_MAPPABLE; 637 else 638 flags = PIN_HIGH; 639 640 return i915_ggtt_pin(vma, NULL, 0, flags); 641 } 642 643 static int init_status_page(struct intel_engine_cs *engine) 644 { 645 struct drm_i915_gem_object *obj; 646 struct i915_vma *vma; 647 void *vaddr; 648 int ret; 649 650 /* 651 * Though the HWS register does support 36bit addresses, historically 652 * we have had hangs and corruption reported due to wild writes if 653 * the HWS is placed above 4G. We only allow objects to be allocated 654 * in GFP_DMA32 for i965, and no earlier physical address users had 655 * access to more than 4G. 656 */ 657 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); 658 if (IS_ERR(obj)) { 659 drm_err(&engine->i915->drm, 660 "Failed to allocate status page\n"); 661 return PTR_ERR(obj); 662 } 663 664 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 665 666 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); 667 if (IS_ERR(vma)) { 668 ret = PTR_ERR(vma); 669 goto err; 670 } 671 672 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); 673 if (IS_ERR(vaddr)) { 674 ret = PTR_ERR(vaddr); 675 goto err; 676 } 677 678 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE); 679 engine->status_page.vma = vma; 680 681 if (!HWS_NEEDS_PHYSICAL(engine->i915)) { 682 ret = pin_ggtt_status_page(engine, vma); 683 if (ret) 684 goto err_unpin; 685 } 686 687 return 0; 688 689 err_unpin: 690 i915_gem_object_unpin_map(obj); 691 err: 692 i915_gem_object_put(obj); 693 return ret; 694 } 695 696 static int engine_setup_common(struct intel_engine_cs *engine) 697 { 698 int err; 699 700 init_llist_head(&engine->barrier_tasks); 701 702 err = init_status_page(engine); 703 if (err) 704 return err; 705 706 engine->breadcrumbs = intel_breadcrumbs_create(engine); 707 if (!engine->breadcrumbs) { 708 err = -ENOMEM; 709 goto err_status; 710 } 711 712 intel_engine_init_active(engine, ENGINE_PHYSICAL); 713 intel_engine_init_execlists(engine); 714 intel_engine_init_cmd_parser(engine); 715 intel_engine_init__pm(engine); 716 intel_engine_init_retire(engine); 717 718 /* Use the whole device by default */ 719 engine->sseu = 720 intel_sseu_from_device_info(&engine->gt->info.sseu); 721 722 intel_engine_init_workarounds(engine); 723 intel_engine_init_whitelist(engine); 724 intel_engine_init_ctx_wa(engine); 725 726 return 0; 727 728 err_status: 729 cleanup_status_page(engine); 730 return err; 731 } 732 733 struct measure_breadcrumb { 734 struct i915_request rq; 735 struct intel_ring ring; 736 u32 cs[2048]; 737 }; 738 739 static int measure_breadcrumb_dw(struct intel_context *ce) 740 { 741 struct intel_engine_cs *engine = ce->engine; 742 struct measure_breadcrumb *frame; 743 int dw; 744 745 GEM_BUG_ON(!engine->gt->scratch); 746 747 frame = kzalloc(sizeof(*frame), GFP_KERNEL); 748 if (!frame) 749 return -ENOMEM; 750 751 frame->rq.engine = engine; 752 frame->rq.context = ce; 753 rcu_assign_pointer(frame->rq.timeline, ce->timeline); 754 755 frame->ring.vaddr = frame->cs; 756 frame->ring.size = sizeof(frame->cs); 757 frame->ring.wrap = 758 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size); 759 frame->ring.effective_size = frame->ring.size; 760 intel_ring_update_space(&frame->ring); 761 frame->rq.ring = &frame->ring; 762 763 mutex_lock(&ce->timeline->mutex); 764 spin_lock_irq(&engine->active.lock); 765 766 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs; 767 768 spin_unlock_irq(&engine->active.lock); 769 mutex_unlock(&ce->timeline->mutex); 770 771 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */ 772 773 kfree(frame); 774 return dw; 775 } 776 777 void 778 intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass) 779 { 780 INIT_LIST_HEAD(&engine->active.requests); 781 INIT_LIST_HEAD(&engine->active.hold); 782 783 spin_lock_init(&engine->active.lock); 784 lockdep_set_subclass(&engine->active.lock, subclass); 785 786 /* 787 * Due to an interesting quirk in lockdep's internal debug tracking, 788 * after setting a subclass we must ensure the lock is used. Otherwise, 789 * nr_unused_locks is incremented once too often. 790 */ 791 #ifdef CONFIG_DEBUG_LOCK_ALLOC 792 local_irq_disable(); 793 lock_map_acquire(&engine->active.lock.dep_map); 794 lock_map_release(&engine->active.lock.dep_map); 795 local_irq_enable(); 796 #endif 797 } 798 799 static struct intel_context * 800 create_pinned_context(struct intel_engine_cs *engine, 801 unsigned int hwsp, 802 struct lock_class_key *key, 803 const char *name) 804 { 805 struct intel_context *ce; 806 int err; 807 808 ce = intel_context_create(engine); 809 if (IS_ERR(ce)) 810 return ce; 811 812 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags); 813 ce->timeline = page_pack_bits(NULL, hwsp); 814 815 err = intel_context_pin(ce); /* perma-pin so it is always available */ 816 if (err) { 817 intel_context_put(ce); 818 return ERR_PTR(err); 819 } 820 821 /* 822 * Give our perma-pinned kernel timelines a separate lockdep class, 823 * so that we can use them from within the normal user timelines 824 * should we need to inject GPU operations during their request 825 * construction. 826 */ 827 lockdep_set_class_and_name(&ce->timeline->mutex, key, name); 828 829 return ce; 830 } 831 832 static struct intel_context * 833 create_kernel_context(struct intel_engine_cs *engine) 834 { 835 static struct lock_class_key kernel; 836 837 return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR, 838 &kernel, "kernel_context"); 839 } 840 841 /** 842 * intel_engines_init_common - initialize cengine state which might require hw access 843 * @engine: Engine to initialize. 844 * 845 * Initializes @engine@ structure members shared between legacy and execlists 846 * submission modes which do require hardware access. 847 * 848 * Typcally done at later stages of submission mode specific engine setup. 849 * 850 * Returns zero on success or an error code on failure. 851 */ 852 static int engine_init_common(struct intel_engine_cs *engine) 853 { 854 struct intel_context *ce; 855 int ret; 856 857 engine->set_default_submission(engine); 858 859 /* 860 * We may need to do things with the shrinker which 861 * require us to immediately switch back to the default 862 * context. This can cause a problem as pinning the 863 * default context also requires GTT space which may not 864 * be available. To avoid this we always pin the default 865 * context. 866 */ 867 ce = create_kernel_context(engine); 868 if (IS_ERR(ce)) 869 return PTR_ERR(ce); 870 871 ret = measure_breadcrumb_dw(ce); 872 if (ret < 0) 873 goto err_context; 874 875 engine->emit_fini_breadcrumb_dw = ret; 876 engine->kernel_context = ce; 877 878 return 0; 879 880 err_context: 881 intel_context_put(ce); 882 return ret; 883 } 884 885 int intel_engines_init(struct intel_gt *gt) 886 { 887 int (*setup)(struct intel_engine_cs *engine); 888 struct intel_engine_cs *engine; 889 enum intel_engine_id id; 890 int err; 891 892 if (HAS_EXECLISTS(gt->i915)) 893 setup = intel_execlists_submission_setup; 894 else 895 setup = intel_ring_submission_setup; 896 897 for_each_engine(engine, gt, id) { 898 err = engine_setup_common(engine); 899 if (err) 900 return err; 901 902 err = setup(engine); 903 if (err) 904 return err; 905 906 err = engine_init_common(engine); 907 if (err) 908 return err; 909 910 intel_engine_add_user(engine); 911 } 912 913 return 0; 914 } 915 916 /** 917 * intel_engines_cleanup_common - cleans up the engine state created by 918 * the common initiailizers. 919 * @engine: Engine to cleanup. 920 * 921 * This cleans up everything created by the common helpers. 922 */ 923 void intel_engine_cleanup_common(struct intel_engine_cs *engine) 924 { 925 GEM_BUG_ON(!list_empty(&engine->active.requests)); 926 tasklet_kill(&engine->execlists.tasklet); /* flush the callback */ 927 928 cleanup_status_page(engine); 929 intel_breadcrumbs_free(engine->breadcrumbs); 930 931 intel_engine_fini_retire(engine); 932 intel_engine_cleanup_cmd_parser(engine); 933 934 if (engine->default_state) 935 fput(engine->default_state); 936 937 if (engine->kernel_context) { 938 intel_context_unpin(engine->kernel_context); 939 intel_context_put(engine->kernel_context); 940 } 941 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks)); 942 943 intel_wa_list_free(&engine->ctx_wa_list); 944 intel_wa_list_free(&engine->wa_list); 945 intel_wa_list_free(&engine->whitelist); 946 } 947 948 /** 949 * intel_engine_resume - re-initializes the HW state of the engine 950 * @engine: Engine to resume. 951 * 952 * Returns zero on success or an error code on failure. 953 */ 954 int intel_engine_resume(struct intel_engine_cs *engine) 955 { 956 intel_engine_apply_workarounds(engine); 957 intel_engine_apply_whitelist(engine); 958 959 return engine->resume(engine); 960 } 961 962 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine) 963 { 964 struct drm_i915_private *i915 = engine->i915; 965 966 u64 acthd; 967 968 if (INTEL_GEN(i915) >= 8) 969 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW); 970 else if (INTEL_GEN(i915) >= 4) 971 acthd = ENGINE_READ(engine, RING_ACTHD); 972 else 973 acthd = ENGINE_READ(engine, ACTHD); 974 975 return acthd; 976 } 977 978 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine) 979 { 980 u64 bbaddr; 981 982 if (INTEL_GEN(engine->i915) >= 8) 983 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW); 984 else 985 bbaddr = ENGINE_READ(engine, RING_BBADDR); 986 987 return bbaddr; 988 } 989 990 static unsigned long stop_timeout(const struct intel_engine_cs *engine) 991 { 992 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */ 993 return 0; 994 995 /* 996 * If we are doing a normal GPU reset, we can take our time and allow 997 * the engine to quiesce. We've stopped submission to the engine, and 998 * if we wait long enough an innocent context should complete and 999 * leave the engine idle. So they should not be caught unaware by 1000 * the forthcoming GPU reset (which usually follows the stop_cs)! 1001 */ 1002 return READ_ONCE(engine->props.stop_timeout_ms); 1003 } 1004 1005 int intel_engine_stop_cs(struct intel_engine_cs *engine) 1006 { 1007 struct intel_uncore *uncore = engine->uncore; 1008 const u32 base = engine->mmio_base; 1009 const i915_reg_t mode = RING_MI_MODE(base); 1010 int err; 1011 1012 if (INTEL_GEN(engine->i915) < 3) 1013 return -ENODEV; 1014 1015 ENGINE_TRACE(engine, "\n"); 1016 1017 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); 1018 1019 err = 0; 1020 if (__intel_wait_for_register_fw(uncore, 1021 mode, MODE_IDLE, MODE_IDLE, 1022 1000, stop_timeout(engine), 1023 NULL)) { 1024 ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n"); 1025 err = -ETIMEDOUT; 1026 } 1027 1028 /* A final mmio read to let GPU writes be hopefully flushed to memory */ 1029 intel_uncore_posting_read_fw(uncore, mode); 1030 1031 return err; 1032 } 1033 1034 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) 1035 { 1036 ENGINE_TRACE(engine, "\n"); 1037 1038 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); 1039 } 1040 1041 const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 1042 { 1043 switch (type) { 1044 case I915_CACHE_NONE: return " uncached"; 1045 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 1046 case I915_CACHE_L3_LLC: return " L3+LLC"; 1047 case I915_CACHE_WT: return " WT"; 1048 default: return ""; 1049 } 1050 } 1051 1052 static u32 1053 read_subslice_reg(const struct intel_engine_cs *engine, 1054 int slice, int subslice, i915_reg_t reg) 1055 { 1056 struct drm_i915_private *i915 = engine->i915; 1057 struct intel_uncore *uncore = engine->uncore; 1058 u32 mcr_mask, mcr_ss, mcr, old_mcr, val; 1059 enum forcewake_domains fw_domains; 1060 1061 if (INTEL_GEN(i915) >= 11) { 1062 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1063 mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1064 } else { 1065 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1066 mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1067 } 1068 1069 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, 1070 FW_REG_READ); 1071 fw_domains |= intel_uncore_forcewake_for_reg(uncore, 1072 GEN8_MCR_SELECTOR, 1073 FW_REG_READ | FW_REG_WRITE); 1074 1075 spin_lock_irq(&uncore->lock); 1076 intel_uncore_forcewake_get__locked(uncore, fw_domains); 1077 1078 old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); 1079 1080 mcr &= ~mcr_mask; 1081 mcr |= mcr_ss; 1082 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); 1083 1084 val = intel_uncore_read_fw(uncore, reg); 1085 1086 mcr &= ~mcr_mask; 1087 mcr |= old_mcr & mcr_mask; 1088 1089 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); 1090 1091 intel_uncore_forcewake_put__locked(uncore, fw_domains); 1092 spin_unlock_irq(&uncore->lock); 1093 1094 return val; 1095 } 1096 1097 /* NB: please notice the memset */ 1098 void intel_engine_get_instdone(const struct intel_engine_cs *engine, 1099 struct intel_instdone *instdone) 1100 { 1101 struct drm_i915_private *i915 = engine->i915; 1102 const struct sseu_dev_info *sseu = &engine->gt->info.sseu; 1103 struct intel_uncore *uncore = engine->uncore; 1104 u32 mmio_base = engine->mmio_base; 1105 int slice; 1106 int subslice; 1107 1108 memset(instdone, 0, sizeof(*instdone)); 1109 1110 switch (INTEL_GEN(i915)) { 1111 default: 1112 instdone->instdone = 1113 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1114 1115 if (engine->id != RCS0) 1116 break; 1117 1118 instdone->slice_common = 1119 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1120 if (INTEL_GEN(i915) >= 12) { 1121 instdone->slice_common_extra[0] = 1122 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA); 1123 instdone->slice_common_extra[1] = 1124 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2); 1125 } 1126 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) { 1127 instdone->sampler[slice][subslice] = 1128 read_subslice_reg(engine, slice, subslice, 1129 GEN7_SAMPLER_INSTDONE); 1130 instdone->row[slice][subslice] = 1131 read_subslice_reg(engine, slice, subslice, 1132 GEN7_ROW_INSTDONE); 1133 } 1134 break; 1135 case 7: 1136 instdone->instdone = 1137 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1138 1139 if (engine->id != RCS0) 1140 break; 1141 1142 instdone->slice_common = 1143 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1144 instdone->sampler[0][0] = 1145 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE); 1146 instdone->row[0][0] = 1147 intel_uncore_read(uncore, GEN7_ROW_INSTDONE); 1148 1149 break; 1150 case 6: 1151 case 5: 1152 case 4: 1153 instdone->instdone = 1154 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1155 if (engine->id == RCS0) 1156 /* HACK: Using the wrong struct member */ 1157 instdone->slice_common = 1158 intel_uncore_read(uncore, GEN4_INSTDONE1); 1159 break; 1160 case 3: 1161 case 2: 1162 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE); 1163 break; 1164 } 1165 } 1166 1167 static bool ring_is_idle(struct intel_engine_cs *engine) 1168 { 1169 bool idle = true; 1170 1171 if (I915_SELFTEST_ONLY(!engine->mmio_base)) 1172 return true; 1173 1174 if (!intel_engine_pm_get_if_awake(engine)) 1175 return true; 1176 1177 /* First check that no commands are left in the ring */ 1178 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) != 1179 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR)) 1180 idle = false; 1181 1182 /* No bit for gen2, so assume the CS parser is idle */ 1183 if (INTEL_GEN(engine->i915) > 2 && 1184 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE)) 1185 idle = false; 1186 1187 intel_engine_pm_put(engine); 1188 1189 return idle; 1190 } 1191 1192 void intel_engine_flush_submission(struct intel_engine_cs *engine) 1193 { 1194 struct tasklet_struct *t = &engine->execlists.tasklet; 1195 1196 if (!t->func) 1197 return; 1198 1199 /* Synchronise and wait for the tasklet on another CPU */ 1200 tasklet_kill(t); 1201 1202 /* Having cancelled the tasklet, ensure that is run */ 1203 local_bh_disable(); 1204 if (tasklet_trylock(t)) { 1205 /* Must wait for any GPU reset in progress. */ 1206 if (__tasklet_is_enabled(t)) 1207 t->func(t->data); 1208 tasklet_unlock(t); 1209 } 1210 local_bh_enable(); 1211 } 1212 1213 /** 1214 * intel_engine_is_idle() - Report if the engine has finished process all work 1215 * @engine: the intel_engine_cs 1216 * 1217 * Return true if there are no requests pending, nothing left to be submitted 1218 * to hardware, and that the engine is idle. 1219 */ 1220 bool intel_engine_is_idle(struct intel_engine_cs *engine) 1221 { 1222 /* More white lies, if wedged, hw state is inconsistent */ 1223 if (intel_gt_is_wedged(engine->gt)) 1224 return true; 1225 1226 if (!intel_engine_pm_is_awake(engine)) 1227 return true; 1228 1229 /* Waiting to drain ELSP? */ 1230 if (execlists_active(&engine->execlists)) { 1231 synchronize_hardirq(engine->i915->drm.pdev->irq); 1232 1233 intel_engine_flush_submission(engine); 1234 1235 if (execlists_active(&engine->execlists)) 1236 return false; 1237 } 1238 1239 /* ELSP is empty, but there are ready requests? E.g. after reset */ 1240 if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)) 1241 return false; 1242 1243 /* Ring stopped? */ 1244 return ring_is_idle(engine); 1245 } 1246 1247 bool intel_engines_are_idle(struct intel_gt *gt) 1248 { 1249 struct intel_engine_cs *engine; 1250 enum intel_engine_id id; 1251 1252 /* 1253 * If the driver is wedged, HW state may be very inconsistent and 1254 * report that it is still busy, even though we have stopped using it. 1255 */ 1256 if (intel_gt_is_wedged(gt)) 1257 return true; 1258 1259 /* Already parked (and passed an idleness test); must still be idle */ 1260 if (!READ_ONCE(gt->awake)) 1261 return true; 1262 1263 for_each_engine(engine, gt, id) { 1264 if (!intel_engine_is_idle(engine)) 1265 return false; 1266 } 1267 1268 return true; 1269 } 1270 1271 void intel_engines_reset_default_submission(struct intel_gt *gt) 1272 { 1273 struct intel_engine_cs *engine; 1274 enum intel_engine_id id; 1275 1276 for_each_engine(engine, gt, id) 1277 engine->set_default_submission(engine); 1278 } 1279 1280 bool intel_engine_can_store_dword(struct intel_engine_cs *engine) 1281 { 1282 switch (INTEL_GEN(engine->i915)) { 1283 case 2: 1284 return false; /* uses physical not virtual addresses */ 1285 case 3: 1286 /* maybe only uses physical not virtual addresses */ 1287 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); 1288 case 4: 1289 return !IS_I965G(engine->i915); /* who knows! */ 1290 case 6: 1291 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ 1292 default: 1293 return true; 1294 } 1295 } 1296 1297 static int print_sched_attr(const struct i915_sched_attr *attr, 1298 char *buf, int x, int len) 1299 { 1300 if (attr->priority == I915_PRIORITY_INVALID) 1301 return x; 1302 1303 x += snprintf(buf + x, len - x, 1304 " prio=%d", attr->priority); 1305 1306 return x; 1307 } 1308 1309 static void print_request(struct drm_printer *m, 1310 struct i915_request *rq, 1311 const char *prefix) 1312 { 1313 const char *name = rq->fence.ops->get_timeline_name(&rq->fence); 1314 char buf[80] = ""; 1315 int x = 0; 1316 1317 x = print_sched_attr(&rq->sched.attr, buf, x, sizeof(buf)); 1318 1319 drm_printf(m, "%s %llx:%llx%s%s %s @ %dms: %s\n", 1320 prefix, 1321 rq->fence.context, rq->fence.seqno, 1322 i915_request_completed(rq) ? "!" : 1323 i915_request_started(rq) ? "*" : 1324 "", 1325 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 1326 &rq->fence.flags) ? "+" : 1327 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 1328 &rq->fence.flags) ? "-" : 1329 "", 1330 buf, 1331 jiffies_to_msecs(jiffies - rq->emitted_jiffies), 1332 name); 1333 } 1334 1335 static struct intel_timeline *get_timeline(struct i915_request *rq) 1336 { 1337 struct intel_timeline *tl; 1338 1339 /* 1340 * Even though we are holding the engine->active.lock here, there 1341 * is no control over the submission queue per-se and we are 1342 * inspecting the active state at a random point in time, with an 1343 * unknown queue. Play safe and make sure the timeline remains valid. 1344 * (Only being used for pretty printing, one extra kref shouldn't 1345 * cause a camel stampede!) 1346 */ 1347 rcu_read_lock(); 1348 tl = rcu_dereference(rq->timeline); 1349 if (!kref_get_unless_zero(&tl->kref)) 1350 tl = NULL; 1351 rcu_read_unlock(); 1352 1353 return tl; 1354 } 1355 1356 static int print_ring(char *buf, int sz, struct i915_request *rq) 1357 { 1358 int len = 0; 1359 1360 if (!i915_request_signaled(rq)) { 1361 struct intel_timeline *tl = get_timeline(rq); 1362 1363 len = scnprintf(buf, sz, 1364 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ", 1365 i915_ggtt_offset(rq->ring->vma), 1366 tl ? tl->hwsp_offset : 0, 1367 hwsp_seqno(rq), 1368 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context), 1369 1000 * 1000)); 1370 1371 if (tl) 1372 intel_timeline_put(tl); 1373 } 1374 1375 return len; 1376 } 1377 1378 static void hexdump(struct drm_printer *m, const void *buf, size_t len) 1379 { 1380 const size_t rowsize = 8 * sizeof(u32); 1381 const void *prev = NULL; 1382 bool skip = false; 1383 size_t pos; 1384 1385 for (pos = 0; pos < len; pos += rowsize) { 1386 char line[128]; 1387 1388 if (prev && !memcmp(prev, buf + pos, rowsize)) { 1389 if (!skip) { 1390 drm_printf(m, "*\n"); 1391 skip = true; 1392 } 1393 continue; 1394 } 1395 1396 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos, 1397 rowsize, sizeof(u32), 1398 line, sizeof(line), 1399 false) >= sizeof(line)); 1400 drm_printf(m, "[%04zx] %s\n", pos, line); 1401 1402 prev = buf + pos; 1403 skip = false; 1404 } 1405 } 1406 1407 static const char *repr_timer(const struct timer_list *t) 1408 { 1409 if (!READ_ONCE(t->expires)) 1410 return "inactive"; 1411 1412 if (timer_pending(t)) 1413 return "active"; 1414 1415 return "expired"; 1416 } 1417 1418 static void intel_engine_print_registers(struct intel_engine_cs *engine, 1419 struct drm_printer *m) 1420 { 1421 struct drm_i915_private *dev_priv = engine->i915; 1422 struct intel_engine_execlists * const execlists = &engine->execlists; 1423 u64 addr; 1424 1425 if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7)) 1426 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID)); 1427 if (HAS_EXECLISTS(dev_priv)) { 1428 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n", 1429 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI)); 1430 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n", 1431 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO)); 1432 } 1433 drm_printf(m, "\tRING_START: 0x%08x\n", 1434 ENGINE_READ(engine, RING_START)); 1435 drm_printf(m, "\tRING_HEAD: 0x%08x\n", 1436 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR); 1437 drm_printf(m, "\tRING_TAIL: 0x%08x\n", 1438 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR); 1439 drm_printf(m, "\tRING_CTL: 0x%08x%s\n", 1440 ENGINE_READ(engine, RING_CTL), 1441 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : ""); 1442 if (INTEL_GEN(engine->i915) > 2) { 1443 drm_printf(m, "\tRING_MODE: 0x%08x%s\n", 1444 ENGINE_READ(engine, RING_MI_MODE), 1445 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : ""); 1446 } 1447 1448 if (INTEL_GEN(dev_priv) >= 6) { 1449 drm_printf(m, "\tRING_IMR: 0x%08x\n", 1450 ENGINE_READ(engine, RING_IMR)); 1451 drm_printf(m, "\tRING_ESR: 0x%08x\n", 1452 ENGINE_READ(engine, RING_ESR)); 1453 drm_printf(m, "\tRING_EMR: 0x%08x\n", 1454 ENGINE_READ(engine, RING_EMR)); 1455 drm_printf(m, "\tRING_EIR: 0x%08x\n", 1456 ENGINE_READ(engine, RING_EIR)); 1457 } 1458 1459 addr = intel_engine_get_active_head(engine); 1460 drm_printf(m, "\tACTHD: 0x%08x_%08x\n", 1461 upper_32_bits(addr), lower_32_bits(addr)); 1462 addr = intel_engine_get_last_batch_head(engine); 1463 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n", 1464 upper_32_bits(addr), lower_32_bits(addr)); 1465 if (INTEL_GEN(dev_priv) >= 8) 1466 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW); 1467 else if (INTEL_GEN(dev_priv) >= 4) 1468 addr = ENGINE_READ(engine, RING_DMA_FADD); 1469 else 1470 addr = ENGINE_READ(engine, DMA_FADD_I8XX); 1471 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n", 1472 upper_32_bits(addr), lower_32_bits(addr)); 1473 if (INTEL_GEN(dev_priv) >= 4) { 1474 drm_printf(m, "\tIPEIR: 0x%08x\n", 1475 ENGINE_READ(engine, RING_IPEIR)); 1476 drm_printf(m, "\tIPEHR: 0x%08x\n", 1477 ENGINE_READ(engine, RING_IPEHR)); 1478 } else { 1479 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR)); 1480 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR)); 1481 } 1482 1483 if (HAS_EXECLISTS(dev_priv)) { 1484 struct i915_request * const *port, *rq; 1485 const u32 *hws = 1486 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; 1487 const u8 num_entries = execlists->csb_size; 1488 unsigned int idx; 1489 u8 read, write; 1490 1491 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n", 1492 yesno(test_bit(TASKLET_STATE_SCHED, 1493 &engine->execlists.tasklet.state)), 1494 enableddisabled(!atomic_read(&engine->execlists.tasklet.count)), 1495 repr_timer(&engine->execlists.preempt), 1496 repr_timer(&engine->execlists.timer)); 1497 1498 read = execlists->csb_head; 1499 write = READ_ONCE(*execlists->csb_write); 1500 1501 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n", 1502 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO), 1503 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI), 1504 read, write, num_entries); 1505 1506 if (read >= num_entries) 1507 read = 0; 1508 if (write >= num_entries) 1509 write = 0; 1510 if (read > write) 1511 write += num_entries; 1512 while (read < write) { 1513 idx = ++read % num_entries; 1514 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", 1515 idx, hws[idx * 2], hws[idx * 2 + 1]); 1516 } 1517 1518 execlists_active_lock_bh(execlists); 1519 rcu_read_lock(); 1520 for (port = execlists->active; (rq = *port); port++) { 1521 char hdr[160]; 1522 int len; 1523 1524 len = scnprintf(hdr, sizeof(hdr), 1525 "\t\tActive[%d]: ccid:%08x%s%s, ", 1526 (int)(port - execlists->active), 1527 rq->context->lrc.ccid, 1528 intel_context_is_closed(rq->context) ? "!" : "", 1529 intel_context_is_banned(rq->context) ? "*" : ""); 1530 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1531 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1532 print_request(m, rq, hdr); 1533 } 1534 for (port = execlists->pending; (rq = *port); port++) { 1535 char hdr[160]; 1536 int len; 1537 1538 len = scnprintf(hdr, sizeof(hdr), 1539 "\t\tPending[%d]: ccid:%08x%s%s, ", 1540 (int)(port - execlists->pending), 1541 rq->context->lrc.ccid, 1542 intel_context_is_closed(rq->context) ? "!" : "", 1543 intel_context_is_banned(rq->context) ? "*" : ""); 1544 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1545 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1546 print_request(m, rq, hdr); 1547 } 1548 rcu_read_unlock(); 1549 execlists_active_unlock_bh(execlists); 1550 } else if (INTEL_GEN(dev_priv) > 6) { 1551 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n", 1552 ENGINE_READ(engine, RING_PP_DIR_BASE)); 1553 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", 1554 ENGINE_READ(engine, RING_PP_DIR_BASE_READ)); 1555 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", 1556 ENGINE_READ(engine, RING_PP_DIR_DCLV)); 1557 } 1558 } 1559 1560 static void print_request_ring(struct drm_printer *m, struct i915_request *rq) 1561 { 1562 void *ring; 1563 int size; 1564 1565 drm_printf(m, 1566 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n", 1567 rq->head, rq->postfix, rq->tail, 1568 rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, 1569 rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); 1570 1571 size = rq->tail - rq->head; 1572 if (rq->tail < rq->head) 1573 size += rq->ring->size; 1574 1575 ring = kmalloc(size, GFP_ATOMIC); 1576 if (ring) { 1577 const void *vaddr = rq->ring->vaddr; 1578 unsigned int head = rq->head; 1579 unsigned int len = 0; 1580 1581 if (rq->tail < head) { 1582 len = rq->ring->size - head; 1583 memcpy(ring, vaddr + head, len); 1584 head = 0; 1585 } 1586 memcpy(ring + len, vaddr + head, size - len); 1587 1588 hexdump(m, ring, size); 1589 kfree(ring); 1590 } 1591 } 1592 1593 static unsigned long list_count(struct list_head *list) 1594 { 1595 struct list_head *pos; 1596 unsigned long count = 0; 1597 1598 list_for_each(pos, list) 1599 count++; 1600 1601 return count; 1602 } 1603 1604 static unsigned long read_ul(void *p, size_t x) 1605 { 1606 return *(unsigned long *)(p + x); 1607 } 1608 1609 static void print_properties(struct intel_engine_cs *engine, 1610 struct drm_printer *m) 1611 { 1612 static const struct pmap { 1613 size_t offset; 1614 const char *name; 1615 } props[] = { 1616 #define P(x) { \ 1617 .offset = offsetof(typeof(engine->props), x), \ 1618 .name = #x \ 1619 } 1620 P(heartbeat_interval_ms), 1621 P(max_busywait_duration_ns), 1622 P(preempt_timeout_ms), 1623 P(stop_timeout_ms), 1624 P(timeslice_duration_ms), 1625 1626 {}, 1627 #undef P 1628 }; 1629 const struct pmap *p; 1630 1631 drm_printf(m, "\tProperties:\n"); 1632 for (p = props; p->name; p++) 1633 drm_printf(m, "\t\t%s: %lu [default %lu]\n", 1634 p->name, 1635 read_ul(&engine->props, p->offset), 1636 read_ul(&engine->defaults, p->offset)); 1637 } 1638 1639 void intel_engine_dump(struct intel_engine_cs *engine, 1640 struct drm_printer *m, 1641 const char *header, ...) 1642 { 1643 struct i915_gpu_error * const error = &engine->i915->gpu_error; 1644 struct i915_request *rq; 1645 intel_wakeref_t wakeref; 1646 unsigned long flags; 1647 ktime_t dummy; 1648 1649 if (header) { 1650 va_list ap; 1651 1652 va_start(ap, header); 1653 drm_vprintf(m, header, &ap); 1654 va_end(ap); 1655 } 1656 1657 if (intel_gt_is_wedged(engine->gt)) 1658 drm_printf(m, "*** WEDGED ***\n"); 1659 1660 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count)); 1661 drm_printf(m, "\tBarriers?: %s\n", 1662 yesno(!llist_empty(&engine->barrier_tasks))); 1663 drm_printf(m, "\tLatency: %luus\n", 1664 ewma__engine_latency_read(&engine->latency)); 1665 if (intel_engine_supports_stats(engine)) 1666 drm_printf(m, "\tRuntime: %llums\n", 1667 ktime_to_ms(intel_engine_get_busy_time(engine, 1668 &dummy))); 1669 drm_printf(m, "\tForcewake: %x domains, %d active\n", 1670 engine->fw_domain, atomic_read(&engine->fw_active)); 1671 1672 rcu_read_lock(); 1673 rq = READ_ONCE(engine->heartbeat.systole); 1674 if (rq) 1675 drm_printf(m, "\tHeartbeat: %d ms ago\n", 1676 jiffies_to_msecs(jiffies - rq->emitted_jiffies)); 1677 rcu_read_unlock(); 1678 drm_printf(m, "\tReset count: %d (global %d)\n", 1679 i915_reset_engine_count(error, engine), 1680 i915_reset_count(error)); 1681 print_properties(engine, m); 1682 1683 drm_printf(m, "\tRequests:\n"); 1684 1685 spin_lock_irqsave(&engine->active.lock, flags); 1686 rq = intel_engine_find_active_request(engine); 1687 if (rq) { 1688 struct intel_timeline *tl = get_timeline(rq); 1689 1690 print_request(m, rq, "\t\tactive "); 1691 1692 drm_printf(m, "\t\tring->start: 0x%08x\n", 1693 i915_ggtt_offset(rq->ring->vma)); 1694 drm_printf(m, "\t\tring->head: 0x%08x\n", 1695 rq->ring->head); 1696 drm_printf(m, "\t\tring->tail: 0x%08x\n", 1697 rq->ring->tail); 1698 drm_printf(m, "\t\tring->emit: 0x%08x\n", 1699 rq->ring->emit); 1700 drm_printf(m, "\t\tring->space: 0x%08x\n", 1701 rq->ring->space); 1702 1703 if (tl) { 1704 drm_printf(m, "\t\tring->hwsp: 0x%08x\n", 1705 tl->hwsp_offset); 1706 intel_timeline_put(tl); 1707 } 1708 1709 print_request_ring(m, rq); 1710 1711 if (rq->context->lrc_reg_state) { 1712 drm_printf(m, "Logical Ring Context:\n"); 1713 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE); 1714 } 1715 } 1716 drm_printf(m, "\tOn hold?: %lu\n", list_count(&engine->active.hold)); 1717 spin_unlock_irqrestore(&engine->active.lock, flags); 1718 1719 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base); 1720 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm); 1721 if (wakeref) { 1722 intel_engine_print_registers(engine, m); 1723 intel_runtime_pm_put(engine->uncore->rpm, wakeref); 1724 } else { 1725 drm_printf(m, "\tDevice is asleep; skipping register dump\n"); 1726 } 1727 1728 intel_execlists_show_requests(engine, m, print_request, 8); 1729 1730 drm_printf(m, "HWSP:\n"); 1731 hexdump(m, engine->status_page.addr, PAGE_SIZE); 1732 1733 drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine))); 1734 1735 intel_engine_print_breadcrumbs(engine, m); 1736 } 1737 1738 static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine, 1739 ktime_t *now) 1740 { 1741 ktime_t total = engine->stats.total; 1742 1743 /* 1744 * If the engine is executing something at the moment 1745 * add it to the total. 1746 */ 1747 *now = ktime_get(); 1748 if (atomic_read(&engine->stats.active)) 1749 total = ktime_add(total, ktime_sub(*now, engine->stats.start)); 1750 1751 return total; 1752 } 1753 1754 /** 1755 * intel_engine_get_busy_time() - Return current accumulated engine busyness 1756 * @engine: engine to report on 1757 * @now: monotonic timestamp of sampling 1758 * 1759 * Returns accumulated time @engine was busy since engine stats were enabled. 1760 */ 1761 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) 1762 { 1763 unsigned int seq; 1764 ktime_t total; 1765 1766 do { 1767 seq = read_seqbegin(&engine->stats.lock); 1768 total = __intel_engine_get_busy_time(engine, now); 1769 } while (read_seqretry(&engine->stats.lock, seq)); 1770 1771 return total; 1772 } 1773 1774 static bool match_ring(struct i915_request *rq) 1775 { 1776 u32 ring = ENGINE_READ(rq->engine, RING_START); 1777 1778 return ring == i915_ggtt_offset(rq->ring->vma); 1779 } 1780 1781 struct i915_request * 1782 intel_engine_find_active_request(struct intel_engine_cs *engine) 1783 { 1784 struct i915_request *request, *active = NULL; 1785 1786 /* 1787 * We are called by the error capture, reset and to dump engine 1788 * state at random points in time. In particular, note that neither is 1789 * crucially ordered with an interrupt. After a hang, the GPU is dead 1790 * and we assume that no more writes can happen (we waited long enough 1791 * for all writes that were in transaction to be flushed) - adding an 1792 * extra delay for a recent interrupt is pointless. Hence, we do 1793 * not need an engine->irq_seqno_barrier() before the seqno reads. 1794 * At all other times, we must assume the GPU is still running, but 1795 * we only care about the snapshot of this moment. 1796 */ 1797 lockdep_assert_held(&engine->active.lock); 1798 1799 rcu_read_lock(); 1800 request = execlists_active(&engine->execlists); 1801 if (request) { 1802 struct intel_timeline *tl = request->context->timeline; 1803 1804 list_for_each_entry_from_reverse(request, &tl->requests, link) { 1805 if (i915_request_completed(request)) 1806 break; 1807 1808 active = request; 1809 } 1810 } 1811 rcu_read_unlock(); 1812 if (active) 1813 return active; 1814 1815 list_for_each_entry(request, &engine->active.requests, sched.link) { 1816 if (i915_request_completed(request)) 1817 continue; 1818 1819 if (!i915_request_started(request)) 1820 continue; 1821 1822 /* More than one preemptible request may match! */ 1823 if (!match_ring(request)) 1824 continue; 1825 1826 active = request; 1827 break; 1828 } 1829 1830 return active; 1831 } 1832 1833 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 1834 #include "mock_engine.c" 1835 #include "selftest_engine.c" 1836 #include "selftest_engine_cs.c" 1837 #endif 1838