1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2016 Intel Corporation 4 */ 5 6 #include <drm/drm_print.h> 7 8 #include "gem/i915_gem_context.h" 9 #include "gt/intel_gt_regs.h" 10 11 #include "i915_cmd_parser.h" 12 #include "i915_drv.h" 13 #include "intel_breadcrumbs.h" 14 #include "intel_context.h" 15 #include "intel_engine.h" 16 #include "intel_engine_pm.h" 17 #include "intel_engine_regs.h" 18 #include "intel_engine_user.h" 19 #include "intel_execlists_submission.h" 20 #include "intel_gt.h" 21 #include "intel_gt_requests.h" 22 #include "intel_gt_pm.h" 23 #include "intel_lrc_reg.h" 24 #include "intel_reset.h" 25 #include "intel_ring.h" 26 #include "uc/intel_guc_submission.h" 27 28 /* Haswell does have the CXT_SIZE register however it does not appear to be 29 * valid. Now, docs explain in dwords what is in the context object. The full 30 * size is 70720 bytes, however, the power context and execlist context will 31 * never be saved (power context is stored elsewhere, and execlists don't work 32 * on HSW) - so the final size, including the extra state required for the 33 * Resource Streamer, is 66944 bytes, which rounds to 17 pages. 34 */ 35 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 36 37 #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 38 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) 39 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 40 #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE) 41 42 #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE) 43 44 #define MAX_MMIO_BASES 3 45 struct engine_info { 46 u8 class; 47 u8 instance; 48 /* mmio bases table *must* be sorted in reverse graphics_ver order */ 49 struct engine_mmio_base { 50 u32 graphics_ver : 8; 51 u32 base : 24; 52 } mmio_bases[MAX_MMIO_BASES]; 53 }; 54 55 static const struct engine_info intel_engines[] = { 56 [RCS0] = { 57 .class = RENDER_CLASS, 58 .instance = 0, 59 .mmio_bases = { 60 { .graphics_ver = 1, .base = RENDER_RING_BASE } 61 }, 62 }, 63 [BCS0] = { 64 .class = COPY_ENGINE_CLASS, 65 .instance = 0, 66 .mmio_bases = { 67 { .graphics_ver = 6, .base = BLT_RING_BASE } 68 }, 69 }, 70 [VCS0] = { 71 .class = VIDEO_DECODE_CLASS, 72 .instance = 0, 73 .mmio_bases = { 74 { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE }, 75 { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE }, 76 { .graphics_ver = 4, .base = BSD_RING_BASE } 77 }, 78 }, 79 [VCS1] = { 80 .class = VIDEO_DECODE_CLASS, 81 .instance = 1, 82 .mmio_bases = { 83 { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE }, 84 { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE } 85 }, 86 }, 87 [VCS2] = { 88 .class = VIDEO_DECODE_CLASS, 89 .instance = 2, 90 .mmio_bases = { 91 { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE } 92 }, 93 }, 94 [VCS3] = { 95 .class = VIDEO_DECODE_CLASS, 96 .instance = 3, 97 .mmio_bases = { 98 { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE } 99 }, 100 }, 101 [VCS4] = { 102 .class = VIDEO_DECODE_CLASS, 103 .instance = 4, 104 .mmio_bases = { 105 { .graphics_ver = 12, .base = XEHP_BSD5_RING_BASE } 106 }, 107 }, 108 [VCS5] = { 109 .class = VIDEO_DECODE_CLASS, 110 .instance = 5, 111 .mmio_bases = { 112 { .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE } 113 }, 114 }, 115 [VCS6] = { 116 .class = VIDEO_DECODE_CLASS, 117 .instance = 6, 118 .mmio_bases = { 119 { .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE } 120 }, 121 }, 122 [VCS7] = { 123 .class = VIDEO_DECODE_CLASS, 124 .instance = 7, 125 .mmio_bases = { 126 { .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE } 127 }, 128 }, 129 [VECS0] = { 130 .class = VIDEO_ENHANCEMENT_CLASS, 131 .instance = 0, 132 .mmio_bases = { 133 { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE }, 134 { .graphics_ver = 7, .base = VEBOX_RING_BASE } 135 }, 136 }, 137 [VECS1] = { 138 .class = VIDEO_ENHANCEMENT_CLASS, 139 .instance = 1, 140 .mmio_bases = { 141 { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE } 142 }, 143 }, 144 [VECS2] = { 145 .class = VIDEO_ENHANCEMENT_CLASS, 146 .instance = 2, 147 .mmio_bases = { 148 { .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE } 149 }, 150 }, 151 [VECS3] = { 152 .class = VIDEO_ENHANCEMENT_CLASS, 153 .instance = 3, 154 .mmio_bases = { 155 { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE } 156 }, 157 }, 158 }; 159 160 /** 161 * intel_engine_context_size() - return the size of the context for an engine 162 * @gt: the gt 163 * @class: engine class 164 * 165 * Each engine class may require a different amount of space for a context 166 * image. 167 * 168 * Return: size (in bytes) of an engine class specific context image 169 * 170 * Note: this size includes the HWSP, which is part of the context image 171 * in LRC mode, but does not include the "shared data page" used with 172 * GuC submission. The caller should account for this if using the GuC. 173 */ 174 u32 intel_engine_context_size(struct intel_gt *gt, u8 class) 175 { 176 struct intel_uncore *uncore = gt->uncore; 177 u32 cxt_size; 178 179 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE); 180 181 switch (class) { 182 case RENDER_CLASS: 183 switch (GRAPHICS_VER(gt->i915)) { 184 default: 185 MISSING_CASE(GRAPHICS_VER(gt->i915)); 186 return DEFAULT_LR_CONTEXT_RENDER_SIZE; 187 case 12: 188 case 11: 189 return GEN11_LR_CONTEXT_RENDER_SIZE; 190 case 9: 191 return GEN9_LR_CONTEXT_RENDER_SIZE; 192 case 8: 193 return GEN8_LR_CONTEXT_RENDER_SIZE; 194 case 7: 195 if (IS_HASWELL(gt->i915)) 196 return HSW_CXT_TOTAL_SIZE; 197 198 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE); 199 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64, 200 PAGE_SIZE); 201 case 6: 202 cxt_size = intel_uncore_read(uncore, CXT_SIZE); 203 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64, 204 PAGE_SIZE); 205 case 5: 206 case 4: 207 /* 208 * There is a discrepancy here between the size reported 209 * by the register and the size of the context layout 210 * in the docs. Both are described as authorative! 211 * 212 * The discrepancy is on the order of a few cachelines, 213 * but the total is under one page (4k), which is our 214 * minimum allocation anyway so it should all come 215 * out in the wash. 216 */ 217 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1; 218 drm_dbg(>->i915->drm, 219 "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n", 220 GRAPHICS_VER(gt->i915), cxt_size * 64, 221 cxt_size - 1); 222 return round_up(cxt_size * 64, PAGE_SIZE); 223 case 3: 224 case 2: 225 /* For the special day when i810 gets merged. */ 226 case 1: 227 return 0; 228 } 229 break; 230 default: 231 MISSING_CASE(class); 232 fallthrough; 233 case VIDEO_DECODE_CLASS: 234 case VIDEO_ENHANCEMENT_CLASS: 235 case COPY_ENGINE_CLASS: 236 if (GRAPHICS_VER(gt->i915) < 8) 237 return 0; 238 return GEN8_LR_CONTEXT_OTHER_SIZE; 239 } 240 } 241 242 static u32 __engine_mmio_base(struct drm_i915_private *i915, 243 const struct engine_mmio_base *bases) 244 { 245 int i; 246 247 for (i = 0; i < MAX_MMIO_BASES; i++) 248 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver) 249 break; 250 251 GEM_BUG_ON(i == MAX_MMIO_BASES); 252 GEM_BUG_ON(!bases[i].base); 253 254 return bases[i].base; 255 } 256 257 static void __sprint_engine_name(struct intel_engine_cs *engine) 258 { 259 /* 260 * Before we know what the uABI name for this engine will be, 261 * we still would like to keep track of this engine in the debug logs. 262 * We throw in a ' here as a reminder that this isn't its final name. 263 */ 264 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u", 265 intel_engine_class_repr(engine->class), 266 engine->instance) >= sizeof(engine->name)); 267 } 268 269 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask) 270 { 271 /* 272 * Though they added more rings on g4x/ilk, they did not add 273 * per-engine HWSTAM until gen6. 274 */ 275 if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS) 276 return; 277 278 if (GRAPHICS_VER(engine->i915) >= 3) 279 ENGINE_WRITE(engine, RING_HWSTAM, mask); 280 else 281 ENGINE_WRITE16(engine, RING_HWSTAM, mask); 282 } 283 284 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine) 285 { 286 /* Mask off all writes into the unknown HWSP */ 287 intel_engine_set_hwsp_writemask(engine, ~0u); 288 } 289 290 static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir) 291 { 292 GEM_DEBUG_WARN_ON(iir); 293 } 294 295 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, 296 u8 logical_instance) 297 { 298 const struct engine_info *info = &intel_engines[id]; 299 struct drm_i915_private *i915 = gt->i915; 300 struct intel_engine_cs *engine; 301 u8 guc_class; 302 303 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH)); 304 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH)); 305 BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1)); 306 BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1)); 307 308 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine))) 309 return -EINVAL; 310 311 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS)) 312 return -EINVAL; 313 314 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE)) 315 return -EINVAL; 316 317 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance])) 318 return -EINVAL; 319 320 engine = kzalloc(sizeof(*engine), GFP_KERNEL); 321 if (!engine) 322 return -ENOMEM; 323 324 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES); 325 326 INIT_LIST_HEAD(&engine->pinned_contexts_list); 327 engine->id = id; 328 engine->legacy_idx = INVALID_ENGINE; 329 engine->mask = BIT(id); 330 if (GRAPHICS_VER(gt->i915) >= 11) { 331 static const u32 engine_reset_domains[] = { 332 [RCS0] = GEN11_GRDOM_RENDER, 333 [BCS0] = GEN11_GRDOM_BLT, 334 [VCS0] = GEN11_GRDOM_MEDIA, 335 [VCS1] = GEN11_GRDOM_MEDIA2, 336 [VCS2] = GEN11_GRDOM_MEDIA3, 337 [VCS3] = GEN11_GRDOM_MEDIA4, 338 [VCS4] = GEN11_GRDOM_MEDIA5, 339 [VCS5] = GEN11_GRDOM_MEDIA6, 340 [VCS6] = GEN11_GRDOM_MEDIA7, 341 [VCS7] = GEN11_GRDOM_MEDIA8, 342 [VECS0] = GEN11_GRDOM_VECS, 343 [VECS1] = GEN11_GRDOM_VECS2, 344 [VECS2] = GEN11_GRDOM_VECS3, 345 [VECS3] = GEN11_GRDOM_VECS4, 346 }; 347 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || 348 !engine_reset_domains[id]); 349 engine->reset_domain = engine_reset_domains[id]; 350 } else { 351 static const u32 engine_reset_domains[] = { 352 [RCS0] = GEN6_GRDOM_RENDER, 353 [BCS0] = GEN6_GRDOM_BLT, 354 [VCS0] = GEN6_GRDOM_MEDIA, 355 [VCS1] = GEN8_GRDOM_MEDIA2, 356 [VECS0] = GEN6_GRDOM_VECS, 357 }; 358 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || 359 !engine_reset_domains[id]); 360 engine->reset_domain = engine_reset_domains[id]; 361 } 362 engine->i915 = i915; 363 engine->gt = gt; 364 engine->uncore = gt->uncore; 365 guc_class = engine_class_to_guc_class(info->class); 366 engine->guc_id = MAKE_GUC_ID(guc_class, info->instance); 367 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases); 368 369 engine->irq_handler = nop_irq_handler; 370 371 engine->class = info->class; 372 engine->instance = info->instance; 373 engine->logical_mask = BIT(logical_instance); 374 __sprint_engine_name(engine); 375 376 engine->props.heartbeat_interval_ms = 377 CONFIG_DRM_I915_HEARTBEAT_INTERVAL; 378 engine->props.max_busywait_duration_ns = 379 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT; 380 engine->props.preempt_timeout_ms = 381 CONFIG_DRM_I915_PREEMPT_TIMEOUT; 382 engine->props.stop_timeout_ms = 383 CONFIG_DRM_I915_STOP_TIMEOUT; 384 engine->props.timeslice_duration_ms = 385 CONFIG_DRM_I915_TIMESLICE_DURATION; 386 387 /* Override to uninterruptible for OpenCL workloads. */ 388 if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS) 389 engine->props.preempt_timeout_ms = 0; 390 391 engine->defaults = engine->props; /* never to change again */ 392 393 engine->context_size = intel_engine_context_size(gt, engine->class); 394 if (WARN_ON(engine->context_size > BIT(20))) 395 engine->context_size = 0; 396 if (engine->context_size) 397 DRIVER_CAPS(i915)->has_logical_contexts = true; 398 399 ewma__engine_latency_init(&engine->latency); 400 seqcount_init(&engine->stats.execlists.lock); 401 402 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); 403 404 /* Scrub mmio state on takeover */ 405 intel_engine_sanitize_mmio(engine); 406 407 gt->engine_class[info->class][info->instance] = engine; 408 gt->engine[id] = engine; 409 410 return 0; 411 } 412 413 static void __setup_engine_capabilities(struct intel_engine_cs *engine) 414 { 415 struct drm_i915_private *i915 = engine->i915; 416 417 if (engine->class == VIDEO_DECODE_CLASS) { 418 /* 419 * HEVC support is present on first engine instance 420 * before Gen11 and on all instances afterwards. 421 */ 422 if (GRAPHICS_VER(i915) >= 11 || 423 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0)) 424 engine->uabi_capabilities |= 425 I915_VIDEO_CLASS_CAPABILITY_HEVC; 426 427 /* 428 * SFC block is present only on even logical engine 429 * instances. 430 */ 431 if ((GRAPHICS_VER(i915) >= 11 && 432 (engine->gt->info.vdbox_sfc_access & 433 BIT(engine->instance))) || 434 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0)) 435 engine->uabi_capabilities |= 436 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 437 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) { 438 if (GRAPHICS_VER(i915) >= 9 && 439 engine->gt->info.sfc_mask & BIT(engine->instance)) 440 engine->uabi_capabilities |= 441 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 442 } 443 } 444 445 static void intel_setup_engine_capabilities(struct intel_gt *gt) 446 { 447 struct intel_engine_cs *engine; 448 enum intel_engine_id id; 449 450 for_each_engine(engine, gt, id) 451 __setup_engine_capabilities(engine); 452 } 453 454 /** 455 * intel_engines_release() - free the resources allocated for Command Streamers 456 * @gt: pointer to struct intel_gt 457 */ 458 void intel_engines_release(struct intel_gt *gt) 459 { 460 struct intel_engine_cs *engine; 461 enum intel_engine_id id; 462 463 /* 464 * Before we release the resources held by engine, we must be certain 465 * that the HW is no longer accessing them -- having the GPU scribble 466 * to or read from a page being used for something else causes no end 467 * of fun. 468 * 469 * The GPU should be reset by this point, but assume the worst just 470 * in case we aborted before completely initialising the engines. 471 */ 472 GEM_BUG_ON(intel_gt_pm_is_awake(gt)); 473 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) 474 __intel_gt_reset(gt, ALL_ENGINES); 475 476 /* Decouple the backend; but keep the layout for late GPU resets */ 477 for_each_engine(engine, gt, id) { 478 if (!engine->release) 479 continue; 480 481 intel_wakeref_wait_for_idle(&engine->wakeref); 482 GEM_BUG_ON(intel_engine_pm_is_awake(engine)); 483 484 engine->release(engine); 485 engine->release = NULL; 486 487 memset(&engine->reset, 0, sizeof(engine->reset)); 488 } 489 } 490 491 void intel_engine_free_request_pool(struct intel_engine_cs *engine) 492 { 493 if (!engine->request_pool) 494 return; 495 496 kmem_cache_free(i915_request_slab_cache(), engine->request_pool); 497 } 498 499 void intel_engines_free(struct intel_gt *gt) 500 { 501 struct intel_engine_cs *engine; 502 enum intel_engine_id id; 503 504 /* Free the requests! dma-resv keeps fences around for an eternity */ 505 rcu_barrier(); 506 507 for_each_engine(engine, gt, id) { 508 intel_engine_free_request_pool(engine); 509 kfree(engine); 510 gt->engine[id] = NULL; 511 } 512 } 513 514 static 515 bool gen11_vdbox_has_sfc(struct intel_gt *gt, 516 unsigned int physical_vdbox, 517 unsigned int logical_vdbox, u16 vdbox_mask) 518 { 519 struct drm_i915_private *i915 = gt->i915; 520 521 /* 522 * In Gen11, only even numbered logical VDBOXes are hooked 523 * up to an SFC (Scaler & Format Converter) unit. 524 * In Gen12, Even numbered physical instance always are connected 525 * to an SFC. Odd numbered physical instances have SFC only if 526 * previous even instance is fused off. 527 * 528 * Starting with Xe_HP, there's also a dedicated SFC_ENABLE field 529 * in the fuse register that tells us whether a specific SFC is present. 530 */ 531 if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0) 532 return false; 533 else if (GRAPHICS_VER(i915) == 12) 534 return (physical_vdbox % 2 == 0) || 535 !(BIT(physical_vdbox - 1) & vdbox_mask); 536 else if (GRAPHICS_VER(i915) == 11) 537 return logical_vdbox % 2 == 0; 538 539 MISSING_CASE(GRAPHICS_VER(i915)); 540 return false; 541 } 542 543 /* 544 * Determine which engines are fused off in our particular hardware. 545 * Note that we have a catch-22 situation where we need to be able to access 546 * the blitter forcewake domain to read the engine fuses, but at the same time 547 * we need to know which engines are available on the system to know which 548 * forcewake domains are present. We solve this by intializing the forcewake 549 * domains based on the full engine mask in the platform capabilities before 550 * calling this function and pruning the domains for fused-off engines 551 * afterwards. 552 */ 553 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) 554 { 555 struct drm_i915_private *i915 = gt->i915; 556 struct intel_gt_info *info = >->info; 557 struct intel_uncore *uncore = gt->uncore; 558 unsigned int logical_vdbox = 0; 559 unsigned int i; 560 u32 media_fuse, fuse1; 561 u16 vdbox_mask; 562 u16 vebox_mask; 563 564 info->engine_mask = INTEL_INFO(i915)->platform_engine_mask; 565 566 if (GRAPHICS_VER(i915) < 11) 567 return info->engine_mask; 568 569 /* 570 * On newer platforms the fusing register is called 'enable' and has 571 * enable semantics, while on older platforms it is called 'disable' 572 * and bits have disable semantices. 573 */ 574 media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); 575 if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) 576 media_fuse = ~media_fuse; 577 578 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; 579 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> 580 GEN11_GT_VEBOX_DISABLE_SHIFT; 581 582 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { 583 fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1); 584 gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1); 585 } else { 586 gt->info.sfc_mask = ~0; 587 } 588 589 for (i = 0; i < I915_MAX_VCS; i++) { 590 if (!HAS_ENGINE(gt, _VCS(i))) { 591 vdbox_mask &= ~BIT(i); 592 continue; 593 } 594 595 if (!(BIT(i) & vdbox_mask)) { 596 info->engine_mask &= ~BIT(_VCS(i)); 597 drm_dbg(&i915->drm, "vcs%u fused off\n", i); 598 continue; 599 } 600 601 if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask)) 602 gt->info.vdbox_sfc_access |= BIT(i); 603 logical_vdbox++; 604 } 605 drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n", 606 vdbox_mask, VDBOX_MASK(gt)); 607 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt)); 608 609 for (i = 0; i < I915_MAX_VECS; i++) { 610 if (!HAS_ENGINE(gt, _VECS(i))) { 611 vebox_mask &= ~BIT(i); 612 continue; 613 } 614 615 if (!(BIT(i) & vebox_mask)) { 616 info->engine_mask &= ~BIT(_VECS(i)); 617 drm_dbg(&i915->drm, "vecs%u fused off\n", i); 618 } 619 } 620 drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n", 621 vebox_mask, VEBOX_MASK(gt)); 622 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); 623 624 return info->engine_mask; 625 } 626 627 static void populate_logical_ids(struct intel_gt *gt, u8 *logical_ids, 628 u8 class, const u8 *map, u8 num_instances) 629 { 630 int i, j; 631 u8 current_logical_id = 0; 632 633 for (j = 0; j < num_instances; ++j) { 634 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) { 635 if (!HAS_ENGINE(gt, i) || 636 intel_engines[i].class != class) 637 continue; 638 639 if (intel_engines[i].instance == map[j]) { 640 logical_ids[intel_engines[i].instance] = 641 current_logical_id++; 642 break; 643 } 644 } 645 } 646 } 647 648 static void setup_logical_ids(struct intel_gt *gt, u8 *logical_ids, u8 class) 649 { 650 int i; 651 u8 map[MAX_ENGINE_INSTANCE + 1]; 652 653 for (i = 0; i < MAX_ENGINE_INSTANCE + 1; ++i) 654 map[i] = i; 655 populate_logical_ids(gt, logical_ids, class, map, ARRAY_SIZE(map)); 656 } 657 658 /** 659 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers 660 * @gt: pointer to struct intel_gt 661 * 662 * Return: non-zero if the initialization failed. 663 */ 664 int intel_engines_init_mmio(struct intel_gt *gt) 665 { 666 struct drm_i915_private *i915 = gt->i915; 667 const unsigned int engine_mask = init_engine_mask(gt); 668 unsigned int mask = 0; 669 unsigned int i, class; 670 u8 logical_ids[MAX_ENGINE_INSTANCE + 1]; 671 int err; 672 673 drm_WARN_ON(&i915->drm, engine_mask == 0); 674 drm_WARN_ON(&i915->drm, engine_mask & 675 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES)); 676 677 if (i915_inject_probe_failure(i915)) 678 return -ENODEV; 679 680 for (class = 0; class < MAX_ENGINE_CLASS + 1; ++class) { 681 setup_logical_ids(gt, logical_ids, class); 682 683 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) { 684 u8 instance = intel_engines[i].instance; 685 686 if (intel_engines[i].class != class || 687 !HAS_ENGINE(gt, i)) 688 continue; 689 690 err = intel_engine_setup(gt, i, 691 logical_ids[instance]); 692 if (err) 693 goto cleanup; 694 695 mask |= BIT(i); 696 } 697 } 698 699 /* 700 * Catch failures to update intel_engines table when the new engines 701 * are added to the driver by a warning and disabling the forgotten 702 * engines. 703 */ 704 if (drm_WARN_ON(&i915->drm, mask != engine_mask)) 705 gt->info.engine_mask = mask; 706 707 gt->info.num_engines = hweight32(mask); 708 709 intel_gt_check_and_clear_faults(gt); 710 711 intel_setup_engine_capabilities(gt); 712 713 intel_uncore_prune_engine_fw_domains(gt->uncore, gt); 714 715 return 0; 716 717 cleanup: 718 intel_engines_free(gt); 719 return err; 720 } 721 722 void intel_engine_init_execlists(struct intel_engine_cs *engine) 723 { 724 struct intel_engine_execlists * const execlists = &engine->execlists; 725 726 execlists->port_mask = 1; 727 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists))); 728 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS); 729 730 memset(execlists->pending, 0, sizeof(execlists->pending)); 731 execlists->active = 732 memset(execlists->inflight, 0, sizeof(execlists->inflight)); 733 } 734 735 static void cleanup_status_page(struct intel_engine_cs *engine) 736 { 737 struct i915_vma *vma; 738 739 /* Prevent writes into HWSP after returning the page to the system */ 740 intel_engine_set_hwsp_writemask(engine, ~0u); 741 742 vma = fetch_and_zero(&engine->status_page.vma); 743 if (!vma) 744 return; 745 746 if (!HWS_NEEDS_PHYSICAL(engine->i915)) 747 i915_vma_unpin(vma); 748 749 i915_gem_object_unpin_map(vma->obj); 750 i915_gem_object_put(vma->obj); 751 } 752 753 static int pin_ggtt_status_page(struct intel_engine_cs *engine, 754 struct i915_gem_ww_ctx *ww, 755 struct i915_vma *vma) 756 { 757 unsigned int flags; 758 759 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) 760 /* 761 * On g33, we cannot place HWS above 256MiB, so 762 * restrict its pinning to the low mappable arena. 763 * Though this restriction is not documented for 764 * gen4, gen5, or byt, they also behave similarly 765 * and hang if the HWS is placed at the top of the 766 * GTT. To generalise, it appears that all !llc 767 * platforms have issues with us placing the HWS 768 * above the mappable region (even though we never 769 * actually map it). 770 */ 771 flags = PIN_MAPPABLE; 772 else 773 flags = PIN_HIGH; 774 775 return i915_ggtt_pin(vma, ww, 0, flags); 776 } 777 778 static int init_status_page(struct intel_engine_cs *engine) 779 { 780 struct drm_i915_gem_object *obj; 781 struct i915_gem_ww_ctx ww; 782 struct i915_vma *vma; 783 void *vaddr; 784 int ret; 785 786 INIT_LIST_HEAD(&engine->status_page.timelines); 787 788 /* 789 * Though the HWS register does support 36bit addresses, historically 790 * we have had hangs and corruption reported due to wild writes if 791 * the HWS is placed above 4G. We only allow objects to be allocated 792 * in GFP_DMA32 for i965, and no earlier physical address users had 793 * access to more than 4G. 794 */ 795 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); 796 if (IS_ERR(obj)) { 797 drm_err(&engine->i915->drm, 798 "Failed to allocate status page\n"); 799 return PTR_ERR(obj); 800 } 801 802 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 803 804 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); 805 if (IS_ERR(vma)) { 806 ret = PTR_ERR(vma); 807 goto err_put; 808 } 809 810 i915_gem_ww_ctx_init(&ww, true); 811 retry: 812 ret = i915_gem_object_lock(obj, &ww); 813 if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915)) 814 ret = pin_ggtt_status_page(engine, &ww, vma); 815 if (ret) 816 goto err; 817 818 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); 819 if (IS_ERR(vaddr)) { 820 ret = PTR_ERR(vaddr); 821 goto err_unpin; 822 } 823 824 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE); 825 engine->status_page.vma = vma; 826 827 err_unpin: 828 if (ret) 829 i915_vma_unpin(vma); 830 err: 831 if (ret == -EDEADLK) { 832 ret = i915_gem_ww_ctx_backoff(&ww); 833 if (!ret) 834 goto retry; 835 } 836 i915_gem_ww_ctx_fini(&ww); 837 err_put: 838 if (ret) 839 i915_gem_object_put(obj); 840 return ret; 841 } 842 843 static int engine_setup_common(struct intel_engine_cs *engine) 844 { 845 int err; 846 847 init_llist_head(&engine->barrier_tasks); 848 849 err = init_status_page(engine); 850 if (err) 851 return err; 852 853 engine->breadcrumbs = intel_breadcrumbs_create(engine); 854 if (!engine->breadcrumbs) { 855 err = -ENOMEM; 856 goto err_status; 857 } 858 859 engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL); 860 if (!engine->sched_engine) { 861 err = -ENOMEM; 862 goto err_sched_engine; 863 } 864 engine->sched_engine->private_data = engine; 865 866 err = intel_engine_init_cmd_parser(engine); 867 if (err) 868 goto err_cmd_parser; 869 870 intel_engine_init_execlists(engine); 871 intel_engine_init__pm(engine); 872 intel_engine_init_retire(engine); 873 874 /* Use the whole device by default */ 875 engine->sseu = 876 intel_sseu_from_device_info(&engine->gt->info.sseu); 877 878 intel_engine_init_workarounds(engine); 879 intel_engine_init_whitelist(engine); 880 intel_engine_init_ctx_wa(engine); 881 882 if (GRAPHICS_VER(engine->i915) >= 12) 883 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO; 884 885 return 0; 886 887 err_cmd_parser: 888 i915_sched_engine_put(engine->sched_engine); 889 err_sched_engine: 890 intel_breadcrumbs_put(engine->breadcrumbs); 891 err_status: 892 cleanup_status_page(engine); 893 return err; 894 } 895 896 struct measure_breadcrumb { 897 struct i915_request rq; 898 struct intel_ring ring; 899 u32 cs[2048]; 900 }; 901 902 static int measure_breadcrumb_dw(struct intel_context *ce) 903 { 904 struct intel_engine_cs *engine = ce->engine; 905 struct measure_breadcrumb *frame; 906 int dw; 907 908 GEM_BUG_ON(!engine->gt->scratch); 909 910 frame = kzalloc(sizeof(*frame), GFP_KERNEL); 911 if (!frame) 912 return -ENOMEM; 913 914 frame->rq.engine = engine; 915 frame->rq.context = ce; 916 rcu_assign_pointer(frame->rq.timeline, ce->timeline); 917 frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno; 918 919 frame->ring.vaddr = frame->cs; 920 frame->ring.size = sizeof(frame->cs); 921 frame->ring.wrap = 922 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size); 923 frame->ring.effective_size = frame->ring.size; 924 intel_ring_update_space(&frame->ring); 925 frame->rq.ring = &frame->ring; 926 927 mutex_lock(&ce->timeline->mutex); 928 spin_lock_irq(&engine->sched_engine->lock); 929 930 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs; 931 932 spin_unlock_irq(&engine->sched_engine->lock); 933 mutex_unlock(&ce->timeline->mutex); 934 935 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */ 936 937 kfree(frame); 938 return dw; 939 } 940 941 struct intel_context * 942 intel_engine_create_pinned_context(struct intel_engine_cs *engine, 943 struct i915_address_space *vm, 944 unsigned int ring_size, 945 unsigned int hwsp, 946 struct lock_class_key *key, 947 const char *name) 948 { 949 struct intel_context *ce; 950 int err; 951 952 ce = intel_context_create(engine); 953 if (IS_ERR(ce)) 954 return ce; 955 956 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags); 957 ce->timeline = page_pack_bits(NULL, hwsp); 958 ce->ring = NULL; 959 ce->ring_size = ring_size; 960 961 i915_vm_put(ce->vm); 962 ce->vm = i915_vm_get(vm); 963 964 err = intel_context_pin(ce); /* perma-pin so it is always available */ 965 if (err) { 966 intel_context_put(ce); 967 return ERR_PTR(err); 968 } 969 970 list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list); 971 972 /* 973 * Give our perma-pinned kernel timelines a separate lockdep class, 974 * so that we can use them from within the normal user timelines 975 * should we need to inject GPU operations during their request 976 * construction. 977 */ 978 lockdep_set_class_and_name(&ce->timeline->mutex, key, name); 979 980 return ce; 981 } 982 983 void intel_engine_destroy_pinned_context(struct intel_context *ce) 984 { 985 struct intel_engine_cs *engine = ce->engine; 986 struct i915_vma *hwsp = engine->status_page.vma; 987 988 GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp); 989 990 mutex_lock(&hwsp->vm->mutex); 991 list_del(&ce->timeline->engine_link); 992 mutex_unlock(&hwsp->vm->mutex); 993 994 list_del(&ce->pinned_contexts_link); 995 intel_context_unpin(ce); 996 intel_context_put(ce); 997 } 998 999 static struct intel_context * 1000 create_kernel_context(struct intel_engine_cs *engine) 1001 { 1002 static struct lock_class_key kernel; 1003 1004 return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K, 1005 I915_GEM_HWS_SEQNO_ADDR, 1006 &kernel, "kernel_context"); 1007 } 1008 1009 /** 1010 * intel_engines_init_common - initialize cengine state which might require hw access 1011 * @engine: Engine to initialize. 1012 * 1013 * Initializes @engine@ structure members shared between legacy and execlists 1014 * submission modes which do require hardware access. 1015 * 1016 * Typcally done at later stages of submission mode specific engine setup. 1017 * 1018 * Returns zero on success or an error code on failure. 1019 */ 1020 static int engine_init_common(struct intel_engine_cs *engine) 1021 { 1022 struct intel_context *ce; 1023 int ret; 1024 1025 engine->set_default_submission(engine); 1026 1027 /* 1028 * We may need to do things with the shrinker which 1029 * require us to immediately switch back to the default 1030 * context. This can cause a problem as pinning the 1031 * default context also requires GTT space which may not 1032 * be available. To avoid this we always pin the default 1033 * context. 1034 */ 1035 ce = create_kernel_context(engine); 1036 if (IS_ERR(ce)) 1037 return PTR_ERR(ce); 1038 1039 ret = measure_breadcrumb_dw(ce); 1040 if (ret < 0) 1041 goto err_context; 1042 1043 engine->emit_fini_breadcrumb_dw = ret; 1044 engine->kernel_context = ce; 1045 1046 return 0; 1047 1048 err_context: 1049 intel_engine_destroy_pinned_context(ce); 1050 return ret; 1051 } 1052 1053 int intel_engines_init(struct intel_gt *gt) 1054 { 1055 int (*setup)(struct intel_engine_cs *engine); 1056 struct intel_engine_cs *engine; 1057 enum intel_engine_id id; 1058 int err; 1059 1060 if (intel_uc_uses_guc_submission(>->uc)) { 1061 gt->submission_method = INTEL_SUBMISSION_GUC; 1062 setup = intel_guc_submission_setup; 1063 } else if (HAS_EXECLISTS(gt->i915)) { 1064 gt->submission_method = INTEL_SUBMISSION_ELSP; 1065 setup = intel_execlists_submission_setup; 1066 } else { 1067 gt->submission_method = INTEL_SUBMISSION_RING; 1068 setup = intel_ring_submission_setup; 1069 } 1070 1071 for_each_engine(engine, gt, id) { 1072 err = engine_setup_common(engine); 1073 if (err) 1074 return err; 1075 1076 err = setup(engine); 1077 if (err) 1078 return err; 1079 1080 err = engine_init_common(engine); 1081 if (err) 1082 return err; 1083 1084 intel_engine_add_user(engine); 1085 } 1086 1087 return 0; 1088 } 1089 1090 /** 1091 * intel_engines_cleanup_common - cleans up the engine state created by 1092 * the common initiailizers. 1093 * @engine: Engine to cleanup. 1094 * 1095 * This cleans up everything created by the common helpers. 1096 */ 1097 void intel_engine_cleanup_common(struct intel_engine_cs *engine) 1098 { 1099 GEM_BUG_ON(!list_empty(&engine->sched_engine->requests)); 1100 1101 i915_sched_engine_put(engine->sched_engine); 1102 intel_breadcrumbs_put(engine->breadcrumbs); 1103 1104 intel_engine_fini_retire(engine); 1105 intel_engine_cleanup_cmd_parser(engine); 1106 1107 if (engine->default_state) 1108 fput(engine->default_state); 1109 1110 if (engine->kernel_context) 1111 intel_engine_destroy_pinned_context(engine->kernel_context); 1112 1113 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks)); 1114 cleanup_status_page(engine); 1115 1116 intel_wa_list_free(&engine->ctx_wa_list); 1117 intel_wa_list_free(&engine->wa_list); 1118 intel_wa_list_free(&engine->whitelist); 1119 } 1120 1121 /** 1122 * intel_engine_resume - re-initializes the HW state of the engine 1123 * @engine: Engine to resume. 1124 * 1125 * Returns zero on success or an error code on failure. 1126 */ 1127 int intel_engine_resume(struct intel_engine_cs *engine) 1128 { 1129 intel_engine_apply_workarounds(engine); 1130 intel_engine_apply_whitelist(engine); 1131 1132 return engine->resume(engine); 1133 } 1134 1135 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine) 1136 { 1137 struct drm_i915_private *i915 = engine->i915; 1138 1139 u64 acthd; 1140 1141 if (GRAPHICS_VER(i915) >= 8) 1142 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW); 1143 else if (GRAPHICS_VER(i915) >= 4) 1144 acthd = ENGINE_READ(engine, RING_ACTHD); 1145 else 1146 acthd = ENGINE_READ(engine, ACTHD); 1147 1148 return acthd; 1149 } 1150 1151 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine) 1152 { 1153 u64 bbaddr; 1154 1155 if (GRAPHICS_VER(engine->i915) >= 8) 1156 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW); 1157 else 1158 bbaddr = ENGINE_READ(engine, RING_BBADDR); 1159 1160 return bbaddr; 1161 } 1162 1163 static unsigned long stop_timeout(const struct intel_engine_cs *engine) 1164 { 1165 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */ 1166 return 0; 1167 1168 /* 1169 * If we are doing a normal GPU reset, we can take our time and allow 1170 * the engine to quiesce. We've stopped submission to the engine, and 1171 * if we wait long enough an innocent context should complete and 1172 * leave the engine idle. So they should not be caught unaware by 1173 * the forthcoming GPU reset (which usually follows the stop_cs)! 1174 */ 1175 return READ_ONCE(engine->props.stop_timeout_ms); 1176 } 1177 1178 static int __intel_engine_stop_cs(struct intel_engine_cs *engine, 1179 int fast_timeout_us, 1180 int slow_timeout_ms) 1181 { 1182 struct intel_uncore *uncore = engine->uncore; 1183 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); 1184 int err; 1185 1186 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); 1187 err = __intel_wait_for_register_fw(engine->uncore, mode, 1188 MODE_IDLE, MODE_IDLE, 1189 fast_timeout_us, 1190 slow_timeout_ms, 1191 NULL); 1192 1193 /* A final mmio read to let GPU writes be hopefully flushed to memory */ 1194 intel_uncore_posting_read_fw(uncore, mode); 1195 return err; 1196 } 1197 1198 int intel_engine_stop_cs(struct intel_engine_cs *engine) 1199 { 1200 int err = 0; 1201 1202 if (GRAPHICS_VER(engine->i915) < 3) 1203 return -ENODEV; 1204 1205 ENGINE_TRACE(engine, "\n"); 1206 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { 1207 ENGINE_TRACE(engine, 1208 "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n", 1209 ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR, 1210 ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR); 1211 1212 /* 1213 * Sometimes we observe that the idle flag is not 1214 * set even though the ring is empty. So double 1215 * check before giving up. 1216 */ 1217 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) != 1218 (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR)) 1219 err = -ETIMEDOUT; 1220 } 1221 1222 return err; 1223 } 1224 1225 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) 1226 { 1227 ENGINE_TRACE(engine, "\n"); 1228 1229 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); 1230 } 1231 1232 const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 1233 { 1234 switch (type) { 1235 case I915_CACHE_NONE: return " uncached"; 1236 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 1237 case I915_CACHE_L3_LLC: return " L3+LLC"; 1238 case I915_CACHE_WT: return " WT"; 1239 default: return ""; 1240 } 1241 } 1242 1243 static u32 1244 read_subslice_reg(const struct intel_engine_cs *engine, 1245 int slice, int subslice, i915_reg_t reg) 1246 { 1247 return intel_uncore_read_with_mcr_steering(engine->uncore, reg, 1248 slice, subslice); 1249 } 1250 1251 /* NB: please notice the memset */ 1252 void intel_engine_get_instdone(const struct intel_engine_cs *engine, 1253 struct intel_instdone *instdone) 1254 { 1255 struct drm_i915_private *i915 = engine->i915; 1256 const struct sseu_dev_info *sseu = &engine->gt->info.sseu; 1257 struct intel_uncore *uncore = engine->uncore; 1258 u32 mmio_base = engine->mmio_base; 1259 int slice; 1260 int subslice; 1261 int iter; 1262 1263 memset(instdone, 0, sizeof(*instdone)); 1264 1265 if (GRAPHICS_VER(i915) >= 8) { 1266 instdone->instdone = 1267 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1268 1269 if (engine->id != RCS0) 1270 return; 1271 1272 instdone->slice_common = 1273 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1274 if (GRAPHICS_VER(i915) >= 12) { 1275 instdone->slice_common_extra[0] = 1276 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA); 1277 instdone->slice_common_extra[1] = 1278 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2); 1279 } 1280 1281 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { 1282 for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) { 1283 instdone->sampler[slice][subslice] = 1284 read_subslice_reg(engine, slice, subslice, 1285 GEN7_SAMPLER_INSTDONE); 1286 instdone->row[slice][subslice] = 1287 read_subslice_reg(engine, slice, subslice, 1288 GEN7_ROW_INSTDONE); 1289 } 1290 } else { 1291 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) { 1292 instdone->sampler[slice][subslice] = 1293 read_subslice_reg(engine, slice, subslice, 1294 GEN7_SAMPLER_INSTDONE); 1295 instdone->row[slice][subslice] = 1296 read_subslice_reg(engine, slice, subslice, 1297 GEN7_ROW_INSTDONE); 1298 } 1299 } 1300 1301 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { 1302 for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) 1303 instdone->geom_svg[slice][subslice] = 1304 read_subslice_reg(engine, slice, subslice, 1305 XEHPG_INSTDONE_GEOM_SVG); 1306 } 1307 } else if (GRAPHICS_VER(i915) >= 7) { 1308 instdone->instdone = 1309 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1310 1311 if (engine->id != RCS0) 1312 return; 1313 1314 instdone->slice_common = 1315 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1316 instdone->sampler[0][0] = 1317 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE); 1318 instdone->row[0][0] = 1319 intel_uncore_read(uncore, GEN7_ROW_INSTDONE); 1320 } else if (GRAPHICS_VER(i915) >= 4) { 1321 instdone->instdone = 1322 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1323 if (engine->id == RCS0) 1324 /* HACK: Using the wrong struct member */ 1325 instdone->slice_common = 1326 intel_uncore_read(uncore, GEN4_INSTDONE1); 1327 } else { 1328 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE); 1329 } 1330 } 1331 1332 static bool ring_is_idle(struct intel_engine_cs *engine) 1333 { 1334 bool idle = true; 1335 1336 if (I915_SELFTEST_ONLY(!engine->mmio_base)) 1337 return true; 1338 1339 if (!intel_engine_pm_get_if_awake(engine)) 1340 return true; 1341 1342 /* First check that no commands are left in the ring */ 1343 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) != 1344 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR)) 1345 idle = false; 1346 1347 /* No bit for gen2, so assume the CS parser is idle */ 1348 if (GRAPHICS_VER(engine->i915) > 2 && 1349 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE)) 1350 idle = false; 1351 1352 intel_engine_pm_put(engine); 1353 1354 return idle; 1355 } 1356 1357 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync) 1358 { 1359 struct tasklet_struct *t = &engine->sched_engine->tasklet; 1360 1361 if (!t->callback) 1362 return; 1363 1364 local_bh_disable(); 1365 if (tasklet_trylock(t)) { 1366 /* Must wait for any GPU reset in progress. */ 1367 if (__tasklet_is_enabled(t)) 1368 t->callback(t); 1369 tasklet_unlock(t); 1370 } 1371 local_bh_enable(); 1372 1373 /* Synchronise and wait for the tasklet on another CPU */ 1374 if (sync) 1375 tasklet_unlock_wait(t); 1376 } 1377 1378 /** 1379 * intel_engine_is_idle() - Report if the engine has finished process all work 1380 * @engine: the intel_engine_cs 1381 * 1382 * Return true if there are no requests pending, nothing left to be submitted 1383 * to hardware, and that the engine is idle. 1384 */ 1385 bool intel_engine_is_idle(struct intel_engine_cs *engine) 1386 { 1387 /* More white lies, if wedged, hw state is inconsistent */ 1388 if (intel_gt_is_wedged(engine->gt)) 1389 return true; 1390 1391 if (!intel_engine_pm_is_awake(engine)) 1392 return true; 1393 1394 /* Waiting to drain ELSP? */ 1395 intel_synchronize_hardirq(engine->i915); 1396 intel_engine_flush_submission(engine); 1397 1398 /* ELSP is empty, but there are ready requests? E.g. after reset */ 1399 if (!i915_sched_engine_is_empty(engine->sched_engine)) 1400 return false; 1401 1402 /* Ring stopped? */ 1403 return ring_is_idle(engine); 1404 } 1405 1406 bool intel_engines_are_idle(struct intel_gt *gt) 1407 { 1408 struct intel_engine_cs *engine; 1409 enum intel_engine_id id; 1410 1411 /* 1412 * If the driver is wedged, HW state may be very inconsistent and 1413 * report that it is still busy, even though we have stopped using it. 1414 */ 1415 if (intel_gt_is_wedged(gt)) 1416 return true; 1417 1418 /* Already parked (and passed an idleness test); must still be idle */ 1419 if (!READ_ONCE(gt->awake)) 1420 return true; 1421 1422 for_each_engine(engine, gt, id) { 1423 if (!intel_engine_is_idle(engine)) 1424 return false; 1425 } 1426 1427 return true; 1428 } 1429 1430 bool intel_engine_irq_enable(struct intel_engine_cs *engine) 1431 { 1432 if (!engine->irq_enable) 1433 return false; 1434 1435 /* Caller disables interrupts */ 1436 spin_lock(&engine->gt->irq_lock); 1437 engine->irq_enable(engine); 1438 spin_unlock(&engine->gt->irq_lock); 1439 1440 return true; 1441 } 1442 1443 void intel_engine_irq_disable(struct intel_engine_cs *engine) 1444 { 1445 if (!engine->irq_disable) 1446 return; 1447 1448 /* Caller disables interrupts */ 1449 spin_lock(&engine->gt->irq_lock); 1450 engine->irq_disable(engine); 1451 spin_unlock(&engine->gt->irq_lock); 1452 } 1453 1454 void intel_engines_reset_default_submission(struct intel_gt *gt) 1455 { 1456 struct intel_engine_cs *engine; 1457 enum intel_engine_id id; 1458 1459 for_each_engine(engine, gt, id) { 1460 if (engine->sanitize) 1461 engine->sanitize(engine); 1462 1463 engine->set_default_submission(engine); 1464 } 1465 } 1466 1467 bool intel_engine_can_store_dword(struct intel_engine_cs *engine) 1468 { 1469 switch (GRAPHICS_VER(engine->i915)) { 1470 case 2: 1471 return false; /* uses physical not virtual addresses */ 1472 case 3: 1473 /* maybe only uses physical not virtual addresses */ 1474 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); 1475 case 4: 1476 return !IS_I965G(engine->i915); /* who knows! */ 1477 case 6: 1478 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ 1479 default: 1480 return true; 1481 } 1482 } 1483 1484 static struct intel_timeline *get_timeline(struct i915_request *rq) 1485 { 1486 struct intel_timeline *tl; 1487 1488 /* 1489 * Even though we are holding the engine->sched_engine->lock here, there 1490 * is no control over the submission queue per-se and we are 1491 * inspecting the active state at a random point in time, with an 1492 * unknown queue. Play safe and make sure the timeline remains valid. 1493 * (Only being used for pretty printing, one extra kref shouldn't 1494 * cause a camel stampede!) 1495 */ 1496 rcu_read_lock(); 1497 tl = rcu_dereference(rq->timeline); 1498 if (!kref_get_unless_zero(&tl->kref)) 1499 tl = NULL; 1500 rcu_read_unlock(); 1501 1502 return tl; 1503 } 1504 1505 static int print_ring(char *buf, int sz, struct i915_request *rq) 1506 { 1507 int len = 0; 1508 1509 if (!i915_request_signaled(rq)) { 1510 struct intel_timeline *tl = get_timeline(rq); 1511 1512 len = scnprintf(buf, sz, 1513 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ", 1514 i915_ggtt_offset(rq->ring->vma), 1515 tl ? tl->hwsp_offset : 0, 1516 hwsp_seqno(rq), 1517 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context), 1518 1000 * 1000)); 1519 1520 if (tl) 1521 intel_timeline_put(tl); 1522 } 1523 1524 return len; 1525 } 1526 1527 static void hexdump(struct drm_printer *m, const void *buf, size_t len) 1528 { 1529 const size_t rowsize = 8 * sizeof(u32); 1530 const void *prev = NULL; 1531 bool skip = false; 1532 size_t pos; 1533 1534 for (pos = 0; pos < len; pos += rowsize) { 1535 char line[128]; 1536 1537 if (prev && !memcmp(prev, buf + pos, rowsize)) { 1538 if (!skip) { 1539 drm_printf(m, "*\n"); 1540 skip = true; 1541 } 1542 continue; 1543 } 1544 1545 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos, 1546 rowsize, sizeof(u32), 1547 line, sizeof(line), 1548 false) >= sizeof(line)); 1549 drm_printf(m, "[%04zx] %s\n", pos, line); 1550 1551 prev = buf + pos; 1552 skip = false; 1553 } 1554 } 1555 1556 static const char *repr_timer(const struct timer_list *t) 1557 { 1558 if (!READ_ONCE(t->expires)) 1559 return "inactive"; 1560 1561 if (timer_pending(t)) 1562 return "active"; 1563 1564 return "expired"; 1565 } 1566 1567 static void intel_engine_print_registers(struct intel_engine_cs *engine, 1568 struct drm_printer *m) 1569 { 1570 struct drm_i915_private *dev_priv = engine->i915; 1571 struct intel_engine_execlists * const execlists = &engine->execlists; 1572 u64 addr; 1573 1574 if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7)) 1575 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID)); 1576 if (HAS_EXECLISTS(dev_priv)) { 1577 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n", 1578 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI)); 1579 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n", 1580 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO)); 1581 } 1582 drm_printf(m, "\tRING_START: 0x%08x\n", 1583 ENGINE_READ(engine, RING_START)); 1584 drm_printf(m, "\tRING_HEAD: 0x%08x\n", 1585 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR); 1586 drm_printf(m, "\tRING_TAIL: 0x%08x\n", 1587 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR); 1588 drm_printf(m, "\tRING_CTL: 0x%08x%s\n", 1589 ENGINE_READ(engine, RING_CTL), 1590 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : ""); 1591 if (GRAPHICS_VER(engine->i915) > 2) { 1592 drm_printf(m, "\tRING_MODE: 0x%08x%s\n", 1593 ENGINE_READ(engine, RING_MI_MODE), 1594 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : ""); 1595 } 1596 1597 if (GRAPHICS_VER(dev_priv) >= 6) { 1598 drm_printf(m, "\tRING_IMR: 0x%08x\n", 1599 ENGINE_READ(engine, RING_IMR)); 1600 drm_printf(m, "\tRING_ESR: 0x%08x\n", 1601 ENGINE_READ(engine, RING_ESR)); 1602 drm_printf(m, "\tRING_EMR: 0x%08x\n", 1603 ENGINE_READ(engine, RING_EMR)); 1604 drm_printf(m, "\tRING_EIR: 0x%08x\n", 1605 ENGINE_READ(engine, RING_EIR)); 1606 } 1607 1608 addr = intel_engine_get_active_head(engine); 1609 drm_printf(m, "\tACTHD: 0x%08x_%08x\n", 1610 upper_32_bits(addr), lower_32_bits(addr)); 1611 addr = intel_engine_get_last_batch_head(engine); 1612 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n", 1613 upper_32_bits(addr), lower_32_bits(addr)); 1614 if (GRAPHICS_VER(dev_priv) >= 8) 1615 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW); 1616 else if (GRAPHICS_VER(dev_priv) >= 4) 1617 addr = ENGINE_READ(engine, RING_DMA_FADD); 1618 else 1619 addr = ENGINE_READ(engine, DMA_FADD_I8XX); 1620 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n", 1621 upper_32_bits(addr), lower_32_bits(addr)); 1622 if (GRAPHICS_VER(dev_priv) >= 4) { 1623 drm_printf(m, "\tIPEIR: 0x%08x\n", 1624 ENGINE_READ(engine, RING_IPEIR)); 1625 drm_printf(m, "\tIPEHR: 0x%08x\n", 1626 ENGINE_READ(engine, RING_IPEHR)); 1627 } else { 1628 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR)); 1629 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR)); 1630 } 1631 1632 if (intel_engine_uses_guc(engine)) { 1633 /* nothing to print yet */ 1634 } else if (HAS_EXECLISTS(dev_priv)) { 1635 struct i915_request * const *port, *rq; 1636 const u32 *hws = 1637 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; 1638 const u8 num_entries = execlists->csb_size; 1639 unsigned int idx; 1640 u8 read, write; 1641 1642 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n", 1643 yesno(test_bit(TASKLET_STATE_SCHED, 1644 &engine->sched_engine->tasklet.state)), 1645 enableddisabled(!atomic_read(&engine->sched_engine->tasklet.count)), 1646 repr_timer(&engine->execlists.preempt), 1647 repr_timer(&engine->execlists.timer)); 1648 1649 read = execlists->csb_head; 1650 write = READ_ONCE(*execlists->csb_write); 1651 1652 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n", 1653 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO), 1654 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI), 1655 read, write, num_entries); 1656 1657 if (read >= num_entries) 1658 read = 0; 1659 if (write >= num_entries) 1660 write = 0; 1661 if (read > write) 1662 write += num_entries; 1663 while (read < write) { 1664 idx = ++read % num_entries; 1665 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", 1666 idx, hws[idx * 2], hws[idx * 2 + 1]); 1667 } 1668 1669 i915_sched_engine_active_lock_bh(engine->sched_engine); 1670 rcu_read_lock(); 1671 for (port = execlists->active; (rq = *port); port++) { 1672 char hdr[160]; 1673 int len; 1674 1675 len = scnprintf(hdr, sizeof(hdr), 1676 "\t\tActive[%d]: ccid:%08x%s%s, ", 1677 (int)(port - execlists->active), 1678 rq->context->lrc.ccid, 1679 intel_context_is_closed(rq->context) ? "!" : "", 1680 intel_context_is_banned(rq->context) ? "*" : ""); 1681 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1682 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1683 i915_request_show(m, rq, hdr, 0); 1684 } 1685 for (port = execlists->pending; (rq = *port); port++) { 1686 char hdr[160]; 1687 int len; 1688 1689 len = scnprintf(hdr, sizeof(hdr), 1690 "\t\tPending[%d]: ccid:%08x%s%s, ", 1691 (int)(port - execlists->pending), 1692 rq->context->lrc.ccid, 1693 intel_context_is_closed(rq->context) ? "!" : "", 1694 intel_context_is_banned(rq->context) ? "*" : ""); 1695 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1696 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1697 i915_request_show(m, rq, hdr, 0); 1698 } 1699 rcu_read_unlock(); 1700 i915_sched_engine_active_unlock_bh(engine->sched_engine); 1701 } else if (GRAPHICS_VER(dev_priv) > 6) { 1702 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n", 1703 ENGINE_READ(engine, RING_PP_DIR_BASE)); 1704 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", 1705 ENGINE_READ(engine, RING_PP_DIR_BASE_READ)); 1706 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", 1707 ENGINE_READ(engine, RING_PP_DIR_DCLV)); 1708 } 1709 } 1710 1711 static void print_request_ring(struct drm_printer *m, struct i915_request *rq) 1712 { 1713 struct i915_vma_snapshot *vsnap = &rq->batch_snapshot; 1714 void *ring; 1715 int size; 1716 1717 if (!i915_vma_snapshot_present(vsnap)) 1718 vsnap = NULL; 1719 1720 drm_printf(m, 1721 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n", 1722 rq->head, rq->postfix, rq->tail, 1723 vsnap ? upper_32_bits(vsnap->gtt_offset) : ~0u, 1724 vsnap ? lower_32_bits(vsnap->gtt_offset) : ~0u); 1725 1726 size = rq->tail - rq->head; 1727 if (rq->tail < rq->head) 1728 size += rq->ring->size; 1729 1730 ring = kmalloc(size, GFP_ATOMIC); 1731 if (ring) { 1732 const void *vaddr = rq->ring->vaddr; 1733 unsigned int head = rq->head; 1734 unsigned int len = 0; 1735 1736 if (rq->tail < head) { 1737 len = rq->ring->size - head; 1738 memcpy(ring, vaddr + head, len); 1739 head = 0; 1740 } 1741 memcpy(ring + len, vaddr + head, size - len); 1742 1743 hexdump(m, ring, size); 1744 kfree(ring); 1745 } 1746 } 1747 1748 static unsigned long list_count(struct list_head *list) 1749 { 1750 struct list_head *pos; 1751 unsigned long count = 0; 1752 1753 list_for_each(pos, list) 1754 count++; 1755 1756 return count; 1757 } 1758 1759 static unsigned long read_ul(void *p, size_t x) 1760 { 1761 return *(unsigned long *)(p + x); 1762 } 1763 1764 static void print_properties(struct intel_engine_cs *engine, 1765 struct drm_printer *m) 1766 { 1767 static const struct pmap { 1768 size_t offset; 1769 const char *name; 1770 } props[] = { 1771 #define P(x) { \ 1772 .offset = offsetof(typeof(engine->props), x), \ 1773 .name = #x \ 1774 } 1775 P(heartbeat_interval_ms), 1776 P(max_busywait_duration_ns), 1777 P(preempt_timeout_ms), 1778 P(stop_timeout_ms), 1779 P(timeslice_duration_ms), 1780 1781 {}, 1782 #undef P 1783 }; 1784 const struct pmap *p; 1785 1786 drm_printf(m, "\tProperties:\n"); 1787 for (p = props; p->name; p++) 1788 drm_printf(m, "\t\t%s: %lu [default %lu]\n", 1789 p->name, 1790 read_ul(&engine->props, p->offset), 1791 read_ul(&engine->defaults, p->offset)); 1792 } 1793 1794 static void engine_dump_request(struct i915_request *rq, struct drm_printer *m, const char *msg) 1795 { 1796 struct intel_timeline *tl = get_timeline(rq); 1797 1798 i915_request_show(m, rq, msg, 0); 1799 1800 drm_printf(m, "\t\tring->start: 0x%08x\n", 1801 i915_ggtt_offset(rq->ring->vma)); 1802 drm_printf(m, "\t\tring->head: 0x%08x\n", 1803 rq->ring->head); 1804 drm_printf(m, "\t\tring->tail: 0x%08x\n", 1805 rq->ring->tail); 1806 drm_printf(m, "\t\tring->emit: 0x%08x\n", 1807 rq->ring->emit); 1808 drm_printf(m, "\t\tring->space: 0x%08x\n", 1809 rq->ring->space); 1810 1811 if (tl) { 1812 drm_printf(m, "\t\tring->hwsp: 0x%08x\n", 1813 tl->hwsp_offset); 1814 intel_timeline_put(tl); 1815 } 1816 1817 print_request_ring(m, rq); 1818 1819 if (rq->context->lrc_reg_state) { 1820 drm_printf(m, "Logical Ring Context:\n"); 1821 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE); 1822 } 1823 } 1824 1825 void intel_engine_dump_active_requests(struct list_head *requests, 1826 struct i915_request *hung_rq, 1827 struct drm_printer *m) 1828 { 1829 struct i915_request *rq; 1830 const char *msg; 1831 enum i915_request_state state; 1832 1833 list_for_each_entry(rq, requests, sched.link) { 1834 if (rq == hung_rq) 1835 continue; 1836 1837 state = i915_test_request_state(rq); 1838 if (state < I915_REQUEST_QUEUED) 1839 continue; 1840 1841 if (state == I915_REQUEST_ACTIVE) 1842 msg = "\t\tactive on engine"; 1843 else 1844 msg = "\t\tactive in queue"; 1845 1846 engine_dump_request(rq, m, msg); 1847 } 1848 } 1849 1850 static void engine_dump_active_requests(struct intel_engine_cs *engine, struct drm_printer *m) 1851 { 1852 struct i915_request *hung_rq = NULL; 1853 struct intel_context *ce; 1854 bool guc; 1855 1856 /* 1857 * No need for an engine->irq_seqno_barrier() before the seqno reads. 1858 * The GPU is still running so requests are still executing and any 1859 * hardware reads will be out of date by the time they are reported. 1860 * But the intention here is just to report an instantaneous snapshot 1861 * so that's fine. 1862 */ 1863 lockdep_assert_held(&engine->sched_engine->lock); 1864 1865 drm_printf(m, "\tRequests:\n"); 1866 1867 guc = intel_uc_uses_guc_submission(&engine->gt->uc); 1868 if (guc) { 1869 ce = intel_engine_get_hung_context(engine); 1870 if (ce) 1871 hung_rq = intel_context_find_active_request(ce); 1872 } else { 1873 hung_rq = intel_engine_execlist_find_hung_request(engine); 1874 } 1875 1876 if (hung_rq) 1877 engine_dump_request(hung_rq, m, "\t\thung"); 1878 1879 if (guc) 1880 intel_guc_dump_active_requests(engine, hung_rq, m); 1881 else 1882 intel_engine_dump_active_requests(&engine->sched_engine->requests, 1883 hung_rq, m); 1884 } 1885 1886 void intel_engine_dump(struct intel_engine_cs *engine, 1887 struct drm_printer *m, 1888 const char *header, ...) 1889 { 1890 struct i915_gpu_error * const error = &engine->i915->gpu_error; 1891 struct i915_request *rq; 1892 intel_wakeref_t wakeref; 1893 unsigned long flags; 1894 ktime_t dummy; 1895 1896 if (header) { 1897 va_list ap; 1898 1899 va_start(ap, header); 1900 drm_vprintf(m, header, &ap); 1901 va_end(ap); 1902 } 1903 1904 if (intel_gt_is_wedged(engine->gt)) 1905 drm_printf(m, "*** WEDGED ***\n"); 1906 1907 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count)); 1908 drm_printf(m, "\tBarriers?: %s\n", 1909 yesno(!llist_empty(&engine->barrier_tasks))); 1910 drm_printf(m, "\tLatency: %luus\n", 1911 ewma__engine_latency_read(&engine->latency)); 1912 if (intel_engine_supports_stats(engine)) 1913 drm_printf(m, "\tRuntime: %llums\n", 1914 ktime_to_ms(intel_engine_get_busy_time(engine, 1915 &dummy))); 1916 drm_printf(m, "\tForcewake: %x domains, %d active\n", 1917 engine->fw_domain, READ_ONCE(engine->fw_active)); 1918 1919 rcu_read_lock(); 1920 rq = READ_ONCE(engine->heartbeat.systole); 1921 if (rq) 1922 drm_printf(m, "\tHeartbeat: %d ms ago\n", 1923 jiffies_to_msecs(jiffies - rq->emitted_jiffies)); 1924 rcu_read_unlock(); 1925 drm_printf(m, "\tReset count: %d (global %d)\n", 1926 i915_reset_engine_count(error, engine), 1927 i915_reset_count(error)); 1928 print_properties(engine, m); 1929 1930 spin_lock_irqsave(&engine->sched_engine->lock, flags); 1931 engine_dump_active_requests(engine, m); 1932 1933 drm_printf(m, "\tOn hold?: %lu\n", 1934 list_count(&engine->sched_engine->hold)); 1935 spin_unlock_irqrestore(&engine->sched_engine->lock, flags); 1936 1937 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base); 1938 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm); 1939 if (wakeref) { 1940 intel_engine_print_registers(engine, m); 1941 intel_runtime_pm_put(engine->uncore->rpm, wakeref); 1942 } else { 1943 drm_printf(m, "\tDevice is asleep; skipping register dump\n"); 1944 } 1945 1946 intel_execlists_show_requests(engine, m, i915_request_show, 8); 1947 1948 drm_printf(m, "HWSP:\n"); 1949 hexdump(m, engine->status_page.addr, PAGE_SIZE); 1950 1951 drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine))); 1952 1953 intel_engine_print_breadcrumbs(engine, m); 1954 } 1955 1956 /** 1957 * intel_engine_get_busy_time() - Return current accumulated engine busyness 1958 * @engine: engine to report on 1959 * @now: monotonic timestamp of sampling 1960 * 1961 * Returns accumulated time @engine was busy since engine stats were enabled. 1962 */ 1963 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) 1964 { 1965 return engine->busyness(engine, now); 1966 } 1967 1968 struct intel_context * 1969 intel_engine_create_virtual(struct intel_engine_cs **siblings, 1970 unsigned int count, unsigned long flags) 1971 { 1972 if (count == 0) 1973 return ERR_PTR(-EINVAL); 1974 1975 if (count == 1 && !(flags & FORCE_VIRTUAL)) 1976 return intel_context_create(siblings[0]); 1977 1978 GEM_BUG_ON(!siblings[0]->cops->create_virtual); 1979 return siblings[0]->cops->create_virtual(siblings, count, flags); 1980 } 1981 1982 struct i915_request * 1983 intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine) 1984 { 1985 struct i915_request *request, *active = NULL; 1986 1987 /* 1988 * This search does not work in GuC submission mode. However, the GuC 1989 * will report the hanging context directly to the driver itself. So 1990 * the driver should never get here when in GuC mode. 1991 */ 1992 GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc)); 1993 1994 /* 1995 * We are called by the error capture, reset and to dump engine 1996 * state at random points in time. In particular, note that neither is 1997 * crucially ordered with an interrupt. After a hang, the GPU is dead 1998 * and we assume that no more writes can happen (we waited long enough 1999 * for all writes that were in transaction to be flushed) - adding an 2000 * extra delay for a recent interrupt is pointless. Hence, we do 2001 * not need an engine->irq_seqno_barrier() before the seqno reads. 2002 * At all other times, we must assume the GPU is still running, but 2003 * we only care about the snapshot of this moment. 2004 */ 2005 lockdep_assert_held(&engine->sched_engine->lock); 2006 2007 rcu_read_lock(); 2008 request = execlists_active(&engine->execlists); 2009 if (request) { 2010 struct intel_timeline *tl = request->context->timeline; 2011 2012 list_for_each_entry_from_reverse(request, &tl->requests, link) { 2013 if (__i915_request_is_complete(request)) 2014 break; 2015 2016 active = request; 2017 } 2018 } 2019 rcu_read_unlock(); 2020 if (active) 2021 return active; 2022 2023 list_for_each_entry(request, &engine->sched_engine->requests, 2024 sched.link) { 2025 if (i915_test_request_state(request) != I915_REQUEST_ACTIVE) 2026 continue; 2027 2028 active = request; 2029 break; 2030 } 2031 2032 return active; 2033 } 2034 2035 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2036 #include "mock_engine.c" 2037 #include "selftest_engine.c" 2038 #include "selftest_engine_cs.c" 2039 #endif 2040