1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2016 Intel Corporation 4 */ 5 6 #include <drm/drm_print.h> 7 8 #include "gem/i915_gem_context.h" 9 10 #include "i915_drv.h" 11 12 #include "intel_breadcrumbs.h" 13 #include "intel_context.h" 14 #include "intel_engine.h" 15 #include "intel_engine_pm.h" 16 #include "intel_engine_user.h" 17 #include "intel_execlists_submission.h" 18 #include "intel_gt.h" 19 #include "intel_gt_requests.h" 20 #include "intel_gt_pm.h" 21 #include "intel_lrc_reg.h" 22 #include "intel_reset.h" 23 #include "intel_ring.h" 24 #include "uc/intel_guc_submission.h" 25 26 /* Haswell does have the CXT_SIZE register however it does not appear to be 27 * valid. Now, docs explain in dwords what is in the context object. The full 28 * size is 70720 bytes, however, the power context and execlist context will 29 * never be saved (power context is stored elsewhere, and execlists don't work 30 * on HSW) - so the final size, including the extra state required for the 31 * Resource Streamer, is 66944 bytes, which rounds to 17 pages. 32 */ 33 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 34 35 #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 36 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) 37 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 38 #define GEN10_LR_CONTEXT_RENDER_SIZE (18 * PAGE_SIZE) 39 #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE) 40 41 #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE) 42 43 #define MAX_MMIO_BASES 3 44 struct engine_info { 45 unsigned int hw_id; 46 u8 class; 47 u8 instance; 48 /* mmio bases table *must* be sorted in reverse gen order */ 49 struct engine_mmio_base { 50 u32 gen : 8; 51 u32 base : 24; 52 } mmio_bases[MAX_MMIO_BASES]; 53 }; 54 55 static const struct engine_info intel_engines[] = { 56 [RCS0] = { 57 .hw_id = RCS0_HW, 58 .class = RENDER_CLASS, 59 .instance = 0, 60 .mmio_bases = { 61 { .gen = 1, .base = RENDER_RING_BASE } 62 }, 63 }, 64 [BCS0] = { 65 .hw_id = BCS0_HW, 66 .class = COPY_ENGINE_CLASS, 67 .instance = 0, 68 .mmio_bases = { 69 { .gen = 6, .base = BLT_RING_BASE } 70 }, 71 }, 72 [VCS0] = { 73 .hw_id = VCS0_HW, 74 .class = VIDEO_DECODE_CLASS, 75 .instance = 0, 76 .mmio_bases = { 77 { .gen = 11, .base = GEN11_BSD_RING_BASE }, 78 { .gen = 6, .base = GEN6_BSD_RING_BASE }, 79 { .gen = 4, .base = BSD_RING_BASE } 80 }, 81 }, 82 [VCS1] = { 83 .hw_id = VCS1_HW, 84 .class = VIDEO_DECODE_CLASS, 85 .instance = 1, 86 .mmio_bases = { 87 { .gen = 11, .base = GEN11_BSD2_RING_BASE }, 88 { .gen = 8, .base = GEN8_BSD2_RING_BASE } 89 }, 90 }, 91 [VCS2] = { 92 .hw_id = VCS2_HW, 93 .class = VIDEO_DECODE_CLASS, 94 .instance = 2, 95 .mmio_bases = { 96 { .gen = 11, .base = GEN11_BSD3_RING_BASE } 97 }, 98 }, 99 [VCS3] = { 100 .hw_id = VCS3_HW, 101 .class = VIDEO_DECODE_CLASS, 102 .instance = 3, 103 .mmio_bases = { 104 { .gen = 11, .base = GEN11_BSD4_RING_BASE } 105 }, 106 }, 107 [VECS0] = { 108 .hw_id = VECS0_HW, 109 .class = VIDEO_ENHANCEMENT_CLASS, 110 .instance = 0, 111 .mmio_bases = { 112 { .gen = 11, .base = GEN11_VEBOX_RING_BASE }, 113 { .gen = 7, .base = VEBOX_RING_BASE } 114 }, 115 }, 116 [VECS1] = { 117 .hw_id = VECS1_HW, 118 .class = VIDEO_ENHANCEMENT_CLASS, 119 .instance = 1, 120 .mmio_bases = { 121 { .gen = 11, .base = GEN11_VEBOX2_RING_BASE } 122 }, 123 }, 124 }; 125 126 /** 127 * intel_engine_context_size() - return the size of the context for an engine 128 * @gt: the gt 129 * @class: engine class 130 * 131 * Each engine class may require a different amount of space for a context 132 * image. 133 * 134 * Return: size (in bytes) of an engine class specific context image 135 * 136 * Note: this size includes the HWSP, which is part of the context image 137 * in LRC mode, but does not include the "shared data page" used with 138 * GuC submission. The caller should account for this if using the GuC. 139 */ 140 u32 intel_engine_context_size(struct intel_gt *gt, u8 class) 141 { 142 struct intel_uncore *uncore = gt->uncore; 143 u32 cxt_size; 144 145 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE); 146 147 switch (class) { 148 case RENDER_CLASS: 149 switch (INTEL_GEN(gt->i915)) { 150 default: 151 MISSING_CASE(INTEL_GEN(gt->i915)); 152 return DEFAULT_LR_CONTEXT_RENDER_SIZE; 153 case 12: 154 case 11: 155 return GEN11_LR_CONTEXT_RENDER_SIZE; 156 case 10: 157 return GEN10_LR_CONTEXT_RENDER_SIZE; 158 case 9: 159 return GEN9_LR_CONTEXT_RENDER_SIZE; 160 case 8: 161 return GEN8_LR_CONTEXT_RENDER_SIZE; 162 case 7: 163 if (IS_HASWELL(gt->i915)) 164 return HSW_CXT_TOTAL_SIZE; 165 166 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE); 167 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64, 168 PAGE_SIZE); 169 case 6: 170 cxt_size = intel_uncore_read(uncore, CXT_SIZE); 171 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64, 172 PAGE_SIZE); 173 case 5: 174 case 4: 175 /* 176 * There is a discrepancy here between the size reported 177 * by the register and the size of the context layout 178 * in the docs. Both are described as authorative! 179 * 180 * The discrepancy is on the order of a few cachelines, 181 * but the total is under one page (4k), which is our 182 * minimum allocation anyway so it should all come 183 * out in the wash. 184 */ 185 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1; 186 drm_dbg(>->i915->drm, 187 "gen%d CXT_SIZE = %d bytes [0x%08x]\n", 188 INTEL_GEN(gt->i915), cxt_size * 64, 189 cxt_size - 1); 190 return round_up(cxt_size * 64, PAGE_SIZE); 191 case 3: 192 case 2: 193 /* For the special day when i810 gets merged. */ 194 case 1: 195 return 0; 196 } 197 break; 198 default: 199 MISSING_CASE(class); 200 fallthrough; 201 case VIDEO_DECODE_CLASS: 202 case VIDEO_ENHANCEMENT_CLASS: 203 case COPY_ENGINE_CLASS: 204 if (INTEL_GEN(gt->i915) < 8) 205 return 0; 206 return GEN8_LR_CONTEXT_OTHER_SIZE; 207 } 208 } 209 210 static u32 __engine_mmio_base(struct drm_i915_private *i915, 211 const struct engine_mmio_base *bases) 212 { 213 int i; 214 215 for (i = 0; i < MAX_MMIO_BASES; i++) 216 if (INTEL_GEN(i915) >= bases[i].gen) 217 break; 218 219 GEM_BUG_ON(i == MAX_MMIO_BASES); 220 GEM_BUG_ON(!bases[i].base); 221 222 return bases[i].base; 223 } 224 225 static void __sprint_engine_name(struct intel_engine_cs *engine) 226 { 227 /* 228 * Before we know what the uABI name for this engine will be, 229 * we still would like to keep track of this engine in the debug logs. 230 * We throw in a ' here as a reminder that this isn't its final name. 231 */ 232 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u", 233 intel_engine_class_repr(engine->class), 234 engine->instance) >= sizeof(engine->name)); 235 } 236 237 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask) 238 { 239 /* 240 * Though they added more rings on g4x/ilk, they did not add 241 * per-engine HWSTAM until gen6. 242 */ 243 if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS) 244 return; 245 246 if (INTEL_GEN(engine->i915) >= 3) 247 ENGINE_WRITE(engine, RING_HWSTAM, mask); 248 else 249 ENGINE_WRITE16(engine, RING_HWSTAM, mask); 250 } 251 252 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine) 253 { 254 /* Mask off all writes into the unknown HWSP */ 255 intel_engine_set_hwsp_writemask(engine, ~0u); 256 } 257 258 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) 259 { 260 const struct engine_info *info = &intel_engines[id]; 261 struct drm_i915_private *i915 = gt->i915; 262 struct intel_engine_cs *engine; 263 264 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH)); 265 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH)); 266 267 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine))) 268 return -EINVAL; 269 270 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS)) 271 return -EINVAL; 272 273 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE)) 274 return -EINVAL; 275 276 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance])) 277 return -EINVAL; 278 279 engine = kzalloc(sizeof(*engine), GFP_KERNEL); 280 if (!engine) 281 return -ENOMEM; 282 283 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES); 284 285 engine->id = id; 286 engine->legacy_idx = INVALID_ENGINE; 287 engine->mask = BIT(id); 288 engine->i915 = i915; 289 engine->gt = gt; 290 engine->uncore = gt->uncore; 291 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases); 292 engine->hw_id = info->hw_id; 293 engine->guc_id = MAKE_GUC_ID(info->class, info->instance); 294 295 engine->class = info->class; 296 engine->instance = info->instance; 297 __sprint_engine_name(engine); 298 299 engine->props.heartbeat_interval_ms = 300 CONFIG_DRM_I915_HEARTBEAT_INTERVAL; 301 engine->props.max_busywait_duration_ns = 302 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT; 303 engine->props.preempt_timeout_ms = 304 CONFIG_DRM_I915_PREEMPT_TIMEOUT; 305 engine->props.stop_timeout_ms = 306 CONFIG_DRM_I915_STOP_TIMEOUT; 307 engine->props.timeslice_duration_ms = 308 CONFIG_DRM_I915_TIMESLICE_DURATION; 309 310 /* Override to uninterruptible for OpenCL workloads. */ 311 if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS) 312 engine->props.preempt_timeout_ms = 0; 313 314 engine->defaults = engine->props; /* never to change again */ 315 316 engine->context_size = intel_engine_context_size(gt, engine->class); 317 if (WARN_ON(engine->context_size > BIT(20))) 318 engine->context_size = 0; 319 if (engine->context_size) 320 DRIVER_CAPS(i915)->has_logical_contexts = true; 321 322 /* Nothing to do here, execute in order of dependencies */ 323 engine->schedule = NULL; 324 325 ewma__engine_latency_init(&engine->latency); 326 seqcount_init(&engine->stats.lock); 327 328 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); 329 330 /* Scrub mmio state on takeover */ 331 intel_engine_sanitize_mmio(engine); 332 333 gt->engine_class[info->class][info->instance] = engine; 334 gt->engine[id] = engine; 335 336 return 0; 337 } 338 339 static void __setup_engine_capabilities(struct intel_engine_cs *engine) 340 { 341 struct drm_i915_private *i915 = engine->i915; 342 343 if (engine->class == VIDEO_DECODE_CLASS) { 344 /* 345 * HEVC support is present on first engine instance 346 * before Gen11 and on all instances afterwards. 347 */ 348 if (INTEL_GEN(i915) >= 11 || 349 (INTEL_GEN(i915) >= 9 && engine->instance == 0)) 350 engine->uabi_capabilities |= 351 I915_VIDEO_CLASS_CAPABILITY_HEVC; 352 353 /* 354 * SFC block is present only on even logical engine 355 * instances. 356 */ 357 if ((INTEL_GEN(i915) >= 11 && 358 (engine->gt->info.vdbox_sfc_access & 359 BIT(engine->instance))) || 360 (INTEL_GEN(i915) >= 9 && engine->instance == 0)) 361 engine->uabi_capabilities |= 362 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 363 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) { 364 if (INTEL_GEN(i915) >= 9) 365 engine->uabi_capabilities |= 366 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 367 } 368 } 369 370 static void intel_setup_engine_capabilities(struct intel_gt *gt) 371 { 372 struct intel_engine_cs *engine; 373 enum intel_engine_id id; 374 375 for_each_engine(engine, gt, id) 376 __setup_engine_capabilities(engine); 377 } 378 379 /** 380 * intel_engines_release() - free the resources allocated for Command Streamers 381 * @gt: pointer to struct intel_gt 382 */ 383 void intel_engines_release(struct intel_gt *gt) 384 { 385 struct intel_engine_cs *engine; 386 enum intel_engine_id id; 387 388 /* 389 * Before we release the resources held by engine, we must be certain 390 * that the HW is no longer accessing them -- having the GPU scribble 391 * to or read from a page being used for something else causes no end 392 * of fun. 393 * 394 * The GPU should be reset by this point, but assume the worst just 395 * in case we aborted before completely initialising the engines. 396 */ 397 GEM_BUG_ON(intel_gt_pm_is_awake(gt)); 398 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) 399 __intel_gt_reset(gt, ALL_ENGINES); 400 401 /* Decouple the backend; but keep the layout for late GPU resets */ 402 for_each_engine(engine, gt, id) { 403 if (!engine->release) 404 continue; 405 406 intel_wakeref_wait_for_idle(&engine->wakeref); 407 GEM_BUG_ON(intel_engine_pm_is_awake(engine)); 408 409 engine->release(engine); 410 engine->release = NULL; 411 412 memset(&engine->reset, 0, sizeof(engine->reset)); 413 } 414 } 415 416 void intel_engine_free_request_pool(struct intel_engine_cs *engine) 417 { 418 if (!engine->request_pool) 419 return; 420 421 kmem_cache_free(i915_request_slab_cache(), engine->request_pool); 422 } 423 424 void intel_engines_free(struct intel_gt *gt) 425 { 426 struct intel_engine_cs *engine; 427 enum intel_engine_id id; 428 429 /* Free the requests! dma-resv keeps fences around for an eternity */ 430 rcu_barrier(); 431 432 for_each_engine(engine, gt, id) { 433 intel_engine_free_request_pool(engine); 434 kfree(engine); 435 gt->engine[id] = NULL; 436 } 437 } 438 439 /* 440 * Determine which engines are fused off in our particular hardware. 441 * Note that we have a catch-22 situation where we need to be able to access 442 * the blitter forcewake domain to read the engine fuses, but at the same time 443 * we need to know which engines are available on the system to know which 444 * forcewake domains are present. We solve this by intializing the forcewake 445 * domains based on the full engine mask in the platform capabilities before 446 * calling this function and pruning the domains for fused-off engines 447 * afterwards. 448 */ 449 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) 450 { 451 struct drm_i915_private *i915 = gt->i915; 452 struct intel_gt_info *info = >->info; 453 struct intel_uncore *uncore = gt->uncore; 454 unsigned int logical_vdbox = 0; 455 unsigned int i; 456 u32 media_fuse; 457 u16 vdbox_mask; 458 u16 vebox_mask; 459 460 info->engine_mask = INTEL_INFO(i915)->platform_engine_mask; 461 462 if (INTEL_GEN(i915) < 11) 463 return info->engine_mask; 464 465 media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); 466 467 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; 468 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> 469 GEN11_GT_VEBOX_DISABLE_SHIFT; 470 471 for (i = 0; i < I915_MAX_VCS; i++) { 472 if (!HAS_ENGINE(gt, _VCS(i))) { 473 vdbox_mask &= ~BIT(i); 474 continue; 475 } 476 477 if (!(BIT(i) & vdbox_mask)) { 478 info->engine_mask &= ~BIT(_VCS(i)); 479 drm_dbg(&i915->drm, "vcs%u fused off\n", i); 480 continue; 481 } 482 483 /* 484 * In Gen11, only even numbered logical VDBOXes are 485 * hooked up to an SFC (Scaler & Format Converter) unit. 486 * In TGL each VDBOX has access to an SFC. 487 */ 488 if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0) 489 gt->info.vdbox_sfc_access |= BIT(i); 490 } 491 drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n", 492 vdbox_mask, VDBOX_MASK(gt)); 493 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt)); 494 495 for (i = 0; i < I915_MAX_VECS; i++) { 496 if (!HAS_ENGINE(gt, _VECS(i))) { 497 vebox_mask &= ~BIT(i); 498 continue; 499 } 500 501 if (!(BIT(i) & vebox_mask)) { 502 info->engine_mask &= ~BIT(_VECS(i)); 503 drm_dbg(&i915->drm, "vecs%u fused off\n", i); 504 } 505 } 506 drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n", 507 vebox_mask, VEBOX_MASK(gt)); 508 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); 509 510 return info->engine_mask; 511 } 512 513 /** 514 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers 515 * @gt: pointer to struct intel_gt 516 * 517 * Return: non-zero if the initialization failed. 518 */ 519 int intel_engines_init_mmio(struct intel_gt *gt) 520 { 521 struct drm_i915_private *i915 = gt->i915; 522 const unsigned int engine_mask = init_engine_mask(gt); 523 unsigned int mask = 0; 524 unsigned int i; 525 int err; 526 527 drm_WARN_ON(&i915->drm, engine_mask == 0); 528 drm_WARN_ON(&i915->drm, engine_mask & 529 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES)); 530 531 if (i915_inject_probe_failure(i915)) 532 return -ENODEV; 533 534 for (i = 0; i < ARRAY_SIZE(intel_engines); i++) { 535 if (!HAS_ENGINE(gt, i)) 536 continue; 537 538 err = intel_engine_setup(gt, i); 539 if (err) 540 goto cleanup; 541 542 mask |= BIT(i); 543 } 544 545 /* 546 * Catch failures to update intel_engines table when the new engines 547 * are added to the driver by a warning and disabling the forgotten 548 * engines. 549 */ 550 if (drm_WARN_ON(&i915->drm, mask != engine_mask)) 551 gt->info.engine_mask = mask; 552 553 gt->info.num_engines = hweight32(mask); 554 555 intel_gt_check_and_clear_faults(gt); 556 557 intel_setup_engine_capabilities(gt); 558 559 intel_uncore_prune_engine_fw_domains(gt->uncore, gt); 560 561 return 0; 562 563 cleanup: 564 intel_engines_free(gt); 565 return err; 566 } 567 568 void intel_engine_init_execlists(struct intel_engine_cs *engine) 569 { 570 struct intel_engine_execlists * const execlists = &engine->execlists; 571 572 execlists->port_mask = 1; 573 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists))); 574 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS); 575 576 memset(execlists->pending, 0, sizeof(execlists->pending)); 577 execlists->active = 578 memset(execlists->inflight, 0, sizeof(execlists->inflight)); 579 580 execlists->queue_priority_hint = INT_MIN; 581 execlists->queue = RB_ROOT_CACHED; 582 } 583 584 static void cleanup_status_page(struct intel_engine_cs *engine) 585 { 586 struct i915_vma *vma; 587 588 /* Prevent writes into HWSP after returning the page to the system */ 589 intel_engine_set_hwsp_writemask(engine, ~0u); 590 591 vma = fetch_and_zero(&engine->status_page.vma); 592 if (!vma) 593 return; 594 595 if (!HWS_NEEDS_PHYSICAL(engine->i915)) 596 i915_vma_unpin(vma); 597 598 i915_gem_object_unpin_map(vma->obj); 599 i915_gem_object_put(vma->obj); 600 } 601 602 static int pin_ggtt_status_page(struct intel_engine_cs *engine, 603 struct i915_gem_ww_ctx *ww, 604 struct i915_vma *vma) 605 { 606 unsigned int flags; 607 608 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) 609 /* 610 * On g33, we cannot place HWS above 256MiB, so 611 * restrict its pinning to the low mappable arena. 612 * Though this restriction is not documented for 613 * gen4, gen5, or byt, they also behave similarly 614 * and hang if the HWS is placed at the top of the 615 * GTT. To generalise, it appears that all !llc 616 * platforms have issues with us placing the HWS 617 * above the mappable region (even though we never 618 * actually map it). 619 */ 620 flags = PIN_MAPPABLE; 621 else 622 flags = PIN_HIGH; 623 624 return i915_ggtt_pin(vma, ww, 0, flags); 625 } 626 627 static int init_status_page(struct intel_engine_cs *engine) 628 { 629 struct drm_i915_gem_object *obj; 630 struct i915_gem_ww_ctx ww; 631 struct i915_vma *vma; 632 void *vaddr; 633 int ret; 634 635 INIT_LIST_HEAD(&engine->status_page.timelines); 636 637 /* 638 * Though the HWS register does support 36bit addresses, historically 639 * we have had hangs and corruption reported due to wild writes if 640 * the HWS is placed above 4G. We only allow objects to be allocated 641 * in GFP_DMA32 for i965, and no earlier physical address users had 642 * access to more than 4G. 643 */ 644 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); 645 if (IS_ERR(obj)) { 646 drm_err(&engine->i915->drm, 647 "Failed to allocate status page\n"); 648 return PTR_ERR(obj); 649 } 650 651 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 652 653 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); 654 if (IS_ERR(vma)) { 655 ret = PTR_ERR(vma); 656 goto err_put; 657 } 658 659 i915_gem_ww_ctx_init(&ww, true); 660 retry: 661 ret = i915_gem_object_lock(obj, &ww); 662 if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915)) 663 ret = pin_ggtt_status_page(engine, &ww, vma); 664 if (ret) 665 goto err; 666 667 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); 668 if (IS_ERR(vaddr)) { 669 ret = PTR_ERR(vaddr); 670 goto err_unpin; 671 } 672 673 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE); 674 engine->status_page.vma = vma; 675 676 err_unpin: 677 if (ret) 678 i915_vma_unpin(vma); 679 err: 680 if (ret == -EDEADLK) { 681 ret = i915_gem_ww_ctx_backoff(&ww); 682 if (!ret) 683 goto retry; 684 } 685 i915_gem_ww_ctx_fini(&ww); 686 err_put: 687 if (ret) 688 i915_gem_object_put(obj); 689 return ret; 690 } 691 692 static int engine_setup_common(struct intel_engine_cs *engine) 693 { 694 int err; 695 696 init_llist_head(&engine->barrier_tasks); 697 698 err = init_status_page(engine); 699 if (err) 700 return err; 701 702 engine->breadcrumbs = intel_breadcrumbs_create(engine); 703 if (!engine->breadcrumbs) { 704 err = -ENOMEM; 705 goto err_status; 706 } 707 708 err = intel_engine_init_cmd_parser(engine); 709 if (err) 710 goto err_cmd_parser; 711 712 intel_engine_init_active(engine, ENGINE_PHYSICAL); 713 intel_engine_init_execlists(engine); 714 intel_engine_init__pm(engine); 715 intel_engine_init_retire(engine); 716 717 /* Use the whole device by default */ 718 engine->sseu = 719 intel_sseu_from_device_info(&engine->gt->info.sseu); 720 721 intel_engine_init_workarounds(engine); 722 intel_engine_init_whitelist(engine); 723 intel_engine_init_ctx_wa(engine); 724 725 if (INTEL_GEN(engine->i915) >= 12) 726 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO; 727 728 return 0; 729 730 err_cmd_parser: 731 intel_breadcrumbs_free(engine->breadcrumbs); 732 err_status: 733 cleanup_status_page(engine); 734 return err; 735 } 736 737 struct measure_breadcrumb { 738 struct i915_request rq; 739 struct intel_ring ring; 740 u32 cs[2048]; 741 }; 742 743 static int measure_breadcrumb_dw(struct intel_context *ce) 744 { 745 struct intel_engine_cs *engine = ce->engine; 746 struct measure_breadcrumb *frame; 747 int dw; 748 749 GEM_BUG_ON(!engine->gt->scratch); 750 751 frame = kzalloc(sizeof(*frame), GFP_KERNEL); 752 if (!frame) 753 return -ENOMEM; 754 755 frame->rq.engine = engine; 756 frame->rq.context = ce; 757 rcu_assign_pointer(frame->rq.timeline, ce->timeline); 758 frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno; 759 760 frame->ring.vaddr = frame->cs; 761 frame->ring.size = sizeof(frame->cs); 762 frame->ring.wrap = 763 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size); 764 frame->ring.effective_size = frame->ring.size; 765 intel_ring_update_space(&frame->ring); 766 frame->rq.ring = &frame->ring; 767 768 mutex_lock(&ce->timeline->mutex); 769 spin_lock_irq(&engine->active.lock); 770 771 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs; 772 773 spin_unlock_irq(&engine->active.lock); 774 mutex_unlock(&ce->timeline->mutex); 775 776 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */ 777 778 kfree(frame); 779 return dw; 780 } 781 782 void 783 intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass) 784 { 785 INIT_LIST_HEAD(&engine->active.requests); 786 INIT_LIST_HEAD(&engine->active.hold); 787 788 spin_lock_init(&engine->active.lock); 789 lockdep_set_subclass(&engine->active.lock, subclass); 790 791 /* 792 * Due to an interesting quirk in lockdep's internal debug tracking, 793 * after setting a subclass we must ensure the lock is used. Otherwise, 794 * nr_unused_locks is incremented once too often. 795 */ 796 #ifdef CONFIG_DEBUG_LOCK_ALLOC 797 local_irq_disable(); 798 lock_map_acquire(&engine->active.lock.dep_map); 799 lock_map_release(&engine->active.lock.dep_map); 800 local_irq_enable(); 801 #endif 802 } 803 804 static struct intel_context * 805 create_pinned_context(struct intel_engine_cs *engine, 806 unsigned int hwsp, 807 struct lock_class_key *key, 808 const char *name) 809 { 810 struct intel_context *ce; 811 int err; 812 813 ce = intel_context_create(engine); 814 if (IS_ERR(ce)) 815 return ce; 816 817 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags); 818 ce->timeline = page_pack_bits(NULL, hwsp); 819 820 err = intel_context_pin(ce); /* perma-pin so it is always available */ 821 if (err) { 822 intel_context_put(ce); 823 return ERR_PTR(err); 824 } 825 826 /* 827 * Give our perma-pinned kernel timelines a separate lockdep class, 828 * so that we can use them from within the normal user timelines 829 * should we need to inject GPU operations during their request 830 * construction. 831 */ 832 lockdep_set_class_and_name(&ce->timeline->mutex, key, name); 833 834 return ce; 835 } 836 837 static void destroy_pinned_context(struct intel_context *ce) 838 { 839 struct intel_engine_cs *engine = ce->engine; 840 struct i915_vma *hwsp = engine->status_page.vma; 841 842 GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp); 843 844 mutex_lock(&hwsp->vm->mutex); 845 list_del(&ce->timeline->engine_link); 846 mutex_unlock(&hwsp->vm->mutex); 847 848 intel_context_unpin(ce); 849 intel_context_put(ce); 850 } 851 852 static struct intel_context * 853 create_kernel_context(struct intel_engine_cs *engine) 854 { 855 static struct lock_class_key kernel; 856 857 return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR, 858 &kernel, "kernel_context"); 859 } 860 861 /** 862 * intel_engines_init_common - initialize cengine state which might require hw access 863 * @engine: Engine to initialize. 864 * 865 * Initializes @engine@ structure members shared between legacy and execlists 866 * submission modes which do require hardware access. 867 * 868 * Typcally done at later stages of submission mode specific engine setup. 869 * 870 * Returns zero on success or an error code on failure. 871 */ 872 static int engine_init_common(struct intel_engine_cs *engine) 873 { 874 struct intel_context *ce; 875 int ret; 876 877 engine->set_default_submission(engine); 878 879 /* 880 * We may need to do things with the shrinker which 881 * require us to immediately switch back to the default 882 * context. This can cause a problem as pinning the 883 * default context also requires GTT space which may not 884 * be available. To avoid this we always pin the default 885 * context. 886 */ 887 ce = create_kernel_context(engine); 888 if (IS_ERR(ce)) 889 return PTR_ERR(ce); 890 891 ret = measure_breadcrumb_dw(ce); 892 if (ret < 0) 893 goto err_context; 894 895 engine->emit_fini_breadcrumb_dw = ret; 896 engine->kernel_context = ce; 897 898 return 0; 899 900 err_context: 901 intel_context_put(ce); 902 return ret; 903 } 904 905 int intel_engines_init(struct intel_gt *gt) 906 { 907 int (*setup)(struct intel_engine_cs *engine); 908 struct intel_engine_cs *engine; 909 enum intel_engine_id id; 910 int err; 911 912 if (intel_uc_uses_guc_submission(>->uc)) 913 setup = intel_guc_submission_setup; 914 else if (HAS_EXECLISTS(gt->i915)) 915 setup = intel_execlists_submission_setup; 916 else 917 setup = intel_ring_submission_setup; 918 919 for_each_engine(engine, gt, id) { 920 err = engine_setup_common(engine); 921 if (err) 922 return err; 923 924 err = setup(engine); 925 if (err) 926 return err; 927 928 err = engine_init_common(engine); 929 if (err) 930 return err; 931 932 intel_engine_add_user(engine); 933 } 934 935 return 0; 936 } 937 938 /** 939 * intel_engines_cleanup_common - cleans up the engine state created by 940 * the common initiailizers. 941 * @engine: Engine to cleanup. 942 * 943 * This cleans up everything created by the common helpers. 944 */ 945 void intel_engine_cleanup_common(struct intel_engine_cs *engine) 946 { 947 GEM_BUG_ON(!list_empty(&engine->active.requests)); 948 tasklet_kill(&engine->execlists.tasklet); /* flush the callback */ 949 950 intel_breadcrumbs_free(engine->breadcrumbs); 951 952 intel_engine_fini_retire(engine); 953 intel_engine_cleanup_cmd_parser(engine); 954 955 if (engine->default_state) 956 fput(engine->default_state); 957 958 if (engine->kernel_context) 959 destroy_pinned_context(engine->kernel_context); 960 961 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks)); 962 cleanup_status_page(engine); 963 964 intel_wa_list_free(&engine->ctx_wa_list); 965 intel_wa_list_free(&engine->wa_list); 966 intel_wa_list_free(&engine->whitelist); 967 } 968 969 /** 970 * intel_engine_resume - re-initializes the HW state of the engine 971 * @engine: Engine to resume. 972 * 973 * Returns zero on success or an error code on failure. 974 */ 975 int intel_engine_resume(struct intel_engine_cs *engine) 976 { 977 intel_engine_apply_workarounds(engine); 978 intel_engine_apply_whitelist(engine); 979 980 return engine->resume(engine); 981 } 982 983 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine) 984 { 985 struct drm_i915_private *i915 = engine->i915; 986 987 u64 acthd; 988 989 if (INTEL_GEN(i915) >= 8) 990 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW); 991 else if (INTEL_GEN(i915) >= 4) 992 acthd = ENGINE_READ(engine, RING_ACTHD); 993 else 994 acthd = ENGINE_READ(engine, ACTHD); 995 996 return acthd; 997 } 998 999 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine) 1000 { 1001 u64 bbaddr; 1002 1003 if (INTEL_GEN(engine->i915) >= 8) 1004 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW); 1005 else 1006 bbaddr = ENGINE_READ(engine, RING_BBADDR); 1007 1008 return bbaddr; 1009 } 1010 1011 static unsigned long stop_timeout(const struct intel_engine_cs *engine) 1012 { 1013 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */ 1014 return 0; 1015 1016 /* 1017 * If we are doing a normal GPU reset, we can take our time and allow 1018 * the engine to quiesce. We've stopped submission to the engine, and 1019 * if we wait long enough an innocent context should complete and 1020 * leave the engine idle. So they should not be caught unaware by 1021 * the forthcoming GPU reset (which usually follows the stop_cs)! 1022 */ 1023 return READ_ONCE(engine->props.stop_timeout_ms); 1024 } 1025 1026 static int __intel_engine_stop_cs(struct intel_engine_cs *engine, 1027 int fast_timeout_us, 1028 int slow_timeout_ms) 1029 { 1030 struct intel_uncore *uncore = engine->uncore; 1031 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); 1032 int err; 1033 1034 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); 1035 err = __intel_wait_for_register_fw(engine->uncore, mode, 1036 MODE_IDLE, MODE_IDLE, 1037 fast_timeout_us, 1038 slow_timeout_ms, 1039 NULL); 1040 1041 /* A final mmio read to let GPU writes be hopefully flushed to memory */ 1042 intel_uncore_posting_read_fw(uncore, mode); 1043 return err; 1044 } 1045 1046 int intel_engine_stop_cs(struct intel_engine_cs *engine) 1047 { 1048 int err = 0; 1049 1050 if (INTEL_GEN(engine->i915) < 3) 1051 return -ENODEV; 1052 1053 ENGINE_TRACE(engine, "\n"); 1054 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { 1055 ENGINE_TRACE(engine, 1056 "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n", 1057 ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR, 1058 ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR); 1059 1060 /* 1061 * Sometimes we observe that the idle flag is not 1062 * set even though the ring is empty. So double 1063 * check before giving up. 1064 */ 1065 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) != 1066 (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR)) 1067 err = -ETIMEDOUT; 1068 } 1069 1070 return err; 1071 } 1072 1073 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) 1074 { 1075 ENGINE_TRACE(engine, "\n"); 1076 1077 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); 1078 } 1079 1080 const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 1081 { 1082 switch (type) { 1083 case I915_CACHE_NONE: return " uncached"; 1084 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 1085 case I915_CACHE_L3_LLC: return " L3+LLC"; 1086 case I915_CACHE_WT: return " WT"; 1087 default: return ""; 1088 } 1089 } 1090 1091 static u32 1092 read_subslice_reg(const struct intel_engine_cs *engine, 1093 int slice, int subslice, i915_reg_t reg) 1094 { 1095 struct drm_i915_private *i915 = engine->i915; 1096 struct intel_uncore *uncore = engine->uncore; 1097 u32 mcr_mask, mcr_ss, mcr, old_mcr, val; 1098 enum forcewake_domains fw_domains; 1099 1100 if (INTEL_GEN(i915) >= 11) { 1101 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1102 mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1103 } else { 1104 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1105 mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1106 } 1107 1108 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, 1109 FW_REG_READ); 1110 fw_domains |= intel_uncore_forcewake_for_reg(uncore, 1111 GEN8_MCR_SELECTOR, 1112 FW_REG_READ | FW_REG_WRITE); 1113 1114 spin_lock_irq(&uncore->lock); 1115 intel_uncore_forcewake_get__locked(uncore, fw_domains); 1116 1117 old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); 1118 1119 mcr &= ~mcr_mask; 1120 mcr |= mcr_ss; 1121 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); 1122 1123 val = intel_uncore_read_fw(uncore, reg); 1124 1125 mcr &= ~mcr_mask; 1126 mcr |= old_mcr & mcr_mask; 1127 1128 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); 1129 1130 intel_uncore_forcewake_put__locked(uncore, fw_domains); 1131 spin_unlock_irq(&uncore->lock); 1132 1133 return val; 1134 } 1135 1136 /* NB: please notice the memset */ 1137 void intel_engine_get_instdone(const struct intel_engine_cs *engine, 1138 struct intel_instdone *instdone) 1139 { 1140 struct drm_i915_private *i915 = engine->i915; 1141 const struct sseu_dev_info *sseu = &engine->gt->info.sseu; 1142 struct intel_uncore *uncore = engine->uncore; 1143 u32 mmio_base = engine->mmio_base; 1144 int slice; 1145 int subslice; 1146 1147 memset(instdone, 0, sizeof(*instdone)); 1148 1149 switch (INTEL_GEN(i915)) { 1150 default: 1151 instdone->instdone = 1152 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1153 1154 if (engine->id != RCS0) 1155 break; 1156 1157 instdone->slice_common = 1158 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1159 if (INTEL_GEN(i915) >= 12) { 1160 instdone->slice_common_extra[0] = 1161 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA); 1162 instdone->slice_common_extra[1] = 1163 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2); 1164 } 1165 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) { 1166 instdone->sampler[slice][subslice] = 1167 read_subslice_reg(engine, slice, subslice, 1168 GEN7_SAMPLER_INSTDONE); 1169 instdone->row[slice][subslice] = 1170 read_subslice_reg(engine, slice, subslice, 1171 GEN7_ROW_INSTDONE); 1172 } 1173 break; 1174 case 7: 1175 instdone->instdone = 1176 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1177 1178 if (engine->id != RCS0) 1179 break; 1180 1181 instdone->slice_common = 1182 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1183 instdone->sampler[0][0] = 1184 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE); 1185 instdone->row[0][0] = 1186 intel_uncore_read(uncore, GEN7_ROW_INSTDONE); 1187 1188 break; 1189 case 6: 1190 case 5: 1191 case 4: 1192 instdone->instdone = 1193 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1194 if (engine->id == RCS0) 1195 /* HACK: Using the wrong struct member */ 1196 instdone->slice_common = 1197 intel_uncore_read(uncore, GEN4_INSTDONE1); 1198 break; 1199 case 3: 1200 case 2: 1201 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE); 1202 break; 1203 } 1204 } 1205 1206 static bool ring_is_idle(struct intel_engine_cs *engine) 1207 { 1208 bool idle = true; 1209 1210 if (I915_SELFTEST_ONLY(!engine->mmio_base)) 1211 return true; 1212 1213 if (!intel_engine_pm_get_if_awake(engine)) 1214 return true; 1215 1216 /* First check that no commands are left in the ring */ 1217 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) != 1218 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR)) 1219 idle = false; 1220 1221 /* No bit for gen2, so assume the CS parser is idle */ 1222 if (INTEL_GEN(engine->i915) > 2 && 1223 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE)) 1224 idle = false; 1225 1226 intel_engine_pm_put(engine); 1227 1228 return idle; 1229 } 1230 1231 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync) 1232 { 1233 struct tasklet_struct *t = &engine->execlists.tasklet; 1234 1235 if (!t->callback) 1236 return; 1237 1238 local_bh_disable(); 1239 if (tasklet_trylock(t)) { 1240 /* Must wait for any GPU reset in progress. */ 1241 if (__tasklet_is_enabled(t)) 1242 t->callback(t); 1243 tasklet_unlock(t); 1244 } 1245 local_bh_enable(); 1246 1247 /* Synchronise and wait for the tasklet on another CPU */ 1248 if (sync) 1249 tasklet_unlock_wait(t); 1250 } 1251 1252 /** 1253 * intel_engine_is_idle() - Report if the engine has finished process all work 1254 * @engine: the intel_engine_cs 1255 * 1256 * Return true if there are no requests pending, nothing left to be submitted 1257 * to hardware, and that the engine is idle. 1258 */ 1259 bool intel_engine_is_idle(struct intel_engine_cs *engine) 1260 { 1261 /* More white lies, if wedged, hw state is inconsistent */ 1262 if (intel_gt_is_wedged(engine->gt)) 1263 return true; 1264 1265 if (!intel_engine_pm_is_awake(engine)) 1266 return true; 1267 1268 /* Waiting to drain ELSP? */ 1269 synchronize_hardirq(to_pci_dev(engine->i915->drm.dev)->irq); 1270 intel_engine_flush_submission(engine); 1271 1272 /* ELSP is empty, but there are ready requests? E.g. after reset */ 1273 if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)) 1274 return false; 1275 1276 /* Ring stopped? */ 1277 return ring_is_idle(engine); 1278 } 1279 1280 bool intel_engines_are_idle(struct intel_gt *gt) 1281 { 1282 struct intel_engine_cs *engine; 1283 enum intel_engine_id id; 1284 1285 /* 1286 * If the driver is wedged, HW state may be very inconsistent and 1287 * report that it is still busy, even though we have stopped using it. 1288 */ 1289 if (intel_gt_is_wedged(gt)) 1290 return true; 1291 1292 /* Already parked (and passed an idleness test); must still be idle */ 1293 if (!READ_ONCE(gt->awake)) 1294 return true; 1295 1296 for_each_engine(engine, gt, id) { 1297 if (!intel_engine_is_idle(engine)) 1298 return false; 1299 } 1300 1301 return true; 1302 } 1303 1304 void intel_engines_reset_default_submission(struct intel_gt *gt) 1305 { 1306 struct intel_engine_cs *engine; 1307 enum intel_engine_id id; 1308 1309 for_each_engine(engine, gt, id) { 1310 if (engine->sanitize) 1311 engine->sanitize(engine); 1312 1313 engine->set_default_submission(engine); 1314 } 1315 } 1316 1317 bool intel_engine_can_store_dword(struct intel_engine_cs *engine) 1318 { 1319 switch (INTEL_GEN(engine->i915)) { 1320 case 2: 1321 return false; /* uses physical not virtual addresses */ 1322 case 3: 1323 /* maybe only uses physical not virtual addresses */ 1324 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); 1325 case 4: 1326 return !IS_I965G(engine->i915); /* who knows! */ 1327 case 6: 1328 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ 1329 default: 1330 return true; 1331 } 1332 } 1333 1334 static struct intel_timeline *get_timeline(struct i915_request *rq) 1335 { 1336 struct intel_timeline *tl; 1337 1338 /* 1339 * Even though we are holding the engine->active.lock here, there 1340 * is no control over the submission queue per-se and we are 1341 * inspecting the active state at a random point in time, with an 1342 * unknown queue. Play safe and make sure the timeline remains valid. 1343 * (Only being used for pretty printing, one extra kref shouldn't 1344 * cause a camel stampede!) 1345 */ 1346 rcu_read_lock(); 1347 tl = rcu_dereference(rq->timeline); 1348 if (!kref_get_unless_zero(&tl->kref)) 1349 tl = NULL; 1350 rcu_read_unlock(); 1351 1352 return tl; 1353 } 1354 1355 static int print_ring(char *buf, int sz, struct i915_request *rq) 1356 { 1357 int len = 0; 1358 1359 if (!i915_request_signaled(rq)) { 1360 struct intel_timeline *tl = get_timeline(rq); 1361 1362 len = scnprintf(buf, sz, 1363 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ", 1364 i915_ggtt_offset(rq->ring->vma), 1365 tl ? tl->hwsp_offset : 0, 1366 hwsp_seqno(rq), 1367 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context), 1368 1000 * 1000)); 1369 1370 if (tl) 1371 intel_timeline_put(tl); 1372 } 1373 1374 return len; 1375 } 1376 1377 static void hexdump(struct drm_printer *m, const void *buf, size_t len) 1378 { 1379 const size_t rowsize = 8 * sizeof(u32); 1380 const void *prev = NULL; 1381 bool skip = false; 1382 size_t pos; 1383 1384 for (pos = 0; pos < len; pos += rowsize) { 1385 char line[128]; 1386 1387 if (prev && !memcmp(prev, buf + pos, rowsize)) { 1388 if (!skip) { 1389 drm_printf(m, "*\n"); 1390 skip = true; 1391 } 1392 continue; 1393 } 1394 1395 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos, 1396 rowsize, sizeof(u32), 1397 line, sizeof(line), 1398 false) >= sizeof(line)); 1399 drm_printf(m, "[%04zx] %s\n", pos, line); 1400 1401 prev = buf + pos; 1402 skip = false; 1403 } 1404 } 1405 1406 static const char *repr_timer(const struct timer_list *t) 1407 { 1408 if (!READ_ONCE(t->expires)) 1409 return "inactive"; 1410 1411 if (timer_pending(t)) 1412 return "active"; 1413 1414 return "expired"; 1415 } 1416 1417 static void intel_engine_print_registers(struct intel_engine_cs *engine, 1418 struct drm_printer *m) 1419 { 1420 struct drm_i915_private *dev_priv = engine->i915; 1421 struct intel_engine_execlists * const execlists = &engine->execlists; 1422 u64 addr; 1423 1424 if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7)) 1425 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID)); 1426 if (HAS_EXECLISTS(dev_priv)) { 1427 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n", 1428 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI)); 1429 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n", 1430 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO)); 1431 } 1432 drm_printf(m, "\tRING_START: 0x%08x\n", 1433 ENGINE_READ(engine, RING_START)); 1434 drm_printf(m, "\tRING_HEAD: 0x%08x\n", 1435 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR); 1436 drm_printf(m, "\tRING_TAIL: 0x%08x\n", 1437 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR); 1438 drm_printf(m, "\tRING_CTL: 0x%08x%s\n", 1439 ENGINE_READ(engine, RING_CTL), 1440 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : ""); 1441 if (INTEL_GEN(engine->i915) > 2) { 1442 drm_printf(m, "\tRING_MODE: 0x%08x%s\n", 1443 ENGINE_READ(engine, RING_MI_MODE), 1444 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : ""); 1445 } 1446 1447 if (INTEL_GEN(dev_priv) >= 6) { 1448 drm_printf(m, "\tRING_IMR: 0x%08x\n", 1449 ENGINE_READ(engine, RING_IMR)); 1450 drm_printf(m, "\tRING_ESR: 0x%08x\n", 1451 ENGINE_READ(engine, RING_ESR)); 1452 drm_printf(m, "\tRING_EMR: 0x%08x\n", 1453 ENGINE_READ(engine, RING_EMR)); 1454 drm_printf(m, "\tRING_EIR: 0x%08x\n", 1455 ENGINE_READ(engine, RING_EIR)); 1456 } 1457 1458 addr = intel_engine_get_active_head(engine); 1459 drm_printf(m, "\tACTHD: 0x%08x_%08x\n", 1460 upper_32_bits(addr), lower_32_bits(addr)); 1461 addr = intel_engine_get_last_batch_head(engine); 1462 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n", 1463 upper_32_bits(addr), lower_32_bits(addr)); 1464 if (INTEL_GEN(dev_priv) >= 8) 1465 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW); 1466 else if (INTEL_GEN(dev_priv) >= 4) 1467 addr = ENGINE_READ(engine, RING_DMA_FADD); 1468 else 1469 addr = ENGINE_READ(engine, DMA_FADD_I8XX); 1470 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n", 1471 upper_32_bits(addr), lower_32_bits(addr)); 1472 if (INTEL_GEN(dev_priv) >= 4) { 1473 drm_printf(m, "\tIPEIR: 0x%08x\n", 1474 ENGINE_READ(engine, RING_IPEIR)); 1475 drm_printf(m, "\tIPEHR: 0x%08x\n", 1476 ENGINE_READ(engine, RING_IPEHR)); 1477 } else { 1478 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR)); 1479 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR)); 1480 } 1481 1482 if (intel_engine_in_guc_submission_mode(engine)) { 1483 /* nothing to print yet */ 1484 } else if (HAS_EXECLISTS(dev_priv)) { 1485 struct i915_request * const *port, *rq; 1486 const u32 *hws = 1487 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; 1488 const u8 num_entries = execlists->csb_size; 1489 unsigned int idx; 1490 u8 read, write; 1491 1492 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n", 1493 yesno(test_bit(TASKLET_STATE_SCHED, 1494 &engine->execlists.tasklet.state)), 1495 enableddisabled(!atomic_read(&engine->execlists.tasklet.count)), 1496 repr_timer(&engine->execlists.preempt), 1497 repr_timer(&engine->execlists.timer)); 1498 1499 read = execlists->csb_head; 1500 write = READ_ONCE(*execlists->csb_write); 1501 1502 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n", 1503 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO), 1504 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI), 1505 read, write, num_entries); 1506 1507 if (read >= num_entries) 1508 read = 0; 1509 if (write >= num_entries) 1510 write = 0; 1511 if (read > write) 1512 write += num_entries; 1513 while (read < write) { 1514 idx = ++read % num_entries; 1515 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", 1516 idx, hws[idx * 2], hws[idx * 2 + 1]); 1517 } 1518 1519 execlists_active_lock_bh(execlists); 1520 rcu_read_lock(); 1521 for (port = execlists->active; (rq = *port); port++) { 1522 char hdr[160]; 1523 int len; 1524 1525 len = scnprintf(hdr, sizeof(hdr), 1526 "\t\tActive[%d]: ccid:%08x%s%s, ", 1527 (int)(port - execlists->active), 1528 rq->context->lrc.ccid, 1529 intel_context_is_closed(rq->context) ? "!" : "", 1530 intel_context_is_banned(rq->context) ? "*" : ""); 1531 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1532 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1533 i915_request_show(m, rq, hdr, 0); 1534 } 1535 for (port = execlists->pending; (rq = *port); port++) { 1536 char hdr[160]; 1537 int len; 1538 1539 len = scnprintf(hdr, sizeof(hdr), 1540 "\t\tPending[%d]: ccid:%08x%s%s, ", 1541 (int)(port - execlists->pending), 1542 rq->context->lrc.ccid, 1543 intel_context_is_closed(rq->context) ? "!" : "", 1544 intel_context_is_banned(rq->context) ? "*" : ""); 1545 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1546 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1547 i915_request_show(m, rq, hdr, 0); 1548 } 1549 rcu_read_unlock(); 1550 execlists_active_unlock_bh(execlists); 1551 } else if (INTEL_GEN(dev_priv) > 6) { 1552 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n", 1553 ENGINE_READ(engine, RING_PP_DIR_BASE)); 1554 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", 1555 ENGINE_READ(engine, RING_PP_DIR_BASE_READ)); 1556 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", 1557 ENGINE_READ(engine, RING_PP_DIR_DCLV)); 1558 } 1559 } 1560 1561 static void print_request_ring(struct drm_printer *m, struct i915_request *rq) 1562 { 1563 void *ring; 1564 int size; 1565 1566 drm_printf(m, 1567 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n", 1568 rq->head, rq->postfix, rq->tail, 1569 rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, 1570 rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); 1571 1572 size = rq->tail - rq->head; 1573 if (rq->tail < rq->head) 1574 size += rq->ring->size; 1575 1576 ring = kmalloc(size, GFP_ATOMIC); 1577 if (ring) { 1578 const void *vaddr = rq->ring->vaddr; 1579 unsigned int head = rq->head; 1580 unsigned int len = 0; 1581 1582 if (rq->tail < head) { 1583 len = rq->ring->size - head; 1584 memcpy(ring, vaddr + head, len); 1585 head = 0; 1586 } 1587 memcpy(ring + len, vaddr + head, size - len); 1588 1589 hexdump(m, ring, size); 1590 kfree(ring); 1591 } 1592 } 1593 1594 static unsigned long list_count(struct list_head *list) 1595 { 1596 struct list_head *pos; 1597 unsigned long count = 0; 1598 1599 list_for_each(pos, list) 1600 count++; 1601 1602 return count; 1603 } 1604 1605 static unsigned long read_ul(void *p, size_t x) 1606 { 1607 return *(unsigned long *)(p + x); 1608 } 1609 1610 static void print_properties(struct intel_engine_cs *engine, 1611 struct drm_printer *m) 1612 { 1613 static const struct pmap { 1614 size_t offset; 1615 const char *name; 1616 } props[] = { 1617 #define P(x) { \ 1618 .offset = offsetof(typeof(engine->props), x), \ 1619 .name = #x \ 1620 } 1621 P(heartbeat_interval_ms), 1622 P(max_busywait_duration_ns), 1623 P(preempt_timeout_ms), 1624 P(stop_timeout_ms), 1625 P(timeslice_duration_ms), 1626 1627 {}, 1628 #undef P 1629 }; 1630 const struct pmap *p; 1631 1632 drm_printf(m, "\tProperties:\n"); 1633 for (p = props; p->name; p++) 1634 drm_printf(m, "\t\t%s: %lu [default %lu]\n", 1635 p->name, 1636 read_ul(&engine->props, p->offset), 1637 read_ul(&engine->defaults, p->offset)); 1638 } 1639 1640 void intel_engine_dump(struct intel_engine_cs *engine, 1641 struct drm_printer *m, 1642 const char *header, ...) 1643 { 1644 struct i915_gpu_error * const error = &engine->i915->gpu_error; 1645 struct i915_request *rq; 1646 intel_wakeref_t wakeref; 1647 unsigned long flags; 1648 ktime_t dummy; 1649 1650 if (header) { 1651 va_list ap; 1652 1653 va_start(ap, header); 1654 drm_vprintf(m, header, &ap); 1655 va_end(ap); 1656 } 1657 1658 if (intel_gt_is_wedged(engine->gt)) 1659 drm_printf(m, "*** WEDGED ***\n"); 1660 1661 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count)); 1662 drm_printf(m, "\tBarriers?: %s\n", 1663 yesno(!llist_empty(&engine->barrier_tasks))); 1664 drm_printf(m, "\tLatency: %luus\n", 1665 ewma__engine_latency_read(&engine->latency)); 1666 if (intel_engine_supports_stats(engine)) 1667 drm_printf(m, "\tRuntime: %llums\n", 1668 ktime_to_ms(intel_engine_get_busy_time(engine, 1669 &dummy))); 1670 drm_printf(m, "\tForcewake: %x domains, %d active\n", 1671 engine->fw_domain, READ_ONCE(engine->fw_active)); 1672 1673 rcu_read_lock(); 1674 rq = READ_ONCE(engine->heartbeat.systole); 1675 if (rq) 1676 drm_printf(m, "\tHeartbeat: %d ms ago\n", 1677 jiffies_to_msecs(jiffies - rq->emitted_jiffies)); 1678 rcu_read_unlock(); 1679 drm_printf(m, "\tReset count: %d (global %d)\n", 1680 i915_reset_engine_count(error, engine), 1681 i915_reset_count(error)); 1682 print_properties(engine, m); 1683 1684 drm_printf(m, "\tRequests:\n"); 1685 1686 spin_lock_irqsave(&engine->active.lock, flags); 1687 rq = intel_engine_find_active_request(engine); 1688 if (rq) { 1689 struct intel_timeline *tl = get_timeline(rq); 1690 1691 i915_request_show(m, rq, "\t\tactive ", 0); 1692 1693 drm_printf(m, "\t\tring->start: 0x%08x\n", 1694 i915_ggtt_offset(rq->ring->vma)); 1695 drm_printf(m, "\t\tring->head: 0x%08x\n", 1696 rq->ring->head); 1697 drm_printf(m, "\t\tring->tail: 0x%08x\n", 1698 rq->ring->tail); 1699 drm_printf(m, "\t\tring->emit: 0x%08x\n", 1700 rq->ring->emit); 1701 drm_printf(m, "\t\tring->space: 0x%08x\n", 1702 rq->ring->space); 1703 1704 if (tl) { 1705 drm_printf(m, "\t\tring->hwsp: 0x%08x\n", 1706 tl->hwsp_offset); 1707 intel_timeline_put(tl); 1708 } 1709 1710 print_request_ring(m, rq); 1711 1712 if (rq->context->lrc_reg_state) { 1713 drm_printf(m, "Logical Ring Context:\n"); 1714 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE); 1715 } 1716 } 1717 drm_printf(m, "\tOn hold?: %lu\n", list_count(&engine->active.hold)); 1718 spin_unlock_irqrestore(&engine->active.lock, flags); 1719 1720 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base); 1721 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm); 1722 if (wakeref) { 1723 intel_engine_print_registers(engine, m); 1724 intel_runtime_pm_put(engine->uncore->rpm, wakeref); 1725 } else { 1726 drm_printf(m, "\tDevice is asleep; skipping register dump\n"); 1727 } 1728 1729 intel_execlists_show_requests(engine, m, i915_request_show, 8); 1730 1731 drm_printf(m, "HWSP:\n"); 1732 hexdump(m, engine->status_page.addr, PAGE_SIZE); 1733 1734 drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine))); 1735 1736 intel_engine_print_breadcrumbs(engine, m); 1737 } 1738 1739 static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine, 1740 ktime_t *now) 1741 { 1742 ktime_t total = engine->stats.total; 1743 1744 /* 1745 * If the engine is executing something at the moment 1746 * add it to the total. 1747 */ 1748 *now = ktime_get(); 1749 if (READ_ONCE(engine->stats.active)) 1750 total = ktime_add(total, ktime_sub(*now, engine->stats.start)); 1751 1752 return total; 1753 } 1754 1755 /** 1756 * intel_engine_get_busy_time() - Return current accumulated engine busyness 1757 * @engine: engine to report on 1758 * @now: monotonic timestamp of sampling 1759 * 1760 * Returns accumulated time @engine was busy since engine stats were enabled. 1761 */ 1762 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) 1763 { 1764 unsigned int seq; 1765 ktime_t total; 1766 1767 do { 1768 seq = read_seqcount_begin(&engine->stats.lock); 1769 total = __intel_engine_get_busy_time(engine, now); 1770 } while (read_seqcount_retry(&engine->stats.lock, seq)); 1771 1772 return total; 1773 } 1774 1775 static bool match_ring(struct i915_request *rq) 1776 { 1777 u32 ring = ENGINE_READ(rq->engine, RING_START); 1778 1779 return ring == i915_ggtt_offset(rq->ring->vma); 1780 } 1781 1782 struct i915_request * 1783 intel_engine_find_active_request(struct intel_engine_cs *engine) 1784 { 1785 struct i915_request *request, *active = NULL; 1786 1787 /* 1788 * We are called by the error capture, reset and to dump engine 1789 * state at random points in time. In particular, note that neither is 1790 * crucially ordered with an interrupt. After a hang, the GPU is dead 1791 * and we assume that no more writes can happen (we waited long enough 1792 * for all writes that were in transaction to be flushed) - adding an 1793 * extra delay for a recent interrupt is pointless. Hence, we do 1794 * not need an engine->irq_seqno_barrier() before the seqno reads. 1795 * At all other times, we must assume the GPU is still running, but 1796 * we only care about the snapshot of this moment. 1797 */ 1798 lockdep_assert_held(&engine->active.lock); 1799 1800 rcu_read_lock(); 1801 request = execlists_active(&engine->execlists); 1802 if (request) { 1803 struct intel_timeline *tl = request->context->timeline; 1804 1805 list_for_each_entry_from_reverse(request, &tl->requests, link) { 1806 if (__i915_request_is_complete(request)) 1807 break; 1808 1809 active = request; 1810 } 1811 } 1812 rcu_read_unlock(); 1813 if (active) 1814 return active; 1815 1816 list_for_each_entry(request, &engine->active.requests, sched.link) { 1817 if (__i915_request_is_complete(request)) 1818 continue; 1819 1820 if (!__i915_request_has_started(request)) 1821 continue; 1822 1823 /* More than one preemptible request may match! */ 1824 if (!match_ring(request)) 1825 continue; 1826 1827 active = request; 1828 break; 1829 } 1830 1831 return active; 1832 } 1833 1834 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 1835 #include "mock_engine.c" 1836 #include "selftest_engine.c" 1837 #include "selftest_engine_cs.c" 1838 #endif 1839