1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2016 Intel Corporation 4 */ 5 6 #include <drm/drm_print.h> 7 8 #include "gem/i915_gem_context.h" 9 10 #include "i915_drv.h" 11 12 #include "intel_breadcrumbs.h" 13 #include "intel_context.h" 14 #include "intel_engine.h" 15 #include "intel_engine_pm.h" 16 #include "intel_engine_user.h" 17 #include "intel_execlists_submission.h" 18 #include "intel_gt.h" 19 #include "intel_gt_requests.h" 20 #include "intel_gt_pm.h" 21 #include "intel_lrc_reg.h" 22 #include "intel_reset.h" 23 #include "intel_ring.h" 24 #include "uc/intel_guc_submission.h" 25 26 /* Haswell does have the CXT_SIZE register however it does not appear to be 27 * valid. Now, docs explain in dwords what is in the context object. The full 28 * size is 70720 bytes, however, the power context and execlist context will 29 * never be saved (power context is stored elsewhere, and execlists don't work 30 * on HSW) - so the final size, including the extra state required for the 31 * Resource Streamer, is 66944 bytes, which rounds to 17 pages. 32 */ 33 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 34 35 #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 36 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) 37 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 38 #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE) 39 40 #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE) 41 42 #define MAX_MMIO_BASES 3 43 struct engine_info { 44 u8 class; 45 u8 instance; 46 /* mmio bases table *must* be sorted in reverse graphics_ver order */ 47 struct engine_mmio_base { 48 u32 graphics_ver : 8; 49 u32 base : 24; 50 } mmio_bases[MAX_MMIO_BASES]; 51 }; 52 53 static const struct engine_info intel_engines[] = { 54 [RCS0] = { 55 .class = RENDER_CLASS, 56 .instance = 0, 57 .mmio_bases = { 58 { .graphics_ver = 1, .base = RENDER_RING_BASE } 59 }, 60 }, 61 [BCS0] = { 62 .class = COPY_ENGINE_CLASS, 63 .instance = 0, 64 .mmio_bases = { 65 { .graphics_ver = 6, .base = BLT_RING_BASE } 66 }, 67 }, 68 [VCS0] = { 69 .class = VIDEO_DECODE_CLASS, 70 .instance = 0, 71 .mmio_bases = { 72 { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE }, 73 { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE }, 74 { .graphics_ver = 4, .base = BSD_RING_BASE } 75 }, 76 }, 77 [VCS1] = { 78 .class = VIDEO_DECODE_CLASS, 79 .instance = 1, 80 .mmio_bases = { 81 { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE }, 82 { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE } 83 }, 84 }, 85 [VCS2] = { 86 .class = VIDEO_DECODE_CLASS, 87 .instance = 2, 88 .mmio_bases = { 89 { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE } 90 }, 91 }, 92 [VCS3] = { 93 .class = VIDEO_DECODE_CLASS, 94 .instance = 3, 95 .mmio_bases = { 96 { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE } 97 }, 98 }, 99 [VCS4] = { 100 .class = VIDEO_DECODE_CLASS, 101 .instance = 4, 102 .mmio_bases = { 103 { .graphics_ver = 12, .base = XEHP_BSD5_RING_BASE } 104 }, 105 }, 106 [VCS5] = { 107 .class = VIDEO_DECODE_CLASS, 108 .instance = 5, 109 .mmio_bases = { 110 { .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE } 111 }, 112 }, 113 [VCS6] = { 114 .class = VIDEO_DECODE_CLASS, 115 .instance = 6, 116 .mmio_bases = { 117 { .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE } 118 }, 119 }, 120 [VCS7] = { 121 .class = VIDEO_DECODE_CLASS, 122 .instance = 7, 123 .mmio_bases = { 124 { .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE } 125 }, 126 }, 127 [VECS0] = { 128 .class = VIDEO_ENHANCEMENT_CLASS, 129 .instance = 0, 130 .mmio_bases = { 131 { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE }, 132 { .graphics_ver = 7, .base = VEBOX_RING_BASE } 133 }, 134 }, 135 [VECS1] = { 136 .class = VIDEO_ENHANCEMENT_CLASS, 137 .instance = 1, 138 .mmio_bases = { 139 { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE } 140 }, 141 }, 142 [VECS2] = { 143 .class = VIDEO_ENHANCEMENT_CLASS, 144 .instance = 2, 145 .mmio_bases = { 146 { .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE } 147 }, 148 }, 149 [VECS3] = { 150 .class = VIDEO_ENHANCEMENT_CLASS, 151 .instance = 3, 152 .mmio_bases = { 153 { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE } 154 }, 155 }, 156 }; 157 158 /** 159 * intel_engine_context_size() - return the size of the context for an engine 160 * @gt: the gt 161 * @class: engine class 162 * 163 * Each engine class may require a different amount of space for a context 164 * image. 165 * 166 * Return: size (in bytes) of an engine class specific context image 167 * 168 * Note: this size includes the HWSP, which is part of the context image 169 * in LRC mode, but does not include the "shared data page" used with 170 * GuC submission. The caller should account for this if using the GuC. 171 */ 172 u32 intel_engine_context_size(struct intel_gt *gt, u8 class) 173 { 174 struct intel_uncore *uncore = gt->uncore; 175 u32 cxt_size; 176 177 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE); 178 179 switch (class) { 180 case RENDER_CLASS: 181 switch (GRAPHICS_VER(gt->i915)) { 182 default: 183 MISSING_CASE(GRAPHICS_VER(gt->i915)); 184 return DEFAULT_LR_CONTEXT_RENDER_SIZE; 185 case 12: 186 case 11: 187 return GEN11_LR_CONTEXT_RENDER_SIZE; 188 case 9: 189 return GEN9_LR_CONTEXT_RENDER_SIZE; 190 case 8: 191 return GEN8_LR_CONTEXT_RENDER_SIZE; 192 case 7: 193 if (IS_HASWELL(gt->i915)) 194 return HSW_CXT_TOTAL_SIZE; 195 196 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE); 197 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64, 198 PAGE_SIZE); 199 case 6: 200 cxt_size = intel_uncore_read(uncore, CXT_SIZE); 201 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64, 202 PAGE_SIZE); 203 case 5: 204 case 4: 205 /* 206 * There is a discrepancy here between the size reported 207 * by the register and the size of the context layout 208 * in the docs. Both are described as authorative! 209 * 210 * The discrepancy is on the order of a few cachelines, 211 * but the total is under one page (4k), which is our 212 * minimum allocation anyway so it should all come 213 * out in the wash. 214 */ 215 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1; 216 drm_dbg(>->i915->drm, 217 "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n", 218 GRAPHICS_VER(gt->i915), cxt_size * 64, 219 cxt_size - 1); 220 return round_up(cxt_size * 64, PAGE_SIZE); 221 case 3: 222 case 2: 223 /* For the special day when i810 gets merged. */ 224 case 1: 225 return 0; 226 } 227 break; 228 default: 229 MISSING_CASE(class); 230 fallthrough; 231 case VIDEO_DECODE_CLASS: 232 case VIDEO_ENHANCEMENT_CLASS: 233 case COPY_ENGINE_CLASS: 234 if (GRAPHICS_VER(gt->i915) < 8) 235 return 0; 236 return GEN8_LR_CONTEXT_OTHER_SIZE; 237 } 238 } 239 240 static u32 __engine_mmio_base(struct drm_i915_private *i915, 241 const struct engine_mmio_base *bases) 242 { 243 int i; 244 245 for (i = 0; i < MAX_MMIO_BASES; i++) 246 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver) 247 break; 248 249 GEM_BUG_ON(i == MAX_MMIO_BASES); 250 GEM_BUG_ON(!bases[i].base); 251 252 return bases[i].base; 253 } 254 255 static void __sprint_engine_name(struct intel_engine_cs *engine) 256 { 257 /* 258 * Before we know what the uABI name for this engine will be, 259 * we still would like to keep track of this engine in the debug logs. 260 * We throw in a ' here as a reminder that this isn't its final name. 261 */ 262 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u", 263 intel_engine_class_repr(engine->class), 264 engine->instance) >= sizeof(engine->name)); 265 } 266 267 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask) 268 { 269 /* 270 * Though they added more rings on g4x/ilk, they did not add 271 * per-engine HWSTAM until gen6. 272 */ 273 if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS) 274 return; 275 276 if (GRAPHICS_VER(engine->i915) >= 3) 277 ENGINE_WRITE(engine, RING_HWSTAM, mask); 278 else 279 ENGINE_WRITE16(engine, RING_HWSTAM, mask); 280 } 281 282 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine) 283 { 284 /* Mask off all writes into the unknown HWSP */ 285 intel_engine_set_hwsp_writemask(engine, ~0u); 286 } 287 288 static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir) 289 { 290 GEM_DEBUG_WARN_ON(iir); 291 } 292 293 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, 294 u8 logical_instance) 295 { 296 const struct engine_info *info = &intel_engines[id]; 297 struct drm_i915_private *i915 = gt->i915; 298 struct intel_engine_cs *engine; 299 u8 guc_class; 300 301 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH)); 302 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH)); 303 BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1)); 304 BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1)); 305 306 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine))) 307 return -EINVAL; 308 309 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS)) 310 return -EINVAL; 311 312 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE)) 313 return -EINVAL; 314 315 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance])) 316 return -EINVAL; 317 318 engine = kzalloc(sizeof(*engine), GFP_KERNEL); 319 if (!engine) 320 return -ENOMEM; 321 322 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES); 323 324 INIT_LIST_HEAD(&engine->pinned_contexts_list); 325 engine->id = id; 326 engine->legacy_idx = INVALID_ENGINE; 327 engine->mask = BIT(id); 328 if (GRAPHICS_VER(gt->i915) >= 11) { 329 static const u32 engine_reset_domains[] = { 330 [RCS0] = GEN11_GRDOM_RENDER, 331 [BCS0] = GEN11_GRDOM_BLT, 332 [VCS0] = GEN11_GRDOM_MEDIA, 333 [VCS1] = GEN11_GRDOM_MEDIA2, 334 [VCS2] = GEN11_GRDOM_MEDIA3, 335 [VCS3] = GEN11_GRDOM_MEDIA4, 336 [VCS4] = GEN11_GRDOM_MEDIA5, 337 [VCS5] = GEN11_GRDOM_MEDIA6, 338 [VCS6] = GEN11_GRDOM_MEDIA7, 339 [VCS7] = GEN11_GRDOM_MEDIA8, 340 [VECS0] = GEN11_GRDOM_VECS, 341 [VECS1] = GEN11_GRDOM_VECS2, 342 [VECS2] = GEN11_GRDOM_VECS3, 343 [VECS3] = GEN11_GRDOM_VECS4, 344 }; 345 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || 346 !engine_reset_domains[id]); 347 engine->reset_domain = engine_reset_domains[id]; 348 } else { 349 static const u32 engine_reset_domains[] = { 350 [RCS0] = GEN6_GRDOM_RENDER, 351 [BCS0] = GEN6_GRDOM_BLT, 352 [VCS0] = GEN6_GRDOM_MEDIA, 353 [VCS1] = GEN8_GRDOM_MEDIA2, 354 [VECS0] = GEN6_GRDOM_VECS, 355 }; 356 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || 357 !engine_reset_domains[id]); 358 engine->reset_domain = engine_reset_domains[id]; 359 } 360 engine->i915 = i915; 361 engine->gt = gt; 362 engine->uncore = gt->uncore; 363 guc_class = engine_class_to_guc_class(info->class); 364 engine->guc_id = MAKE_GUC_ID(guc_class, info->instance); 365 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases); 366 367 engine->irq_handler = nop_irq_handler; 368 369 engine->class = info->class; 370 engine->instance = info->instance; 371 engine->logical_mask = BIT(logical_instance); 372 __sprint_engine_name(engine); 373 374 engine->props.heartbeat_interval_ms = 375 CONFIG_DRM_I915_HEARTBEAT_INTERVAL; 376 engine->props.max_busywait_duration_ns = 377 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT; 378 engine->props.preempt_timeout_ms = 379 CONFIG_DRM_I915_PREEMPT_TIMEOUT; 380 engine->props.stop_timeout_ms = 381 CONFIG_DRM_I915_STOP_TIMEOUT; 382 engine->props.timeslice_duration_ms = 383 CONFIG_DRM_I915_TIMESLICE_DURATION; 384 385 /* Override to uninterruptible for OpenCL workloads. */ 386 if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS) 387 engine->props.preempt_timeout_ms = 0; 388 389 engine->defaults = engine->props; /* never to change again */ 390 391 engine->context_size = intel_engine_context_size(gt, engine->class); 392 if (WARN_ON(engine->context_size > BIT(20))) 393 engine->context_size = 0; 394 if (engine->context_size) 395 DRIVER_CAPS(i915)->has_logical_contexts = true; 396 397 ewma__engine_latency_init(&engine->latency); 398 seqcount_init(&engine->stats.execlists.lock); 399 400 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); 401 402 /* Scrub mmio state on takeover */ 403 intel_engine_sanitize_mmio(engine); 404 405 gt->engine_class[info->class][info->instance] = engine; 406 gt->engine[id] = engine; 407 408 return 0; 409 } 410 411 static void __setup_engine_capabilities(struct intel_engine_cs *engine) 412 { 413 struct drm_i915_private *i915 = engine->i915; 414 415 if (engine->class == VIDEO_DECODE_CLASS) { 416 /* 417 * HEVC support is present on first engine instance 418 * before Gen11 and on all instances afterwards. 419 */ 420 if (GRAPHICS_VER(i915) >= 11 || 421 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0)) 422 engine->uabi_capabilities |= 423 I915_VIDEO_CLASS_CAPABILITY_HEVC; 424 425 /* 426 * SFC block is present only on even logical engine 427 * instances. 428 */ 429 if ((GRAPHICS_VER(i915) >= 11 && 430 (engine->gt->info.vdbox_sfc_access & 431 BIT(engine->instance))) || 432 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0)) 433 engine->uabi_capabilities |= 434 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 435 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) { 436 if (GRAPHICS_VER(i915) >= 9 && 437 engine->gt->info.sfc_mask & BIT(engine->instance)) 438 engine->uabi_capabilities |= 439 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; 440 } 441 } 442 443 static void intel_setup_engine_capabilities(struct intel_gt *gt) 444 { 445 struct intel_engine_cs *engine; 446 enum intel_engine_id id; 447 448 for_each_engine(engine, gt, id) 449 __setup_engine_capabilities(engine); 450 } 451 452 /** 453 * intel_engines_release() - free the resources allocated for Command Streamers 454 * @gt: pointer to struct intel_gt 455 */ 456 void intel_engines_release(struct intel_gt *gt) 457 { 458 struct intel_engine_cs *engine; 459 enum intel_engine_id id; 460 461 /* 462 * Before we release the resources held by engine, we must be certain 463 * that the HW is no longer accessing them -- having the GPU scribble 464 * to or read from a page being used for something else causes no end 465 * of fun. 466 * 467 * The GPU should be reset by this point, but assume the worst just 468 * in case we aborted before completely initialising the engines. 469 */ 470 GEM_BUG_ON(intel_gt_pm_is_awake(gt)); 471 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) 472 __intel_gt_reset(gt, ALL_ENGINES); 473 474 /* Decouple the backend; but keep the layout for late GPU resets */ 475 for_each_engine(engine, gt, id) { 476 if (!engine->release) 477 continue; 478 479 intel_wakeref_wait_for_idle(&engine->wakeref); 480 GEM_BUG_ON(intel_engine_pm_is_awake(engine)); 481 482 engine->release(engine); 483 engine->release = NULL; 484 485 memset(&engine->reset, 0, sizeof(engine->reset)); 486 } 487 } 488 489 void intel_engine_free_request_pool(struct intel_engine_cs *engine) 490 { 491 if (!engine->request_pool) 492 return; 493 494 kmem_cache_free(i915_request_slab_cache(), engine->request_pool); 495 } 496 497 void intel_engines_free(struct intel_gt *gt) 498 { 499 struct intel_engine_cs *engine; 500 enum intel_engine_id id; 501 502 /* Free the requests! dma-resv keeps fences around for an eternity */ 503 rcu_barrier(); 504 505 for_each_engine(engine, gt, id) { 506 intel_engine_free_request_pool(engine); 507 kfree(engine); 508 gt->engine[id] = NULL; 509 } 510 } 511 512 static 513 bool gen11_vdbox_has_sfc(struct intel_gt *gt, 514 unsigned int physical_vdbox, 515 unsigned int logical_vdbox, u16 vdbox_mask) 516 { 517 struct drm_i915_private *i915 = gt->i915; 518 519 /* 520 * In Gen11, only even numbered logical VDBOXes are hooked 521 * up to an SFC (Scaler & Format Converter) unit. 522 * In Gen12, Even numbered physical instance always are connected 523 * to an SFC. Odd numbered physical instances have SFC only if 524 * previous even instance is fused off. 525 * 526 * Starting with Xe_HP, there's also a dedicated SFC_ENABLE field 527 * in the fuse register that tells us whether a specific SFC is present. 528 */ 529 if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0) 530 return false; 531 else if (GRAPHICS_VER(i915) == 12) 532 return (physical_vdbox % 2 == 0) || 533 !(BIT(physical_vdbox - 1) & vdbox_mask); 534 else if (GRAPHICS_VER(i915) == 11) 535 return logical_vdbox % 2 == 0; 536 537 MISSING_CASE(GRAPHICS_VER(i915)); 538 return false; 539 } 540 541 /* 542 * Determine which engines are fused off in our particular hardware. 543 * Note that we have a catch-22 situation where we need to be able to access 544 * the blitter forcewake domain to read the engine fuses, but at the same time 545 * we need to know which engines are available on the system to know which 546 * forcewake domains are present. We solve this by intializing the forcewake 547 * domains based on the full engine mask in the platform capabilities before 548 * calling this function and pruning the domains for fused-off engines 549 * afterwards. 550 */ 551 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) 552 { 553 struct drm_i915_private *i915 = gt->i915; 554 struct intel_gt_info *info = >->info; 555 struct intel_uncore *uncore = gt->uncore; 556 unsigned int logical_vdbox = 0; 557 unsigned int i; 558 u32 media_fuse, fuse1; 559 u16 vdbox_mask; 560 u16 vebox_mask; 561 562 info->engine_mask = INTEL_INFO(i915)->platform_engine_mask; 563 564 if (GRAPHICS_VER(i915) < 11) 565 return info->engine_mask; 566 567 /* 568 * On newer platforms the fusing register is called 'enable' and has 569 * enable semantics, while on older platforms it is called 'disable' 570 * and bits have disable semantices. 571 */ 572 media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); 573 if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) 574 media_fuse = ~media_fuse; 575 576 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; 577 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> 578 GEN11_GT_VEBOX_DISABLE_SHIFT; 579 580 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { 581 fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1); 582 gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1); 583 } else { 584 gt->info.sfc_mask = ~0; 585 } 586 587 for (i = 0; i < I915_MAX_VCS; i++) { 588 if (!HAS_ENGINE(gt, _VCS(i))) { 589 vdbox_mask &= ~BIT(i); 590 continue; 591 } 592 593 if (!(BIT(i) & vdbox_mask)) { 594 info->engine_mask &= ~BIT(_VCS(i)); 595 drm_dbg(&i915->drm, "vcs%u fused off\n", i); 596 continue; 597 } 598 599 if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask)) 600 gt->info.vdbox_sfc_access |= BIT(i); 601 logical_vdbox++; 602 } 603 drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n", 604 vdbox_mask, VDBOX_MASK(gt)); 605 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt)); 606 607 for (i = 0; i < I915_MAX_VECS; i++) { 608 if (!HAS_ENGINE(gt, _VECS(i))) { 609 vebox_mask &= ~BIT(i); 610 continue; 611 } 612 613 if (!(BIT(i) & vebox_mask)) { 614 info->engine_mask &= ~BIT(_VECS(i)); 615 drm_dbg(&i915->drm, "vecs%u fused off\n", i); 616 } 617 } 618 drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n", 619 vebox_mask, VEBOX_MASK(gt)); 620 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); 621 622 return info->engine_mask; 623 } 624 625 static void populate_logical_ids(struct intel_gt *gt, u8 *logical_ids, 626 u8 class, const u8 *map, u8 num_instances) 627 { 628 int i, j; 629 u8 current_logical_id = 0; 630 631 for (j = 0; j < num_instances; ++j) { 632 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) { 633 if (!HAS_ENGINE(gt, i) || 634 intel_engines[i].class != class) 635 continue; 636 637 if (intel_engines[i].instance == map[j]) { 638 logical_ids[intel_engines[i].instance] = 639 current_logical_id++; 640 break; 641 } 642 } 643 } 644 } 645 646 static void setup_logical_ids(struct intel_gt *gt, u8 *logical_ids, u8 class) 647 { 648 int i; 649 u8 map[MAX_ENGINE_INSTANCE + 1]; 650 651 for (i = 0; i < MAX_ENGINE_INSTANCE + 1; ++i) 652 map[i] = i; 653 populate_logical_ids(gt, logical_ids, class, map, ARRAY_SIZE(map)); 654 } 655 656 /** 657 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers 658 * @gt: pointer to struct intel_gt 659 * 660 * Return: non-zero if the initialization failed. 661 */ 662 int intel_engines_init_mmio(struct intel_gt *gt) 663 { 664 struct drm_i915_private *i915 = gt->i915; 665 const unsigned int engine_mask = init_engine_mask(gt); 666 unsigned int mask = 0; 667 unsigned int i, class; 668 u8 logical_ids[MAX_ENGINE_INSTANCE + 1]; 669 int err; 670 671 drm_WARN_ON(&i915->drm, engine_mask == 0); 672 drm_WARN_ON(&i915->drm, engine_mask & 673 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES)); 674 675 if (i915_inject_probe_failure(i915)) 676 return -ENODEV; 677 678 for (class = 0; class < MAX_ENGINE_CLASS + 1; ++class) { 679 setup_logical_ids(gt, logical_ids, class); 680 681 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) { 682 u8 instance = intel_engines[i].instance; 683 684 if (intel_engines[i].class != class || 685 !HAS_ENGINE(gt, i)) 686 continue; 687 688 err = intel_engine_setup(gt, i, 689 logical_ids[instance]); 690 if (err) 691 goto cleanup; 692 693 mask |= BIT(i); 694 } 695 } 696 697 /* 698 * Catch failures to update intel_engines table when the new engines 699 * are added to the driver by a warning and disabling the forgotten 700 * engines. 701 */ 702 if (drm_WARN_ON(&i915->drm, mask != engine_mask)) 703 gt->info.engine_mask = mask; 704 705 gt->info.num_engines = hweight32(mask); 706 707 intel_gt_check_and_clear_faults(gt); 708 709 intel_setup_engine_capabilities(gt); 710 711 intel_uncore_prune_engine_fw_domains(gt->uncore, gt); 712 713 return 0; 714 715 cleanup: 716 intel_engines_free(gt); 717 return err; 718 } 719 720 void intel_engine_init_execlists(struct intel_engine_cs *engine) 721 { 722 struct intel_engine_execlists * const execlists = &engine->execlists; 723 724 execlists->port_mask = 1; 725 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists))); 726 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS); 727 728 memset(execlists->pending, 0, sizeof(execlists->pending)); 729 execlists->active = 730 memset(execlists->inflight, 0, sizeof(execlists->inflight)); 731 } 732 733 static void cleanup_status_page(struct intel_engine_cs *engine) 734 { 735 struct i915_vma *vma; 736 737 /* Prevent writes into HWSP after returning the page to the system */ 738 intel_engine_set_hwsp_writemask(engine, ~0u); 739 740 vma = fetch_and_zero(&engine->status_page.vma); 741 if (!vma) 742 return; 743 744 if (!HWS_NEEDS_PHYSICAL(engine->i915)) 745 i915_vma_unpin(vma); 746 747 i915_gem_object_unpin_map(vma->obj); 748 i915_gem_object_put(vma->obj); 749 } 750 751 static int pin_ggtt_status_page(struct intel_engine_cs *engine, 752 struct i915_gem_ww_ctx *ww, 753 struct i915_vma *vma) 754 { 755 unsigned int flags; 756 757 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) 758 /* 759 * On g33, we cannot place HWS above 256MiB, so 760 * restrict its pinning to the low mappable arena. 761 * Though this restriction is not documented for 762 * gen4, gen5, or byt, they also behave similarly 763 * and hang if the HWS is placed at the top of the 764 * GTT. To generalise, it appears that all !llc 765 * platforms have issues with us placing the HWS 766 * above the mappable region (even though we never 767 * actually map it). 768 */ 769 flags = PIN_MAPPABLE; 770 else 771 flags = PIN_HIGH; 772 773 return i915_ggtt_pin(vma, ww, 0, flags); 774 } 775 776 static int init_status_page(struct intel_engine_cs *engine) 777 { 778 struct drm_i915_gem_object *obj; 779 struct i915_gem_ww_ctx ww; 780 struct i915_vma *vma; 781 void *vaddr; 782 int ret; 783 784 INIT_LIST_HEAD(&engine->status_page.timelines); 785 786 /* 787 * Though the HWS register does support 36bit addresses, historically 788 * we have had hangs and corruption reported due to wild writes if 789 * the HWS is placed above 4G. We only allow objects to be allocated 790 * in GFP_DMA32 for i965, and no earlier physical address users had 791 * access to more than 4G. 792 */ 793 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); 794 if (IS_ERR(obj)) { 795 drm_err(&engine->i915->drm, 796 "Failed to allocate status page\n"); 797 return PTR_ERR(obj); 798 } 799 800 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 801 802 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); 803 if (IS_ERR(vma)) { 804 ret = PTR_ERR(vma); 805 goto err_put; 806 } 807 808 i915_gem_ww_ctx_init(&ww, true); 809 retry: 810 ret = i915_gem_object_lock(obj, &ww); 811 if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915)) 812 ret = pin_ggtt_status_page(engine, &ww, vma); 813 if (ret) 814 goto err; 815 816 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); 817 if (IS_ERR(vaddr)) { 818 ret = PTR_ERR(vaddr); 819 goto err_unpin; 820 } 821 822 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE); 823 engine->status_page.vma = vma; 824 825 err_unpin: 826 if (ret) 827 i915_vma_unpin(vma); 828 err: 829 if (ret == -EDEADLK) { 830 ret = i915_gem_ww_ctx_backoff(&ww); 831 if (!ret) 832 goto retry; 833 } 834 i915_gem_ww_ctx_fini(&ww); 835 err_put: 836 if (ret) 837 i915_gem_object_put(obj); 838 return ret; 839 } 840 841 static int engine_setup_common(struct intel_engine_cs *engine) 842 { 843 int err; 844 845 init_llist_head(&engine->barrier_tasks); 846 847 err = init_status_page(engine); 848 if (err) 849 return err; 850 851 engine->breadcrumbs = intel_breadcrumbs_create(engine); 852 if (!engine->breadcrumbs) { 853 err = -ENOMEM; 854 goto err_status; 855 } 856 857 engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL); 858 if (!engine->sched_engine) { 859 err = -ENOMEM; 860 goto err_sched_engine; 861 } 862 engine->sched_engine->private_data = engine; 863 864 err = intel_engine_init_cmd_parser(engine); 865 if (err) 866 goto err_cmd_parser; 867 868 intel_engine_init_execlists(engine); 869 intel_engine_init__pm(engine); 870 intel_engine_init_retire(engine); 871 872 /* Use the whole device by default */ 873 engine->sseu = 874 intel_sseu_from_device_info(&engine->gt->info.sseu); 875 876 intel_engine_init_workarounds(engine); 877 intel_engine_init_whitelist(engine); 878 intel_engine_init_ctx_wa(engine); 879 880 if (GRAPHICS_VER(engine->i915) >= 12) 881 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO; 882 883 return 0; 884 885 err_cmd_parser: 886 i915_sched_engine_put(engine->sched_engine); 887 err_sched_engine: 888 intel_breadcrumbs_put(engine->breadcrumbs); 889 err_status: 890 cleanup_status_page(engine); 891 return err; 892 } 893 894 struct measure_breadcrumb { 895 struct i915_request rq; 896 struct intel_ring ring; 897 u32 cs[2048]; 898 }; 899 900 static int measure_breadcrumb_dw(struct intel_context *ce) 901 { 902 struct intel_engine_cs *engine = ce->engine; 903 struct measure_breadcrumb *frame; 904 int dw; 905 906 GEM_BUG_ON(!engine->gt->scratch); 907 908 frame = kzalloc(sizeof(*frame), GFP_KERNEL); 909 if (!frame) 910 return -ENOMEM; 911 912 frame->rq.engine = engine; 913 frame->rq.context = ce; 914 rcu_assign_pointer(frame->rq.timeline, ce->timeline); 915 frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno; 916 917 frame->ring.vaddr = frame->cs; 918 frame->ring.size = sizeof(frame->cs); 919 frame->ring.wrap = 920 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size); 921 frame->ring.effective_size = frame->ring.size; 922 intel_ring_update_space(&frame->ring); 923 frame->rq.ring = &frame->ring; 924 925 mutex_lock(&ce->timeline->mutex); 926 spin_lock_irq(&engine->sched_engine->lock); 927 928 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs; 929 930 spin_unlock_irq(&engine->sched_engine->lock); 931 mutex_unlock(&ce->timeline->mutex); 932 933 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */ 934 935 kfree(frame); 936 return dw; 937 } 938 939 struct intel_context * 940 intel_engine_create_pinned_context(struct intel_engine_cs *engine, 941 struct i915_address_space *vm, 942 unsigned int ring_size, 943 unsigned int hwsp, 944 struct lock_class_key *key, 945 const char *name) 946 { 947 struct intel_context *ce; 948 int err; 949 950 ce = intel_context_create(engine); 951 if (IS_ERR(ce)) 952 return ce; 953 954 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags); 955 ce->timeline = page_pack_bits(NULL, hwsp); 956 ce->ring = NULL; 957 ce->ring_size = ring_size; 958 959 i915_vm_put(ce->vm); 960 ce->vm = i915_vm_get(vm); 961 962 err = intel_context_pin(ce); /* perma-pin so it is always available */ 963 if (err) { 964 intel_context_put(ce); 965 return ERR_PTR(err); 966 } 967 968 list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list); 969 970 /* 971 * Give our perma-pinned kernel timelines a separate lockdep class, 972 * so that we can use them from within the normal user timelines 973 * should we need to inject GPU operations during their request 974 * construction. 975 */ 976 lockdep_set_class_and_name(&ce->timeline->mutex, key, name); 977 978 return ce; 979 } 980 981 void intel_engine_destroy_pinned_context(struct intel_context *ce) 982 { 983 struct intel_engine_cs *engine = ce->engine; 984 struct i915_vma *hwsp = engine->status_page.vma; 985 986 GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp); 987 988 mutex_lock(&hwsp->vm->mutex); 989 list_del(&ce->timeline->engine_link); 990 mutex_unlock(&hwsp->vm->mutex); 991 992 list_del(&ce->pinned_contexts_link); 993 intel_context_unpin(ce); 994 intel_context_put(ce); 995 } 996 997 static struct intel_context * 998 create_kernel_context(struct intel_engine_cs *engine) 999 { 1000 static struct lock_class_key kernel; 1001 1002 return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K, 1003 I915_GEM_HWS_SEQNO_ADDR, 1004 &kernel, "kernel_context"); 1005 } 1006 1007 /** 1008 * intel_engines_init_common - initialize cengine state which might require hw access 1009 * @engine: Engine to initialize. 1010 * 1011 * Initializes @engine@ structure members shared between legacy and execlists 1012 * submission modes which do require hardware access. 1013 * 1014 * Typcally done at later stages of submission mode specific engine setup. 1015 * 1016 * Returns zero on success or an error code on failure. 1017 */ 1018 static int engine_init_common(struct intel_engine_cs *engine) 1019 { 1020 struct intel_context *ce; 1021 int ret; 1022 1023 engine->set_default_submission(engine); 1024 1025 /* 1026 * We may need to do things with the shrinker which 1027 * require us to immediately switch back to the default 1028 * context. This can cause a problem as pinning the 1029 * default context also requires GTT space which may not 1030 * be available. To avoid this we always pin the default 1031 * context. 1032 */ 1033 ce = create_kernel_context(engine); 1034 if (IS_ERR(ce)) 1035 return PTR_ERR(ce); 1036 1037 ret = measure_breadcrumb_dw(ce); 1038 if (ret < 0) 1039 goto err_context; 1040 1041 engine->emit_fini_breadcrumb_dw = ret; 1042 engine->kernel_context = ce; 1043 1044 return 0; 1045 1046 err_context: 1047 intel_engine_destroy_pinned_context(ce); 1048 return ret; 1049 } 1050 1051 int intel_engines_init(struct intel_gt *gt) 1052 { 1053 int (*setup)(struct intel_engine_cs *engine); 1054 struct intel_engine_cs *engine; 1055 enum intel_engine_id id; 1056 int err; 1057 1058 if (intel_uc_uses_guc_submission(>->uc)) { 1059 gt->submission_method = INTEL_SUBMISSION_GUC; 1060 setup = intel_guc_submission_setup; 1061 } else if (HAS_EXECLISTS(gt->i915)) { 1062 gt->submission_method = INTEL_SUBMISSION_ELSP; 1063 setup = intel_execlists_submission_setup; 1064 } else { 1065 gt->submission_method = INTEL_SUBMISSION_RING; 1066 setup = intel_ring_submission_setup; 1067 } 1068 1069 for_each_engine(engine, gt, id) { 1070 err = engine_setup_common(engine); 1071 if (err) 1072 return err; 1073 1074 err = setup(engine); 1075 if (err) 1076 return err; 1077 1078 err = engine_init_common(engine); 1079 if (err) 1080 return err; 1081 1082 intel_engine_add_user(engine); 1083 } 1084 1085 return 0; 1086 } 1087 1088 /** 1089 * intel_engines_cleanup_common - cleans up the engine state created by 1090 * the common initiailizers. 1091 * @engine: Engine to cleanup. 1092 * 1093 * This cleans up everything created by the common helpers. 1094 */ 1095 void intel_engine_cleanup_common(struct intel_engine_cs *engine) 1096 { 1097 GEM_BUG_ON(!list_empty(&engine->sched_engine->requests)); 1098 1099 i915_sched_engine_put(engine->sched_engine); 1100 intel_breadcrumbs_put(engine->breadcrumbs); 1101 1102 intel_engine_fini_retire(engine); 1103 intel_engine_cleanup_cmd_parser(engine); 1104 1105 if (engine->default_state) 1106 fput(engine->default_state); 1107 1108 if (engine->kernel_context) 1109 intel_engine_destroy_pinned_context(engine->kernel_context); 1110 1111 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks)); 1112 cleanup_status_page(engine); 1113 1114 intel_wa_list_free(&engine->ctx_wa_list); 1115 intel_wa_list_free(&engine->wa_list); 1116 intel_wa_list_free(&engine->whitelist); 1117 } 1118 1119 /** 1120 * intel_engine_resume - re-initializes the HW state of the engine 1121 * @engine: Engine to resume. 1122 * 1123 * Returns zero on success or an error code on failure. 1124 */ 1125 int intel_engine_resume(struct intel_engine_cs *engine) 1126 { 1127 intel_engine_apply_workarounds(engine); 1128 intel_engine_apply_whitelist(engine); 1129 1130 return engine->resume(engine); 1131 } 1132 1133 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine) 1134 { 1135 struct drm_i915_private *i915 = engine->i915; 1136 1137 u64 acthd; 1138 1139 if (GRAPHICS_VER(i915) >= 8) 1140 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW); 1141 else if (GRAPHICS_VER(i915) >= 4) 1142 acthd = ENGINE_READ(engine, RING_ACTHD); 1143 else 1144 acthd = ENGINE_READ(engine, ACTHD); 1145 1146 return acthd; 1147 } 1148 1149 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine) 1150 { 1151 u64 bbaddr; 1152 1153 if (GRAPHICS_VER(engine->i915) >= 8) 1154 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW); 1155 else 1156 bbaddr = ENGINE_READ(engine, RING_BBADDR); 1157 1158 return bbaddr; 1159 } 1160 1161 static unsigned long stop_timeout(const struct intel_engine_cs *engine) 1162 { 1163 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */ 1164 return 0; 1165 1166 /* 1167 * If we are doing a normal GPU reset, we can take our time and allow 1168 * the engine to quiesce. We've stopped submission to the engine, and 1169 * if we wait long enough an innocent context should complete and 1170 * leave the engine idle. So they should not be caught unaware by 1171 * the forthcoming GPU reset (which usually follows the stop_cs)! 1172 */ 1173 return READ_ONCE(engine->props.stop_timeout_ms); 1174 } 1175 1176 static int __intel_engine_stop_cs(struct intel_engine_cs *engine, 1177 int fast_timeout_us, 1178 int slow_timeout_ms) 1179 { 1180 struct intel_uncore *uncore = engine->uncore; 1181 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); 1182 int err; 1183 1184 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); 1185 err = __intel_wait_for_register_fw(engine->uncore, mode, 1186 MODE_IDLE, MODE_IDLE, 1187 fast_timeout_us, 1188 slow_timeout_ms, 1189 NULL); 1190 1191 /* A final mmio read to let GPU writes be hopefully flushed to memory */ 1192 intel_uncore_posting_read_fw(uncore, mode); 1193 return err; 1194 } 1195 1196 int intel_engine_stop_cs(struct intel_engine_cs *engine) 1197 { 1198 int err = 0; 1199 1200 if (GRAPHICS_VER(engine->i915) < 3) 1201 return -ENODEV; 1202 1203 ENGINE_TRACE(engine, "\n"); 1204 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { 1205 ENGINE_TRACE(engine, 1206 "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n", 1207 ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR, 1208 ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR); 1209 1210 /* 1211 * Sometimes we observe that the idle flag is not 1212 * set even though the ring is empty. So double 1213 * check before giving up. 1214 */ 1215 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) != 1216 (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR)) 1217 err = -ETIMEDOUT; 1218 } 1219 1220 return err; 1221 } 1222 1223 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) 1224 { 1225 ENGINE_TRACE(engine, "\n"); 1226 1227 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); 1228 } 1229 1230 const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 1231 { 1232 switch (type) { 1233 case I915_CACHE_NONE: return " uncached"; 1234 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 1235 case I915_CACHE_L3_LLC: return " L3+LLC"; 1236 case I915_CACHE_WT: return " WT"; 1237 default: return ""; 1238 } 1239 } 1240 1241 static u32 1242 read_subslice_reg(const struct intel_engine_cs *engine, 1243 int slice, int subslice, i915_reg_t reg) 1244 { 1245 return intel_uncore_read_with_mcr_steering(engine->uncore, reg, 1246 slice, subslice); 1247 } 1248 1249 /* NB: please notice the memset */ 1250 void intel_engine_get_instdone(const struct intel_engine_cs *engine, 1251 struct intel_instdone *instdone) 1252 { 1253 struct drm_i915_private *i915 = engine->i915; 1254 const struct sseu_dev_info *sseu = &engine->gt->info.sseu; 1255 struct intel_uncore *uncore = engine->uncore; 1256 u32 mmio_base = engine->mmio_base; 1257 int slice; 1258 int subslice; 1259 int iter; 1260 1261 memset(instdone, 0, sizeof(*instdone)); 1262 1263 if (GRAPHICS_VER(i915) >= 8) { 1264 instdone->instdone = 1265 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1266 1267 if (engine->id != RCS0) 1268 return; 1269 1270 instdone->slice_common = 1271 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1272 if (GRAPHICS_VER(i915) >= 12) { 1273 instdone->slice_common_extra[0] = 1274 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA); 1275 instdone->slice_common_extra[1] = 1276 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2); 1277 } 1278 1279 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { 1280 for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) { 1281 instdone->sampler[slice][subslice] = 1282 read_subslice_reg(engine, slice, subslice, 1283 GEN7_SAMPLER_INSTDONE); 1284 instdone->row[slice][subslice] = 1285 read_subslice_reg(engine, slice, subslice, 1286 GEN7_ROW_INSTDONE); 1287 } 1288 } else { 1289 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) { 1290 instdone->sampler[slice][subslice] = 1291 read_subslice_reg(engine, slice, subslice, 1292 GEN7_SAMPLER_INSTDONE); 1293 instdone->row[slice][subslice] = 1294 read_subslice_reg(engine, slice, subslice, 1295 GEN7_ROW_INSTDONE); 1296 } 1297 } 1298 1299 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { 1300 for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) 1301 instdone->geom_svg[slice][subslice] = 1302 read_subslice_reg(engine, slice, subslice, 1303 XEHPG_INSTDONE_GEOM_SVG); 1304 } 1305 } else if (GRAPHICS_VER(i915) >= 7) { 1306 instdone->instdone = 1307 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1308 1309 if (engine->id != RCS0) 1310 return; 1311 1312 instdone->slice_common = 1313 intel_uncore_read(uncore, GEN7_SC_INSTDONE); 1314 instdone->sampler[0][0] = 1315 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE); 1316 instdone->row[0][0] = 1317 intel_uncore_read(uncore, GEN7_ROW_INSTDONE); 1318 } else if (GRAPHICS_VER(i915) >= 4) { 1319 instdone->instdone = 1320 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); 1321 if (engine->id == RCS0) 1322 /* HACK: Using the wrong struct member */ 1323 instdone->slice_common = 1324 intel_uncore_read(uncore, GEN4_INSTDONE1); 1325 } else { 1326 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE); 1327 } 1328 } 1329 1330 static bool ring_is_idle(struct intel_engine_cs *engine) 1331 { 1332 bool idle = true; 1333 1334 if (I915_SELFTEST_ONLY(!engine->mmio_base)) 1335 return true; 1336 1337 if (!intel_engine_pm_get_if_awake(engine)) 1338 return true; 1339 1340 /* First check that no commands are left in the ring */ 1341 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) != 1342 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR)) 1343 idle = false; 1344 1345 /* No bit for gen2, so assume the CS parser is idle */ 1346 if (GRAPHICS_VER(engine->i915) > 2 && 1347 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE)) 1348 idle = false; 1349 1350 intel_engine_pm_put(engine); 1351 1352 return idle; 1353 } 1354 1355 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync) 1356 { 1357 struct tasklet_struct *t = &engine->sched_engine->tasklet; 1358 1359 if (!t->callback) 1360 return; 1361 1362 local_bh_disable(); 1363 if (tasklet_trylock(t)) { 1364 /* Must wait for any GPU reset in progress. */ 1365 if (__tasklet_is_enabled(t)) 1366 t->callback(t); 1367 tasklet_unlock(t); 1368 } 1369 local_bh_enable(); 1370 1371 /* Synchronise and wait for the tasklet on another CPU */ 1372 if (sync) 1373 tasklet_unlock_wait(t); 1374 } 1375 1376 /** 1377 * intel_engine_is_idle() - Report if the engine has finished process all work 1378 * @engine: the intel_engine_cs 1379 * 1380 * Return true if there are no requests pending, nothing left to be submitted 1381 * to hardware, and that the engine is idle. 1382 */ 1383 bool intel_engine_is_idle(struct intel_engine_cs *engine) 1384 { 1385 /* More white lies, if wedged, hw state is inconsistent */ 1386 if (intel_gt_is_wedged(engine->gt)) 1387 return true; 1388 1389 if (!intel_engine_pm_is_awake(engine)) 1390 return true; 1391 1392 /* Waiting to drain ELSP? */ 1393 intel_synchronize_hardirq(engine->i915); 1394 intel_engine_flush_submission(engine); 1395 1396 /* ELSP is empty, but there are ready requests? E.g. after reset */ 1397 if (!i915_sched_engine_is_empty(engine->sched_engine)) 1398 return false; 1399 1400 /* Ring stopped? */ 1401 return ring_is_idle(engine); 1402 } 1403 1404 bool intel_engines_are_idle(struct intel_gt *gt) 1405 { 1406 struct intel_engine_cs *engine; 1407 enum intel_engine_id id; 1408 1409 /* 1410 * If the driver is wedged, HW state may be very inconsistent and 1411 * report that it is still busy, even though we have stopped using it. 1412 */ 1413 if (intel_gt_is_wedged(gt)) 1414 return true; 1415 1416 /* Already parked (and passed an idleness test); must still be idle */ 1417 if (!READ_ONCE(gt->awake)) 1418 return true; 1419 1420 for_each_engine(engine, gt, id) { 1421 if (!intel_engine_is_idle(engine)) 1422 return false; 1423 } 1424 1425 return true; 1426 } 1427 1428 bool intel_engine_irq_enable(struct intel_engine_cs *engine) 1429 { 1430 if (!engine->irq_enable) 1431 return false; 1432 1433 /* Caller disables interrupts */ 1434 spin_lock(&engine->gt->irq_lock); 1435 engine->irq_enable(engine); 1436 spin_unlock(&engine->gt->irq_lock); 1437 1438 return true; 1439 } 1440 1441 void intel_engine_irq_disable(struct intel_engine_cs *engine) 1442 { 1443 if (!engine->irq_disable) 1444 return; 1445 1446 /* Caller disables interrupts */ 1447 spin_lock(&engine->gt->irq_lock); 1448 engine->irq_disable(engine); 1449 spin_unlock(&engine->gt->irq_lock); 1450 } 1451 1452 void intel_engines_reset_default_submission(struct intel_gt *gt) 1453 { 1454 struct intel_engine_cs *engine; 1455 enum intel_engine_id id; 1456 1457 for_each_engine(engine, gt, id) { 1458 if (engine->sanitize) 1459 engine->sanitize(engine); 1460 1461 engine->set_default_submission(engine); 1462 } 1463 } 1464 1465 bool intel_engine_can_store_dword(struct intel_engine_cs *engine) 1466 { 1467 switch (GRAPHICS_VER(engine->i915)) { 1468 case 2: 1469 return false; /* uses physical not virtual addresses */ 1470 case 3: 1471 /* maybe only uses physical not virtual addresses */ 1472 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); 1473 case 4: 1474 return !IS_I965G(engine->i915); /* who knows! */ 1475 case 6: 1476 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ 1477 default: 1478 return true; 1479 } 1480 } 1481 1482 static struct intel_timeline *get_timeline(struct i915_request *rq) 1483 { 1484 struct intel_timeline *tl; 1485 1486 /* 1487 * Even though we are holding the engine->sched_engine->lock here, there 1488 * is no control over the submission queue per-se and we are 1489 * inspecting the active state at a random point in time, with an 1490 * unknown queue. Play safe and make sure the timeline remains valid. 1491 * (Only being used for pretty printing, one extra kref shouldn't 1492 * cause a camel stampede!) 1493 */ 1494 rcu_read_lock(); 1495 tl = rcu_dereference(rq->timeline); 1496 if (!kref_get_unless_zero(&tl->kref)) 1497 tl = NULL; 1498 rcu_read_unlock(); 1499 1500 return tl; 1501 } 1502 1503 static int print_ring(char *buf, int sz, struct i915_request *rq) 1504 { 1505 int len = 0; 1506 1507 if (!i915_request_signaled(rq)) { 1508 struct intel_timeline *tl = get_timeline(rq); 1509 1510 len = scnprintf(buf, sz, 1511 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ", 1512 i915_ggtt_offset(rq->ring->vma), 1513 tl ? tl->hwsp_offset : 0, 1514 hwsp_seqno(rq), 1515 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context), 1516 1000 * 1000)); 1517 1518 if (tl) 1519 intel_timeline_put(tl); 1520 } 1521 1522 return len; 1523 } 1524 1525 static void hexdump(struct drm_printer *m, const void *buf, size_t len) 1526 { 1527 const size_t rowsize = 8 * sizeof(u32); 1528 const void *prev = NULL; 1529 bool skip = false; 1530 size_t pos; 1531 1532 for (pos = 0; pos < len; pos += rowsize) { 1533 char line[128]; 1534 1535 if (prev && !memcmp(prev, buf + pos, rowsize)) { 1536 if (!skip) { 1537 drm_printf(m, "*\n"); 1538 skip = true; 1539 } 1540 continue; 1541 } 1542 1543 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos, 1544 rowsize, sizeof(u32), 1545 line, sizeof(line), 1546 false) >= sizeof(line)); 1547 drm_printf(m, "[%04zx] %s\n", pos, line); 1548 1549 prev = buf + pos; 1550 skip = false; 1551 } 1552 } 1553 1554 static const char *repr_timer(const struct timer_list *t) 1555 { 1556 if (!READ_ONCE(t->expires)) 1557 return "inactive"; 1558 1559 if (timer_pending(t)) 1560 return "active"; 1561 1562 return "expired"; 1563 } 1564 1565 static void intel_engine_print_registers(struct intel_engine_cs *engine, 1566 struct drm_printer *m) 1567 { 1568 struct drm_i915_private *dev_priv = engine->i915; 1569 struct intel_engine_execlists * const execlists = &engine->execlists; 1570 u64 addr; 1571 1572 if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7)) 1573 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID)); 1574 if (HAS_EXECLISTS(dev_priv)) { 1575 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n", 1576 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI)); 1577 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n", 1578 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO)); 1579 } 1580 drm_printf(m, "\tRING_START: 0x%08x\n", 1581 ENGINE_READ(engine, RING_START)); 1582 drm_printf(m, "\tRING_HEAD: 0x%08x\n", 1583 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR); 1584 drm_printf(m, "\tRING_TAIL: 0x%08x\n", 1585 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR); 1586 drm_printf(m, "\tRING_CTL: 0x%08x%s\n", 1587 ENGINE_READ(engine, RING_CTL), 1588 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : ""); 1589 if (GRAPHICS_VER(engine->i915) > 2) { 1590 drm_printf(m, "\tRING_MODE: 0x%08x%s\n", 1591 ENGINE_READ(engine, RING_MI_MODE), 1592 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : ""); 1593 } 1594 1595 if (GRAPHICS_VER(dev_priv) >= 6) { 1596 drm_printf(m, "\tRING_IMR: 0x%08x\n", 1597 ENGINE_READ(engine, RING_IMR)); 1598 drm_printf(m, "\tRING_ESR: 0x%08x\n", 1599 ENGINE_READ(engine, RING_ESR)); 1600 drm_printf(m, "\tRING_EMR: 0x%08x\n", 1601 ENGINE_READ(engine, RING_EMR)); 1602 drm_printf(m, "\tRING_EIR: 0x%08x\n", 1603 ENGINE_READ(engine, RING_EIR)); 1604 } 1605 1606 addr = intel_engine_get_active_head(engine); 1607 drm_printf(m, "\tACTHD: 0x%08x_%08x\n", 1608 upper_32_bits(addr), lower_32_bits(addr)); 1609 addr = intel_engine_get_last_batch_head(engine); 1610 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n", 1611 upper_32_bits(addr), lower_32_bits(addr)); 1612 if (GRAPHICS_VER(dev_priv) >= 8) 1613 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW); 1614 else if (GRAPHICS_VER(dev_priv) >= 4) 1615 addr = ENGINE_READ(engine, RING_DMA_FADD); 1616 else 1617 addr = ENGINE_READ(engine, DMA_FADD_I8XX); 1618 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n", 1619 upper_32_bits(addr), lower_32_bits(addr)); 1620 if (GRAPHICS_VER(dev_priv) >= 4) { 1621 drm_printf(m, "\tIPEIR: 0x%08x\n", 1622 ENGINE_READ(engine, RING_IPEIR)); 1623 drm_printf(m, "\tIPEHR: 0x%08x\n", 1624 ENGINE_READ(engine, RING_IPEHR)); 1625 } else { 1626 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR)); 1627 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR)); 1628 } 1629 1630 if (intel_engine_uses_guc(engine)) { 1631 /* nothing to print yet */ 1632 } else if (HAS_EXECLISTS(dev_priv)) { 1633 struct i915_request * const *port, *rq; 1634 const u32 *hws = 1635 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; 1636 const u8 num_entries = execlists->csb_size; 1637 unsigned int idx; 1638 u8 read, write; 1639 1640 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n", 1641 yesno(test_bit(TASKLET_STATE_SCHED, 1642 &engine->sched_engine->tasklet.state)), 1643 enableddisabled(!atomic_read(&engine->sched_engine->tasklet.count)), 1644 repr_timer(&engine->execlists.preempt), 1645 repr_timer(&engine->execlists.timer)); 1646 1647 read = execlists->csb_head; 1648 write = READ_ONCE(*execlists->csb_write); 1649 1650 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n", 1651 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO), 1652 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI), 1653 read, write, num_entries); 1654 1655 if (read >= num_entries) 1656 read = 0; 1657 if (write >= num_entries) 1658 write = 0; 1659 if (read > write) 1660 write += num_entries; 1661 while (read < write) { 1662 idx = ++read % num_entries; 1663 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", 1664 idx, hws[idx * 2], hws[idx * 2 + 1]); 1665 } 1666 1667 i915_sched_engine_active_lock_bh(engine->sched_engine); 1668 rcu_read_lock(); 1669 for (port = execlists->active; (rq = *port); port++) { 1670 char hdr[160]; 1671 int len; 1672 1673 len = scnprintf(hdr, sizeof(hdr), 1674 "\t\tActive[%d]: ccid:%08x%s%s, ", 1675 (int)(port - execlists->active), 1676 rq->context->lrc.ccid, 1677 intel_context_is_closed(rq->context) ? "!" : "", 1678 intel_context_is_banned(rq->context) ? "*" : ""); 1679 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1680 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1681 i915_request_show(m, rq, hdr, 0); 1682 } 1683 for (port = execlists->pending; (rq = *port); port++) { 1684 char hdr[160]; 1685 int len; 1686 1687 len = scnprintf(hdr, sizeof(hdr), 1688 "\t\tPending[%d]: ccid:%08x%s%s, ", 1689 (int)(port - execlists->pending), 1690 rq->context->lrc.ccid, 1691 intel_context_is_closed(rq->context) ? "!" : "", 1692 intel_context_is_banned(rq->context) ? "*" : ""); 1693 len += print_ring(hdr + len, sizeof(hdr) - len, rq); 1694 scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); 1695 i915_request_show(m, rq, hdr, 0); 1696 } 1697 rcu_read_unlock(); 1698 i915_sched_engine_active_unlock_bh(engine->sched_engine); 1699 } else if (GRAPHICS_VER(dev_priv) > 6) { 1700 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n", 1701 ENGINE_READ(engine, RING_PP_DIR_BASE)); 1702 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", 1703 ENGINE_READ(engine, RING_PP_DIR_BASE_READ)); 1704 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", 1705 ENGINE_READ(engine, RING_PP_DIR_DCLV)); 1706 } 1707 } 1708 1709 static void print_request_ring(struct drm_printer *m, struct i915_request *rq) 1710 { 1711 struct i915_vma_snapshot *vsnap = &rq->batch_snapshot; 1712 void *ring; 1713 int size; 1714 1715 if (!i915_vma_snapshot_present(vsnap)) 1716 vsnap = NULL; 1717 1718 drm_printf(m, 1719 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n", 1720 rq->head, rq->postfix, rq->tail, 1721 vsnap ? upper_32_bits(vsnap->gtt_offset) : ~0u, 1722 vsnap ? lower_32_bits(vsnap->gtt_offset) : ~0u); 1723 1724 size = rq->tail - rq->head; 1725 if (rq->tail < rq->head) 1726 size += rq->ring->size; 1727 1728 ring = kmalloc(size, GFP_ATOMIC); 1729 if (ring) { 1730 const void *vaddr = rq->ring->vaddr; 1731 unsigned int head = rq->head; 1732 unsigned int len = 0; 1733 1734 if (rq->tail < head) { 1735 len = rq->ring->size - head; 1736 memcpy(ring, vaddr + head, len); 1737 head = 0; 1738 } 1739 memcpy(ring + len, vaddr + head, size - len); 1740 1741 hexdump(m, ring, size); 1742 kfree(ring); 1743 } 1744 } 1745 1746 static unsigned long list_count(struct list_head *list) 1747 { 1748 struct list_head *pos; 1749 unsigned long count = 0; 1750 1751 list_for_each(pos, list) 1752 count++; 1753 1754 return count; 1755 } 1756 1757 static unsigned long read_ul(void *p, size_t x) 1758 { 1759 return *(unsigned long *)(p + x); 1760 } 1761 1762 static void print_properties(struct intel_engine_cs *engine, 1763 struct drm_printer *m) 1764 { 1765 static const struct pmap { 1766 size_t offset; 1767 const char *name; 1768 } props[] = { 1769 #define P(x) { \ 1770 .offset = offsetof(typeof(engine->props), x), \ 1771 .name = #x \ 1772 } 1773 P(heartbeat_interval_ms), 1774 P(max_busywait_duration_ns), 1775 P(preempt_timeout_ms), 1776 P(stop_timeout_ms), 1777 P(timeslice_duration_ms), 1778 1779 {}, 1780 #undef P 1781 }; 1782 const struct pmap *p; 1783 1784 drm_printf(m, "\tProperties:\n"); 1785 for (p = props; p->name; p++) 1786 drm_printf(m, "\t\t%s: %lu [default %lu]\n", 1787 p->name, 1788 read_ul(&engine->props, p->offset), 1789 read_ul(&engine->defaults, p->offset)); 1790 } 1791 1792 static void engine_dump_request(struct i915_request *rq, struct drm_printer *m, const char *msg) 1793 { 1794 struct intel_timeline *tl = get_timeline(rq); 1795 1796 i915_request_show(m, rq, msg, 0); 1797 1798 drm_printf(m, "\t\tring->start: 0x%08x\n", 1799 i915_ggtt_offset(rq->ring->vma)); 1800 drm_printf(m, "\t\tring->head: 0x%08x\n", 1801 rq->ring->head); 1802 drm_printf(m, "\t\tring->tail: 0x%08x\n", 1803 rq->ring->tail); 1804 drm_printf(m, "\t\tring->emit: 0x%08x\n", 1805 rq->ring->emit); 1806 drm_printf(m, "\t\tring->space: 0x%08x\n", 1807 rq->ring->space); 1808 1809 if (tl) { 1810 drm_printf(m, "\t\tring->hwsp: 0x%08x\n", 1811 tl->hwsp_offset); 1812 intel_timeline_put(tl); 1813 } 1814 1815 print_request_ring(m, rq); 1816 1817 if (rq->context->lrc_reg_state) { 1818 drm_printf(m, "Logical Ring Context:\n"); 1819 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE); 1820 } 1821 } 1822 1823 void intel_engine_dump_active_requests(struct list_head *requests, 1824 struct i915_request *hung_rq, 1825 struct drm_printer *m) 1826 { 1827 struct i915_request *rq; 1828 const char *msg; 1829 enum i915_request_state state; 1830 1831 list_for_each_entry(rq, requests, sched.link) { 1832 if (rq == hung_rq) 1833 continue; 1834 1835 state = i915_test_request_state(rq); 1836 if (state < I915_REQUEST_QUEUED) 1837 continue; 1838 1839 if (state == I915_REQUEST_ACTIVE) 1840 msg = "\t\tactive on engine"; 1841 else 1842 msg = "\t\tactive in queue"; 1843 1844 engine_dump_request(rq, m, msg); 1845 } 1846 } 1847 1848 static void engine_dump_active_requests(struct intel_engine_cs *engine, struct drm_printer *m) 1849 { 1850 struct i915_request *hung_rq = NULL; 1851 struct intel_context *ce; 1852 bool guc; 1853 1854 /* 1855 * No need for an engine->irq_seqno_barrier() before the seqno reads. 1856 * The GPU is still running so requests are still executing and any 1857 * hardware reads will be out of date by the time they are reported. 1858 * But the intention here is just to report an instantaneous snapshot 1859 * so that's fine. 1860 */ 1861 lockdep_assert_held(&engine->sched_engine->lock); 1862 1863 drm_printf(m, "\tRequests:\n"); 1864 1865 guc = intel_uc_uses_guc_submission(&engine->gt->uc); 1866 if (guc) { 1867 ce = intel_engine_get_hung_context(engine); 1868 if (ce) 1869 hung_rq = intel_context_find_active_request(ce); 1870 } else { 1871 hung_rq = intel_engine_execlist_find_hung_request(engine); 1872 } 1873 1874 if (hung_rq) 1875 engine_dump_request(hung_rq, m, "\t\thung"); 1876 1877 if (guc) 1878 intel_guc_dump_active_requests(engine, hung_rq, m); 1879 else 1880 intel_engine_dump_active_requests(&engine->sched_engine->requests, 1881 hung_rq, m); 1882 } 1883 1884 void intel_engine_dump(struct intel_engine_cs *engine, 1885 struct drm_printer *m, 1886 const char *header, ...) 1887 { 1888 struct i915_gpu_error * const error = &engine->i915->gpu_error; 1889 struct i915_request *rq; 1890 intel_wakeref_t wakeref; 1891 unsigned long flags; 1892 ktime_t dummy; 1893 1894 if (header) { 1895 va_list ap; 1896 1897 va_start(ap, header); 1898 drm_vprintf(m, header, &ap); 1899 va_end(ap); 1900 } 1901 1902 if (intel_gt_is_wedged(engine->gt)) 1903 drm_printf(m, "*** WEDGED ***\n"); 1904 1905 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count)); 1906 drm_printf(m, "\tBarriers?: %s\n", 1907 yesno(!llist_empty(&engine->barrier_tasks))); 1908 drm_printf(m, "\tLatency: %luus\n", 1909 ewma__engine_latency_read(&engine->latency)); 1910 if (intel_engine_supports_stats(engine)) 1911 drm_printf(m, "\tRuntime: %llums\n", 1912 ktime_to_ms(intel_engine_get_busy_time(engine, 1913 &dummy))); 1914 drm_printf(m, "\tForcewake: %x domains, %d active\n", 1915 engine->fw_domain, READ_ONCE(engine->fw_active)); 1916 1917 rcu_read_lock(); 1918 rq = READ_ONCE(engine->heartbeat.systole); 1919 if (rq) 1920 drm_printf(m, "\tHeartbeat: %d ms ago\n", 1921 jiffies_to_msecs(jiffies - rq->emitted_jiffies)); 1922 rcu_read_unlock(); 1923 drm_printf(m, "\tReset count: %d (global %d)\n", 1924 i915_reset_engine_count(error, engine), 1925 i915_reset_count(error)); 1926 print_properties(engine, m); 1927 1928 spin_lock_irqsave(&engine->sched_engine->lock, flags); 1929 engine_dump_active_requests(engine, m); 1930 1931 drm_printf(m, "\tOn hold?: %lu\n", 1932 list_count(&engine->sched_engine->hold)); 1933 spin_unlock_irqrestore(&engine->sched_engine->lock, flags); 1934 1935 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base); 1936 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm); 1937 if (wakeref) { 1938 intel_engine_print_registers(engine, m); 1939 intel_runtime_pm_put(engine->uncore->rpm, wakeref); 1940 } else { 1941 drm_printf(m, "\tDevice is asleep; skipping register dump\n"); 1942 } 1943 1944 intel_execlists_show_requests(engine, m, i915_request_show, 8); 1945 1946 drm_printf(m, "HWSP:\n"); 1947 hexdump(m, engine->status_page.addr, PAGE_SIZE); 1948 1949 drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine))); 1950 1951 intel_engine_print_breadcrumbs(engine, m); 1952 } 1953 1954 /** 1955 * intel_engine_get_busy_time() - Return current accumulated engine busyness 1956 * @engine: engine to report on 1957 * @now: monotonic timestamp of sampling 1958 * 1959 * Returns accumulated time @engine was busy since engine stats were enabled. 1960 */ 1961 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) 1962 { 1963 return engine->busyness(engine, now); 1964 } 1965 1966 struct intel_context * 1967 intel_engine_create_virtual(struct intel_engine_cs **siblings, 1968 unsigned int count, unsigned long flags) 1969 { 1970 if (count == 0) 1971 return ERR_PTR(-EINVAL); 1972 1973 if (count == 1 && !(flags & FORCE_VIRTUAL)) 1974 return intel_context_create(siblings[0]); 1975 1976 GEM_BUG_ON(!siblings[0]->cops->create_virtual); 1977 return siblings[0]->cops->create_virtual(siblings, count, flags); 1978 } 1979 1980 struct i915_request * 1981 intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine) 1982 { 1983 struct i915_request *request, *active = NULL; 1984 1985 /* 1986 * This search does not work in GuC submission mode. However, the GuC 1987 * will report the hanging context directly to the driver itself. So 1988 * the driver should never get here when in GuC mode. 1989 */ 1990 GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc)); 1991 1992 /* 1993 * We are called by the error capture, reset and to dump engine 1994 * state at random points in time. In particular, note that neither is 1995 * crucially ordered with an interrupt. After a hang, the GPU is dead 1996 * and we assume that no more writes can happen (we waited long enough 1997 * for all writes that were in transaction to be flushed) - adding an 1998 * extra delay for a recent interrupt is pointless. Hence, we do 1999 * not need an engine->irq_seqno_barrier() before the seqno reads. 2000 * At all other times, we must assume the GPU is still running, but 2001 * we only care about the snapshot of this moment. 2002 */ 2003 lockdep_assert_held(&engine->sched_engine->lock); 2004 2005 rcu_read_lock(); 2006 request = execlists_active(&engine->execlists); 2007 if (request) { 2008 struct intel_timeline *tl = request->context->timeline; 2009 2010 list_for_each_entry_from_reverse(request, &tl->requests, link) { 2011 if (__i915_request_is_complete(request)) 2012 break; 2013 2014 active = request; 2015 } 2016 } 2017 rcu_read_unlock(); 2018 if (active) 2019 return active; 2020 2021 list_for_each_entry(request, &engine->sched_engine->requests, 2022 sched.link) { 2023 if (i915_test_request_state(request) != I915_REQUEST_ACTIVE) 2024 continue; 2025 2026 active = request; 2027 break; 2028 } 2029 2030 return active; 2031 } 2032 2033 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2034 #include "mock_engine.c" 2035 #include "selftest_engine.c" 2036 #include "selftest_engine_cs.c" 2037 #endif 2038