1 /* SPDX-License-Identifier: MIT */
2 #ifndef _INTEL_RINGBUFFER_H_
3 #define _INTEL_RINGBUFFER_H_
4 
5 #include <drm/drm_util.h>
6 
7 #include <linux/hashtable.h>
8 #include <linux/irq_work.h>
9 #include <linux/random.h>
10 #include <linux/seqlock.h>
11 
12 #include "i915_gem_batch_pool.h"
13 #include "i915_pmu.h"
14 #include "i915_reg.h"
15 #include "i915_request.h"
16 #include "i915_selftest.h"
17 #include "gt/intel_timeline.h"
18 #include "intel_engine_types.h"
19 #include "intel_gpu_commands.h"
20 #include "intel_workarounds.h"
21 
22 struct drm_printer;
23 
24 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
25  * but keeps the logic simple. Indeed, the whole purpose of this macro is just
26  * to give some inclination as to some of the magic values used in the various
27  * workarounds!
28  */
29 #define CACHELINE_BYTES 64
30 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
31 
32 /*
33  * The register defines to be used with the following macros need to accept a
34  * base param, e.g:
35  *
36  * REG_FOO(base) _MMIO((base) + <relative offset>)
37  * ENGINE_READ(engine, REG_FOO);
38  *
39  * register arrays are to be defined and accessed as follows:
40  *
41  * REG_BAR(base, i) _MMIO((base) + <relative offset> + (i) * <shift>)
42  * ENGINE_READ_IDX(engine, REG_BAR, i)
43  */
44 
45 #define __ENGINE_REG_OP(op__, engine__, ...) \
46 	intel_uncore_##op__((engine__)->uncore, __VA_ARGS__)
47 
48 #define __ENGINE_READ_OP(op__, engine__, reg__) \
49 	__ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base))
50 
51 #define ENGINE_READ16(...)	__ENGINE_READ_OP(read16, __VA_ARGS__)
52 #define ENGINE_READ(...)	__ENGINE_READ_OP(read, __VA_ARGS__)
53 #define ENGINE_READ_FW(...)	__ENGINE_READ_OP(read_fw, __VA_ARGS__)
54 #define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read_fw, __VA_ARGS__)
55 #define ENGINE_POSTING_READ16(...) __ENGINE_READ_OP(posting_read16, __VA_ARGS__)
56 
57 #define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \
58 	__ENGINE_REG_OP(read64_2x32, (engine__), \
59 			lower_reg__((engine__)->mmio_base), \
60 			upper_reg__((engine__)->mmio_base))
61 
62 #define ENGINE_READ_IDX(engine__, reg__, idx__) \
63 	__ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__)))
64 
65 #define __ENGINE_WRITE_OP(op__, engine__, reg__, val__) \
66 	__ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))
67 
68 #define ENGINE_WRITE16(...)	__ENGINE_WRITE_OP(write16, __VA_ARGS__)
69 #define ENGINE_WRITE(...)	__ENGINE_WRITE_OP(write, __VA_ARGS__)
70 #define ENGINE_WRITE_FW(...)	__ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
71 
72 #define GEN6_RING_FAULT_REG_READ(engine__) \
73 	intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
74 
75 #define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
76 	intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
77 
78 #define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
79 ({ \
80 	u32 __val; \
81 \
82 	__val = intel_uncore_read((engine__)->uncore, \
83 				  RING_FAULT_REG(engine__)); \
84 	__val &= ~(clear__); \
85 	__val |= (set__); \
86 	intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
87 			   __val); \
88 })
89 
90 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
91  * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
92  */
93 enum intel_engine_hangcheck_action {
94 	ENGINE_IDLE = 0,
95 	ENGINE_WAIT,
96 	ENGINE_ACTIVE_SEQNO,
97 	ENGINE_ACTIVE_HEAD,
98 	ENGINE_ACTIVE_SUBUNITS,
99 	ENGINE_WAIT_KICK,
100 	ENGINE_DEAD,
101 };
102 
103 static inline const char *
104 hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
105 {
106 	switch (a) {
107 	case ENGINE_IDLE:
108 		return "idle";
109 	case ENGINE_WAIT:
110 		return "wait";
111 	case ENGINE_ACTIVE_SEQNO:
112 		return "active seqno";
113 	case ENGINE_ACTIVE_HEAD:
114 		return "active head";
115 	case ENGINE_ACTIVE_SUBUNITS:
116 		return "active subunits";
117 	case ENGINE_WAIT_KICK:
118 		return "wait kick";
119 	case ENGINE_DEAD:
120 		return "dead";
121 	}
122 
123 	return "unknown";
124 }
125 
126 void intel_engines_set_scheduler_caps(struct drm_i915_private *i915);
127 
128 static inline unsigned int
129 execlists_num_ports(const struct intel_engine_execlists * const execlists)
130 {
131 	return execlists->port_mask + 1;
132 }
133 
134 static inline struct i915_request *
135 execlists_active(const struct intel_engine_execlists *execlists)
136 {
137 	GEM_BUG_ON(execlists->active - execlists->inflight >
138 		   execlists_num_ports(execlists));
139 	return READ_ONCE(*execlists->active);
140 }
141 
142 void
143 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists);
144 
145 struct i915_request *
146 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
147 
148 static inline u32
149 intel_read_status_page(const struct intel_engine_cs *engine, int reg)
150 {
151 	/* Ensure that the compiler doesn't optimize away the load. */
152 	return READ_ONCE(engine->status_page.addr[reg]);
153 }
154 
155 static inline void
156 intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
157 {
158 	/* Writing into the status page should be done sparingly. Since
159 	 * we do when we are uncertain of the device state, we take a bit
160 	 * of extra paranoia to try and ensure that the HWS takes the value
161 	 * we give and that it doesn't end up trapped inside the CPU!
162 	 */
163 	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
164 		mb();
165 		clflush(&engine->status_page.addr[reg]);
166 		engine->status_page.addr[reg] = value;
167 		clflush(&engine->status_page.addr[reg]);
168 		mb();
169 	} else {
170 		WRITE_ONCE(engine->status_page.addr[reg], value);
171 	}
172 }
173 
174 /*
175  * Reads a dword out of the status page, which is written to from the command
176  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
177  * MI_STORE_DATA_IMM.
178  *
179  * The following dwords have a reserved meaning:
180  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
181  * 0x04: ring 0 head pointer
182  * 0x05: ring 1 head pointer (915-class)
183  * 0x06: ring 2 head pointer (915-class)
184  * 0x10-0x1b: Context status DWords (GM45)
185  * 0x1f: Last written status offset. (GM45)
186  * 0x20-0x2f: Reserved (Gen6+)
187  *
188  * The area from dword 0x30 to 0x3ff is available for driver usage.
189  */
190 #define I915_GEM_HWS_PREEMPT		0x32
191 #define I915_GEM_HWS_PREEMPT_ADDR	(I915_GEM_HWS_PREEMPT * sizeof(u32))
192 #define I915_GEM_HWS_SEQNO		0x40
193 #define I915_GEM_HWS_SEQNO_ADDR		(I915_GEM_HWS_SEQNO * sizeof(u32))
194 #define I915_GEM_HWS_SCRATCH		0x80
195 #define I915_GEM_HWS_SCRATCH_ADDR	(I915_GEM_HWS_SCRATCH * sizeof(u32))
196 
197 #define I915_HWS_CSB_BUF0_INDEX		0x10
198 #define I915_HWS_CSB_WRITE_INDEX	0x1f
199 #define CNL_HWS_CSB_WRITE_INDEX		0x2f
200 
201 struct intel_ring *
202 intel_engine_create_ring(struct intel_engine_cs *engine,
203 			 struct intel_timeline *timeline,
204 			 int size);
205 int intel_ring_pin(struct intel_ring *ring);
206 void intel_ring_reset(struct intel_ring *ring, u32 tail);
207 unsigned int intel_ring_update_space(struct intel_ring *ring);
208 void intel_ring_unpin(struct intel_ring *ring);
209 void intel_ring_free(struct kref *ref);
210 
211 static inline struct intel_ring *intel_ring_get(struct intel_ring *ring)
212 {
213 	kref_get(&ring->ref);
214 	return ring;
215 }
216 
217 static inline void intel_ring_put(struct intel_ring *ring)
218 {
219 	kref_put(&ring->ref, intel_ring_free);
220 }
221 
222 void intel_engine_stop(struct intel_engine_cs *engine);
223 void intel_engine_cleanup(struct intel_engine_cs *engine);
224 
225 int __must_check intel_ring_cacheline_align(struct i915_request *rq);
226 
227 u32 __must_check *intel_ring_begin(struct i915_request *rq, unsigned int n);
228 
229 static inline void intel_ring_advance(struct i915_request *rq, u32 *cs)
230 {
231 	/* Dummy function.
232 	 *
233 	 * This serves as a placeholder in the code so that the reader
234 	 * can compare against the preceding intel_ring_begin() and
235 	 * check that the number of dwords emitted matches the space
236 	 * reserved for the command packet (i.e. the value passed to
237 	 * intel_ring_begin()).
238 	 */
239 	GEM_BUG_ON((rq->ring->vaddr + rq->ring->emit) != cs);
240 }
241 
242 static inline u32 intel_ring_wrap(const struct intel_ring *ring, u32 pos)
243 {
244 	return pos & (ring->size - 1);
245 }
246 
247 static inline bool
248 intel_ring_offset_valid(const struct intel_ring *ring,
249 			unsigned int pos)
250 {
251 	if (pos & -ring->size) /* must be strictly within the ring */
252 		return false;
253 
254 	if (!IS_ALIGNED(pos, 8)) /* must be qword aligned */
255 		return false;
256 
257 	return true;
258 }
259 
260 static inline u32 intel_ring_offset(const struct i915_request *rq, void *addr)
261 {
262 	/* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
263 	u32 offset = addr - rq->ring->vaddr;
264 	GEM_BUG_ON(offset > rq->ring->size);
265 	return intel_ring_wrap(rq->ring, offset);
266 }
267 
268 static inline void
269 assert_ring_tail_valid(const struct intel_ring *ring, unsigned int tail)
270 {
271 	GEM_BUG_ON(!intel_ring_offset_valid(ring, tail));
272 
273 	/*
274 	 * "Ring Buffer Use"
275 	 *	Gen2 BSpec "1. Programming Environment" / 1.4.4.6
276 	 *	Gen3 BSpec "1c Memory Interface Functions" / 2.3.4.5
277 	 *	Gen4+ BSpec "1c Memory Interface and Command Stream" / 5.3.4.5
278 	 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
279 	 * same cacheline, the Head Pointer must not be greater than the Tail
280 	 * Pointer."
281 	 *
282 	 * We use ring->head as the last known location of the actual RING_HEAD,
283 	 * it may have advanced but in the worst case it is equally the same
284 	 * as ring->head and so we should never program RING_TAIL to advance
285 	 * into the same cacheline as ring->head.
286 	 */
287 #define cacheline(a) round_down(a, CACHELINE_BYTES)
288 	GEM_BUG_ON(cacheline(tail) == cacheline(ring->head) &&
289 		   tail < ring->head);
290 #undef cacheline
291 }
292 
293 static inline unsigned int
294 intel_ring_set_tail(struct intel_ring *ring, unsigned int tail)
295 {
296 	/* Whilst writes to the tail are strictly order, there is no
297 	 * serialisation between readers and the writers. The tail may be
298 	 * read by i915_request_retire() just as it is being updated
299 	 * by execlists, as although the breadcrumb is complete, the context
300 	 * switch hasn't been seen.
301 	 */
302 	assert_ring_tail_valid(ring, tail);
303 	ring->tail = tail;
304 	return tail;
305 }
306 
307 static inline unsigned int
308 __intel_ring_space(unsigned int head, unsigned int tail, unsigned int size)
309 {
310 	/*
311 	 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
312 	 * same cacheline, the Head Pointer must not be greater than the Tail
313 	 * Pointer."
314 	 */
315 	GEM_BUG_ON(!is_power_of_2(size));
316 	return (head - tail - CACHELINE_BYTES) & (size - 1);
317 }
318 
319 int intel_engines_init_mmio(struct drm_i915_private *i915);
320 int intel_engines_setup(struct drm_i915_private *i915);
321 int intel_engines_init(struct drm_i915_private *i915);
322 void intel_engines_cleanup(struct drm_i915_private *i915);
323 
324 int intel_engine_init_common(struct intel_engine_cs *engine);
325 void intel_engine_cleanup_common(struct intel_engine_cs *engine);
326 
327 int intel_ring_submission_setup(struct intel_engine_cs *engine);
328 int intel_ring_submission_init(struct intel_engine_cs *engine);
329 
330 int intel_engine_stop_cs(struct intel_engine_cs *engine);
331 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
332 
333 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
334 
335 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
336 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);
337 
338 void intel_engine_get_instdone(struct intel_engine_cs *engine,
339 			       struct intel_instdone *instdone);
340 
341 void intel_engine_init_execlists(struct intel_engine_cs *engine);
342 
343 void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
344 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
345 
346 void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine);
347 void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine);
348 
349 void intel_engine_signal_breadcrumbs(struct intel_engine_cs *engine);
350 void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
351 
352 static inline void
353 intel_engine_queue_breadcrumbs(struct intel_engine_cs *engine)
354 {
355 	irq_work_queue(&engine->breadcrumbs.irq_work);
356 }
357 
358 void intel_engine_breadcrumbs_irq(struct intel_engine_cs *engine);
359 
360 void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
361 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
362 
363 void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
364 				    struct drm_printer *p);
365 
366 static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
367 {
368 	memset(batch, 0, 6 * sizeof(u32));
369 
370 	batch[0] = GFX_OP_PIPE_CONTROL(6);
371 	batch[1] = flags;
372 	batch[2] = offset;
373 
374 	return batch + 6;
375 }
376 
377 static inline u32 *
378 gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
379 {
380 	/* We're using qword write, offset should be aligned to 8 bytes. */
381 	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
382 
383 	/* w/a for post sync ops following a GPGPU operation we
384 	 * need a prior CS_STALL, which is emitted by the flush
385 	 * following the batch.
386 	 */
387 	*cs++ = GFX_OP_PIPE_CONTROL(6);
388 	*cs++ = flags | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;
389 	*cs++ = gtt_offset;
390 	*cs++ = 0;
391 	*cs++ = value;
392 	/* We're thrashing one dword of HWS. */
393 	*cs++ = 0;
394 
395 	return cs;
396 }
397 
398 static inline u32 *
399 gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
400 {
401 	/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
402 	GEM_BUG_ON(gtt_offset & (1 << 5));
403 	/* Offset should be aligned to 8 bytes for both (QW/DW) write types */
404 	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
405 
406 	*cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW | flags;
407 	*cs++ = gtt_offset | MI_FLUSH_DW_USE_GTT;
408 	*cs++ = 0;
409 	*cs++ = value;
410 
411 	return cs;
412 }
413 
414 static inline void __intel_engine_reset(struct intel_engine_cs *engine,
415 					bool stalled)
416 {
417 	if (engine->reset.reset)
418 		engine->reset.reset(engine, stalled);
419 	engine->serial++; /* contexts lost */
420 }
421 
422 bool intel_engine_is_idle(struct intel_engine_cs *engine);
423 bool intel_engines_are_idle(struct intel_gt *gt);
424 
425 void intel_engines_reset_default_submission(struct intel_gt *gt);
426 unsigned int intel_engines_has_context_isolation(struct drm_i915_private *i915);
427 
428 bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
429 
430 __printf(3, 4)
431 void intel_engine_dump(struct intel_engine_cs *engine,
432 		       struct drm_printer *m,
433 		       const char *header, ...);
434 
435 struct intel_engine_cs *
436 intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance);
437 
438 static inline void intel_engine_context_in(struct intel_engine_cs *engine)
439 {
440 	unsigned long flags;
441 
442 	if (READ_ONCE(engine->stats.enabled) == 0)
443 		return;
444 
445 	write_seqlock_irqsave(&engine->stats.lock, flags);
446 
447 	if (engine->stats.enabled > 0) {
448 		if (engine->stats.active++ == 0)
449 			engine->stats.start = ktime_get();
450 		GEM_BUG_ON(engine->stats.active == 0);
451 	}
452 
453 	write_sequnlock_irqrestore(&engine->stats.lock, flags);
454 }
455 
456 static inline void intel_engine_context_out(struct intel_engine_cs *engine)
457 {
458 	unsigned long flags;
459 
460 	if (READ_ONCE(engine->stats.enabled) == 0)
461 		return;
462 
463 	write_seqlock_irqsave(&engine->stats.lock, flags);
464 
465 	if (engine->stats.enabled > 0) {
466 		ktime_t last;
467 
468 		if (engine->stats.active && --engine->stats.active == 0) {
469 			/*
470 			 * Decrement the active context count and in case GPU
471 			 * is now idle add up to the running total.
472 			 */
473 			last = ktime_sub(ktime_get(), engine->stats.start);
474 
475 			engine->stats.total = ktime_add(engine->stats.total,
476 							last);
477 		} else if (engine->stats.active == 0) {
478 			/*
479 			 * After turning on engine stats, context out might be
480 			 * the first event in which case we account from the
481 			 * time stats gathering was turned on.
482 			 */
483 			last = ktime_sub(ktime_get(), engine->stats.enabled_at);
484 
485 			engine->stats.total = ktime_add(engine->stats.total,
486 							last);
487 		}
488 	}
489 
490 	write_sequnlock_irqrestore(&engine->stats.lock, flags);
491 }
492 
493 int intel_enable_engine_stats(struct intel_engine_cs *engine);
494 void intel_disable_engine_stats(struct intel_engine_cs *engine);
495 
496 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine);
497 
498 struct i915_request *
499 intel_engine_find_active_request(struct intel_engine_cs *engine);
500 
501 u32 intel_engine_context_size(struct drm_i915_private *i915, u8 class);
502 
503 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
504 
505 static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists)
506 {
507 	if (!execlists->preempt_hang.inject_hang)
508 		return false;
509 
510 	complete(&execlists->preempt_hang.completion);
511 	return true;
512 }
513 
514 #else
515 
516 static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists)
517 {
518 	return false;
519 }
520 
521 #endif
522 
523 void intel_engine_init_active(struct intel_engine_cs *engine,
524 			      unsigned int subclass);
525 #define ENGINE_PHYSICAL	0
526 #define ENGINE_MOCK	1
527 #define ENGINE_VIRTUAL	2
528 
529 #endif /* _INTEL_RINGBUFFER_H_ */
530