1 /* SPDX-License-Identifier: MIT */ 2 #ifndef _INTEL_RINGBUFFER_H_ 3 #define _INTEL_RINGBUFFER_H_ 4 5 #include <asm/cacheflush.h> 6 #include <drm/drm_util.h> 7 8 #include <linux/hashtable.h> 9 #include <linux/irq_work.h> 10 #include <linux/random.h> 11 #include <linux/seqlock.h> 12 13 #include "i915_pmu.h" 14 #include "i915_request.h" 15 #include "i915_selftest.h" 16 #include "intel_engine_types.h" 17 #include "intel_gt_types.h" 18 #include "intel_timeline.h" 19 #include "intel_workarounds.h" 20 21 struct drm_printer; 22 struct intel_context; 23 struct intel_gt; 24 struct lock_class_key; 25 26 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, 27 * but keeps the logic simple. Indeed, the whole purpose of this macro is just 28 * to give some inclination as to some of the magic values used in the various 29 * workarounds! 30 */ 31 #define CACHELINE_BYTES 64 32 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32)) 33 34 #define ENGINE_TRACE(e, fmt, ...) do { \ 35 const struct intel_engine_cs *e__ __maybe_unused = (e); \ 36 GEM_TRACE("%s %s: " fmt, \ 37 dev_name(e__->i915->drm.dev), e__->name, \ 38 ##__VA_ARGS__); \ 39 } while (0) 40 41 /* 42 * The register defines to be used with the following macros need to accept a 43 * base param, e.g: 44 * 45 * REG_FOO(base) _MMIO((base) + <relative offset>) 46 * ENGINE_READ(engine, REG_FOO); 47 * 48 * register arrays are to be defined and accessed as follows: 49 * 50 * REG_BAR(base, i) _MMIO((base) + <relative offset> + (i) * <shift>) 51 * ENGINE_READ_IDX(engine, REG_BAR, i) 52 */ 53 54 #define __ENGINE_REG_OP(op__, engine__, ...) \ 55 intel_uncore_##op__((engine__)->uncore, __VA_ARGS__) 56 57 #define __ENGINE_READ_OP(op__, engine__, reg__) \ 58 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base)) 59 60 #define ENGINE_READ16(...) __ENGINE_READ_OP(read16, __VA_ARGS__) 61 #define ENGINE_READ(...) __ENGINE_READ_OP(read, __VA_ARGS__) 62 #define ENGINE_READ_FW(...) __ENGINE_READ_OP(read_fw, __VA_ARGS__) 63 #define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read_fw, __VA_ARGS__) 64 #define ENGINE_POSTING_READ16(...) __ENGINE_READ_OP(posting_read16, __VA_ARGS__) 65 66 #define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \ 67 __ENGINE_REG_OP(read64_2x32, (engine__), \ 68 lower_reg__((engine__)->mmio_base), \ 69 upper_reg__((engine__)->mmio_base)) 70 71 #define ENGINE_READ_IDX(engine__, reg__, idx__) \ 72 __ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__))) 73 74 #define __ENGINE_WRITE_OP(op__, engine__, reg__, val__) \ 75 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__)) 76 77 #define ENGINE_WRITE16(...) __ENGINE_WRITE_OP(write16, __VA_ARGS__) 78 #define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__) 79 #define ENGINE_WRITE_FW(...) __ENGINE_WRITE_OP(write_fw, __VA_ARGS__) 80 81 #define GEN6_RING_FAULT_REG_READ(engine__) \ 82 intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__)) 83 84 #define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \ 85 intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__)) 86 87 #define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \ 88 ({ \ 89 u32 __val; \ 90 \ 91 __val = intel_uncore_read((engine__)->uncore, \ 92 RING_FAULT_REG(engine__)); \ 93 __val &= ~(clear__); \ 94 __val |= (set__); \ 95 intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \ 96 __val); \ 97 }) 98 99 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to 100 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. 101 */ 102 103 static inline unsigned int 104 execlists_num_ports(const struct intel_engine_execlists * const execlists) 105 { 106 return execlists->port_mask + 1; 107 } 108 109 static inline struct i915_request * 110 execlists_active(const struct intel_engine_execlists *execlists) 111 { 112 struct i915_request * const *cur, * const *old, *active; 113 114 cur = READ_ONCE(execlists->active); 115 smp_rmb(); /* pairs with overwrite protection in process_csb() */ 116 do { 117 old = cur; 118 119 active = READ_ONCE(*cur); 120 cur = READ_ONCE(execlists->active); 121 122 smp_rmb(); /* and complete the seqlock retry */ 123 } while (unlikely(cur != old)); 124 125 return active; 126 } 127 128 struct i915_request * 129 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists); 130 131 static inline u32 132 intel_read_status_page(const struct intel_engine_cs *engine, int reg) 133 { 134 /* Ensure that the compiler doesn't optimize away the load. */ 135 return READ_ONCE(engine->status_page.addr[reg]); 136 } 137 138 static inline void 139 intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) 140 { 141 /* Writing into the status page should be done sparingly. Since 142 * we do when we are uncertain of the device state, we take a bit 143 * of extra paranoia to try and ensure that the HWS takes the value 144 * we give and that it doesn't end up trapped inside the CPU! 145 */ 146 if (static_cpu_has(X86_FEATURE_CLFLUSH)) { 147 mb(); 148 clflush(&engine->status_page.addr[reg]); 149 engine->status_page.addr[reg] = value; 150 clflush(&engine->status_page.addr[reg]); 151 mb(); 152 } else { 153 WRITE_ONCE(engine->status_page.addr[reg], value); 154 } 155 } 156 157 /* 158 * Reads a dword out of the status page, which is written to from the command 159 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 160 * MI_STORE_DATA_IMM. 161 * 162 * The following dwords have a reserved meaning: 163 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 164 * 0x04: ring 0 head pointer 165 * 0x05: ring 1 head pointer (915-class) 166 * 0x06: ring 2 head pointer (915-class) 167 * 0x10-0x1b: Context status DWords (GM45) 168 * 0x1f: Last written status offset. (GM45) 169 * 0x20-0x2f: Reserved (Gen6+) 170 * 171 * The area from dword 0x30 to 0x3ff is available for driver usage. 172 */ 173 #define I915_GEM_HWS_PREEMPT 0x32 174 #define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32)) 175 #define I915_GEM_HWS_SEQNO 0x40 176 #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32)) 177 #define I915_GEM_HWS_MIGRATE (0x42 * sizeof(u32)) 178 #define I915_GEM_HWS_PXP 0x60 179 #define I915_GEM_HWS_PXP_ADDR (I915_GEM_HWS_PXP * sizeof(u32)) 180 #define I915_GEM_HWS_SCRATCH 0x80 181 182 #define I915_HWS_CSB_BUF0_INDEX 0x10 183 #define I915_HWS_CSB_WRITE_INDEX 0x1f 184 #define ICL_HWS_CSB_WRITE_INDEX 0x2f 185 #define INTEL_HWS_CSB_WRITE_INDEX(__i915) \ 186 (GRAPHICS_VER(__i915) >= 11 ? ICL_HWS_CSB_WRITE_INDEX : I915_HWS_CSB_WRITE_INDEX) 187 188 void intel_engine_stop(struct intel_engine_cs *engine); 189 void intel_engine_cleanup(struct intel_engine_cs *engine); 190 191 int intel_engines_init_mmio(struct intel_gt *gt); 192 int intel_engines_init(struct intel_gt *gt); 193 194 void intel_engine_free_request_pool(struct intel_engine_cs *engine); 195 196 void intel_engines_release(struct intel_gt *gt); 197 void intel_engines_free(struct intel_gt *gt); 198 199 int intel_engine_init_common(struct intel_engine_cs *engine); 200 void intel_engine_cleanup_common(struct intel_engine_cs *engine); 201 202 int intel_engine_resume(struct intel_engine_cs *engine); 203 204 int intel_ring_submission_setup(struct intel_engine_cs *engine); 205 206 int intel_engine_stop_cs(struct intel_engine_cs *engine); 207 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine); 208 209 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask); 210 211 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine); 212 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine); 213 214 void intel_engine_get_instdone(const struct intel_engine_cs *engine, 215 struct intel_instdone *instdone); 216 217 void intel_engine_init_execlists(struct intel_engine_cs *engine); 218 219 bool intel_engine_irq_enable(struct intel_engine_cs *engine); 220 void intel_engine_irq_disable(struct intel_engine_cs *engine); 221 222 static inline void __intel_engine_reset(struct intel_engine_cs *engine, 223 bool stalled) 224 { 225 if (engine->reset.rewind) 226 engine->reset.rewind(engine, stalled); 227 engine->serial++; /* contexts lost */ 228 } 229 230 bool intel_engines_are_idle(struct intel_gt *gt); 231 bool intel_engine_is_idle(struct intel_engine_cs *engine); 232 233 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync); 234 static inline void intel_engine_flush_submission(struct intel_engine_cs *engine) 235 { 236 __intel_engine_flush_submission(engine, true); 237 } 238 239 void intel_engines_reset_default_submission(struct intel_gt *gt); 240 241 bool intel_engine_can_store_dword(struct intel_engine_cs *engine); 242 243 __printf(3, 4) 244 void intel_engine_dump(struct intel_engine_cs *engine, 245 struct drm_printer *m, 246 const char *header, ...); 247 void intel_engine_dump_active_requests(struct list_head *requests, 248 struct i915_request *hung_rq, 249 struct drm_printer *m); 250 251 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, 252 ktime_t *now); 253 254 struct i915_request * 255 intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine); 256 257 u32 intel_engine_context_size(struct intel_gt *gt, u8 class); 258 struct intel_context * 259 intel_engine_create_pinned_context(struct intel_engine_cs *engine, 260 struct i915_address_space *vm, 261 unsigned int ring_size, 262 unsigned int hwsp, 263 struct lock_class_key *key, 264 const char *name); 265 266 void intel_engine_destroy_pinned_context(struct intel_context *ce); 267 268 void xehp_enable_ccs_engines(struct intel_engine_cs *engine); 269 270 #define ENGINE_PHYSICAL 0 271 #define ENGINE_MOCK 1 272 #define ENGINE_VIRTUAL 2 273 274 static inline bool intel_engine_uses_guc(const struct intel_engine_cs *engine) 275 { 276 return engine->gt->submission_method >= INTEL_SUBMISSION_GUC; 277 } 278 279 static inline bool 280 intel_engine_has_preempt_reset(const struct intel_engine_cs *engine) 281 { 282 if (!CONFIG_DRM_I915_PREEMPT_TIMEOUT) 283 return false; 284 285 return intel_engine_has_preemption(engine); 286 } 287 288 #define FORCE_VIRTUAL BIT(0) 289 struct intel_context * 290 intel_engine_create_virtual(struct intel_engine_cs **siblings, 291 unsigned int count, unsigned long flags); 292 293 static inline struct intel_context * 294 intel_engine_create_parallel(struct intel_engine_cs **engines, 295 unsigned int num_engines, 296 unsigned int width) 297 { 298 GEM_BUG_ON(!engines[0]->cops->create_parallel); 299 return engines[0]->cops->create_parallel(engines, num_engines, width); 300 } 301 302 static inline bool 303 intel_virtual_engine_has_heartbeat(const struct intel_engine_cs *engine) 304 { 305 /* 306 * For non-GuC submission we expect the back-end to look at the 307 * heartbeat status of the actual physical engine that the work 308 * has been (or is being) scheduled on, so we should only reach 309 * here with GuC submission enabled. 310 */ 311 GEM_BUG_ON(!intel_engine_uses_guc(engine)); 312 313 return intel_guc_virtual_engine_has_heartbeat(engine); 314 } 315 316 static inline bool 317 intel_engine_has_heartbeat(const struct intel_engine_cs *engine) 318 { 319 if (!CONFIG_DRM_I915_HEARTBEAT_INTERVAL) 320 return false; 321 322 if (intel_engine_is_virtual(engine)) 323 return intel_virtual_engine_has_heartbeat(engine); 324 else 325 return READ_ONCE(engine->props.heartbeat_interval_ms); 326 } 327 328 static inline struct intel_engine_cs * 329 intel_engine_get_sibling(struct intel_engine_cs *engine, unsigned int sibling) 330 { 331 GEM_BUG_ON(!intel_engine_is_virtual(engine)); 332 return engine->cops->get_sibling(engine, sibling); 333 } 334 335 static inline void 336 intel_engine_set_hung_context(struct intel_engine_cs *engine, 337 struct intel_context *ce) 338 { 339 engine->hung_ce = ce; 340 } 341 342 static inline void 343 intel_engine_clear_hung_context(struct intel_engine_cs *engine) 344 { 345 intel_engine_set_hung_context(engine, NULL); 346 } 347 348 static inline struct intel_context * 349 intel_engine_get_hung_context(struct intel_engine_cs *engine) 350 { 351 return engine->hung_ce; 352 } 353 354 #endif /* _INTEL_RINGBUFFER_H_ */ 355