1 /* SPDX-License-Identifier: MIT */
2 #ifndef _INTEL_RINGBUFFER_H_
3 #define _INTEL_RINGBUFFER_H_
4 
5 #include <drm/drm_util.h>
6 
7 #include <linux/hashtable.h>
8 #include <linux/irq_work.h>
9 #include <linux/random.h>
10 #include <linux/seqlock.h>
11 
12 #include "i915_pmu.h"
13 #include "i915_reg.h"
14 #include "i915_request.h"
15 #include "i915_selftest.h"
16 #include "gt/intel_timeline.h"
17 #include "intel_engine_types.h"
18 #include "intel_gpu_commands.h"
19 #include "intel_workarounds.h"
20 
21 struct drm_printer;
22 struct intel_gt;
23 
24 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
25  * but keeps the logic simple. Indeed, the whole purpose of this macro is just
26  * to give some inclination as to some of the magic values used in the various
27  * workarounds!
28  */
29 #define CACHELINE_BYTES 64
30 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
31 
32 /*
33  * The register defines to be used with the following macros need to accept a
34  * base param, e.g:
35  *
36  * REG_FOO(base) _MMIO((base) + <relative offset>)
37  * ENGINE_READ(engine, REG_FOO);
38  *
39  * register arrays are to be defined and accessed as follows:
40  *
41  * REG_BAR(base, i) _MMIO((base) + <relative offset> + (i) * <shift>)
42  * ENGINE_READ_IDX(engine, REG_BAR, i)
43  */
44 
45 #define __ENGINE_REG_OP(op__, engine__, ...) \
46 	intel_uncore_##op__((engine__)->uncore, __VA_ARGS__)
47 
48 #define __ENGINE_READ_OP(op__, engine__, reg__) \
49 	__ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base))
50 
51 #define ENGINE_READ16(...)	__ENGINE_READ_OP(read16, __VA_ARGS__)
52 #define ENGINE_READ(...)	__ENGINE_READ_OP(read, __VA_ARGS__)
53 #define ENGINE_READ_FW(...)	__ENGINE_READ_OP(read_fw, __VA_ARGS__)
54 #define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read_fw, __VA_ARGS__)
55 #define ENGINE_POSTING_READ16(...) __ENGINE_READ_OP(posting_read16, __VA_ARGS__)
56 
57 #define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \
58 	__ENGINE_REG_OP(read64_2x32, (engine__), \
59 			lower_reg__((engine__)->mmio_base), \
60 			upper_reg__((engine__)->mmio_base))
61 
62 #define ENGINE_READ_IDX(engine__, reg__, idx__) \
63 	__ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__)))
64 
65 #define __ENGINE_WRITE_OP(op__, engine__, reg__, val__) \
66 	__ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))
67 
68 #define ENGINE_WRITE16(...)	__ENGINE_WRITE_OP(write16, __VA_ARGS__)
69 #define ENGINE_WRITE(...)	__ENGINE_WRITE_OP(write, __VA_ARGS__)
70 #define ENGINE_WRITE_FW(...)	__ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
71 
72 #define GEN6_RING_FAULT_REG_READ(engine__) \
73 	intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
74 
75 #define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
76 	intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
77 
78 #define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
79 ({ \
80 	u32 __val; \
81 \
82 	__val = intel_uncore_read((engine__)->uncore, \
83 				  RING_FAULT_REG(engine__)); \
84 	__val &= ~(clear__); \
85 	__val |= (set__); \
86 	intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
87 			   __val); \
88 })
89 
90 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
91  * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
92  */
93 
94 static inline unsigned int
95 execlists_num_ports(const struct intel_engine_execlists * const execlists)
96 {
97 	return execlists->port_mask + 1;
98 }
99 
100 static inline struct i915_request *
101 execlists_active(const struct intel_engine_execlists *execlists)
102 {
103 	GEM_BUG_ON(execlists->active - execlists->inflight >
104 		   execlists_num_ports(execlists));
105 	return READ_ONCE(*execlists->active);
106 }
107 
108 static inline void
109 execlists_active_lock_bh(struct intel_engine_execlists *execlists)
110 {
111 	local_bh_disable(); /* prevent local softirq and lock recursion */
112 	tasklet_lock(&execlists->tasklet);
113 }
114 
115 static inline void
116 execlists_active_unlock_bh(struct intel_engine_execlists *execlists)
117 {
118 	tasklet_unlock(&execlists->tasklet);
119 	local_bh_enable(); /* restore softirq, and kick ksoftirqd! */
120 }
121 
122 struct i915_request *
123 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
124 
125 static inline u32
126 intel_read_status_page(const struct intel_engine_cs *engine, int reg)
127 {
128 	/* Ensure that the compiler doesn't optimize away the load. */
129 	return READ_ONCE(engine->status_page.addr[reg]);
130 }
131 
132 static inline void
133 intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
134 {
135 	/* Writing into the status page should be done sparingly. Since
136 	 * we do when we are uncertain of the device state, we take a bit
137 	 * of extra paranoia to try and ensure that the HWS takes the value
138 	 * we give and that it doesn't end up trapped inside the CPU!
139 	 */
140 	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
141 		mb();
142 		clflush(&engine->status_page.addr[reg]);
143 		engine->status_page.addr[reg] = value;
144 		clflush(&engine->status_page.addr[reg]);
145 		mb();
146 	} else {
147 		WRITE_ONCE(engine->status_page.addr[reg], value);
148 	}
149 }
150 
151 /*
152  * Reads a dword out of the status page, which is written to from the command
153  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
154  * MI_STORE_DATA_IMM.
155  *
156  * The following dwords have a reserved meaning:
157  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
158  * 0x04: ring 0 head pointer
159  * 0x05: ring 1 head pointer (915-class)
160  * 0x06: ring 2 head pointer (915-class)
161  * 0x10-0x1b: Context status DWords (GM45)
162  * 0x1f: Last written status offset. (GM45)
163  * 0x20-0x2f: Reserved (Gen6+)
164  *
165  * The area from dword 0x30 to 0x3ff is available for driver usage.
166  */
167 #define I915_GEM_HWS_PREEMPT		0x32
168 #define I915_GEM_HWS_PREEMPT_ADDR	(I915_GEM_HWS_PREEMPT * sizeof(u32))
169 #define I915_GEM_HWS_SEQNO		0x40
170 #define I915_GEM_HWS_SEQNO_ADDR		(I915_GEM_HWS_SEQNO * sizeof(u32))
171 #define I915_GEM_HWS_SCRATCH		0x80
172 #define I915_GEM_HWS_SCRATCH_ADDR	(I915_GEM_HWS_SCRATCH * sizeof(u32))
173 
174 #define I915_HWS_CSB_BUF0_INDEX		0x10
175 #define I915_HWS_CSB_WRITE_INDEX	0x1f
176 #define CNL_HWS_CSB_WRITE_INDEX		0x2f
177 
178 void intel_engine_stop(struct intel_engine_cs *engine);
179 void intel_engine_cleanup(struct intel_engine_cs *engine);
180 
181 int intel_engines_init_mmio(struct intel_gt *gt);
182 int intel_engines_setup(struct intel_gt *gt);
183 int intel_engines_init(struct intel_gt *gt);
184 void intel_engines_cleanup(struct intel_gt *gt);
185 
186 int intel_engine_init_common(struct intel_engine_cs *engine);
187 void intel_engine_cleanup_common(struct intel_engine_cs *engine);
188 
189 int intel_ring_submission_setup(struct intel_engine_cs *engine);
190 int intel_ring_submission_init(struct intel_engine_cs *engine);
191 
192 int intel_engine_stop_cs(struct intel_engine_cs *engine);
193 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
194 
195 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
196 
197 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
198 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);
199 
200 void intel_engine_get_instdone(struct intel_engine_cs *engine,
201 			       struct intel_instdone *instdone);
202 
203 void intel_engine_init_execlists(struct intel_engine_cs *engine);
204 
205 void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
206 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
207 
208 void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
209 
210 static inline void
211 intel_engine_queue_breadcrumbs(struct intel_engine_cs *engine)
212 {
213 	irq_work_queue(&engine->breadcrumbs.irq_work);
214 }
215 
216 void intel_engine_breadcrumbs_irq(struct intel_engine_cs *engine);
217 
218 void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
219 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
220 
221 void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
222 				    struct drm_printer *p);
223 
224 static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
225 {
226 	memset(batch, 0, 6 * sizeof(u32));
227 
228 	batch[0] = GFX_OP_PIPE_CONTROL(6);
229 	batch[1] = flags;
230 	batch[2] = offset;
231 
232 	return batch + 6;
233 }
234 
235 static inline u32 *
236 gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
237 {
238 	/* We're using qword write, offset should be aligned to 8 bytes. */
239 	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
240 
241 	/* w/a for post sync ops following a GPGPU operation we
242 	 * need a prior CS_STALL, which is emitted by the flush
243 	 * following the batch.
244 	 */
245 	*cs++ = GFX_OP_PIPE_CONTROL(6);
246 	*cs++ = flags | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;
247 	*cs++ = gtt_offset;
248 	*cs++ = 0;
249 	*cs++ = value;
250 	/* We're thrashing one dword of HWS. */
251 	*cs++ = 0;
252 
253 	return cs;
254 }
255 
256 static inline u32 *
257 gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
258 {
259 	/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
260 	GEM_BUG_ON(gtt_offset & (1 << 5));
261 	/* Offset should be aligned to 8 bytes for both (QW/DW) write types */
262 	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
263 
264 	*cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW | flags;
265 	*cs++ = gtt_offset | MI_FLUSH_DW_USE_GTT;
266 	*cs++ = 0;
267 	*cs++ = value;
268 
269 	return cs;
270 }
271 
272 static inline void __intel_engine_reset(struct intel_engine_cs *engine,
273 					bool stalled)
274 {
275 	if (engine->reset.reset)
276 		engine->reset.reset(engine, stalled);
277 	engine->serial++; /* contexts lost */
278 }
279 
280 bool intel_engines_are_idle(struct intel_gt *gt);
281 bool intel_engine_is_idle(struct intel_engine_cs *engine);
282 void intel_engine_flush_submission(struct intel_engine_cs *engine);
283 
284 void intel_engines_reset_default_submission(struct intel_gt *gt);
285 
286 bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
287 
288 __printf(3, 4)
289 void intel_engine_dump(struct intel_engine_cs *engine,
290 		       struct drm_printer *m,
291 		       const char *header, ...);
292 
293 int intel_enable_engine_stats(struct intel_engine_cs *engine);
294 void intel_disable_engine_stats(struct intel_engine_cs *engine);
295 
296 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine);
297 
298 struct i915_request *
299 intel_engine_find_active_request(struct intel_engine_cs *engine);
300 
301 u32 intel_engine_context_size(struct drm_i915_private *i915, u8 class);
302 
303 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
304 
305 static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists)
306 {
307 	if (!execlists->preempt_hang.inject_hang)
308 		return false;
309 
310 	complete(&execlists->preempt_hang.completion);
311 	return true;
312 }
313 
314 #else
315 
316 static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists)
317 {
318 	return false;
319 }
320 
321 #endif
322 
323 void intel_engine_init_active(struct intel_engine_cs *engine,
324 			      unsigned int subclass);
325 #define ENGINE_PHYSICAL	0
326 #define ENGINE_MOCK	1
327 #define ENGINE_VIRTUAL	2
328 
329 static inline bool
330 intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
331 {
332 	if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT))
333 		return false;
334 
335 	return intel_engine_has_preemption(engine);
336 }
337 
338 static inline bool
339 intel_engine_has_timeslices(const struct intel_engine_cs *engine)
340 {
341 	if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
342 		return false;
343 
344 	return intel_engine_has_semaphores(engine);
345 }
346 
347 #endif /* _INTEL_RINGBUFFER_H_ */
348