1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2019 Intel Corporation 5 */ 6 7 #ifndef __INTEL_CONTEXT_TYPES__ 8 #define __INTEL_CONTEXT_TYPES__ 9 10 #include <linux/average.h> 11 #include <linux/kref.h> 12 #include <linux/list.h> 13 #include <linux/mutex.h> 14 #include <linux/types.h> 15 16 #include "i915_active_types.h" 17 #include "i915_utils.h" 18 #include "intel_engine_types.h" 19 #include "intel_sseu.h" 20 21 #define CONTEXT_REDZONE POISON_INUSE 22 23 DECLARE_EWMA(runtime, 3, 8); 24 25 struct i915_gem_context; 26 struct i915_gem_ww_ctx; 27 struct i915_vma; 28 struct intel_context; 29 struct intel_ring; 30 31 struct intel_context_ops { 32 int (*alloc)(struct intel_context *ce); 33 34 int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void **vaddr); 35 int (*pin)(struct intel_context *ce, void *vaddr); 36 void (*unpin)(struct intel_context *ce); 37 void (*post_unpin)(struct intel_context *ce); 38 39 void (*enter)(struct intel_context *ce); 40 void (*exit)(struct intel_context *ce); 41 42 void (*reset)(struct intel_context *ce); 43 void (*destroy)(struct kref *kref); 44 }; 45 46 struct intel_context { 47 struct kref ref; 48 49 struct intel_engine_cs *engine; 50 struct intel_engine_cs *inflight; 51 #define intel_context_inflight(ce) ptr_mask_bits(READ_ONCE((ce)->inflight), 2) 52 #define intel_context_inflight_count(ce) ptr_unmask_bits(READ_ONCE((ce)->inflight), 2) 53 54 struct i915_address_space *vm; 55 struct i915_gem_context __rcu *gem_context; 56 57 struct list_head signal_link; 58 struct list_head signals; 59 60 struct i915_vma *state; 61 struct intel_ring *ring; 62 struct intel_timeline *timeline; 63 64 unsigned long flags; 65 #define CONTEXT_BARRIER_BIT 0 66 #define CONTEXT_ALLOC_BIT 1 67 #define CONTEXT_VALID_BIT 2 68 #define CONTEXT_CLOSED_BIT 3 69 #define CONTEXT_USE_SEMAPHORES 4 70 #define CONTEXT_BANNED 5 71 #define CONTEXT_FORCE_SINGLE_SUBMISSION 6 72 #define CONTEXT_NOPREEMPT 7 73 74 u32 *lrc_reg_state; 75 union { 76 struct { 77 u32 lrca; 78 u32 ccid; 79 }; 80 u64 desc; 81 } lrc; 82 u32 tag; /* cookie passed to HW to track this context on submission */ 83 84 /* Time on GPU as tracked by the hw. */ 85 struct { 86 struct ewma_runtime avg; 87 u64 total; 88 u32 last; 89 I915_SELFTEST_DECLARE(u32 num_underflow); 90 I915_SELFTEST_DECLARE(u32 max_underflow); 91 } runtime; 92 93 unsigned int active_count; /* protected by timeline->mutex */ 94 95 atomic_t pin_count; 96 struct mutex pin_mutex; /* guards pinning and associated on-gpuing */ 97 98 /** 99 * active: Active tracker for the rq activity (inc. external) on this 100 * intel_context object. 101 */ 102 struct i915_active active; 103 104 const struct intel_context_ops *ops; 105 106 /** sseu: Control eu/slice partitioning */ 107 struct intel_sseu sseu; 108 109 u8 wa_bb_page; /* if set, page num reserved for context workarounds */ 110 }; 111 112 #endif /* __INTEL_CONTEXT_TYPES__ */ 113