1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014 Intel Corporation 4 */ 5 6 #ifndef __GEN8_ENGINE_CS_H__ 7 #define __GEN8_ENGINE_CS_H__ 8 9 #include <linux/string.h> 10 #include <linux/types.h> 11 12 #include "i915_gem.h" /* GEM_BUG_ON */ 13 #include "intel_gt_regs.h" 14 #include "intel_gpu_commands.h" 15 16 struct i915_request; 17 18 int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode); 19 int gen11_emit_flush_rcs(struct i915_request *rq, u32 mode); 20 int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode); 21 22 int gen8_emit_flush_xcs(struct i915_request *rq, u32 mode); 23 int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode); 24 25 int gen8_emit_init_breadcrumb(struct i915_request *rq); 26 27 int gen8_emit_bb_start_noarb(struct i915_request *rq, 28 u64 offset, u32 len, 29 const unsigned int flags); 30 int gen8_emit_bb_start(struct i915_request *rq, 31 u64 offset, u32 len, 32 const unsigned int flags); 33 34 int gen125_emit_bb_start_noarb(struct i915_request *rq, 35 u64 offset, u32 len, 36 const unsigned int flags); 37 int gen125_emit_bb_start(struct i915_request *rq, 38 u64 offset, u32 len, 39 const unsigned int flags); 40 41 u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs); 42 u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs); 43 44 u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs); 45 u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs); 46 u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs); 47 48 u32 *gen12_emit_aux_table_inv(u32 *cs, const i915_reg_t inv_reg); 49 50 static inline u32 * 51 __gen8_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset) 52 { 53 memset(batch, 0, 6 * sizeof(u32)); 54 55 batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0; 56 batch[1] = flags1; 57 batch[2] = offset; 58 59 return batch + 6; 60 } 61 62 static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset) 63 { 64 return __gen8_emit_pipe_control(batch, 0, flags, offset); 65 } 66 67 static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset) 68 { 69 return __gen8_emit_pipe_control(batch, flags0, flags1, offset); 70 } 71 72 static inline u32 * 73 __gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1) 74 { 75 *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0; 76 *cs++ = flags1 | PIPE_CONTROL_QW_WRITE; 77 *cs++ = offset; 78 *cs++ = 0; 79 *cs++ = value; 80 *cs++ = 0; /* We're thrashing one extra dword. */ 81 82 return cs; 83 } 84 85 static inline u32* 86 gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags) 87 { 88 /* We're using qword write, offset should be aligned to 8 bytes. */ 89 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8)); 90 91 return __gen8_emit_write_rcs(cs, 92 value, 93 gtt_offset, 94 0, 95 flags | PIPE_CONTROL_GLOBAL_GTT_IVB); 96 } 97 98 static inline u32* 99 gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1) 100 { 101 /* We're using qword write, offset should be aligned to 8 bytes. */ 102 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8)); 103 104 return __gen8_emit_write_rcs(cs, 105 value, 106 gtt_offset, 107 flags0, 108 flags1 | PIPE_CONTROL_GLOBAL_GTT_IVB); 109 } 110 111 static inline u32 * 112 __gen8_emit_flush_dw(u32 *cs, u32 value, u32 gtt_offset, u32 flags) 113 { 114 *cs++ = (MI_FLUSH_DW + 1) | flags; 115 *cs++ = gtt_offset; 116 *cs++ = 0; 117 *cs++ = value; 118 119 return cs; 120 } 121 122 static inline u32 * 123 gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags) 124 { 125 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ 126 GEM_BUG_ON(gtt_offset & (1 << 5)); 127 /* Offset should be aligned to 8 bytes for both (QW/DW) write types */ 128 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8)); 129 130 return __gen8_emit_flush_dw(cs, 131 value, 132 gtt_offset | MI_FLUSH_DW_USE_GTT, 133 flags | MI_FLUSH_DW_OP_STOREDW); 134 } 135 136 #endif /* __GEN8_ENGINE_CS_H__ */ 137