1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014 Intel Corporation 4 */ 5 6 #include "gen8_engine_cs.h" 7 #include "i915_drv.h" 8 #include "intel_gpu_commands.h" 9 #include "intel_gt_regs.h" 10 #include "intel_lrc.h" 11 #include "intel_ring.h" 12 13 int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode) 14 { 15 bool vf_flush_wa = false, dc_flush_wa = false; 16 u32 *cs, flags = 0; 17 int len; 18 19 flags |= PIPE_CONTROL_CS_STALL; 20 21 if (mode & EMIT_FLUSH) { 22 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 23 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 24 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; 25 flags |= PIPE_CONTROL_FLUSH_ENABLE; 26 } 27 28 if (mode & EMIT_INVALIDATE) { 29 flags |= PIPE_CONTROL_TLB_INVALIDATE; 30 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 31 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 32 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 33 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 34 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 35 flags |= PIPE_CONTROL_QW_WRITE; 36 flags |= PIPE_CONTROL_STORE_DATA_INDEX; 37 38 /* 39 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL 40 * pipe control. 41 */ 42 if (GRAPHICS_VER(rq->engine->i915) == 9) 43 vf_flush_wa = true; 44 45 /* WaForGAMHang:kbl */ 46 if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0)) 47 dc_flush_wa = true; 48 } 49 50 len = 6; 51 52 if (vf_flush_wa) 53 len += 6; 54 55 if (dc_flush_wa) 56 len += 12; 57 58 cs = intel_ring_begin(rq, len); 59 if (IS_ERR(cs)) 60 return PTR_ERR(cs); 61 62 if (vf_flush_wa) 63 cs = gen8_emit_pipe_control(cs, 0, 0); 64 65 if (dc_flush_wa) 66 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, 67 0); 68 69 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); 70 71 if (dc_flush_wa) 72 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); 73 74 intel_ring_advance(rq, cs); 75 76 return 0; 77 } 78 79 int gen8_emit_flush_xcs(struct i915_request *rq, u32 mode) 80 { 81 u32 cmd, *cs; 82 83 cs = intel_ring_begin(rq, 4); 84 if (IS_ERR(cs)) 85 return PTR_ERR(cs); 86 87 cmd = MI_FLUSH_DW + 1; 88 89 /* 90 * We always require a command barrier so that subsequent 91 * commands, such as breadcrumb interrupts, are strictly ordered 92 * wrt the contents of the write cache being flushed to memory 93 * (and thus being coherent from the CPU). 94 */ 95 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; 96 97 if (mode & EMIT_INVALIDATE) { 98 cmd |= MI_INVALIDATE_TLB; 99 if (rq->engine->class == VIDEO_DECODE_CLASS) 100 cmd |= MI_INVALIDATE_BSD; 101 } 102 103 *cs++ = cmd; 104 *cs++ = LRC_PPHWSP_SCRATCH_ADDR; 105 *cs++ = 0; /* upper addr */ 106 *cs++ = 0; /* value */ 107 intel_ring_advance(rq, cs); 108 109 return 0; 110 } 111 112 int gen11_emit_flush_rcs(struct i915_request *rq, u32 mode) 113 { 114 if (mode & EMIT_FLUSH) { 115 u32 *cs; 116 u32 flags = 0; 117 118 flags |= PIPE_CONTROL_CS_STALL; 119 120 flags |= PIPE_CONTROL_TILE_CACHE_FLUSH; 121 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 122 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 123 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; 124 flags |= PIPE_CONTROL_FLUSH_ENABLE; 125 flags |= PIPE_CONTROL_QW_WRITE; 126 flags |= PIPE_CONTROL_STORE_DATA_INDEX; 127 128 cs = intel_ring_begin(rq, 6); 129 if (IS_ERR(cs)) 130 return PTR_ERR(cs); 131 132 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); 133 intel_ring_advance(rq, cs); 134 } 135 136 if (mode & EMIT_INVALIDATE) { 137 u32 *cs; 138 u32 flags = 0; 139 140 flags |= PIPE_CONTROL_CS_STALL; 141 142 flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE; 143 flags |= PIPE_CONTROL_TLB_INVALIDATE; 144 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 145 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 146 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 147 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 148 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 149 flags |= PIPE_CONTROL_QW_WRITE; 150 flags |= PIPE_CONTROL_STORE_DATA_INDEX; 151 152 cs = intel_ring_begin(rq, 6); 153 if (IS_ERR(cs)) 154 return PTR_ERR(cs); 155 156 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); 157 intel_ring_advance(rq, cs); 158 } 159 160 return 0; 161 } 162 163 static u32 preparser_disable(bool state) 164 { 165 return MI_ARB_CHECK | 1 << 8 | state; 166 } 167 168 static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine) 169 { 170 static const i915_reg_t vd[] = { 171 GEN12_VD0_AUX_NV, 172 GEN12_VD1_AUX_NV, 173 GEN12_VD2_AUX_NV, 174 GEN12_VD3_AUX_NV, 175 }; 176 177 static const i915_reg_t ve[] = { 178 GEN12_VE0_AUX_NV, 179 GEN12_VE1_AUX_NV, 180 }; 181 182 if (engine->class == VIDEO_DECODE_CLASS) 183 return vd[engine->instance]; 184 185 if (engine->class == VIDEO_ENHANCEMENT_CLASS) 186 return ve[engine->instance]; 187 188 GEM_BUG_ON("unknown aux_inv reg\n"); 189 return INVALID_MMIO_REG; 190 } 191 192 static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs) 193 { 194 *cs++ = MI_LOAD_REGISTER_IMM(1); 195 *cs++ = i915_mmio_reg_offset(inv_reg); 196 *cs++ = AUX_INV; 197 *cs++ = MI_NOOP; 198 199 return cs; 200 } 201 202 int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) 203 { 204 struct intel_engine_cs *engine = rq->engine; 205 206 if (mode & EMIT_FLUSH) { 207 u32 flags = 0; 208 u32 *cs; 209 210 flags |= PIPE_CONTROL_TILE_CACHE_FLUSH; 211 flags |= PIPE_CONTROL_FLUSH_L3; 212 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 213 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 214 /* Wa_1409600907:tgl,adl-p */ 215 flags |= PIPE_CONTROL_DEPTH_STALL; 216 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; 217 flags |= PIPE_CONTROL_FLUSH_ENABLE; 218 219 flags |= PIPE_CONTROL_STORE_DATA_INDEX; 220 flags |= PIPE_CONTROL_QW_WRITE; 221 222 flags |= PIPE_CONTROL_CS_STALL; 223 224 if (engine->class == COMPUTE_CLASS) 225 flags &= ~PIPE_CONTROL_3D_FLAGS; 226 227 cs = intel_ring_begin(rq, 6); 228 if (IS_ERR(cs)) 229 return PTR_ERR(cs); 230 231 cs = gen12_emit_pipe_control(cs, 232 PIPE_CONTROL0_HDC_PIPELINE_FLUSH, 233 flags, LRC_PPHWSP_SCRATCH_ADDR); 234 intel_ring_advance(rq, cs); 235 } 236 237 if (mode & EMIT_INVALIDATE) { 238 u32 flags = 0; 239 u32 *cs; 240 241 flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE; 242 flags |= PIPE_CONTROL_TLB_INVALIDATE; 243 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 244 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 245 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 246 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 247 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 248 249 flags |= PIPE_CONTROL_STORE_DATA_INDEX; 250 flags |= PIPE_CONTROL_QW_WRITE; 251 252 flags |= PIPE_CONTROL_CS_STALL; 253 254 if (engine->class == COMPUTE_CLASS) 255 flags &= ~PIPE_CONTROL_3D_FLAGS; 256 257 cs = intel_ring_begin(rq, 8 + 4); 258 if (IS_ERR(cs)) 259 return PTR_ERR(cs); 260 261 /* 262 * Prevent the pre-parser from skipping past the TLB 263 * invalidate and loading a stale page for the batch 264 * buffer / request payload. 265 */ 266 *cs++ = preparser_disable(true); 267 268 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); 269 270 /* hsdes: 1809175790 */ 271 cs = gen12_emit_aux_table_inv(GEN12_GFX_CCS_AUX_NV, cs); 272 273 *cs++ = preparser_disable(false); 274 intel_ring_advance(rq, cs); 275 } 276 277 return 0; 278 } 279 280 int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) 281 { 282 intel_engine_mask_t aux_inv = 0; 283 u32 cmd, *cs; 284 285 cmd = 4; 286 if (mode & EMIT_INVALIDATE) 287 cmd += 2; 288 if (mode & EMIT_INVALIDATE) 289 aux_inv = rq->engine->mask & ~BIT(BCS0); 290 if (aux_inv) 291 cmd += 2 * hweight32(aux_inv) + 2; 292 293 cs = intel_ring_begin(rq, cmd); 294 if (IS_ERR(cs)) 295 return PTR_ERR(cs); 296 297 if (mode & EMIT_INVALIDATE) 298 *cs++ = preparser_disable(true); 299 300 cmd = MI_FLUSH_DW + 1; 301 302 /* 303 * We always require a command barrier so that subsequent 304 * commands, such as breadcrumb interrupts, are strictly ordered 305 * wrt the contents of the write cache being flushed to memory 306 * (and thus being coherent from the CPU). 307 */ 308 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; 309 310 if (mode & EMIT_INVALIDATE) { 311 cmd |= MI_INVALIDATE_TLB; 312 if (rq->engine->class == VIDEO_DECODE_CLASS) 313 cmd |= MI_INVALIDATE_BSD; 314 } 315 316 *cs++ = cmd; 317 *cs++ = LRC_PPHWSP_SCRATCH_ADDR; 318 *cs++ = 0; /* upper addr */ 319 *cs++ = 0; /* value */ 320 321 if (aux_inv) { /* hsdes: 1809175790 */ 322 struct intel_engine_cs *engine; 323 unsigned int tmp; 324 325 *cs++ = MI_LOAD_REGISTER_IMM(hweight32(aux_inv)); 326 for_each_engine_masked(engine, rq->engine->gt, aux_inv, tmp) { 327 *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine)); 328 *cs++ = AUX_INV; 329 } 330 *cs++ = MI_NOOP; 331 } 332 333 if (mode & EMIT_INVALIDATE) 334 *cs++ = preparser_disable(false); 335 336 intel_ring_advance(rq, cs); 337 338 return 0; 339 } 340 341 static u32 preempt_address(struct intel_engine_cs *engine) 342 { 343 return (i915_ggtt_offset(engine->status_page.vma) + 344 I915_GEM_HWS_PREEMPT_ADDR); 345 } 346 347 static u32 hwsp_offset(const struct i915_request *rq) 348 { 349 const struct intel_timeline *tl; 350 351 /* Before the request is executed, the timeline is fixed */ 352 tl = rcu_dereference_protected(rq->timeline, 353 !i915_request_signaled(rq)); 354 355 /* See the comment in i915_request_active_seqno(). */ 356 return page_mask_bits(tl->hwsp_offset) + offset_in_page(rq->hwsp_seqno); 357 } 358 359 int gen8_emit_init_breadcrumb(struct i915_request *rq) 360 { 361 u32 *cs; 362 363 GEM_BUG_ON(i915_request_has_initial_breadcrumb(rq)); 364 if (!i915_request_timeline(rq)->has_initial_breadcrumb) 365 return 0; 366 367 cs = intel_ring_begin(rq, 6); 368 if (IS_ERR(cs)) 369 return PTR_ERR(cs); 370 371 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; 372 *cs++ = hwsp_offset(rq); 373 *cs++ = 0; 374 *cs++ = rq->fence.seqno - 1; 375 376 /* 377 * Check if we have been preempted before we even get started. 378 * 379 * After this point i915_request_started() reports true, even if 380 * we get preempted and so are no longer running. 381 * 382 * i915_request_started() is used during preemption processing 383 * to decide if the request is currently inside the user payload 384 * or spinning on a kernel semaphore (or earlier). For no-preemption 385 * requests, we do allow preemption on the semaphore before the user 386 * payload, but do not allow preemption once the request is started. 387 * 388 * i915_request_started() is similarly used during GPU hangs to 389 * determine if the user's payload was guilty, and if so, the 390 * request is banned. Before the request is started, it is assumed 391 * to be unharmed and an innocent victim of another's hang. 392 */ 393 *cs++ = MI_NOOP; 394 *cs++ = MI_ARB_CHECK; 395 396 intel_ring_advance(rq, cs); 397 398 /* Record the updated position of the request's payload */ 399 rq->infix = intel_ring_offset(rq, cs); 400 401 __set_bit(I915_FENCE_FLAG_INITIAL_BREADCRUMB, &rq->fence.flags); 402 403 return 0; 404 } 405 406 int gen8_emit_bb_start_noarb(struct i915_request *rq, 407 u64 offset, u32 len, 408 const unsigned int flags) 409 { 410 u32 *cs; 411 412 cs = intel_ring_begin(rq, 4); 413 if (IS_ERR(cs)) 414 return PTR_ERR(cs); 415 416 /* 417 * WaDisableCtxRestoreArbitration:bdw,chv 418 * 419 * We don't need to perform MI_ARB_ENABLE as often as we do (in 420 * particular all the gen that do not need the w/a at all!), if we 421 * took care to make sure that on every switch into this context 422 * (both ordinary and for preemption) that arbitrartion was enabled 423 * we would be fine. However, for gen8 there is another w/a that 424 * requires us to not preempt inside GPGPU execution, so we keep 425 * arbitration disabled for gen8 batches. Arbitration will be 426 * re-enabled before we close the request 427 * (engine->emit_fini_breadcrumb). 428 */ 429 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 430 431 /* FIXME(BDW+): Address space and security selectors. */ 432 *cs++ = MI_BATCH_BUFFER_START_GEN8 | 433 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)); 434 *cs++ = lower_32_bits(offset); 435 *cs++ = upper_32_bits(offset); 436 437 intel_ring_advance(rq, cs); 438 439 return 0; 440 } 441 442 int gen8_emit_bb_start(struct i915_request *rq, 443 u64 offset, u32 len, 444 const unsigned int flags) 445 { 446 u32 *cs; 447 448 if (unlikely(i915_request_has_nopreempt(rq))) 449 return gen8_emit_bb_start_noarb(rq, offset, len, flags); 450 451 cs = intel_ring_begin(rq, 6); 452 if (IS_ERR(cs)) 453 return PTR_ERR(cs); 454 455 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 456 457 *cs++ = MI_BATCH_BUFFER_START_GEN8 | 458 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)); 459 *cs++ = lower_32_bits(offset); 460 *cs++ = upper_32_bits(offset); 461 462 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 463 *cs++ = MI_NOOP; 464 465 intel_ring_advance(rq, cs); 466 467 return 0; 468 } 469 470 static void assert_request_valid(struct i915_request *rq) 471 { 472 struct intel_ring *ring __maybe_unused = rq->ring; 473 474 /* Can we unwind this request without appearing to go forwards? */ 475 GEM_BUG_ON(intel_ring_direction(ring, rq->wa_tail, rq->head) <= 0); 476 } 477 478 /* 479 * Reserve space for 2 NOOPs at the end of each request to be 480 * used as a workaround for not being allowed to do lite 481 * restore with HEAD==TAIL (WaIdleLiteRestore). 482 */ 483 static u32 *gen8_emit_wa_tail(struct i915_request *rq, u32 *cs) 484 { 485 /* Ensure there's always at least one preemption point per-request. */ 486 *cs++ = MI_ARB_CHECK; 487 *cs++ = MI_NOOP; 488 rq->wa_tail = intel_ring_offset(rq, cs); 489 490 /* Check that entire request is less than half the ring */ 491 assert_request_valid(rq); 492 493 return cs; 494 } 495 496 static u32 *emit_preempt_busywait(struct i915_request *rq, u32 *cs) 497 { 498 *cs++ = MI_ARB_CHECK; /* trigger IDLE->ACTIVE first */ 499 *cs++ = MI_SEMAPHORE_WAIT | 500 MI_SEMAPHORE_GLOBAL_GTT | 501 MI_SEMAPHORE_POLL | 502 MI_SEMAPHORE_SAD_EQ_SDD; 503 *cs++ = 0; 504 *cs++ = preempt_address(rq->engine); 505 *cs++ = 0; 506 *cs++ = MI_NOOP; 507 508 return cs; 509 } 510 511 static __always_inline u32* 512 gen8_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs) 513 { 514 *cs++ = MI_USER_INTERRUPT; 515 516 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 517 if (intel_engine_has_semaphores(rq->engine) && 518 !intel_uc_uses_guc_submission(&rq->engine->gt->uc)) 519 cs = emit_preempt_busywait(rq, cs); 520 521 rq->tail = intel_ring_offset(rq, cs); 522 assert_ring_tail_valid(rq->ring, rq->tail); 523 524 return gen8_emit_wa_tail(rq, cs); 525 } 526 527 static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs) 528 { 529 return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0); 530 } 531 532 u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs) 533 { 534 return gen8_emit_fini_breadcrumb_tail(rq, emit_xcs_breadcrumb(rq, cs)); 535 } 536 537 u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) 538 { 539 cs = gen8_emit_pipe_control(cs, 540 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | 541 PIPE_CONTROL_DEPTH_CACHE_FLUSH | 542 PIPE_CONTROL_DC_FLUSH_ENABLE, 543 0); 544 545 /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */ 546 cs = gen8_emit_ggtt_write_rcs(cs, 547 rq->fence.seqno, 548 hwsp_offset(rq), 549 PIPE_CONTROL_FLUSH_ENABLE | 550 PIPE_CONTROL_CS_STALL); 551 552 return gen8_emit_fini_breadcrumb_tail(rq, cs); 553 } 554 555 u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) 556 { 557 cs = gen8_emit_ggtt_write_rcs(cs, 558 rq->fence.seqno, 559 hwsp_offset(rq), 560 PIPE_CONTROL_CS_STALL | 561 PIPE_CONTROL_TILE_CACHE_FLUSH | 562 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | 563 PIPE_CONTROL_DEPTH_CACHE_FLUSH | 564 PIPE_CONTROL_DC_FLUSH_ENABLE | 565 PIPE_CONTROL_FLUSH_ENABLE); 566 567 return gen8_emit_fini_breadcrumb_tail(rq, cs); 568 } 569 570 /* 571 * Note that the CS instruction pre-parser will not stall on the breadcrumb 572 * flush and will continue pre-fetching the instructions after it before the 573 * memory sync is completed. On pre-gen12 HW, the pre-parser will stop at 574 * BB_START/END instructions, so, even though we might pre-fetch the pre-amble 575 * of the next request before the memory has been flushed, we're guaranteed that 576 * we won't access the batch itself too early. 577 * However, on gen12+ the parser can pre-fetch across the BB_START/END commands, 578 * so, if the current request is modifying an instruction in the next request on 579 * the same intel_context, we might pre-fetch and then execute the pre-update 580 * instruction. To avoid this, the users of self-modifying code should either 581 * disable the parser around the code emitting the memory writes, via a new flag 582 * added to MI_ARB_CHECK, or emit the writes from a different intel_context. For 583 * the in-kernel use-cases we've opted to use a separate context, see 584 * reloc_gpu() as an example. 585 * All the above applies only to the instructions themselves. Non-inline data 586 * used by the instructions is not pre-fetched. 587 */ 588 589 static u32 *gen12_emit_preempt_busywait(struct i915_request *rq, u32 *cs) 590 { 591 *cs++ = MI_ARB_CHECK; /* trigger IDLE->ACTIVE first */ 592 *cs++ = MI_SEMAPHORE_WAIT_TOKEN | 593 MI_SEMAPHORE_GLOBAL_GTT | 594 MI_SEMAPHORE_POLL | 595 MI_SEMAPHORE_SAD_EQ_SDD; 596 *cs++ = 0; 597 *cs++ = preempt_address(rq->engine); 598 *cs++ = 0; 599 *cs++ = 0; 600 601 return cs; 602 } 603 604 static __always_inline u32* 605 gen12_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs) 606 { 607 *cs++ = MI_USER_INTERRUPT; 608 609 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 610 if (intel_engine_has_semaphores(rq->engine) && 611 !intel_uc_uses_guc_submission(&rq->engine->gt->uc)) 612 cs = gen12_emit_preempt_busywait(rq, cs); 613 614 rq->tail = intel_ring_offset(rq, cs); 615 assert_ring_tail_valid(rq->ring, rq->tail); 616 617 return gen8_emit_wa_tail(rq, cs); 618 } 619 620 u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs) 621 { 622 /* XXX Stalling flush before seqno write; post-sync not */ 623 cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0)); 624 return gen12_emit_fini_breadcrumb_tail(rq, cs); 625 } 626 627 u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) 628 { 629 struct drm_i915_private *i915 = rq->engine->i915; 630 u32 flags = (PIPE_CONTROL_CS_STALL | 631 PIPE_CONTROL_TILE_CACHE_FLUSH | 632 PIPE_CONTROL_FLUSH_L3 | 633 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | 634 PIPE_CONTROL_DEPTH_CACHE_FLUSH | 635 PIPE_CONTROL_DC_FLUSH_ENABLE | 636 PIPE_CONTROL_FLUSH_ENABLE); 637 638 if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) 639 /* Wa_1409600907 */ 640 flags |= PIPE_CONTROL_DEPTH_STALL; 641 642 if (rq->engine->class == COMPUTE_CLASS) 643 flags &= ~PIPE_CONTROL_3D_FLAGS; 644 645 cs = gen12_emit_ggtt_write_rcs(cs, 646 rq->fence.seqno, 647 hwsp_offset(rq), 648 PIPE_CONTROL0_HDC_PIPELINE_FLUSH, 649 flags); 650 651 return gen12_emit_fini_breadcrumb_tail(rq, cs); 652 } 653