1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014 Intel Corporation 4 */ 5 6 #include "gen8_engine_cs.h" 7 #include "i915_drv.h" 8 #include "intel_gpu_commands.h" 9 #include "intel_gt_regs.h" 10 #include "intel_lrc.h" 11 #include "intel_ring.h" 12 13 int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode) 14 { 15 bool vf_flush_wa = false, dc_flush_wa = false; 16 u32 *cs, flags = 0; 17 int len; 18 19 flags |= PIPE_CONTROL_CS_STALL; 20 21 if (mode & EMIT_FLUSH) { 22 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 23 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 24 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; 25 flags |= PIPE_CONTROL_FLUSH_ENABLE; 26 } 27 28 if (mode & EMIT_INVALIDATE) { 29 flags |= PIPE_CONTROL_TLB_INVALIDATE; 30 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 31 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 32 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 33 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 34 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 35 flags |= PIPE_CONTROL_QW_WRITE; 36 flags |= PIPE_CONTROL_STORE_DATA_INDEX; 37 38 /* 39 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL 40 * pipe control. 41 */ 42 if (GRAPHICS_VER(rq->engine->i915) == 9) 43 vf_flush_wa = true; 44 45 /* WaForGAMHang:kbl */ 46 if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0)) 47 dc_flush_wa = true; 48 } 49 50 len = 6; 51 52 if (vf_flush_wa) 53 len += 6; 54 55 if (dc_flush_wa) 56 len += 12; 57 58 cs = intel_ring_begin(rq, len); 59 if (IS_ERR(cs)) 60 return PTR_ERR(cs); 61 62 if (vf_flush_wa) 63 cs = gen8_emit_pipe_control(cs, 0, 0); 64 65 if (dc_flush_wa) 66 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, 67 0); 68 69 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); 70 71 if (dc_flush_wa) 72 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); 73 74 intel_ring_advance(rq, cs); 75 76 return 0; 77 } 78 79 int gen8_emit_flush_xcs(struct i915_request *rq, u32 mode) 80 { 81 u32 cmd, *cs; 82 83 cs = intel_ring_begin(rq, 4); 84 if (IS_ERR(cs)) 85 return PTR_ERR(cs); 86 87 cmd = MI_FLUSH_DW + 1; 88 89 /* 90 * We always require a command barrier so that subsequent 91 * commands, such as breadcrumb interrupts, are strictly ordered 92 * wrt the contents of the write cache being flushed to memory 93 * (and thus being coherent from the CPU). 94 */ 95 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; 96 97 if (mode & EMIT_INVALIDATE) { 98 cmd |= MI_INVALIDATE_TLB; 99 if (rq->engine->class == VIDEO_DECODE_CLASS) 100 cmd |= MI_INVALIDATE_BSD; 101 } 102 103 *cs++ = cmd; 104 *cs++ = LRC_PPHWSP_SCRATCH_ADDR; 105 *cs++ = 0; /* upper addr */ 106 *cs++ = 0; /* value */ 107 intel_ring_advance(rq, cs); 108 109 return 0; 110 } 111 112 int gen11_emit_flush_rcs(struct i915_request *rq, u32 mode) 113 { 114 if (mode & EMIT_FLUSH) { 115 u32 *cs; 116 u32 flags = 0; 117 118 flags |= PIPE_CONTROL_CS_STALL; 119 120 flags |= PIPE_CONTROL_TILE_CACHE_FLUSH; 121 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 122 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 123 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; 124 flags |= PIPE_CONTROL_FLUSH_ENABLE; 125 flags |= PIPE_CONTROL_QW_WRITE; 126 flags |= PIPE_CONTROL_STORE_DATA_INDEX; 127 128 cs = intel_ring_begin(rq, 6); 129 if (IS_ERR(cs)) 130 return PTR_ERR(cs); 131 132 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); 133 intel_ring_advance(rq, cs); 134 } 135 136 if (mode & EMIT_INVALIDATE) { 137 u32 *cs; 138 u32 flags = 0; 139 140 flags |= PIPE_CONTROL_CS_STALL; 141 142 flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE; 143 flags |= PIPE_CONTROL_TLB_INVALIDATE; 144 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 145 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 146 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 147 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 148 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 149 flags |= PIPE_CONTROL_QW_WRITE; 150 flags |= PIPE_CONTROL_STORE_DATA_INDEX; 151 152 cs = intel_ring_begin(rq, 6); 153 if (IS_ERR(cs)) 154 return PTR_ERR(cs); 155 156 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); 157 intel_ring_advance(rq, cs); 158 } 159 160 return 0; 161 } 162 163 static u32 preparser_disable(bool state) 164 { 165 return MI_ARB_CHECK | 1 << 8 | state; 166 } 167 168 static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine) 169 { 170 static const i915_reg_t vd[] = { 171 GEN12_VD0_AUX_NV, 172 GEN12_VD1_AUX_NV, 173 GEN12_VD2_AUX_NV, 174 GEN12_VD3_AUX_NV, 175 }; 176 177 static const i915_reg_t ve[] = { 178 GEN12_VE0_AUX_NV, 179 GEN12_VE1_AUX_NV, 180 }; 181 182 if (engine->class == VIDEO_DECODE_CLASS) 183 return vd[engine->instance]; 184 185 if (engine->class == VIDEO_ENHANCEMENT_CLASS) 186 return ve[engine->instance]; 187 188 GEM_BUG_ON("unknown aux_inv reg\n"); 189 return INVALID_MMIO_REG; 190 } 191 192 static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs) 193 { 194 *cs++ = MI_LOAD_REGISTER_IMM(1); 195 *cs++ = i915_mmio_reg_offset(inv_reg); 196 *cs++ = AUX_INV; 197 *cs++ = MI_NOOP; 198 199 return cs; 200 } 201 202 int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) 203 { 204 if (mode & EMIT_FLUSH) { 205 u32 flags = 0; 206 u32 *cs; 207 208 flags |= PIPE_CONTROL_TILE_CACHE_FLUSH; 209 flags |= PIPE_CONTROL_FLUSH_L3; 210 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 211 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 212 /* Wa_1409600907:tgl,adl-p */ 213 flags |= PIPE_CONTROL_DEPTH_STALL; 214 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; 215 flags |= PIPE_CONTROL_FLUSH_ENABLE; 216 217 flags |= PIPE_CONTROL_STORE_DATA_INDEX; 218 flags |= PIPE_CONTROL_QW_WRITE; 219 220 flags |= PIPE_CONTROL_CS_STALL; 221 222 cs = intel_ring_begin(rq, 6); 223 if (IS_ERR(cs)) 224 return PTR_ERR(cs); 225 226 cs = gen12_emit_pipe_control(cs, 227 PIPE_CONTROL0_HDC_PIPELINE_FLUSH, 228 flags, LRC_PPHWSP_SCRATCH_ADDR); 229 intel_ring_advance(rq, cs); 230 } 231 232 if (mode & EMIT_INVALIDATE) { 233 u32 flags = 0; 234 u32 *cs; 235 236 flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE; 237 flags |= PIPE_CONTROL_TLB_INVALIDATE; 238 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 239 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 240 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 241 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 242 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 243 244 flags |= PIPE_CONTROL_STORE_DATA_INDEX; 245 flags |= PIPE_CONTROL_QW_WRITE; 246 247 flags |= PIPE_CONTROL_CS_STALL; 248 249 cs = intel_ring_begin(rq, 8 + 4); 250 if (IS_ERR(cs)) 251 return PTR_ERR(cs); 252 253 /* 254 * Prevent the pre-parser from skipping past the TLB 255 * invalidate and loading a stale page for the batch 256 * buffer / request payload. 257 */ 258 *cs++ = preparser_disable(true); 259 260 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); 261 262 /* hsdes: 1809175790 */ 263 cs = gen12_emit_aux_table_inv(GEN12_GFX_CCS_AUX_NV, cs); 264 265 *cs++ = preparser_disable(false); 266 intel_ring_advance(rq, cs); 267 } 268 269 return 0; 270 } 271 272 int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) 273 { 274 intel_engine_mask_t aux_inv = 0; 275 u32 cmd, *cs; 276 277 cmd = 4; 278 if (mode & EMIT_INVALIDATE) 279 cmd += 2; 280 if (mode & EMIT_INVALIDATE) 281 aux_inv = rq->engine->mask & ~BIT(BCS0); 282 if (aux_inv) 283 cmd += 2 * hweight32(aux_inv) + 2; 284 285 cs = intel_ring_begin(rq, cmd); 286 if (IS_ERR(cs)) 287 return PTR_ERR(cs); 288 289 if (mode & EMIT_INVALIDATE) 290 *cs++ = preparser_disable(true); 291 292 cmd = MI_FLUSH_DW + 1; 293 294 /* 295 * We always require a command barrier so that subsequent 296 * commands, such as breadcrumb interrupts, are strictly ordered 297 * wrt the contents of the write cache being flushed to memory 298 * (and thus being coherent from the CPU). 299 */ 300 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; 301 302 if (mode & EMIT_INVALIDATE) { 303 cmd |= MI_INVALIDATE_TLB; 304 if (rq->engine->class == VIDEO_DECODE_CLASS) 305 cmd |= MI_INVALIDATE_BSD; 306 } 307 308 *cs++ = cmd; 309 *cs++ = LRC_PPHWSP_SCRATCH_ADDR; 310 *cs++ = 0; /* upper addr */ 311 *cs++ = 0; /* value */ 312 313 if (aux_inv) { /* hsdes: 1809175790 */ 314 struct intel_engine_cs *engine; 315 unsigned int tmp; 316 317 *cs++ = MI_LOAD_REGISTER_IMM(hweight32(aux_inv)); 318 for_each_engine_masked(engine, rq->engine->gt, aux_inv, tmp) { 319 *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine)); 320 *cs++ = AUX_INV; 321 } 322 *cs++ = MI_NOOP; 323 } 324 325 if (mode & EMIT_INVALIDATE) 326 *cs++ = preparser_disable(false); 327 328 intel_ring_advance(rq, cs); 329 330 return 0; 331 } 332 333 static u32 preempt_address(struct intel_engine_cs *engine) 334 { 335 return (i915_ggtt_offset(engine->status_page.vma) + 336 I915_GEM_HWS_PREEMPT_ADDR); 337 } 338 339 static u32 hwsp_offset(const struct i915_request *rq) 340 { 341 const struct intel_timeline *tl; 342 343 /* Before the request is executed, the timeline is fixed */ 344 tl = rcu_dereference_protected(rq->timeline, 345 !i915_request_signaled(rq)); 346 347 /* See the comment in i915_request_active_seqno(). */ 348 return page_mask_bits(tl->hwsp_offset) + offset_in_page(rq->hwsp_seqno); 349 } 350 351 int gen8_emit_init_breadcrumb(struct i915_request *rq) 352 { 353 u32 *cs; 354 355 GEM_BUG_ON(i915_request_has_initial_breadcrumb(rq)); 356 if (!i915_request_timeline(rq)->has_initial_breadcrumb) 357 return 0; 358 359 cs = intel_ring_begin(rq, 6); 360 if (IS_ERR(cs)) 361 return PTR_ERR(cs); 362 363 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; 364 *cs++ = hwsp_offset(rq); 365 *cs++ = 0; 366 *cs++ = rq->fence.seqno - 1; 367 368 /* 369 * Check if we have been preempted before we even get started. 370 * 371 * After this point i915_request_started() reports true, even if 372 * we get preempted and so are no longer running. 373 * 374 * i915_request_started() is used during preemption processing 375 * to decide if the request is currently inside the user payload 376 * or spinning on a kernel semaphore (or earlier). For no-preemption 377 * requests, we do allow preemption on the semaphore before the user 378 * payload, but do not allow preemption once the request is started. 379 * 380 * i915_request_started() is similarly used during GPU hangs to 381 * determine if the user's payload was guilty, and if so, the 382 * request is banned. Before the request is started, it is assumed 383 * to be unharmed and an innocent victim of another's hang. 384 */ 385 *cs++ = MI_NOOP; 386 *cs++ = MI_ARB_CHECK; 387 388 intel_ring_advance(rq, cs); 389 390 /* Record the updated position of the request's payload */ 391 rq->infix = intel_ring_offset(rq, cs); 392 393 __set_bit(I915_FENCE_FLAG_INITIAL_BREADCRUMB, &rq->fence.flags); 394 395 return 0; 396 } 397 398 int gen8_emit_bb_start_noarb(struct i915_request *rq, 399 u64 offset, u32 len, 400 const unsigned int flags) 401 { 402 u32 *cs; 403 404 cs = intel_ring_begin(rq, 4); 405 if (IS_ERR(cs)) 406 return PTR_ERR(cs); 407 408 /* 409 * WaDisableCtxRestoreArbitration:bdw,chv 410 * 411 * We don't need to perform MI_ARB_ENABLE as often as we do (in 412 * particular all the gen that do not need the w/a at all!), if we 413 * took care to make sure that on every switch into this context 414 * (both ordinary and for preemption) that arbitrartion was enabled 415 * we would be fine. However, for gen8 there is another w/a that 416 * requires us to not preempt inside GPGPU execution, so we keep 417 * arbitration disabled for gen8 batches. Arbitration will be 418 * re-enabled before we close the request 419 * (engine->emit_fini_breadcrumb). 420 */ 421 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 422 423 /* FIXME(BDW+): Address space and security selectors. */ 424 *cs++ = MI_BATCH_BUFFER_START_GEN8 | 425 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)); 426 *cs++ = lower_32_bits(offset); 427 *cs++ = upper_32_bits(offset); 428 429 intel_ring_advance(rq, cs); 430 431 return 0; 432 } 433 434 int gen8_emit_bb_start(struct i915_request *rq, 435 u64 offset, u32 len, 436 const unsigned int flags) 437 { 438 u32 *cs; 439 440 if (unlikely(i915_request_has_nopreempt(rq))) 441 return gen8_emit_bb_start_noarb(rq, offset, len, flags); 442 443 cs = intel_ring_begin(rq, 6); 444 if (IS_ERR(cs)) 445 return PTR_ERR(cs); 446 447 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 448 449 *cs++ = MI_BATCH_BUFFER_START_GEN8 | 450 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)); 451 *cs++ = lower_32_bits(offset); 452 *cs++ = upper_32_bits(offset); 453 454 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 455 *cs++ = MI_NOOP; 456 457 intel_ring_advance(rq, cs); 458 459 return 0; 460 } 461 462 static void assert_request_valid(struct i915_request *rq) 463 { 464 struct intel_ring *ring __maybe_unused = rq->ring; 465 466 /* Can we unwind this request without appearing to go forwards? */ 467 GEM_BUG_ON(intel_ring_direction(ring, rq->wa_tail, rq->head) <= 0); 468 } 469 470 /* 471 * Reserve space for 2 NOOPs at the end of each request to be 472 * used as a workaround for not being allowed to do lite 473 * restore with HEAD==TAIL (WaIdleLiteRestore). 474 */ 475 static u32 *gen8_emit_wa_tail(struct i915_request *rq, u32 *cs) 476 { 477 /* Ensure there's always at least one preemption point per-request. */ 478 *cs++ = MI_ARB_CHECK; 479 *cs++ = MI_NOOP; 480 rq->wa_tail = intel_ring_offset(rq, cs); 481 482 /* Check that entire request is less than half the ring */ 483 assert_request_valid(rq); 484 485 return cs; 486 } 487 488 static u32 *emit_preempt_busywait(struct i915_request *rq, u32 *cs) 489 { 490 *cs++ = MI_ARB_CHECK; /* trigger IDLE->ACTIVE first */ 491 *cs++ = MI_SEMAPHORE_WAIT | 492 MI_SEMAPHORE_GLOBAL_GTT | 493 MI_SEMAPHORE_POLL | 494 MI_SEMAPHORE_SAD_EQ_SDD; 495 *cs++ = 0; 496 *cs++ = preempt_address(rq->engine); 497 *cs++ = 0; 498 *cs++ = MI_NOOP; 499 500 return cs; 501 } 502 503 static __always_inline u32* 504 gen8_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs) 505 { 506 *cs++ = MI_USER_INTERRUPT; 507 508 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 509 if (intel_engine_has_semaphores(rq->engine) && 510 !intel_uc_uses_guc_submission(&rq->engine->gt->uc)) 511 cs = emit_preempt_busywait(rq, cs); 512 513 rq->tail = intel_ring_offset(rq, cs); 514 assert_ring_tail_valid(rq->ring, rq->tail); 515 516 return gen8_emit_wa_tail(rq, cs); 517 } 518 519 static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs) 520 { 521 return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0); 522 } 523 524 u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs) 525 { 526 return gen8_emit_fini_breadcrumb_tail(rq, emit_xcs_breadcrumb(rq, cs)); 527 } 528 529 u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) 530 { 531 cs = gen8_emit_pipe_control(cs, 532 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | 533 PIPE_CONTROL_DEPTH_CACHE_FLUSH | 534 PIPE_CONTROL_DC_FLUSH_ENABLE, 535 0); 536 537 /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */ 538 cs = gen8_emit_ggtt_write_rcs(cs, 539 rq->fence.seqno, 540 hwsp_offset(rq), 541 PIPE_CONTROL_FLUSH_ENABLE | 542 PIPE_CONTROL_CS_STALL); 543 544 return gen8_emit_fini_breadcrumb_tail(rq, cs); 545 } 546 547 u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) 548 { 549 cs = gen8_emit_ggtt_write_rcs(cs, 550 rq->fence.seqno, 551 hwsp_offset(rq), 552 PIPE_CONTROL_CS_STALL | 553 PIPE_CONTROL_TILE_CACHE_FLUSH | 554 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | 555 PIPE_CONTROL_DEPTH_CACHE_FLUSH | 556 PIPE_CONTROL_DC_FLUSH_ENABLE | 557 PIPE_CONTROL_FLUSH_ENABLE); 558 559 return gen8_emit_fini_breadcrumb_tail(rq, cs); 560 } 561 562 /* 563 * Note that the CS instruction pre-parser will not stall on the breadcrumb 564 * flush and will continue pre-fetching the instructions after it before the 565 * memory sync is completed. On pre-gen12 HW, the pre-parser will stop at 566 * BB_START/END instructions, so, even though we might pre-fetch the pre-amble 567 * of the next request before the memory has been flushed, we're guaranteed that 568 * we won't access the batch itself too early. 569 * However, on gen12+ the parser can pre-fetch across the BB_START/END commands, 570 * so, if the current request is modifying an instruction in the next request on 571 * the same intel_context, we might pre-fetch and then execute the pre-update 572 * instruction. To avoid this, the users of self-modifying code should either 573 * disable the parser around the code emitting the memory writes, via a new flag 574 * added to MI_ARB_CHECK, or emit the writes from a different intel_context. For 575 * the in-kernel use-cases we've opted to use a separate context, see 576 * reloc_gpu() as an example. 577 * All the above applies only to the instructions themselves. Non-inline data 578 * used by the instructions is not pre-fetched. 579 */ 580 581 static u32 *gen12_emit_preempt_busywait(struct i915_request *rq, u32 *cs) 582 { 583 *cs++ = MI_ARB_CHECK; /* trigger IDLE->ACTIVE first */ 584 *cs++ = MI_SEMAPHORE_WAIT_TOKEN | 585 MI_SEMAPHORE_GLOBAL_GTT | 586 MI_SEMAPHORE_POLL | 587 MI_SEMAPHORE_SAD_EQ_SDD; 588 *cs++ = 0; 589 *cs++ = preempt_address(rq->engine); 590 *cs++ = 0; 591 *cs++ = 0; 592 593 return cs; 594 } 595 596 static __always_inline u32* 597 gen12_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs) 598 { 599 *cs++ = MI_USER_INTERRUPT; 600 601 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 602 if (intel_engine_has_semaphores(rq->engine) && 603 !intel_uc_uses_guc_submission(&rq->engine->gt->uc)) 604 cs = gen12_emit_preempt_busywait(rq, cs); 605 606 rq->tail = intel_ring_offset(rq, cs); 607 assert_ring_tail_valid(rq->ring, rq->tail); 608 609 return gen8_emit_wa_tail(rq, cs); 610 } 611 612 u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs) 613 { 614 /* XXX Stalling flush before seqno write; post-sync not */ 615 cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0)); 616 return gen12_emit_fini_breadcrumb_tail(rq, cs); 617 } 618 619 u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) 620 { 621 cs = gen12_emit_ggtt_write_rcs(cs, 622 rq->fence.seqno, 623 hwsp_offset(rq), 624 PIPE_CONTROL0_HDC_PIPELINE_FLUSH, 625 PIPE_CONTROL_CS_STALL | 626 PIPE_CONTROL_TILE_CACHE_FLUSH | 627 PIPE_CONTROL_FLUSH_L3 | 628 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | 629 PIPE_CONTROL_DEPTH_CACHE_FLUSH | 630 /* Wa_1409600907:tgl */ 631 PIPE_CONTROL_DEPTH_STALL | 632 PIPE_CONTROL_DC_FLUSH_ENABLE | 633 PIPE_CONTROL_FLUSH_ENABLE); 634 635 return gen12_emit_fini_breadcrumb_tail(rq, cs); 636 } 637