1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2008,2010 Intel Corporation 5 */ 6 7 #include <linux/dma-resv.h> 8 #include <linux/highmem.h> 9 #include <linux/sync_file.h> 10 #include <linux/uaccess.h> 11 12 #include <drm/drm_syncobj.h> 13 14 #include "display/intel_frontbuffer.h" 15 16 #include "gem/i915_gem_ioctls.h" 17 #include "gt/intel_context.h" 18 #include "gt/intel_gpu_commands.h" 19 #include "gt/intel_gt.h" 20 #include "gt/intel_gt_buffer_pool.h" 21 #include "gt/intel_gt_pm.h" 22 #include "gt/intel_ring.h" 23 24 #include "pxp/intel_pxp.h" 25 26 #include "i915_cmd_parser.h" 27 #include "i915_drv.h" 28 #include "i915_file_private.h" 29 #include "i915_gem_clflush.h" 30 #include "i915_gem_context.h" 31 #include "i915_gem_evict.h" 32 #include "i915_gem_ioctls.h" 33 #include "i915_trace.h" 34 #include "i915_user_extensions.h" 35 36 struct eb_vma { 37 struct i915_vma *vma; 38 unsigned int flags; 39 40 /** This vma's place in the execbuf reservation list */ 41 struct drm_i915_gem_exec_object2 *exec; 42 struct list_head bind_link; 43 struct list_head reloc_link; 44 45 struct hlist_node node; 46 u32 handle; 47 }; 48 49 enum { 50 FORCE_CPU_RELOC = 1, 51 FORCE_GTT_RELOC, 52 FORCE_GPU_RELOC, 53 #define DBG_FORCE_RELOC 0 /* choose one of the above! */ 54 }; 55 56 /* __EXEC_OBJECT_ flags > BIT(29) defined in i915_vma.h */ 57 #define __EXEC_OBJECT_HAS_PIN BIT(29) 58 #define __EXEC_OBJECT_HAS_FENCE BIT(28) 59 #define __EXEC_OBJECT_USERPTR_INIT BIT(27) 60 #define __EXEC_OBJECT_NEEDS_MAP BIT(26) 61 #define __EXEC_OBJECT_NEEDS_BIAS BIT(25) 62 #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 25) /* all of the above + */ 63 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE) 64 65 #define __EXEC_HAS_RELOC BIT(31) 66 #define __EXEC_ENGINE_PINNED BIT(30) 67 #define __EXEC_USERPTR_USED BIT(29) 68 #define __EXEC_INTERNAL_FLAGS (~0u << 29) 69 #define UPDATE PIN_OFFSET_FIXED 70 71 #define BATCH_OFFSET_BIAS (256*1024) 72 73 #define __I915_EXEC_ILLEGAL_FLAGS \ 74 (__I915_EXEC_UNKNOWN_FLAGS | \ 75 I915_EXEC_CONSTANTS_MASK | \ 76 I915_EXEC_RESOURCE_STREAMER) 77 78 /* Catch emission of unexpected errors for CI! */ 79 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) 80 #undef EINVAL 81 #define EINVAL ({ \ 82 DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \ 83 22; \ 84 }) 85 #endif 86 87 /** 88 * DOC: User command execution 89 * 90 * Userspace submits commands to be executed on the GPU as an instruction 91 * stream within a GEM object we call a batchbuffer. This instructions may 92 * refer to other GEM objects containing auxiliary state such as kernels, 93 * samplers, render targets and even secondary batchbuffers. Userspace does 94 * not know where in the GPU memory these objects reside and so before the 95 * batchbuffer is passed to the GPU for execution, those addresses in the 96 * batchbuffer and auxiliary objects are updated. This is known as relocation, 97 * or patching. To try and avoid having to relocate each object on the next 98 * execution, userspace is told the location of those objects in this pass, 99 * but this remains just a hint as the kernel may choose a new location for 100 * any object in the future. 101 * 102 * At the level of talking to the hardware, submitting a batchbuffer for the 103 * GPU to execute is to add content to a buffer from which the HW 104 * command streamer is reading. 105 * 106 * 1. Add a command to load the HW context. For Logical Ring Contexts, i.e. 107 * Execlists, this command is not placed on the same buffer as the 108 * remaining items. 109 * 110 * 2. Add a command to invalidate caches to the buffer. 111 * 112 * 3. Add a batchbuffer start command to the buffer; the start command is 113 * essentially a token together with the GPU address of the batchbuffer 114 * to be executed. 115 * 116 * 4. Add a pipeline flush to the buffer. 117 * 118 * 5. Add a memory write command to the buffer to record when the GPU 119 * is done executing the batchbuffer. The memory write writes the 120 * global sequence number of the request, ``i915_request::global_seqno``; 121 * the i915 driver uses the current value in the register to determine 122 * if the GPU has completed the batchbuffer. 123 * 124 * 6. Add a user interrupt command to the buffer. This command instructs 125 * the GPU to issue an interrupt when the command, pipeline flush and 126 * memory write are completed. 127 * 128 * 7. Inform the hardware of the additional commands added to the buffer 129 * (by updating the tail pointer). 130 * 131 * Processing an execbuf ioctl is conceptually split up into a few phases. 132 * 133 * 1. Validation - Ensure all the pointers, handles and flags are valid. 134 * 2. Reservation - Assign GPU address space for every object 135 * 3. Relocation - Update any addresses to point to the final locations 136 * 4. Serialisation - Order the request with respect to its dependencies 137 * 5. Construction - Construct a request to execute the batchbuffer 138 * 6. Submission (at some point in the future execution) 139 * 140 * Reserving resources for the execbuf is the most complicated phase. We 141 * neither want to have to migrate the object in the address space, nor do 142 * we want to have to update any relocations pointing to this object. Ideally, 143 * we want to leave the object where it is and for all the existing relocations 144 * to match. If the object is given a new address, or if userspace thinks the 145 * object is elsewhere, we have to parse all the relocation entries and update 146 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that 147 * all the target addresses in all of its objects match the value in the 148 * relocation entries and that they all match the presumed offsets given by the 149 * list of execbuffer objects. Using this knowledge, we know that if we haven't 150 * moved any buffers, all the relocation entries are valid and we can skip 151 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU 152 * hang.) The requirement for using I915_EXEC_NO_RELOC are: 153 * 154 * The addresses written in the objects must match the corresponding 155 * reloc.presumed_offset which in turn must match the corresponding 156 * execobject.offset. 157 * 158 * Any render targets written to in the batch must be flagged with 159 * EXEC_OBJECT_WRITE. 160 * 161 * To avoid stalling, execobject.offset should match the current 162 * address of that object within the active context. 163 * 164 * The reservation is done is multiple phases. First we try and keep any 165 * object already bound in its current location - so as long as meets the 166 * constraints imposed by the new execbuffer. Any object left unbound after the 167 * first pass is then fitted into any available idle space. If an object does 168 * not fit, all objects are removed from the reservation and the process rerun 169 * after sorting the objects into a priority order (more difficult to fit 170 * objects are tried first). Failing that, the entire VM is cleared and we try 171 * to fit the execbuf once last time before concluding that it simply will not 172 * fit. 173 * 174 * A small complication to all of this is that we allow userspace not only to 175 * specify an alignment and a size for the object in the address space, but 176 * we also allow userspace to specify the exact offset. This objects are 177 * simpler to place (the location is known a priori) all we have to do is make 178 * sure the space is available. 179 * 180 * Once all the objects are in place, patching up the buried pointers to point 181 * to the final locations is a fairly simple job of walking over the relocation 182 * entry arrays, looking up the right address and rewriting the value into 183 * the object. Simple! ... The relocation entries are stored in user memory 184 * and so to access them we have to copy them into a local buffer. That copy 185 * has to avoid taking any pagefaults as they may lead back to a GEM object 186 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split 187 * the relocation into multiple passes. First we try to do everything within an 188 * atomic context (avoid the pagefaults) which requires that we never wait. If 189 * we detect that we may wait, or if we need to fault, then we have to fallback 190 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm 191 * bells yet?) Dropping the mutex means that we lose all the state we have 192 * built up so far for the execbuf and we must reset any global data. However, 193 * we do leave the objects pinned in their final locations - which is a 194 * potential issue for concurrent execbufs. Once we have left the mutex, we can 195 * allocate and copy all the relocation entries into a large array at our 196 * leisure, reacquire the mutex, reclaim all the objects and other state and 197 * then proceed to update any incorrect addresses with the objects. 198 * 199 * As we process the relocation entries, we maintain a record of whether the 200 * object is being written to. Using NORELOC, we expect userspace to provide 201 * this information instead. We also check whether we can skip the relocation 202 * by comparing the expected value inside the relocation entry with the target's 203 * final address. If they differ, we have to map the current object and rewrite 204 * the 4 or 8 byte pointer within. 205 * 206 * Serialising an execbuf is quite simple according to the rules of the GEM 207 * ABI. Execution within each context is ordered by the order of submission. 208 * Writes to any GEM object are in order of submission and are exclusive. Reads 209 * from a GEM object are unordered with respect to other reads, but ordered by 210 * writes. A write submitted after a read cannot occur before the read, and 211 * similarly any read submitted after a write cannot occur before the write. 212 * Writes are ordered between engines such that only one write occurs at any 213 * time (completing any reads beforehand) - using semaphores where available 214 * and CPU serialisation otherwise. Other GEM access obey the same rules, any 215 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU 216 * reads before starting, and any read (either using set-domain or pread) must 217 * flush all GPU writes before starting. (Note we only employ a barrier before, 218 * we currently rely on userspace not concurrently starting a new execution 219 * whilst reading or writing to an object. This may be an advantage or not 220 * depending on how much you trust userspace not to shoot themselves in the 221 * foot.) Serialisation may just result in the request being inserted into 222 * a DAG awaiting its turn, but most simple is to wait on the CPU until 223 * all dependencies are resolved. 224 * 225 * After all of that, is just a matter of closing the request and handing it to 226 * the hardware (well, leaving it in a queue to be executed). However, we also 227 * offer the ability for batchbuffers to be run with elevated privileges so 228 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.) 229 * Before any batch is given extra privileges we first must check that it 230 * contains no nefarious instructions, we check that each instruction is from 231 * our whitelist and all registers are also from an allowed list. We first 232 * copy the user's batchbuffer to a shadow (so that the user doesn't have 233 * access to it, either by the CPU or GPU as we scan it) and then parse each 234 * instruction. If everything is ok, we set a flag telling the hardware to run 235 * the batchbuffer in trusted mode, otherwise the ioctl is rejected. 236 */ 237 238 struct eb_fence { 239 struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */ 240 struct dma_fence *dma_fence; 241 u64 value; 242 struct dma_fence_chain *chain_fence; 243 }; 244 245 struct i915_execbuffer { 246 struct drm_i915_private *i915; /** i915 backpointer */ 247 struct drm_file *file; /** per-file lookup tables and limits */ 248 struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */ 249 struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */ 250 struct eb_vma *vma; 251 252 struct intel_gt *gt; /* gt for the execbuf */ 253 struct intel_context *context; /* logical state for the request */ 254 struct i915_gem_context *gem_context; /** caller's context */ 255 256 /** our requests to build */ 257 struct i915_request *requests[MAX_ENGINE_INSTANCE + 1]; 258 /** identity of the batch obj/vma */ 259 struct eb_vma *batches[MAX_ENGINE_INSTANCE + 1]; 260 struct i915_vma *trampoline; /** trampoline used for chaining */ 261 262 /** used for excl fence in dma_resv objects when > 1 BB submitted */ 263 struct dma_fence *composite_fence; 264 265 /** actual size of execobj[] as we may extend it for the cmdparser */ 266 unsigned int buffer_count; 267 268 /* number of batches in execbuf IOCTL */ 269 unsigned int num_batches; 270 271 /** list of vma not yet bound during reservation phase */ 272 struct list_head unbound; 273 274 /** list of vma that have execobj.relocation_count */ 275 struct list_head relocs; 276 277 struct i915_gem_ww_ctx ww; 278 279 /** 280 * Track the most recently used object for relocations, as we 281 * frequently have to perform multiple relocations within the same 282 * obj/page 283 */ 284 struct reloc_cache { 285 struct drm_mm_node node; /** temporary GTT binding */ 286 unsigned long vaddr; /** Current kmap address */ 287 unsigned long page; /** Currently mapped page index */ 288 unsigned int graphics_ver; /** Cached value of GRAPHICS_VER */ 289 bool use_64bit_reloc : 1; 290 bool has_llc : 1; 291 bool has_fence : 1; 292 bool needs_unfenced : 1; 293 } reloc_cache; 294 295 u64 invalid_flags; /** Set of execobj.flags that are invalid */ 296 297 /** Length of batch within object */ 298 u64 batch_len[MAX_ENGINE_INSTANCE + 1]; 299 u32 batch_start_offset; /** Location within object of batch */ 300 u32 batch_flags; /** Flags composed for emit_bb_start() */ 301 struct intel_gt_buffer_pool_node *batch_pool; /** pool node for batch buffer */ 302 303 /** 304 * Indicate either the size of the hastable used to resolve 305 * relocation handles, or if negative that we are using a direct 306 * index into the execobj[]. 307 */ 308 int lut_size; 309 struct hlist_head *buckets; /** ht for relocation handles */ 310 311 struct eb_fence *fences; 312 unsigned long num_fences; 313 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 314 struct i915_capture_list *capture_lists[MAX_ENGINE_INSTANCE + 1]; 315 #endif 316 }; 317 318 static int eb_parse(struct i915_execbuffer *eb); 319 static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle); 320 static void eb_unpin_engine(struct i915_execbuffer *eb); 321 static void eb_capture_release(struct i915_execbuffer *eb); 322 323 static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb) 324 { 325 return intel_engine_requires_cmd_parser(eb->context->engine) || 326 (intel_engine_using_cmd_parser(eb->context->engine) && 327 eb->args->batch_len); 328 } 329 330 static int eb_create(struct i915_execbuffer *eb) 331 { 332 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) { 333 unsigned int size = 1 + ilog2(eb->buffer_count); 334 335 /* 336 * Without a 1:1 association between relocation handles and 337 * the execobject[] index, we instead create a hashtable. 338 * We size it dynamically based on available memory, starting 339 * first with 1:1 assocative hash and scaling back until 340 * the allocation succeeds. 341 * 342 * Later on we use a positive lut_size to indicate we are 343 * using this hashtable, and a negative value to indicate a 344 * direct lookup. 345 */ 346 do { 347 gfp_t flags; 348 349 /* While we can still reduce the allocation size, don't 350 * raise a warning and allow the allocation to fail. 351 * On the last pass though, we want to try as hard 352 * as possible to perform the allocation and warn 353 * if it fails. 354 */ 355 flags = GFP_KERNEL; 356 if (size > 1) 357 flags |= __GFP_NORETRY | __GFP_NOWARN; 358 359 eb->buckets = kzalloc(sizeof(struct hlist_head) << size, 360 flags); 361 if (eb->buckets) 362 break; 363 } while (--size); 364 365 if (unlikely(!size)) 366 return -ENOMEM; 367 368 eb->lut_size = size; 369 } else { 370 eb->lut_size = -eb->buffer_count; 371 } 372 373 return 0; 374 } 375 376 static bool 377 eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry, 378 const struct i915_vma *vma, 379 unsigned int flags) 380 { 381 const u64 start = i915_vma_offset(vma); 382 const u64 size = i915_vma_size(vma); 383 384 if (size < entry->pad_to_size) 385 return true; 386 387 if (entry->alignment && !IS_ALIGNED(start, entry->alignment)) 388 return true; 389 390 if (flags & EXEC_OBJECT_PINNED && 391 start != entry->offset) 392 return true; 393 394 if (flags & __EXEC_OBJECT_NEEDS_BIAS && 395 start < BATCH_OFFSET_BIAS) 396 return true; 397 398 if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) && 399 (start + size + 4095) >> 32) 400 return true; 401 402 if (flags & __EXEC_OBJECT_NEEDS_MAP && 403 !i915_vma_is_map_and_fenceable(vma)) 404 return true; 405 406 return false; 407 } 408 409 static u64 eb_pin_flags(const struct drm_i915_gem_exec_object2 *entry, 410 unsigned int exec_flags) 411 { 412 u64 pin_flags = 0; 413 414 if (exec_flags & EXEC_OBJECT_NEEDS_GTT) 415 pin_flags |= PIN_GLOBAL; 416 417 /* 418 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, 419 * limit address to the first 4GBs for unflagged objects. 420 */ 421 if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)) 422 pin_flags |= PIN_ZONE_4G; 423 424 if (exec_flags & __EXEC_OBJECT_NEEDS_MAP) 425 pin_flags |= PIN_MAPPABLE; 426 427 if (exec_flags & EXEC_OBJECT_PINNED) 428 pin_flags |= entry->offset | PIN_OFFSET_FIXED; 429 else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS) 430 pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; 431 432 return pin_flags; 433 } 434 435 static inline int 436 eb_pin_vma(struct i915_execbuffer *eb, 437 const struct drm_i915_gem_exec_object2 *entry, 438 struct eb_vma *ev) 439 { 440 struct i915_vma *vma = ev->vma; 441 u64 pin_flags; 442 int err; 443 444 if (vma->node.size) 445 pin_flags = __i915_vma_offset(vma); 446 else 447 pin_flags = entry->offset & PIN_OFFSET_MASK; 448 449 pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED | PIN_VALIDATE; 450 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_GTT)) 451 pin_flags |= PIN_GLOBAL; 452 453 /* Attempt to reuse the current location if available */ 454 err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, pin_flags); 455 if (err == -EDEADLK) 456 return err; 457 458 if (unlikely(err)) { 459 if (entry->flags & EXEC_OBJECT_PINNED) 460 return err; 461 462 /* Failing that pick any _free_ space if suitable */ 463 err = i915_vma_pin_ww(vma, &eb->ww, 464 entry->pad_to_size, 465 entry->alignment, 466 eb_pin_flags(entry, ev->flags) | 467 PIN_USER | PIN_NOEVICT | PIN_VALIDATE); 468 if (unlikely(err)) 469 return err; 470 } 471 472 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) { 473 err = i915_vma_pin_fence(vma); 474 if (unlikely(err)) 475 return err; 476 477 if (vma->fence) 478 ev->flags |= __EXEC_OBJECT_HAS_FENCE; 479 } 480 481 ev->flags |= __EXEC_OBJECT_HAS_PIN; 482 if (eb_vma_misplaced(entry, vma, ev->flags)) 483 return -EBADSLT; 484 485 return 0; 486 } 487 488 static inline void 489 eb_unreserve_vma(struct eb_vma *ev) 490 { 491 if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE)) 492 __i915_vma_unpin_fence(ev->vma); 493 494 ev->flags &= ~__EXEC_OBJECT_RESERVED; 495 } 496 497 static int 498 eb_validate_vma(struct i915_execbuffer *eb, 499 struct drm_i915_gem_exec_object2 *entry, 500 struct i915_vma *vma) 501 { 502 /* Relocations are disallowed for all platforms after TGL-LP. This 503 * also covers all platforms with local memory. 504 */ 505 if (entry->relocation_count && 506 GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915)) 507 return -EINVAL; 508 509 if (unlikely(entry->flags & eb->invalid_flags)) 510 return -EINVAL; 511 512 if (unlikely(entry->alignment && 513 !is_power_of_2_u64(entry->alignment))) 514 return -EINVAL; 515 516 /* 517 * Offset can be used as input (EXEC_OBJECT_PINNED), reject 518 * any non-page-aligned or non-canonical addresses. 519 */ 520 if (unlikely(entry->flags & EXEC_OBJECT_PINNED && 521 entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK))) 522 return -EINVAL; 523 524 /* pad_to_size was once a reserved field, so sanitize it */ 525 if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) { 526 if (unlikely(offset_in_page(entry->pad_to_size))) 527 return -EINVAL; 528 } else { 529 entry->pad_to_size = 0; 530 } 531 /* 532 * From drm_mm perspective address space is continuous, 533 * so from this point we're always using non-canonical 534 * form internally. 535 */ 536 entry->offset = gen8_noncanonical_addr(entry->offset); 537 538 if (!eb->reloc_cache.has_fence) { 539 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; 540 } else { 541 if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE || 542 eb->reloc_cache.needs_unfenced) && 543 i915_gem_object_is_tiled(vma->obj)) 544 entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP; 545 } 546 547 return 0; 548 } 549 550 static inline bool 551 is_batch_buffer(struct i915_execbuffer *eb, unsigned int buffer_idx) 552 { 553 return eb->args->flags & I915_EXEC_BATCH_FIRST ? 554 buffer_idx < eb->num_batches : 555 buffer_idx >= eb->args->buffer_count - eb->num_batches; 556 } 557 558 static int 559 eb_add_vma(struct i915_execbuffer *eb, 560 unsigned int *current_batch, 561 unsigned int i, 562 struct i915_vma *vma) 563 { 564 struct drm_i915_private *i915 = eb->i915; 565 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; 566 struct eb_vma *ev = &eb->vma[i]; 567 568 ev->vma = vma; 569 ev->exec = entry; 570 ev->flags = entry->flags; 571 572 if (eb->lut_size > 0) { 573 ev->handle = entry->handle; 574 hlist_add_head(&ev->node, 575 &eb->buckets[hash_32(entry->handle, 576 eb->lut_size)]); 577 } 578 579 if (entry->relocation_count) 580 list_add_tail(&ev->reloc_link, &eb->relocs); 581 582 /* 583 * SNA is doing fancy tricks with compressing batch buffers, which leads 584 * to negative relocation deltas. Usually that works out ok since the 585 * relocate address is still positive, except when the batch is placed 586 * very low in the GTT. Ensure this doesn't happen. 587 * 588 * Note that actual hangs have only been observed on gen7, but for 589 * paranoia do it everywhere. 590 */ 591 if (is_batch_buffer(eb, i)) { 592 if (entry->relocation_count && 593 !(ev->flags & EXEC_OBJECT_PINNED)) 594 ev->flags |= __EXEC_OBJECT_NEEDS_BIAS; 595 if (eb->reloc_cache.has_fence) 596 ev->flags |= EXEC_OBJECT_NEEDS_FENCE; 597 598 eb->batches[*current_batch] = ev; 599 600 if (unlikely(ev->flags & EXEC_OBJECT_WRITE)) { 601 drm_dbg(&i915->drm, 602 "Attempting to use self-modifying batch buffer\n"); 603 return -EINVAL; 604 } 605 606 if (range_overflows_t(u64, 607 eb->batch_start_offset, 608 eb->args->batch_len, 609 ev->vma->size)) { 610 drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n"); 611 return -EINVAL; 612 } 613 614 if (eb->args->batch_len == 0) 615 eb->batch_len[*current_batch] = ev->vma->size - 616 eb->batch_start_offset; 617 else 618 eb->batch_len[*current_batch] = eb->args->batch_len; 619 if (unlikely(eb->batch_len[*current_batch] == 0)) { /* impossible! */ 620 drm_dbg(&i915->drm, "Invalid batch length\n"); 621 return -EINVAL; 622 } 623 624 ++*current_batch; 625 } 626 627 return 0; 628 } 629 630 static inline int use_cpu_reloc(const struct reloc_cache *cache, 631 const struct drm_i915_gem_object *obj) 632 { 633 if (!i915_gem_object_has_struct_page(obj)) 634 return false; 635 636 if (DBG_FORCE_RELOC == FORCE_CPU_RELOC) 637 return true; 638 639 if (DBG_FORCE_RELOC == FORCE_GTT_RELOC) 640 return false; 641 642 return (cache->has_llc || 643 obj->cache_dirty || 644 obj->cache_level != I915_CACHE_NONE); 645 } 646 647 static int eb_reserve_vma(struct i915_execbuffer *eb, 648 struct eb_vma *ev, 649 u64 pin_flags) 650 { 651 struct drm_i915_gem_exec_object2 *entry = ev->exec; 652 struct i915_vma *vma = ev->vma; 653 int err; 654 655 if (drm_mm_node_allocated(&vma->node) && 656 eb_vma_misplaced(entry, vma, ev->flags)) { 657 err = i915_vma_unbind(vma); 658 if (err) 659 return err; 660 } 661 662 err = i915_vma_pin_ww(vma, &eb->ww, 663 entry->pad_to_size, entry->alignment, 664 eb_pin_flags(entry, ev->flags) | pin_flags); 665 if (err) 666 return err; 667 668 if (entry->offset != i915_vma_offset(vma)) { 669 entry->offset = i915_vma_offset(vma) | UPDATE; 670 eb->args->flags |= __EXEC_HAS_RELOC; 671 } 672 673 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) { 674 err = i915_vma_pin_fence(vma); 675 if (unlikely(err)) 676 return err; 677 678 if (vma->fence) 679 ev->flags |= __EXEC_OBJECT_HAS_FENCE; 680 } 681 682 ev->flags |= __EXEC_OBJECT_HAS_PIN; 683 GEM_BUG_ON(eb_vma_misplaced(entry, vma, ev->flags)); 684 685 return 0; 686 } 687 688 static bool eb_unbind(struct i915_execbuffer *eb, bool force) 689 { 690 const unsigned int count = eb->buffer_count; 691 unsigned int i; 692 struct list_head last; 693 bool unpinned = false; 694 695 /* Resort *all* the objects into priority order */ 696 INIT_LIST_HEAD(&eb->unbound); 697 INIT_LIST_HEAD(&last); 698 699 for (i = 0; i < count; i++) { 700 struct eb_vma *ev = &eb->vma[i]; 701 unsigned int flags = ev->flags; 702 703 if (!force && flags & EXEC_OBJECT_PINNED && 704 flags & __EXEC_OBJECT_HAS_PIN) 705 continue; 706 707 unpinned = true; 708 eb_unreserve_vma(ev); 709 710 if (flags & EXEC_OBJECT_PINNED) 711 /* Pinned must have their slot */ 712 list_add(&ev->bind_link, &eb->unbound); 713 else if (flags & __EXEC_OBJECT_NEEDS_MAP) 714 /* Map require the lowest 256MiB (aperture) */ 715 list_add_tail(&ev->bind_link, &eb->unbound); 716 else if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)) 717 /* Prioritise 4GiB region for restricted bo */ 718 list_add(&ev->bind_link, &last); 719 else 720 list_add_tail(&ev->bind_link, &last); 721 } 722 723 list_splice_tail(&last, &eb->unbound); 724 return unpinned; 725 } 726 727 static int eb_reserve(struct i915_execbuffer *eb) 728 { 729 struct eb_vma *ev; 730 unsigned int pass; 731 int err = 0; 732 bool unpinned; 733 734 /* 735 * Attempt to pin all of the buffers into the GTT. 736 * This is done in 2 phases: 737 * 738 * 1. Unbind all objects that do not match the GTT constraints for 739 * the execbuffer (fenceable, mappable, alignment etc). 740 * 2. Bind new objects. 741 * 742 * This avoid unnecessary unbinding of later objects in order to make 743 * room for the earlier objects *unless* we need to defragment. 744 * 745 * Defragmenting is skipped if all objects are pinned at a fixed location. 746 */ 747 for (pass = 0; pass <= 2; pass++) { 748 int pin_flags = PIN_USER | PIN_VALIDATE; 749 750 if (pass == 0) 751 pin_flags |= PIN_NONBLOCK; 752 753 if (pass >= 1) 754 unpinned = eb_unbind(eb, pass == 2); 755 756 if (pass == 2) { 757 err = mutex_lock_interruptible(&eb->context->vm->mutex); 758 if (!err) { 759 err = i915_gem_evict_vm(eb->context->vm, &eb->ww); 760 mutex_unlock(&eb->context->vm->mutex); 761 } 762 if (err) 763 return err; 764 } 765 766 list_for_each_entry(ev, &eb->unbound, bind_link) { 767 err = eb_reserve_vma(eb, ev, pin_flags); 768 if (err) 769 break; 770 } 771 772 if (err != -ENOSPC) 773 break; 774 } 775 776 return err; 777 } 778 779 static int eb_select_context(struct i915_execbuffer *eb) 780 { 781 struct i915_gem_context *ctx; 782 783 ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1); 784 if (unlikely(IS_ERR(ctx))) 785 return PTR_ERR(ctx); 786 787 eb->gem_context = ctx; 788 if (i915_gem_context_has_full_ppgtt(ctx)) 789 eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT; 790 791 return 0; 792 } 793 794 static int __eb_add_lut(struct i915_execbuffer *eb, 795 u32 handle, struct i915_vma *vma) 796 { 797 struct i915_gem_context *ctx = eb->gem_context; 798 struct i915_lut_handle *lut; 799 int err; 800 801 lut = i915_lut_handle_alloc(); 802 if (unlikely(!lut)) 803 return -ENOMEM; 804 805 i915_vma_get(vma); 806 if (!atomic_fetch_inc(&vma->open_count)) 807 i915_vma_reopen(vma); 808 lut->handle = handle; 809 lut->ctx = ctx; 810 811 /* Check that the context hasn't been closed in the meantime */ 812 err = -EINTR; 813 if (!mutex_lock_interruptible(&ctx->lut_mutex)) { 814 if (likely(!i915_gem_context_is_closed(ctx))) 815 err = radix_tree_insert(&ctx->handles_vma, handle, vma); 816 else 817 err = -ENOENT; 818 if (err == 0) { /* And nor has this handle */ 819 struct drm_i915_gem_object *obj = vma->obj; 820 821 spin_lock(&obj->lut_lock); 822 if (idr_find(&eb->file->object_idr, handle) == obj) { 823 list_add(&lut->obj_link, &obj->lut_list); 824 } else { 825 radix_tree_delete(&ctx->handles_vma, handle); 826 err = -ENOENT; 827 } 828 spin_unlock(&obj->lut_lock); 829 } 830 mutex_unlock(&ctx->lut_mutex); 831 } 832 if (unlikely(err)) 833 goto err; 834 835 return 0; 836 837 err: 838 i915_vma_close(vma); 839 i915_vma_put(vma); 840 i915_lut_handle_free(lut); 841 return err; 842 } 843 844 static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle) 845 { 846 struct i915_address_space *vm = eb->context->vm; 847 848 do { 849 struct drm_i915_gem_object *obj; 850 struct i915_vma *vma; 851 int err; 852 853 rcu_read_lock(); 854 vma = radix_tree_lookup(&eb->gem_context->handles_vma, handle); 855 if (likely(vma && vma->vm == vm)) 856 vma = i915_vma_tryget(vma); 857 rcu_read_unlock(); 858 if (likely(vma)) 859 return vma; 860 861 obj = i915_gem_object_lookup(eb->file, handle); 862 if (unlikely(!obj)) 863 return ERR_PTR(-ENOENT); 864 865 /* 866 * If the user has opted-in for protected-object tracking, make 867 * sure the object encryption can be used. 868 * We only need to do this when the object is first used with 869 * this context, because the context itself will be banned when 870 * the protected objects become invalid. 871 */ 872 if (i915_gem_context_uses_protected_content(eb->gem_context) && 873 i915_gem_object_is_protected(obj)) { 874 err = intel_pxp_key_check(&vm->gt->pxp, obj, true); 875 if (err) { 876 i915_gem_object_put(obj); 877 return ERR_PTR(err); 878 } 879 } 880 881 vma = i915_vma_instance(obj, vm, NULL); 882 if (IS_ERR(vma)) { 883 i915_gem_object_put(obj); 884 return vma; 885 } 886 887 err = __eb_add_lut(eb, handle, vma); 888 if (likely(!err)) 889 return vma; 890 891 i915_gem_object_put(obj); 892 if (err != -EEXIST) 893 return ERR_PTR(err); 894 } while (1); 895 } 896 897 static int eb_lookup_vmas(struct i915_execbuffer *eb) 898 { 899 unsigned int i, current_batch = 0; 900 int err = 0; 901 902 INIT_LIST_HEAD(&eb->relocs); 903 904 for (i = 0; i < eb->buffer_count; i++) { 905 struct i915_vma *vma; 906 907 vma = eb_lookup_vma(eb, eb->exec[i].handle); 908 if (IS_ERR(vma)) { 909 err = PTR_ERR(vma); 910 goto err; 911 } 912 913 err = eb_validate_vma(eb, &eb->exec[i], vma); 914 if (unlikely(err)) { 915 i915_vma_put(vma); 916 goto err; 917 } 918 919 err = eb_add_vma(eb, ¤t_batch, i, vma); 920 if (err) 921 return err; 922 923 if (i915_gem_object_is_userptr(vma->obj)) { 924 err = i915_gem_object_userptr_submit_init(vma->obj); 925 if (err) { 926 if (i + 1 < eb->buffer_count) { 927 /* 928 * Execbuffer code expects last vma entry to be NULL, 929 * since we already initialized this entry, 930 * set the next value to NULL or we mess up 931 * cleanup handling. 932 */ 933 eb->vma[i + 1].vma = NULL; 934 } 935 936 return err; 937 } 938 939 eb->vma[i].flags |= __EXEC_OBJECT_USERPTR_INIT; 940 eb->args->flags |= __EXEC_USERPTR_USED; 941 } 942 } 943 944 return 0; 945 946 err: 947 eb->vma[i].vma = NULL; 948 return err; 949 } 950 951 static int eb_lock_vmas(struct i915_execbuffer *eb) 952 { 953 unsigned int i; 954 int err; 955 956 for (i = 0; i < eb->buffer_count; i++) { 957 struct eb_vma *ev = &eb->vma[i]; 958 struct i915_vma *vma = ev->vma; 959 960 err = i915_gem_object_lock(vma->obj, &eb->ww); 961 if (err) 962 return err; 963 } 964 965 return 0; 966 } 967 968 static int eb_validate_vmas(struct i915_execbuffer *eb) 969 { 970 unsigned int i; 971 int err; 972 973 INIT_LIST_HEAD(&eb->unbound); 974 975 err = eb_lock_vmas(eb); 976 if (err) 977 return err; 978 979 for (i = 0; i < eb->buffer_count; i++) { 980 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; 981 struct eb_vma *ev = &eb->vma[i]; 982 struct i915_vma *vma = ev->vma; 983 984 err = eb_pin_vma(eb, entry, ev); 985 if (err == -EDEADLK) 986 return err; 987 988 if (!err) { 989 if (entry->offset != i915_vma_offset(vma)) { 990 entry->offset = i915_vma_offset(vma) | UPDATE; 991 eb->args->flags |= __EXEC_HAS_RELOC; 992 } 993 } else { 994 eb_unreserve_vma(ev); 995 996 list_add_tail(&ev->bind_link, &eb->unbound); 997 if (drm_mm_node_allocated(&vma->node)) { 998 err = i915_vma_unbind(vma); 999 if (err) 1000 return err; 1001 } 1002 } 1003 1004 /* Reserve enough slots to accommodate composite fences */ 1005 err = dma_resv_reserve_fences(vma->obj->base.resv, eb->num_batches); 1006 if (err) 1007 return err; 1008 1009 GEM_BUG_ON(drm_mm_node_allocated(&vma->node) && 1010 eb_vma_misplaced(&eb->exec[i], vma, ev->flags)); 1011 } 1012 1013 if (!list_empty(&eb->unbound)) 1014 return eb_reserve(eb); 1015 1016 return 0; 1017 } 1018 1019 static struct eb_vma * 1020 eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) 1021 { 1022 if (eb->lut_size < 0) { 1023 if (handle >= -eb->lut_size) 1024 return NULL; 1025 return &eb->vma[handle]; 1026 } else { 1027 struct hlist_head *head; 1028 struct eb_vma *ev; 1029 1030 head = &eb->buckets[hash_32(handle, eb->lut_size)]; 1031 hlist_for_each_entry(ev, head, node) { 1032 if (ev->handle == handle) 1033 return ev; 1034 } 1035 return NULL; 1036 } 1037 } 1038 1039 static void eb_release_vmas(struct i915_execbuffer *eb, bool final) 1040 { 1041 const unsigned int count = eb->buffer_count; 1042 unsigned int i; 1043 1044 for (i = 0; i < count; i++) { 1045 struct eb_vma *ev = &eb->vma[i]; 1046 struct i915_vma *vma = ev->vma; 1047 1048 if (!vma) 1049 break; 1050 1051 eb_unreserve_vma(ev); 1052 1053 if (final) 1054 i915_vma_put(vma); 1055 } 1056 1057 eb_capture_release(eb); 1058 eb_unpin_engine(eb); 1059 } 1060 1061 static void eb_destroy(const struct i915_execbuffer *eb) 1062 { 1063 if (eb->lut_size > 0) 1064 kfree(eb->buckets); 1065 } 1066 1067 static inline u64 1068 relocation_target(const struct drm_i915_gem_relocation_entry *reloc, 1069 const struct i915_vma *target) 1070 { 1071 return gen8_canonical_addr((int)reloc->delta + i915_vma_offset(target)); 1072 } 1073 1074 static void reloc_cache_init(struct reloc_cache *cache, 1075 struct drm_i915_private *i915) 1076 { 1077 cache->page = -1; 1078 cache->vaddr = 0; 1079 /* Must be a variable in the struct to allow GCC to unroll. */ 1080 cache->graphics_ver = GRAPHICS_VER(i915); 1081 cache->has_llc = HAS_LLC(i915); 1082 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915); 1083 cache->has_fence = cache->graphics_ver < 4; 1084 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; 1085 cache->node.flags = 0; 1086 } 1087 1088 static inline void *unmask_page(unsigned long p) 1089 { 1090 return (void *)(uintptr_t)(p & PAGE_MASK); 1091 } 1092 1093 static inline unsigned int unmask_flags(unsigned long p) 1094 { 1095 return p & ~PAGE_MASK; 1096 } 1097 1098 #define KMAP 0x4 /* after CLFLUSH_FLAGS */ 1099 1100 static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache) 1101 { 1102 struct drm_i915_private *i915 = 1103 container_of(cache, struct i915_execbuffer, reloc_cache)->i915; 1104 return to_gt(i915)->ggtt; 1105 } 1106 1107 static void reloc_cache_unmap(struct reloc_cache *cache) 1108 { 1109 void *vaddr; 1110 1111 if (!cache->vaddr) 1112 return; 1113 1114 vaddr = unmask_page(cache->vaddr); 1115 if (cache->vaddr & KMAP) 1116 kunmap_atomic(vaddr); 1117 else 1118 io_mapping_unmap_atomic((void __iomem *)vaddr); 1119 } 1120 1121 static void reloc_cache_remap(struct reloc_cache *cache, 1122 struct drm_i915_gem_object *obj) 1123 { 1124 void *vaddr; 1125 1126 if (!cache->vaddr) 1127 return; 1128 1129 if (cache->vaddr & KMAP) { 1130 struct page *page = i915_gem_object_get_page(obj, cache->page); 1131 1132 vaddr = kmap_atomic(page); 1133 cache->vaddr = unmask_flags(cache->vaddr) | 1134 (unsigned long)vaddr; 1135 } else { 1136 struct i915_ggtt *ggtt = cache_to_ggtt(cache); 1137 unsigned long offset; 1138 1139 offset = cache->node.start; 1140 if (!drm_mm_node_allocated(&cache->node)) 1141 offset += cache->page << PAGE_SHIFT; 1142 1143 cache->vaddr = (unsigned long) 1144 io_mapping_map_atomic_wc(&ggtt->iomap, offset); 1145 } 1146 } 1147 1148 static void reloc_cache_reset(struct reloc_cache *cache, struct i915_execbuffer *eb) 1149 { 1150 void *vaddr; 1151 1152 if (!cache->vaddr) 1153 return; 1154 1155 vaddr = unmask_page(cache->vaddr); 1156 if (cache->vaddr & KMAP) { 1157 struct drm_i915_gem_object *obj = 1158 (struct drm_i915_gem_object *)cache->node.mm; 1159 if (cache->vaddr & CLFLUSH_AFTER) 1160 mb(); 1161 1162 kunmap_atomic(vaddr); 1163 i915_gem_object_finish_access(obj); 1164 } else { 1165 struct i915_ggtt *ggtt = cache_to_ggtt(cache); 1166 1167 intel_gt_flush_ggtt_writes(ggtt->vm.gt); 1168 io_mapping_unmap_atomic((void __iomem *)vaddr); 1169 1170 if (drm_mm_node_allocated(&cache->node)) { 1171 ggtt->vm.clear_range(&ggtt->vm, 1172 cache->node.start, 1173 cache->node.size); 1174 mutex_lock(&ggtt->vm.mutex); 1175 drm_mm_remove_node(&cache->node); 1176 mutex_unlock(&ggtt->vm.mutex); 1177 } else { 1178 i915_vma_unpin((struct i915_vma *)cache->node.mm); 1179 } 1180 } 1181 1182 cache->vaddr = 0; 1183 cache->page = -1; 1184 } 1185 1186 static void *reloc_kmap(struct drm_i915_gem_object *obj, 1187 struct reloc_cache *cache, 1188 unsigned long pageno) 1189 { 1190 void *vaddr; 1191 struct page *page; 1192 1193 if (cache->vaddr) { 1194 kunmap_atomic(unmask_page(cache->vaddr)); 1195 } else { 1196 unsigned int flushes; 1197 int err; 1198 1199 err = i915_gem_object_prepare_write(obj, &flushes); 1200 if (err) 1201 return ERR_PTR(err); 1202 1203 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); 1204 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); 1205 1206 cache->vaddr = flushes | KMAP; 1207 cache->node.mm = (void *)obj; 1208 if (flushes) 1209 mb(); 1210 } 1211 1212 page = i915_gem_object_get_page(obj, pageno); 1213 if (!obj->mm.dirty) 1214 set_page_dirty(page); 1215 1216 vaddr = kmap_atomic(page); 1217 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr; 1218 cache->page = pageno; 1219 1220 return vaddr; 1221 } 1222 1223 static void *reloc_iomap(struct i915_vma *batch, 1224 struct i915_execbuffer *eb, 1225 unsigned long page) 1226 { 1227 struct drm_i915_gem_object *obj = batch->obj; 1228 struct reloc_cache *cache = &eb->reloc_cache; 1229 struct i915_ggtt *ggtt = cache_to_ggtt(cache); 1230 unsigned long offset; 1231 void *vaddr; 1232 1233 if (cache->vaddr) { 1234 intel_gt_flush_ggtt_writes(ggtt->vm.gt); 1235 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr)); 1236 } else { 1237 struct i915_vma *vma = ERR_PTR(-ENODEV); 1238 int err; 1239 1240 if (i915_gem_object_is_tiled(obj)) 1241 return ERR_PTR(-EINVAL); 1242 1243 if (use_cpu_reloc(cache, obj)) 1244 return NULL; 1245 1246 err = i915_gem_object_set_to_gtt_domain(obj, true); 1247 if (err) 1248 return ERR_PTR(err); 1249 1250 /* 1251 * i915_gem_object_ggtt_pin_ww may attempt to remove the batch 1252 * VMA from the object list because we no longer pin. 1253 * 1254 * Only attempt to pin the batch buffer to ggtt if the current batch 1255 * is not inside ggtt, or the batch buffer is not misplaced. 1256 */ 1257 if (!i915_is_ggtt(batch->vm) || 1258 !i915_vma_misplaced(batch, 0, 0, PIN_MAPPABLE)) { 1259 vma = i915_gem_object_ggtt_pin_ww(obj, &eb->ww, NULL, 0, 0, 1260 PIN_MAPPABLE | 1261 PIN_NONBLOCK /* NOWARN */ | 1262 PIN_NOEVICT); 1263 } 1264 1265 if (vma == ERR_PTR(-EDEADLK)) 1266 return vma; 1267 1268 if (IS_ERR(vma)) { 1269 memset(&cache->node, 0, sizeof(cache->node)); 1270 mutex_lock(&ggtt->vm.mutex); 1271 err = drm_mm_insert_node_in_range 1272 (&ggtt->vm.mm, &cache->node, 1273 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE, 1274 0, ggtt->mappable_end, 1275 DRM_MM_INSERT_LOW); 1276 mutex_unlock(&ggtt->vm.mutex); 1277 if (err) /* no inactive aperture space, use cpu reloc */ 1278 return NULL; 1279 } else { 1280 cache->node.start = i915_ggtt_offset(vma); 1281 cache->node.mm = (void *)vma; 1282 } 1283 } 1284 1285 offset = cache->node.start; 1286 if (drm_mm_node_allocated(&cache->node)) { 1287 ggtt->vm.insert_page(&ggtt->vm, 1288 i915_gem_object_get_dma_address(obj, page), 1289 offset, I915_CACHE_NONE, 0); 1290 } else { 1291 offset += page << PAGE_SHIFT; 1292 } 1293 1294 vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap, 1295 offset); 1296 cache->page = page; 1297 cache->vaddr = (unsigned long)vaddr; 1298 1299 return vaddr; 1300 } 1301 1302 static void *reloc_vaddr(struct i915_vma *vma, 1303 struct i915_execbuffer *eb, 1304 unsigned long page) 1305 { 1306 struct reloc_cache *cache = &eb->reloc_cache; 1307 void *vaddr; 1308 1309 if (cache->page == page) { 1310 vaddr = unmask_page(cache->vaddr); 1311 } else { 1312 vaddr = NULL; 1313 if ((cache->vaddr & KMAP) == 0) 1314 vaddr = reloc_iomap(vma, eb, page); 1315 if (!vaddr) 1316 vaddr = reloc_kmap(vma->obj, cache, page); 1317 } 1318 1319 return vaddr; 1320 } 1321 1322 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) 1323 { 1324 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { 1325 if (flushes & CLFLUSH_BEFORE) 1326 drm_clflush_virt_range(addr, sizeof(*addr)); 1327 1328 *addr = value; 1329 1330 /* 1331 * Writes to the same cacheline are serialised by the CPU 1332 * (including clflush). On the write path, we only require 1333 * that it hits memory in an orderly fashion and place 1334 * mb barriers at the start and end of the relocation phase 1335 * to ensure ordering of clflush wrt to the system. 1336 */ 1337 if (flushes & CLFLUSH_AFTER) 1338 drm_clflush_virt_range(addr, sizeof(*addr)); 1339 } else 1340 *addr = value; 1341 } 1342 1343 static u64 1344 relocate_entry(struct i915_vma *vma, 1345 const struct drm_i915_gem_relocation_entry *reloc, 1346 struct i915_execbuffer *eb, 1347 const struct i915_vma *target) 1348 { 1349 u64 target_addr = relocation_target(reloc, target); 1350 u64 offset = reloc->offset; 1351 bool wide = eb->reloc_cache.use_64bit_reloc; 1352 void *vaddr; 1353 1354 repeat: 1355 vaddr = reloc_vaddr(vma, eb, 1356 offset >> PAGE_SHIFT); 1357 if (IS_ERR(vaddr)) 1358 return PTR_ERR(vaddr); 1359 1360 GEM_BUG_ON(!IS_ALIGNED(offset, sizeof(u32))); 1361 clflush_write32(vaddr + offset_in_page(offset), 1362 lower_32_bits(target_addr), 1363 eb->reloc_cache.vaddr); 1364 1365 if (wide) { 1366 offset += sizeof(u32); 1367 target_addr >>= 32; 1368 wide = false; 1369 goto repeat; 1370 } 1371 1372 return target->node.start | UPDATE; 1373 } 1374 1375 static u64 1376 eb_relocate_entry(struct i915_execbuffer *eb, 1377 struct eb_vma *ev, 1378 const struct drm_i915_gem_relocation_entry *reloc) 1379 { 1380 struct drm_i915_private *i915 = eb->i915; 1381 struct eb_vma *target; 1382 int err; 1383 1384 /* we've already hold a reference to all valid objects */ 1385 target = eb_get_vma(eb, reloc->target_handle); 1386 if (unlikely(!target)) 1387 return -ENOENT; 1388 1389 /* Validate that the target is in a valid r/w GPU domain */ 1390 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { 1391 drm_dbg(&i915->drm, "reloc with multiple write domains: " 1392 "target %d offset %d " 1393 "read %08x write %08x", 1394 reloc->target_handle, 1395 (int) reloc->offset, 1396 reloc->read_domains, 1397 reloc->write_domain); 1398 return -EINVAL; 1399 } 1400 if (unlikely((reloc->write_domain | reloc->read_domains) 1401 & ~I915_GEM_GPU_DOMAINS)) { 1402 drm_dbg(&i915->drm, "reloc with read/write non-GPU domains: " 1403 "target %d offset %d " 1404 "read %08x write %08x", 1405 reloc->target_handle, 1406 (int) reloc->offset, 1407 reloc->read_domains, 1408 reloc->write_domain); 1409 return -EINVAL; 1410 } 1411 1412 if (reloc->write_domain) { 1413 target->flags |= EXEC_OBJECT_WRITE; 1414 1415 /* 1416 * Sandybridge PPGTT errata: We need a global gtt mapping 1417 * for MI and pipe_control writes because the gpu doesn't 1418 * properly redirect them through the ppgtt for non_secure 1419 * batchbuffers. 1420 */ 1421 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && 1422 GRAPHICS_VER(eb->i915) == 6 && 1423 !i915_vma_is_bound(target->vma, I915_VMA_GLOBAL_BIND)) { 1424 struct i915_vma *vma = target->vma; 1425 1426 reloc_cache_unmap(&eb->reloc_cache); 1427 mutex_lock(&vma->vm->mutex); 1428 err = i915_vma_bind(target->vma, 1429 target->vma->obj->cache_level, 1430 PIN_GLOBAL, NULL, NULL); 1431 mutex_unlock(&vma->vm->mutex); 1432 reloc_cache_remap(&eb->reloc_cache, ev->vma->obj); 1433 if (err) 1434 return err; 1435 } 1436 } 1437 1438 /* 1439 * If the relocation already has the right value in it, no 1440 * more work needs to be done. 1441 */ 1442 if (!DBG_FORCE_RELOC && 1443 gen8_canonical_addr(i915_vma_offset(target->vma)) == reloc->presumed_offset) 1444 return 0; 1445 1446 /* Check that the relocation address is valid... */ 1447 if (unlikely(reloc->offset > 1448 ev->vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) { 1449 drm_dbg(&i915->drm, "Relocation beyond object bounds: " 1450 "target %d offset %d size %d.\n", 1451 reloc->target_handle, 1452 (int)reloc->offset, 1453 (int)ev->vma->size); 1454 return -EINVAL; 1455 } 1456 if (unlikely(reloc->offset & 3)) { 1457 drm_dbg(&i915->drm, "Relocation not 4-byte aligned: " 1458 "target %d offset %d.\n", 1459 reloc->target_handle, 1460 (int)reloc->offset); 1461 return -EINVAL; 1462 } 1463 1464 /* 1465 * If we write into the object, we need to force the synchronisation 1466 * barrier, either with an asynchronous clflush or if we executed the 1467 * patching using the GPU (though that should be serialised by the 1468 * timeline). To be completely sure, and since we are required to 1469 * do relocations we are already stalling, disable the user's opt 1470 * out of our synchronisation. 1471 */ 1472 ev->flags &= ~EXEC_OBJECT_ASYNC; 1473 1474 /* and update the user's relocation entry */ 1475 return relocate_entry(ev->vma, reloc, eb, target->vma); 1476 } 1477 1478 static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) 1479 { 1480 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) 1481 struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; 1482 const struct drm_i915_gem_exec_object2 *entry = ev->exec; 1483 struct drm_i915_gem_relocation_entry __user *urelocs = 1484 u64_to_user_ptr(entry->relocs_ptr); 1485 unsigned long remain = entry->relocation_count; 1486 1487 if (unlikely(remain > N_RELOC(ULONG_MAX))) 1488 return -EINVAL; 1489 1490 /* 1491 * We must check that the entire relocation array is safe 1492 * to read. However, if the array is not writable the user loses 1493 * the updated relocation values. 1494 */ 1495 if (unlikely(!access_ok(urelocs, remain * sizeof(*urelocs)))) 1496 return -EFAULT; 1497 1498 do { 1499 struct drm_i915_gem_relocation_entry *r = stack; 1500 unsigned int count = 1501 min_t(unsigned long, remain, ARRAY_SIZE(stack)); 1502 unsigned int copied; 1503 1504 /* 1505 * This is the fast path and we cannot handle a pagefault 1506 * whilst holding the struct mutex lest the user pass in the 1507 * relocations contained within a mmaped bo. For in such a case 1508 * we, the page fault handler would call i915_gem_fault() and 1509 * we would try to acquire the struct mutex again. Obviously 1510 * this is bad and so lockdep complains vehemently. 1511 */ 1512 pagefault_disable(); 1513 copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0])); 1514 pagefault_enable(); 1515 if (unlikely(copied)) { 1516 remain = -EFAULT; 1517 goto out; 1518 } 1519 1520 remain -= count; 1521 do { 1522 u64 offset = eb_relocate_entry(eb, ev, r); 1523 1524 if (likely(offset == 0)) { 1525 } else if ((s64)offset < 0) { 1526 remain = (int)offset; 1527 goto out; 1528 } else { 1529 /* 1530 * Note that reporting an error now 1531 * leaves everything in an inconsistent 1532 * state as we have *already* changed 1533 * the relocation value inside the 1534 * object. As we have not changed the 1535 * reloc.presumed_offset or will not 1536 * change the execobject.offset, on the 1537 * call we may not rewrite the value 1538 * inside the object, leaving it 1539 * dangling and causing a GPU hang. Unless 1540 * userspace dynamically rebuilds the 1541 * relocations on each execbuf rather than 1542 * presume a static tree. 1543 * 1544 * We did previously check if the relocations 1545 * were writable (access_ok), an error now 1546 * would be a strange race with mprotect, 1547 * having already demonstrated that we 1548 * can read from this userspace address. 1549 */ 1550 offset = gen8_canonical_addr(offset & ~UPDATE); 1551 __put_user(offset, 1552 &urelocs[r - stack].presumed_offset); 1553 } 1554 } while (r++, --count); 1555 urelocs += ARRAY_SIZE(stack); 1556 } while (remain); 1557 out: 1558 reloc_cache_reset(&eb->reloc_cache, eb); 1559 return remain; 1560 } 1561 1562 static int 1563 eb_relocate_vma_slow(struct i915_execbuffer *eb, struct eb_vma *ev) 1564 { 1565 const struct drm_i915_gem_exec_object2 *entry = ev->exec; 1566 struct drm_i915_gem_relocation_entry *relocs = 1567 u64_to_ptr(typeof(*relocs), entry->relocs_ptr); 1568 unsigned int i; 1569 int err; 1570 1571 for (i = 0; i < entry->relocation_count; i++) { 1572 u64 offset = eb_relocate_entry(eb, ev, &relocs[i]); 1573 1574 if ((s64)offset < 0) { 1575 err = (int)offset; 1576 goto err; 1577 } 1578 } 1579 err = 0; 1580 err: 1581 reloc_cache_reset(&eb->reloc_cache, eb); 1582 return err; 1583 } 1584 1585 static int check_relocations(const struct drm_i915_gem_exec_object2 *entry) 1586 { 1587 const char __user *addr, *end; 1588 unsigned long size; 1589 char __maybe_unused c; 1590 1591 size = entry->relocation_count; 1592 if (size == 0) 1593 return 0; 1594 1595 if (size > N_RELOC(ULONG_MAX)) 1596 return -EINVAL; 1597 1598 addr = u64_to_user_ptr(entry->relocs_ptr); 1599 size *= sizeof(struct drm_i915_gem_relocation_entry); 1600 if (!access_ok(addr, size)) 1601 return -EFAULT; 1602 1603 end = addr + size; 1604 for (; addr < end; addr += PAGE_SIZE) { 1605 int err = __get_user(c, addr); 1606 if (err) 1607 return err; 1608 } 1609 return __get_user(c, end - 1); 1610 } 1611 1612 static int eb_copy_relocations(const struct i915_execbuffer *eb) 1613 { 1614 struct drm_i915_gem_relocation_entry *relocs; 1615 const unsigned int count = eb->buffer_count; 1616 unsigned int i; 1617 int err; 1618 1619 for (i = 0; i < count; i++) { 1620 const unsigned int nreloc = eb->exec[i].relocation_count; 1621 struct drm_i915_gem_relocation_entry __user *urelocs; 1622 unsigned long size; 1623 unsigned long copied; 1624 1625 if (nreloc == 0) 1626 continue; 1627 1628 err = check_relocations(&eb->exec[i]); 1629 if (err) 1630 goto err; 1631 1632 urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr); 1633 size = nreloc * sizeof(*relocs); 1634 1635 relocs = kvmalloc_array(size, 1, GFP_KERNEL); 1636 if (!relocs) { 1637 err = -ENOMEM; 1638 goto err; 1639 } 1640 1641 /* copy_from_user is limited to < 4GiB */ 1642 copied = 0; 1643 do { 1644 unsigned int len = 1645 min_t(u64, BIT_ULL(31), size - copied); 1646 1647 if (__copy_from_user((char *)relocs + copied, 1648 (char __user *)urelocs + copied, 1649 len)) 1650 goto end; 1651 1652 copied += len; 1653 } while (copied < size); 1654 1655 /* 1656 * As we do not update the known relocation offsets after 1657 * relocating (due to the complexities in lock handling), 1658 * we need to mark them as invalid now so that we force the 1659 * relocation processing next time. Just in case the target 1660 * object is evicted and then rebound into its old 1661 * presumed_offset before the next execbuffer - if that 1662 * happened we would make the mistake of assuming that the 1663 * relocations were valid. 1664 */ 1665 if (!user_access_begin(urelocs, size)) 1666 goto end; 1667 1668 for (copied = 0; copied < nreloc; copied++) 1669 unsafe_put_user(-1, 1670 &urelocs[copied].presumed_offset, 1671 end_user); 1672 user_access_end(); 1673 1674 eb->exec[i].relocs_ptr = (uintptr_t)relocs; 1675 } 1676 1677 return 0; 1678 1679 end_user: 1680 user_access_end(); 1681 end: 1682 kvfree(relocs); 1683 err = -EFAULT; 1684 err: 1685 while (i--) { 1686 relocs = u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr); 1687 if (eb->exec[i].relocation_count) 1688 kvfree(relocs); 1689 } 1690 return err; 1691 } 1692 1693 static int eb_prefault_relocations(const struct i915_execbuffer *eb) 1694 { 1695 const unsigned int count = eb->buffer_count; 1696 unsigned int i; 1697 1698 for (i = 0; i < count; i++) { 1699 int err; 1700 1701 err = check_relocations(&eb->exec[i]); 1702 if (err) 1703 return err; 1704 } 1705 1706 return 0; 1707 } 1708 1709 static int eb_reinit_userptr(struct i915_execbuffer *eb) 1710 { 1711 const unsigned int count = eb->buffer_count; 1712 unsigned int i; 1713 int ret; 1714 1715 if (likely(!(eb->args->flags & __EXEC_USERPTR_USED))) 1716 return 0; 1717 1718 for (i = 0; i < count; i++) { 1719 struct eb_vma *ev = &eb->vma[i]; 1720 1721 if (!i915_gem_object_is_userptr(ev->vma->obj)) 1722 continue; 1723 1724 ret = i915_gem_object_userptr_submit_init(ev->vma->obj); 1725 if (ret) 1726 return ret; 1727 1728 ev->flags |= __EXEC_OBJECT_USERPTR_INIT; 1729 } 1730 1731 return 0; 1732 } 1733 1734 static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) 1735 { 1736 bool have_copy = false; 1737 struct eb_vma *ev; 1738 int err = 0; 1739 1740 repeat: 1741 if (signal_pending(current)) { 1742 err = -ERESTARTSYS; 1743 goto out; 1744 } 1745 1746 /* We may process another execbuffer during the unlock... */ 1747 eb_release_vmas(eb, false); 1748 i915_gem_ww_ctx_fini(&eb->ww); 1749 1750 /* 1751 * We take 3 passes through the slowpatch. 1752 * 1753 * 1 - we try to just prefault all the user relocation entries and 1754 * then attempt to reuse the atomic pagefault disabled fast path again. 1755 * 1756 * 2 - we copy the user entries to a local buffer here outside of the 1757 * local and allow ourselves to wait upon any rendering before 1758 * relocations 1759 * 1760 * 3 - we already have a local copy of the relocation entries, but 1761 * were interrupted (EAGAIN) whilst waiting for the objects, try again. 1762 */ 1763 if (!err) { 1764 err = eb_prefault_relocations(eb); 1765 } else if (!have_copy) { 1766 err = eb_copy_relocations(eb); 1767 have_copy = err == 0; 1768 } else { 1769 cond_resched(); 1770 err = 0; 1771 } 1772 1773 if (!err) 1774 err = eb_reinit_userptr(eb); 1775 1776 i915_gem_ww_ctx_init(&eb->ww, true); 1777 if (err) 1778 goto out; 1779 1780 /* reacquire the objects */ 1781 repeat_validate: 1782 err = eb_pin_engine(eb, false); 1783 if (err) 1784 goto err; 1785 1786 err = eb_validate_vmas(eb); 1787 if (err) 1788 goto err; 1789 1790 GEM_BUG_ON(!eb->batches[0]); 1791 1792 list_for_each_entry(ev, &eb->relocs, reloc_link) { 1793 if (!have_copy) { 1794 err = eb_relocate_vma(eb, ev); 1795 if (err) 1796 break; 1797 } else { 1798 err = eb_relocate_vma_slow(eb, ev); 1799 if (err) 1800 break; 1801 } 1802 } 1803 1804 if (err == -EDEADLK) 1805 goto err; 1806 1807 if (err && !have_copy) 1808 goto repeat; 1809 1810 if (err) 1811 goto err; 1812 1813 /* as last step, parse the command buffer */ 1814 err = eb_parse(eb); 1815 if (err) 1816 goto err; 1817 1818 /* 1819 * Leave the user relocations as are, this is the painfully slow path, 1820 * and we want to avoid the complication of dropping the lock whilst 1821 * having buffers reserved in the aperture and so causing spurious 1822 * ENOSPC for random operations. 1823 */ 1824 1825 err: 1826 if (err == -EDEADLK) { 1827 eb_release_vmas(eb, false); 1828 err = i915_gem_ww_ctx_backoff(&eb->ww); 1829 if (!err) 1830 goto repeat_validate; 1831 } 1832 1833 if (err == -EAGAIN) 1834 goto repeat; 1835 1836 out: 1837 if (have_copy) { 1838 const unsigned int count = eb->buffer_count; 1839 unsigned int i; 1840 1841 for (i = 0; i < count; i++) { 1842 const struct drm_i915_gem_exec_object2 *entry = 1843 &eb->exec[i]; 1844 struct drm_i915_gem_relocation_entry *relocs; 1845 1846 if (!entry->relocation_count) 1847 continue; 1848 1849 relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr); 1850 kvfree(relocs); 1851 } 1852 } 1853 1854 return err; 1855 } 1856 1857 static int eb_relocate_parse(struct i915_execbuffer *eb) 1858 { 1859 int err; 1860 bool throttle = true; 1861 1862 retry: 1863 err = eb_pin_engine(eb, throttle); 1864 if (err) { 1865 if (err != -EDEADLK) 1866 return err; 1867 1868 goto err; 1869 } 1870 1871 /* only throttle once, even if we didn't need to throttle */ 1872 throttle = false; 1873 1874 err = eb_validate_vmas(eb); 1875 if (err == -EAGAIN) 1876 goto slow; 1877 else if (err) 1878 goto err; 1879 1880 /* The objects are in their final locations, apply the relocations. */ 1881 if (eb->args->flags & __EXEC_HAS_RELOC) { 1882 struct eb_vma *ev; 1883 1884 list_for_each_entry(ev, &eb->relocs, reloc_link) { 1885 err = eb_relocate_vma(eb, ev); 1886 if (err) 1887 break; 1888 } 1889 1890 if (err == -EDEADLK) 1891 goto err; 1892 else if (err) 1893 goto slow; 1894 } 1895 1896 if (!err) 1897 err = eb_parse(eb); 1898 1899 err: 1900 if (err == -EDEADLK) { 1901 eb_release_vmas(eb, false); 1902 err = i915_gem_ww_ctx_backoff(&eb->ww); 1903 if (!err) 1904 goto retry; 1905 } 1906 1907 return err; 1908 1909 slow: 1910 err = eb_relocate_parse_slow(eb); 1911 if (err) 1912 /* 1913 * If the user expects the execobject.offset and 1914 * reloc.presumed_offset to be an exact match, 1915 * as for using NO_RELOC, then we cannot update 1916 * the execobject.offset until we have completed 1917 * relocation. 1918 */ 1919 eb->args->flags &= ~__EXEC_HAS_RELOC; 1920 1921 return err; 1922 } 1923 1924 /* 1925 * Using two helper loops for the order of which requests / batches are created 1926 * and added the to backend. Requests are created in order from the parent to 1927 * the last child. Requests are added in the reverse order, from the last child 1928 * to parent. This is done for locking reasons as the timeline lock is acquired 1929 * during request creation and released when the request is added to the 1930 * backend. To make lockdep happy (see intel_context_timeline_lock) this must be 1931 * the ordering. 1932 */ 1933 #define for_each_batch_create_order(_eb, _i) \ 1934 for ((_i) = 0; (_i) < (_eb)->num_batches; ++(_i)) 1935 #define for_each_batch_add_order(_eb, _i) \ 1936 BUILD_BUG_ON(!typecheck(int, _i)); \ 1937 for ((_i) = (_eb)->num_batches - 1; (_i) >= 0; --(_i)) 1938 1939 static struct i915_request * 1940 eb_find_first_request_added(struct i915_execbuffer *eb) 1941 { 1942 int i; 1943 1944 for_each_batch_add_order(eb, i) 1945 if (eb->requests[i]) 1946 return eb->requests[i]; 1947 1948 GEM_BUG_ON("Request not found"); 1949 1950 return NULL; 1951 } 1952 1953 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1954 1955 /* Stage with GFP_KERNEL allocations before we enter the signaling critical path */ 1956 static int eb_capture_stage(struct i915_execbuffer *eb) 1957 { 1958 const unsigned int count = eb->buffer_count; 1959 unsigned int i = count, j; 1960 1961 while (i--) { 1962 struct eb_vma *ev = &eb->vma[i]; 1963 struct i915_vma *vma = ev->vma; 1964 unsigned int flags = ev->flags; 1965 1966 if (!(flags & EXEC_OBJECT_CAPTURE)) 1967 continue; 1968 1969 if (i915_gem_context_is_recoverable(eb->gem_context) && 1970 (IS_DGFX(eb->i915) || GRAPHICS_VER_FULL(eb->i915) > IP_VER(12, 0))) 1971 return -EINVAL; 1972 1973 for_each_batch_create_order(eb, j) { 1974 struct i915_capture_list *capture; 1975 1976 capture = kmalloc(sizeof(*capture), GFP_KERNEL); 1977 if (!capture) 1978 continue; 1979 1980 capture->next = eb->capture_lists[j]; 1981 capture->vma_res = i915_vma_resource_get(vma->resource); 1982 eb->capture_lists[j] = capture; 1983 } 1984 } 1985 1986 return 0; 1987 } 1988 1989 /* Commit once we're in the critical path */ 1990 static void eb_capture_commit(struct i915_execbuffer *eb) 1991 { 1992 unsigned int j; 1993 1994 for_each_batch_create_order(eb, j) { 1995 struct i915_request *rq = eb->requests[j]; 1996 1997 if (!rq) 1998 break; 1999 2000 rq->capture_list = eb->capture_lists[j]; 2001 eb->capture_lists[j] = NULL; 2002 } 2003 } 2004 2005 /* 2006 * Release anything that didn't get committed due to errors. 2007 * The capture_list will otherwise be freed at request retire. 2008 */ 2009 static void eb_capture_release(struct i915_execbuffer *eb) 2010 { 2011 unsigned int j; 2012 2013 for_each_batch_create_order(eb, j) { 2014 if (eb->capture_lists[j]) { 2015 i915_request_free_capture_list(eb->capture_lists[j]); 2016 eb->capture_lists[j] = NULL; 2017 } 2018 } 2019 } 2020 2021 static void eb_capture_list_clear(struct i915_execbuffer *eb) 2022 { 2023 memset(eb->capture_lists, 0, sizeof(eb->capture_lists)); 2024 } 2025 2026 #else 2027 2028 static int eb_capture_stage(struct i915_execbuffer *eb) 2029 { 2030 return 0; 2031 } 2032 2033 static void eb_capture_commit(struct i915_execbuffer *eb) 2034 { 2035 } 2036 2037 static void eb_capture_release(struct i915_execbuffer *eb) 2038 { 2039 } 2040 2041 static void eb_capture_list_clear(struct i915_execbuffer *eb) 2042 { 2043 } 2044 2045 #endif 2046 2047 static int eb_move_to_gpu(struct i915_execbuffer *eb) 2048 { 2049 const unsigned int count = eb->buffer_count; 2050 unsigned int i = count; 2051 int err = 0, j; 2052 2053 while (i--) { 2054 struct eb_vma *ev = &eb->vma[i]; 2055 struct i915_vma *vma = ev->vma; 2056 unsigned int flags = ev->flags; 2057 struct drm_i915_gem_object *obj = vma->obj; 2058 2059 assert_vma_held(vma); 2060 2061 /* 2062 * If the GPU is not _reading_ through the CPU cache, we need 2063 * to make sure that any writes (both previous GPU writes from 2064 * before a change in snooping levels and normal CPU writes) 2065 * caught in that cache are flushed to main memory. 2066 * 2067 * We want to say 2068 * obj->cache_dirty && 2069 * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ) 2070 * but gcc's optimiser doesn't handle that as well and emits 2071 * two jumps instead of one. Maybe one day... 2072 * 2073 * FIXME: There is also sync flushing in set_pages(), which 2074 * serves a different purpose(some of the time at least). 2075 * 2076 * We should consider: 2077 * 2078 * 1. Rip out the async flush code. 2079 * 2080 * 2. Or make the sync flushing use the async clflush path 2081 * using mandatory fences underneath. Currently the below 2082 * async flush happens after we bind the object. 2083 */ 2084 if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) { 2085 if (i915_gem_clflush_object(obj, 0)) 2086 flags &= ~EXEC_OBJECT_ASYNC; 2087 } 2088 2089 /* We only need to await on the first request */ 2090 if (err == 0 && !(flags & EXEC_OBJECT_ASYNC)) { 2091 err = i915_request_await_object 2092 (eb_find_first_request_added(eb), obj, 2093 flags & EXEC_OBJECT_WRITE); 2094 } 2095 2096 for_each_batch_add_order(eb, j) { 2097 if (err) 2098 break; 2099 if (!eb->requests[j]) 2100 continue; 2101 2102 err = _i915_vma_move_to_active(vma, eb->requests[j], 2103 j ? NULL : 2104 eb->composite_fence ? 2105 eb->composite_fence : 2106 &eb->requests[j]->fence, 2107 flags | __EXEC_OBJECT_NO_RESERVE | 2108 __EXEC_OBJECT_NO_REQUEST_AWAIT); 2109 } 2110 } 2111 2112 #ifdef CONFIG_MMU_NOTIFIER 2113 if (!err && (eb->args->flags & __EXEC_USERPTR_USED)) { 2114 read_lock(&eb->i915->mm.notifier_lock); 2115 2116 /* 2117 * count is always at least 1, otherwise __EXEC_USERPTR_USED 2118 * could not have been set 2119 */ 2120 for (i = 0; i < count; i++) { 2121 struct eb_vma *ev = &eb->vma[i]; 2122 struct drm_i915_gem_object *obj = ev->vma->obj; 2123 2124 if (!i915_gem_object_is_userptr(obj)) 2125 continue; 2126 2127 err = i915_gem_object_userptr_submit_done(obj); 2128 if (err) 2129 break; 2130 } 2131 2132 read_unlock(&eb->i915->mm.notifier_lock); 2133 } 2134 #endif 2135 2136 if (unlikely(err)) 2137 goto err_skip; 2138 2139 /* Unconditionally flush any chipset caches (for streaming writes). */ 2140 intel_gt_chipset_flush(eb->gt); 2141 eb_capture_commit(eb); 2142 2143 return 0; 2144 2145 err_skip: 2146 for_each_batch_create_order(eb, j) { 2147 if (!eb->requests[j]) 2148 break; 2149 2150 i915_request_set_error_once(eb->requests[j], err); 2151 } 2152 return err; 2153 } 2154 2155 static int i915_gem_check_execbuffer(struct drm_i915_private *i915, 2156 struct drm_i915_gem_execbuffer2 *exec) 2157 { 2158 if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS) 2159 return -EINVAL; 2160 2161 /* Kernel clipping was a DRI1 misfeature */ 2162 if (!(exec->flags & (I915_EXEC_FENCE_ARRAY | 2163 I915_EXEC_USE_EXTENSIONS))) { 2164 if (exec->num_cliprects || exec->cliprects_ptr) 2165 return -EINVAL; 2166 } 2167 2168 if (exec->DR4 == 0xffffffff) { 2169 drm_dbg(&i915->drm, "UXA submitting garbage DR4, fixing up\n"); 2170 exec->DR4 = 0; 2171 } 2172 if (exec->DR1 || exec->DR4) 2173 return -EINVAL; 2174 2175 if ((exec->batch_start_offset | exec->batch_len) & 0x7) 2176 return -EINVAL; 2177 2178 return 0; 2179 } 2180 2181 static int i915_reset_gen7_sol_offsets(struct i915_request *rq) 2182 { 2183 u32 *cs; 2184 int i; 2185 2186 if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) { 2187 drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n"); 2188 return -EINVAL; 2189 } 2190 2191 cs = intel_ring_begin(rq, 4 * 2 + 2); 2192 if (IS_ERR(cs)) 2193 return PTR_ERR(cs); 2194 2195 *cs++ = MI_LOAD_REGISTER_IMM(4); 2196 for (i = 0; i < 4; i++) { 2197 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i)); 2198 *cs++ = 0; 2199 } 2200 *cs++ = MI_NOOP; 2201 intel_ring_advance(rq, cs); 2202 2203 return 0; 2204 } 2205 2206 static struct i915_vma * 2207 shadow_batch_pin(struct i915_execbuffer *eb, 2208 struct drm_i915_gem_object *obj, 2209 struct i915_address_space *vm, 2210 unsigned int flags) 2211 { 2212 struct i915_vma *vma; 2213 int err; 2214 2215 vma = i915_vma_instance(obj, vm, NULL); 2216 if (IS_ERR(vma)) 2217 return vma; 2218 2219 err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, flags | PIN_VALIDATE); 2220 if (err) 2221 return ERR_PTR(err); 2222 2223 return vma; 2224 } 2225 2226 static struct i915_vma *eb_dispatch_secure(struct i915_execbuffer *eb, struct i915_vma *vma) 2227 { 2228 /* 2229 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure 2230 * batch" bit. Hence we need to pin secure batches into the global gtt. 2231 * hsw should have this fixed, but bdw mucks it up again. */ 2232 if (eb->batch_flags & I915_DISPATCH_SECURE) 2233 return i915_gem_object_ggtt_pin_ww(vma->obj, &eb->ww, NULL, 0, 0, PIN_VALIDATE); 2234 2235 return NULL; 2236 } 2237 2238 static int eb_parse(struct i915_execbuffer *eb) 2239 { 2240 struct drm_i915_private *i915 = eb->i915; 2241 struct intel_gt_buffer_pool_node *pool = eb->batch_pool; 2242 struct i915_vma *shadow, *trampoline, *batch; 2243 unsigned long len; 2244 int err; 2245 2246 if (!eb_use_cmdparser(eb)) { 2247 batch = eb_dispatch_secure(eb, eb->batches[0]->vma); 2248 if (IS_ERR(batch)) 2249 return PTR_ERR(batch); 2250 2251 goto secure_batch; 2252 } 2253 2254 if (intel_context_is_parallel(eb->context)) 2255 return -EINVAL; 2256 2257 len = eb->batch_len[0]; 2258 if (!CMDPARSER_USES_GGTT(eb->i915)) { 2259 /* 2260 * ppGTT backed shadow buffers must be mapped RO, to prevent 2261 * post-scan tampering 2262 */ 2263 if (!eb->context->vm->has_read_only) { 2264 drm_dbg(&i915->drm, 2265 "Cannot prevent post-scan tampering without RO capable vm\n"); 2266 return -EINVAL; 2267 } 2268 } else { 2269 len += I915_CMD_PARSER_TRAMPOLINE_SIZE; 2270 } 2271 if (unlikely(len < eb->batch_len[0])) /* last paranoid check of overflow */ 2272 return -EINVAL; 2273 2274 if (!pool) { 2275 pool = intel_gt_get_buffer_pool(eb->gt, len, 2276 I915_MAP_WB); 2277 if (IS_ERR(pool)) 2278 return PTR_ERR(pool); 2279 eb->batch_pool = pool; 2280 } 2281 2282 err = i915_gem_object_lock(pool->obj, &eb->ww); 2283 if (err) 2284 return err; 2285 2286 shadow = shadow_batch_pin(eb, pool->obj, eb->context->vm, PIN_USER); 2287 if (IS_ERR(shadow)) 2288 return PTR_ERR(shadow); 2289 2290 intel_gt_buffer_pool_mark_used(pool); 2291 i915_gem_object_set_readonly(shadow->obj); 2292 shadow->private = pool; 2293 2294 trampoline = NULL; 2295 if (CMDPARSER_USES_GGTT(eb->i915)) { 2296 trampoline = shadow; 2297 2298 shadow = shadow_batch_pin(eb, pool->obj, 2299 &eb->gt->ggtt->vm, 2300 PIN_GLOBAL); 2301 if (IS_ERR(shadow)) 2302 return PTR_ERR(shadow); 2303 2304 shadow->private = pool; 2305 2306 eb->batch_flags |= I915_DISPATCH_SECURE; 2307 } 2308 2309 batch = eb_dispatch_secure(eb, shadow); 2310 if (IS_ERR(batch)) 2311 return PTR_ERR(batch); 2312 2313 err = dma_resv_reserve_fences(shadow->obj->base.resv, 1); 2314 if (err) 2315 return err; 2316 2317 err = intel_engine_cmd_parser(eb->context->engine, 2318 eb->batches[0]->vma, 2319 eb->batch_start_offset, 2320 eb->batch_len[0], 2321 shadow, trampoline); 2322 if (err) 2323 return err; 2324 2325 eb->batches[0] = &eb->vma[eb->buffer_count++]; 2326 eb->batches[0]->vma = i915_vma_get(shadow); 2327 eb->batches[0]->flags = __EXEC_OBJECT_HAS_PIN; 2328 2329 eb->trampoline = trampoline; 2330 eb->batch_start_offset = 0; 2331 2332 secure_batch: 2333 if (batch) { 2334 if (intel_context_is_parallel(eb->context)) 2335 return -EINVAL; 2336 2337 eb->batches[0] = &eb->vma[eb->buffer_count++]; 2338 eb->batches[0]->flags = __EXEC_OBJECT_HAS_PIN; 2339 eb->batches[0]->vma = i915_vma_get(batch); 2340 } 2341 return 0; 2342 } 2343 2344 static int eb_request_submit(struct i915_execbuffer *eb, 2345 struct i915_request *rq, 2346 struct i915_vma *batch, 2347 u64 batch_len) 2348 { 2349 int err; 2350 2351 if (intel_context_nopreempt(rq->context)) 2352 __set_bit(I915_FENCE_FLAG_NOPREEMPT, &rq->fence.flags); 2353 2354 if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) { 2355 err = i915_reset_gen7_sol_offsets(rq); 2356 if (err) 2357 return err; 2358 } 2359 2360 /* 2361 * After we completed waiting for other engines (using HW semaphores) 2362 * then we can signal that this request/batch is ready to run. This 2363 * allows us to determine if the batch is still waiting on the GPU 2364 * or actually running by checking the breadcrumb. 2365 */ 2366 if (rq->context->engine->emit_init_breadcrumb) { 2367 err = rq->context->engine->emit_init_breadcrumb(rq); 2368 if (err) 2369 return err; 2370 } 2371 2372 err = rq->context->engine->emit_bb_start(rq, 2373 i915_vma_offset(batch) + 2374 eb->batch_start_offset, 2375 batch_len, 2376 eb->batch_flags); 2377 if (err) 2378 return err; 2379 2380 if (eb->trampoline) { 2381 GEM_BUG_ON(intel_context_is_parallel(rq->context)); 2382 GEM_BUG_ON(eb->batch_start_offset); 2383 err = rq->context->engine->emit_bb_start(rq, 2384 i915_vma_offset(eb->trampoline) + 2385 batch_len, 0, 0); 2386 if (err) 2387 return err; 2388 } 2389 2390 return 0; 2391 } 2392 2393 static int eb_submit(struct i915_execbuffer *eb) 2394 { 2395 unsigned int i; 2396 int err; 2397 2398 err = eb_move_to_gpu(eb); 2399 2400 for_each_batch_create_order(eb, i) { 2401 if (!eb->requests[i]) 2402 break; 2403 2404 trace_i915_request_queue(eb->requests[i], eb->batch_flags); 2405 if (!err) 2406 err = eb_request_submit(eb, eb->requests[i], 2407 eb->batches[i]->vma, 2408 eb->batch_len[i]); 2409 } 2410 2411 return err; 2412 } 2413 2414 static int num_vcs_engines(struct drm_i915_private *i915) 2415 { 2416 return hweight_long(VDBOX_MASK(to_gt(i915))); 2417 } 2418 2419 /* 2420 * Find one BSD ring to dispatch the corresponding BSD command. 2421 * The engine index is returned. 2422 */ 2423 static unsigned int 2424 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv, 2425 struct drm_file *file) 2426 { 2427 struct drm_i915_file_private *file_priv = file->driver_priv; 2428 2429 /* Check whether the file_priv has already selected one ring. */ 2430 if ((int)file_priv->bsd_engine < 0) 2431 file_priv->bsd_engine = 2432 prandom_u32_max(num_vcs_engines(dev_priv)); 2433 2434 return file_priv->bsd_engine; 2435 } 2436 2437 static const enum intel_engine_id user_ring_map[] = { 2438 [I915_EXEC_DEFAULT] = RCS0, 2439 [I915_EXEC_RENDER] = RCS0, 2440 [I915_EXEC_BLT] = BCS0, 2441 [I915_EXEC_BSD] = VCS0, 2442 [I915_EXEC_VEBOX] = VECS0 2443 }; 2444 2445 static struct i915_request *eb_throttle(struct i915_execbuffer *eb, struct intel_context *ce) 2446 { 2447 struct intel_ring *ring = ce->ring; 2448 struct intel_timeline *tl = ce->timeline; 2449 struct i915_request *rq; 2450 2451 /* 2452 * Completely unscientific finger-in-the-air estimates for suitable 2453 * maximum user request size (to avoid blocking) and then backoff. 2454 */ 2455 if (intel_ring_update_space(ring) >= PAGE_SIZE) 2456 return NULL; 2457 2458 /* 2459 * Find a request that after waiting upon, there will be at least half 2460 * the ring available. The hysteresis allows us to compete for the 2461 * shared ring and should mean that we sleep less often prior to 2462 * claiming our resources, but not so long that the ring completely 2463 * drains before we can submit our next request. 2464 */ 2465 list_for_each_entry(rq, &tl->requests, link) { 2466 if (rq->ring != ring) 2467 continue; 2468 2469 if (__intel_ring_space(rq->postfix, 2470 ring->emit, ring->size) > ring->size / 2) 2471 break; 2472 } 2473 if (&rq->link == &tl->requests) 2474 return NULL; /* weird, we will check again later for real */ 2475 2476 return i915_request_get(rq); 2477 } 2478 2479 static int eb_pin_timeline(struct i915_execbuffer *eb, struct intel_context *ce, 2480 bool throttle) 2481 { 2482 struct intel_timeline *tl; 2483 struct i915_request *rq = NULL; 2484 2485 /* 2486 * Take a local wakeref for preparing to dispatch the execbuf as 2487 * we expect to access the hardware fairly frequently in the 2488 * process, and require the engine to be kept awake between accesses. 2489 * Upon dispatch, we acquire another prolonged wakeref that we hold 2490 * until the timeline is idle, which in turn releases the wakeref 2491 * taken on the engine, and the parent device. 2492 */ 2493 tl = intel_context_timeline_lock(ce); 2494 if (IS_ERR(tl)) 2495 return PTR_ERR(tl); 2496 2497 intel_context_enter(ce); 2498 if (throttle) 2499 rq = eb_throttle(eb, ce); 2500 intel_context_timeline_unlock(tl); 2501 2502 if (rq) { 2503 bool nonblock = eb->file->filp->f_flags & O_NONBLOCK; 2504 long timeout = nonblock ? 0 : MAX_SCHEDULE_TIMEOUT; 2505 2506 if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, 2507 timeout) < 0) { 2508 i915_request_put(rq); 2509 2510 /* 2511 * Error path, cannot use intel_context_timeline_lock as 2512 * that is user interruptable and this clean up step 2513 * must be done. 2514 */ 2515 mutex_lock(&ce->timeline->mutex); 2516 intel_context_exit(ce); 2517 mutex_unlock(&ce->timeline->mutex); 2518 2519 if (nonblock) 2520 return -EWOULDBLOCK; 2521 else 2522 return -EINTR; 2523 } 2524 i915_request_put(rq); 2525 } 2526 2527 return 0; 2528 } 2529 2530 static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle) 2531 { 2532 struct intel_context *ce = eb->context, *child; 2533 int err; 2534 int i = 0, j = 0; 2535 2536 GEM_BUG_ON(eb->args->flags & __EXEC_ENGINE_PINNED); 2537 2538 if (unlikely(intel_context_is_banned(ce))) 2539 return -EIO; 2540 2541 /* 2542 * Pinning the contexts may generate requests in order to acquire 2543 * GGTT space, so do this first before we reserve a seqno for 2544 * ourselves. 2545 */ 2546 err = intel_context_pin_ww(ce, &eb->ww); 2547 if (err) 2548 return err; 2549 for_each_child(ce, child) { 2550 err = intel_context_pin_ww(child, &eb->ww); 2551 GEM_BUG_ON(err); /* perma-pinned should incr a counter */ 2552 } 2553 2554 for_each_child(ce, child) { 2555 err = eb_pin_timeline(eb, child, throttle); 2556 if (err) 2557 goto unwind; 2558 ++i; 2559 } 2560 err = eb_pin_timeline(eb, ce, throttle); 2561 if (err) 2562 goto unwind; 2563 2564 eb->args->flags |= __EXEC_ENGINE_PINNED; 2565 return 0; 2566 2567 unwind: 2568 for_each_child(ce, child) { 2569 if (j++ < i) { 2570 mutex_lock(&child->timeline->mutex); 2571 intel_context_exit(child); 2572 mutex_unlock(&child->timeline->mutex); 2573 } 2574 } 2575 for_each_child(ce, child) 2576 intel_context_unpin(child); 2577 intel_context_unpin(ce); 2578 return err; 2579 } 2580 2581 static void eb_unpin_engine(struct i915_execbuffer *eb) 2582 { 2583 struct intel_context *ce = eb->context, *child; 2584 2585 if (!(eb->args->flags & __EXEC_ENGINE_PINNED)) 2586 return; 2587 2588 eb->args->flags &= ~__EXEC_ENGINE_PINNED; 2589 2590 for_each_child(ce, child) { 2591 mutex_lock(&child->timeline->mutex); 2592 intel_context_exit(child); 2593 mutex_unlock(&child->timeline->mutex); 2594 2595 intel_context_unpin(child); 2596 } 2597 2598 mutex_lock(&ce->timeline->mutex); 2599 intel_context_exit(ce); 2600 mutex_unlock(&ce->timeline->mutex); 2601 2602 intel_context_unpin(ce); 2603 } 2604 2605 static unsigned int 2606 eb_select_legacy_ring(struct i915_execbuffer *eb) 2607 { 2608 struct drm_i915_private *i915 = eb->i915; 2609 struct drm_i915_gem_execbuffer2 *args = eb->args; 2610 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK; 2611 2612 if (user_ring_id != I915_EXEC_BSD && 2613 (args->flags & I915_EXEC_BSD_MASK)) { 2614 drm_dbg(&i915->drm, 2615 "execbuf with non bsd ring but with invalid " 2616 "bsd dispatch flags: %d\n", (int)(args->flags)); 2617 return -1; 2618 } 2619 2620 if (user_ring_id == I915_EXEC_BSD && num_vcs_engines(i915) > 1) { 2621 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK; 2622 2623 if (bsd_idx == I915_EXEC_BSD_DEFAULT) { 2624 bsd_idx = gen8_dispatch_bsd_engine(i915, eb->file); 2625 } else if (bsd_idx >= I915_EXEC_BSD_RING1 && 2626 bsd_idx <= I915_EXEC_BSD_RING2) { 2627 bsd_idx >>= I915_EXEC_BSD_SHIFT; 2628 bsd_idx--; 2629 } else { 2630 drm_dbg(&i915->drm, 2631 "execbuf with unknown bsd ring: %u\n", 2632 bsd_idx); 2633 return -1; 2634 } 2635 2636 return _VCS(bsd_idx); 2637 } 2638 2639 if (user_ring_id >= ARRAY_SIZE(user_ring_map)) { 2640 drm_dbg(&i915->drm, "execbuf with unknown ring: %u\n", 2641 user_ring_id); 2642 return -1; 2643 } 2644 2645 return user_ring_map[user_ring_id]; 2646 } 2647 2648 static int 2649 eb_select_engine(struct i915_execbuffer *eb) 2650 { 2651 struct intel_context *ce, *child; 2652 unsigned int idx; 2653 int err; 2654 2655 if (i915_gem_context_user_engines(eb->gem_context)) 2656 idx = eb->args->flags & I915_EXEC_RING_MASK; 2657 else 2658 idx = eb_select_legacy_ring(eb); 2659 2660 ce = i915_gem_context_get_engine(eb->gem_context, idx); 2661 if (IS_ERR(ce)) 2662 return PTR_ERR(ce); 2663 2664 if (intel_context_is_parallel(ce)) { 2665 if (eb->buffer_count < ce->parallel.number_children + 1) { 2666 intel_context_put(ce); 2667 return -EINVAL; 2668 } 2669 if (eb->batch_start_offset || eb->args->batch_len) { 2670 intel_context_put(ce); 2671 return -EINVAL; 2672 } 2673 } 2674 eb->num_batches = ce->parallel.number_children + 1; 2675 2676 for_each_child(ce, child) 2677 intel_context_get(child); 2678 intel_gt_pm_get(ce->engine->gt); 2679 2680 if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) { 2681 err = intel_context_alloc_state(ce); 2682 if (err) 2683 goto err; 2684 } 2685 for_each_child(ce, child) { 2686 if (!test_bit(CONTEXT_ALLOC_BIT, &child->flags)) { 2687 err = intel_context_alloc_state(child); 2688 if (err) 2689 goto err; 2690 } 2691 } 2692 2693 /* 2694 * ABI: Before userspace accesses the GPU (e.g. execbuffer), report 2695 * EIO if the GPU is already wedged. 2696 */ 2697 err = intel_gt_terminally_wedged(ce->engine->gt); 2698 if (err) 2699 goto err; 2700 2701 if (!i915_vm_tryget(ce->vm)) { 2702 err = -ENOENT; 2703 goto err; 2704 } 2705 2706 eb->context = ce; 2707 eb->gt = ce->engine->gt; 2708 2709 /* 2710 * Make sure engine pool stays alive even if we call intel_context_put 2711 * during ww handling. The pool is destroyed when last pm reference 2712 * is dropped, which breaks our -EDEADLK handling. 2713 */ 2714 return err; 2715 2716 err: 2717 intel_gt_pm_put(ce->engine->gt); 2718 for_each_child(ce, child) 2719 intel_context_put(child); 2720 intel_context_put(ce); 2721 return err; 2722 } 2723 2724 static void 2725 eb_put_engine(struct i915_execbuffer *eb) 2726 { 2727 struct intel_context *child; 2728 2729 i915_vm_put(eb->context->vm); 2730 intel_gt_pm_put(eb->gt); 2731 for_each_child(eb->context, child) 2732 intel_context_put(child); 2733 intel_context_put(eb->context); 2734 } 2735 2736 static void 2737 __free_fence_array(struct eb_fence *fences, unsigned int n) 2738 { 2739 while (n--) { 2740 drm_syncobj_put(ptr_mask_bits(fences[n].syncobj, 2)); 2741 dma_fence_put(fences[n].dma_fence); 2742 dma_fence_chain_free(fences[n].chain_fence); 2743 } 2744 kvfree(fences); 2745 } 2746 2747 static int 2748 add_timeline_fence_array(struct i915_execbuffer *eb, 2749 const struct drm_i915_gem_execbuffer_ext_timeline_fences *timeline_fences) 2750 { 2751 struct drm_i915_gem_exec_fence __user *user_fences; 2752 u64 __user *user_values; 2753 struct eb_fence *f; 2754 u64 nfences; 2755 int err = 0; 2756 2757 nfences = timeline_fences->fence_count; 2758 if (!nfences) 2759 return 0; 2760 2761 /* Check multiplication overflow for access_ok() and kvmalloc_array() */ 2762 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long)); 2763 if (nfences > min_t(unsigned long, 2764 ULONG_MAX / sizeof(*user_fences), 2765 SIZE_MAX / sizeof(*f)) - eb->num_fences) 2766 return -EINVAL; 2767 2768 user_fences = u64_to_user_ptr(timeline_fences->handles_ptr); 2769 if (!access_ok(user_fences, nfences * sizeof(*user_fences))) 2770 return -EFAULT; 2771 2772 user_values = u64_to_user_ptr(timeline_fences->values_ptr); 2773 if (!access_ok(user_values, nfences * sizeof(*user_values))) 2774 return -EFAULT; 2775 2776 f = krealloc(eb->fences, 2777 (eb->num_fences + nfences) * sizeof(*f), 2778 __GFP_NOWARN | GFP_KERNEL); 2779 if (!f) 2780 return -ENOMEM; 2781 2782 eb->fences = f; 2783 f += eb->num_fences; 2784 2785 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) & 2786 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS); 2787 2788 while (nfences--) { 2789 struct drm_i915_gem_exec_fence user_fence; 2790 struct drm_syncobj *syncobj; 2791 struct dma_fence *fence = NULL; 2792 u64 point; 2793 2794 if (__copy_from_user(&user_fence, 2795 user_fences++, 2796 sizeof(user_fence))) 2797 return -EFAULT; 2798 2799 if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) 2800 return -EINVAL; 2801 2802 if (__get_user(point, user_values++)) 2803 return -EFAULT; 2804 2805 syncobj = drm_syncobj_find(eb->file, user_fence.handle); 2806 if (!syncobj) { 2807 drm_dbg(&eb->i915->drm, 2808 "Invalid syncobj handle provided\n"); 2809 return -ENOENT; 2810 } 2811 2812 fence = drm_syncobj_fence_get(syncobj); 2813 2814 if (!fence && user_fence.flags && 2815 !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) { 2816 drm_dbg(&eb->i915->drm, 2817 "Syncobj handle has no fence\n"); 2818 drm_syncobj_put(syncobj); 2819 return -EINVAL; 2820 } 2821 2822 if (fence) 2823 err = dma_fence_chain_find_seqno(&fence, point); 2824 2825 if (err && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) { 2826 drm_dbg(&eb->i915->drm, 2827 "Syncobj handle missing requested point %llu\n", 2828 point); 2829 dma_fence_put(fence); 2830 drm_syncobj_put(syncobj); 2831 return err; 2832 } 2833 2834 /* 2835 * A point might have been signaled already and 2836 * garbage collected from the timeline. In this case 2837 * just ignore the point and carry on. 2838 */ 2839 if (!fence && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) { 2840 drm_syncobj_put(syncobj); 2841 continue; 2842 } 2843 2844 /* 2845 * For timeline syncobjs we need to preallocate chains for 2846 * later signaling. 2847 */ 2848 if (point != 0 && user_fence.flags & I915_EXEC_FENCE_SIGNAL) { 2849 /* 2850 * Waiting and signaling the same point (when point != 2851 * 0) would break the timeline. 2852 */ 2853 if (user_fence.flags & I915_EXEC_FENCE_WAIT) { 2854 drm_dbg(&eb->i915->drm, 2855 "Trying to wait & signal the same timeline point.\n"); 2856 dma_fence_put(fence); 2857 drm_syncobj_put(syncobj); 2858 return -EINVAL; 2859 } 2860 2861 f->chain_fence = dma_fence_chain_alloc(); 2862 if (!f->chain_fence) { 2863 drm_syncobj_put(syncobj); 2864 dma_fence_put(fence); 2865 return -ENOMEM; 2866 } 2867 } else { 2868 f->chain_fence = NULL; 2869 } 2870 2871 f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2); 2872 f->dma_fence = fence; 2873 f->value = point; 2874 f++; 2875 eb->num_fences++; 2876 } 2877 2878 return 0; 2879 } 2880 2881 static int add_fence_array(struct i915_execbuffer *eb) 2882 { 2883 struct drm_i915_gem_execbuffer2 *args = eb->args; 2884 struct drm_i915_gem_exec_fence __user *user; 2885 unsigned long num_fences = args->num_cliprects; 2886 struct eb_fence *f; 2887 2888 if (!(args->flags & I915_EXEC_FENCE_ARRAY)) 2889 return 0; 2890 2891 if (!num_fences) 2892 return 0; 2893 2894 /* Check multiplication overflow for access_ok() and kvmalloc_array() */ 2895 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long)); 2896 if (num_fences > min_t(unsigned long, 2897 ULONG_MAX / sizeof(*user), 2898 SIZE_MAX / sizeof(*f) - eb->num_fences)) 2899 return -EINVAL; 2900 2901 user = u64_to_user_ptr(args->cliprects_ptr); 2902 if (!access_ok(user, num_fences * sizeof(*user))) 2903 return -EFAULT; 2904 2905 f = krealloc(eb->fences, 2906 (eb->num_fences + num_fences) * sizeof(*f), 2907 __GFP_NOWARN | GFP_KERNEL); 2908 if (!f) 2909 return -ENOMEM; 2910 2911 eb->fences = f; 2912 f += eb->num_fences; 2913 while (num_fences--) { 2914 struct drm_i915_gem_exec_fence user_fence; 2915 struct drm_syncobj *syncobj; 2916 struct dma_fence *fence = NULL; 2917 2918 if (__copy_from_user(&user_fence, user++, sizeof(user_fence))) 2919 return -EFAULT; 2920 2921 if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) 2922 return -EINVAL; 2923 2924 syncobj = drm_syncobj_find(eb->file, user_fence.handle); 2925 if (!syncobj) { 2926 drm_dbg(&eb->i915->drm, 2927 "Invalid syncobj handle provided\n"); 2928 return -ENOENT; 2929 } 2930 2931 if (user_fence.flags & I915_EXEC_FENCE_WAIT) { 2932 fence = drm_syncobj_fence_get(syncobj); 2933 if (!fence) { 2934 drm_dbg(&eb->i915->drm, 2935 "Syncobj handle has no fence\n"); 2936 drm_syncobj_put(syncobj); 2937 return -EINVAL; 2938 } 2939 } 2940 2941 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) & 2942 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS); 2943 2944 f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2); 2945 f->dma_fence = fence; 2946 f->value = 0; 2947 f->chain_fence = NULL; 2948 f++; 2949 eb->num_fences++; 2950 } 2951 2952 return 0; 2953 } 2954 2955 static void put_fence_array(struct eb_fence *fences, int num_fences) 2956 { 2957 if (fences) 2958 __free_fence_array(fences, num_fences); 2959 } 2960 2961 static int 2962 await_fence_array(struct i915_execbuffer *eb, 2963 struct i915_request *rq) 2964 { 2965 unsigned int n; 2966 int err; 2967 2968 for (n = 0; n < eb->num_fences; n++) { 2969 if (!eb->fences[n].dma_fence) 2970 continue; 2971 2972 err = i915_request_await_dma_fence(rq, eb->fences[n].dma_fence); 2973 if (err < 0) 2974 return err; 2975 } 2976 2977 return 0; 2978 } 2979 2980 static void signal_fence_array(const struct i915_execbuffer *eb, 2981 struct dma_fence * const fence) 2982 { 2983 unsigned int n; 2984 2985 for (n = 0; n < eb->num_fences; n++) { 2986 struct drm_syncobj *syncobj; 2987 unsigned int flags; 2988 2989 syncobj = ptr_unpack_bits(eb->fences[n].syncobj, &flags, 2); 2990 if (!(flags & I915_EXEC_FENCE_SIGNAL)) 2991 continue; 2992 2993 if (eb->fences[n].chain_fence) { 2994 drm_syncobj_add_point(syncobj, 2995 eb->fences[n].chain_fence, 2996 fence, 2997 eb->fences[n].value); 2998 /* 2999 * The chain's ownership is transferred to the 3000 * timeline. 3001 */ 3002 eb->fences[n].chain_fence = NULL; 3003 } else { 3004 drm_syncobj_replace_fence(syncobj, fence); 3005 } 3006 } 3007 } 3008 3009 static int 3010 parse_timeline_fences(struct i915_user_extension __user *ext, void *data) 3011 { 3012 struct i915_execbuffer *eb = data; 3013 struct drm_i915_gem_execbuffer_ext_timeline_fences timeline_fences; 3014 3015 if (copy_from_user(&timeline_fences, ext, sizeof(timeline_fences))) 3016 return -EFAULT; 3017 3018 return add_timeline_fence_array(eb, &timeline_fences); 3019 } 3020 3021 static void retire_requests(struct intel_timeline *tl, struct i915_request *end) 3022 { 3023 struct i915_request *rq, *rn; 3024 3025 list_for_each_entry_safe(rq, rn, &tl->requests, link) 3026 if (rq == end || !i915_request_retire(rq)) 3027 break; 3028 } 3029 3030 static int eb_request_add(struct i915_execbuffer *eb, struct i915_request *rq, 3031 int err, bool last_parallel) 3032 { 3033 struct intel_timeline * const tl = i915_request_timeline(rq); 3034 struct i915_sched_attr attr = {}; 3035 struct i915_request *prev; 3036 3037 lockdep_assert_held(&tl->mutex); 3038 lockdep_unpin_lock(&tl->mutex, rq->cookie); 3039 3040 trace_i915_request_add(rq); 3041 3042 prev = __i915_request_commit(rq); 3043 3044 /* Check that the context wasn't destroyed before submission */ 3045 if (likely(!intel_context_is_closed(eb->context))) { 3046 attr = eb->gem_context->sched; 3047 } else { 3048 /* Serialise with context_close via the add_to_timeline */ 3049 i915_request_set_error_once(rq, -ENOENT); 3050 __i915_request_skip(rq); 3051 err = -ENOENT; /* override any transient errors */ 3052 } 3053 3054 if (intel_context_is_parallel(eb->context)) { 3055 if (err) { 3056 __i915_request_skip(rq); 3057 set_bit(I915_FENCE_FLAG_SKIP_PARALLEL, 3058 &rq->fence.flags); 3059 } 3060 if (last_parallel) 3061 set_bit(I915_FENCE_FLAG_SUBMIT_PARALLEL, 3062 &rq->fence.flags); 3063 } 3064 3065 __i915_request_queue(rq, &attr); 3066 3067 /* Try to clean up the client's timeline after submitting the request */ 3068 if (prev) 3069 retire_requests(tl, prev); 3070 3071 mutex_unlock(&tl->mutex); 3072 3073 return err; 3074 } 3075 3076 static int eb_requests_add(struct i915_execbuffer *eb, int err) 3077 { 3078 int i; 3079 3080 /* 3081 * We iterate in reverse order of creation to release timeline mutexes in 3082 * same order. 3083 */ 3084 for_each_batch_add_order(eb, i) { 3085 struct i915_request *rq = eb->requests[i]; 3086 3087 if (!rq) 3088 continue; 3089 err |= eb_request_add(eb, rq, err, i == 0); 3090 } 3091 3092 return err; 3093 } 3094 3095 static const i915_user_extension_fn execbuf_extensions[] = { 3096 [DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES] = parse_timeline_fences, 3097 }; 3098 3099 static int 3100 parse_execbuf2_extensions(struct drm_i915_gem_execbuffer2 *args, 3101 struct i915_execbuffer *eb) 3102 { 3103 if (!(args->flags & I915_EXEC_USE_EXTENSIONS)) 3104 return 0; 3105 3106 /* The execbuf2 extension mechanism reuses cliprects_ptr. So we cannot 3107 * have another flag also using it at the same time. 3108 */ 3109 if (eb->args->flags & I915_EXEC_FENCE_ARRAY) 3110 return -EINVAL; 3111 3112 if (args->num_cliprects != 0) 3113 return -EINVAL; 3114 3115 return i915_user_extensions(u64_to_user_ptr(args->cliprects_ptr), 3116 execbuf_extensions, 3117 ARRAY_SIZE(execbuf_extensions), 3118 eb); 3119 } 3120 3121 static void eb_requests_get(struct i915_execbuffer *eb) 3122 { 3123 unsigned int i; 3124 3125 for_each_batch_create_order(eb, i) { 3126 if (!eb->requests[i]) 3127 break; 3128 3129 i915_request_get(eb->requests[i]); 3130 } 3131 } 3132 3133 static void eb_requests_put(struct i915_execbuffer *eb) 3134 { 3135 unsigned int i; 3136 3137 for_each_batch_create_order(eb, i) { 3138 if (!eb->requests[i]) 3139 break; 3140 3141 i915_request_put(eb->requests[i]); 3142 } 3143 } 3144 3145 static struct sync_file * 3146 eb_composite_fence_create(struct i915_execbuffer *eb, int out_fence_fd) 3147 { 3148 struct sync_file *out_fence = NULL; 3149 struct dma_fence_array *fence_array; 3150 struct dma_fence **fences; 3151 unsigned int i; 3152 3153 GEM_BUG_ON(!intel_context_is_parent(eb->context)); 3154 3155 fences = kmalloc_array(eb->num_batches, sizeof(*fences), GFP_KERNEL); 3156 if (!fences) 3157 return ERR_PTR(-ENOMEM); 3158 3159 for_each_batch_create_order(eb, i) { 3160 fences[i] = &eb->requests[i]->fence; 3161 __set_bit(I915_FENCE_FLAG_COMPOSITE, 3162 &eb->requests[i]->fence.flags); 3163 } 3164 3165 fence_array = dma_fence_array_create(eb->num_batches, 3166 fences, 3167 eb->context->parallel.fence_context, 3168 eb->context->parallel.seqno++, 3169 false); 3170 if (!fence_array) { 3171 kfree(fences); 3172 return ERR_PTR(-ENOMEM); 3173 } 3174 3175 /* Move ownership to the dma_fence_array created above */ 3176 for_each_batch_create_order(eb, i) 3177 dma_fence_get(fences[i]); 3178 3179 if (out_fence_fd != -1) { 3180 out_fence = sync_file_create(&fence_array->base); 3181 /* sync_file now owns fence_arry, drop creation ref */ 3182 dma_fence_put(&fence_array->base); 3183 if (!out_fence) 3184 return ERR_PTR(-ENOMEM); 3185 } 3186 3187 eb->composite_fence = &fence_array->base; 3188 3189 return out_fence; 3190 } 3191 3192 static struct sync_file * 3193 eb_fences_add(struct i915_execbuffer *eb, struct i915_request *rq, 3194 struct dma_fence *in_fence, int out_fence_fd) 3195 { 3196 struct sync_file *out_fence = NULL; 3197 int err; 3198 3199 if (unlikely(eb->gem_context->syncobj)) { 3200 struct dma_fence *fence; 3201 3202 fence = drm_syncobj_fence_get(eb->gem_context->syncobj); 3203 err = i915_request_await_dma_fence(rq, fence); 3204 dma_fence_put(fence); 3205 if (err) 3206 return ERR_PTR(err); 3207 } 3208 3209 if (in_fence) { 3210 if (eb->args->flags & I915_EXEC_FENCE_SUBMIT) 3211 err = i915_request_await_execution(rq, in_fence); 3212 else 3213 err = i915_request_await_dma_fence(rq, in_fence); 3214 if (err < 0) 3215 return ERR_PTR(err); 3216 } 3217 3218 if (eb->fences) { 3219 err = await_fence_array(eb, rq); 3220 if (err) 3221 return ERR_PTR(err); 3222 } 3223 3224 if (intel_context_is_parallel(eb->context)) { 3225 out_fence = eb_composite_fence_create(eb, out_fence_fd); 3226 if (IS_ERR(out_fence)) 3227 return ERR_PTR(-ENOMEM); 3228 } else if (out_fence_fd != -1) { 3229 out_fence = sync_file_create(&rq->fence); 3230 if (!out_fence) 3231 return ERR_PTR(-ENOMEM); 3232 } 3233 3234 return out_fence; 3235 } 3236 3237 static struct intel_context * 3238 eb_find_context(struct i915_execbuffer *eb, unsigned int context_number) 3239 { 3240 struct intel_context *child; 3241 3242 if (likely(context_number == 0)) 3243 return eb->context; 3244 3245 for_each_child(eb->context, child) 3246 if (!--context_number) 3247 return child; 3248 3249 GEM_BUG_ON("Context not found"); 3250 3251 return NULL; 3252 } 3253 3254 static struct sync_file * 3255 eb_requests_create(struct i915_execbuffer *eb, struct dma_fence *in_fence, 3256 int out_fence_fd) 3257 { 3258 struct sync_file *out_fence = NULL; 3259 unsigned int i; 3260 3261 for_each_batch_create_order(eb, i) { 3262 /* Allocate a request for this batch buffer nice and early. */ 3263 eb->requests[i] = i915_request_create(eb_find_context(eb, i)); 3264 if (IS_ERR(eb->requests[i])) { 3265 out_fence = ERR_CAST(eb->requests[i]); 3266 eb->requests[i] = NULL; 3267 return out_fence; 3268 } 3269 3270 /* 3271 * Only the first request added (committed to backend) has to 3272 * take the in fences into account as all subsequent requests 3273 * will have fences inserted inbetween them. 3274 */ 3275 if (i + 1 == eb->num_batches) { 3276 out_fence = eb_fences_add(eb, eb->requests[i], 3277 in_fence, out_fence_fd); 3278 if (IS_ERR(out_fence)) 3279 return out_fence; 3280 } 3281 3282 /* 3283 * Not really on stack, but we don't want to call 3284 * kfree on the batch_snapshot when we put it, so use the 3285 * _onstack interface. 3286 */ 3287 if (eb->batches[i]->vma) 3288 eb->requests[i]->batch_res = 3289 i915_vma_resource_get(eb->batches[i]->vma->resource); 3290 if (eb->batch_pool) { 3291 GEM_BUG_ON(intel_context_is_parallel(eb->context)); 3292 intel_gt_buffer_pool_mark_active(eb->batch_pool, 3293 eb->requests[i]); 3294 } 3295 } 3296 3297 return out_fence; 3298 } 3299 3300 static int 3301 i915_gem_do_execbuffer(struct drm_device *dev, 3302 struct drm_file *file, 3303 struct drm_i915_gem_execbuffer2 *args, 3304 struct drm_i915_gem_exec_object2 *exec) 3305 { 3306 struct drm_i915_private *i915 = to_i915(dev); 3307 struct i915_execbuffer eb; 3308 struct dma_fence *in_fence = NULL; 3309 struct sync_file *out_fence = NULL; 3310 int out_fence_fd = -1; 3311 int err; 3312 3313 BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS); 3314 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS & 3315 ~__EXEC_OBJECT_UNKNOWN_FLAGS); 3316 3317 eb.i915 = i915; 3318 eb.file = file; 3319 eb.args = args; 3320 if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC)) 3321 args->flags |= __EXEC_HAS_RELOC; 3322 3323 eb.exec = exec; 3324 eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1); 3325 eb.vma[0].vma = NULL; 3326 eb.batch_pool = NULL; 3327 3328 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; 3329 reloc_cache_init(&eb.reloc_cache, eb.i915); 3330 3331 eb.buffer_count = args->buffer_count; 3332 eb.batch_start_offset = args->batch_start_offset; 3333 eb.trampoline = NULL; 3334 3335 eb.fences = NULL; 3336 eb.num_fences = 0; 3337 3338 eb_capture_list_clear(&eb); 3339 3340 memset(eb.requests, 0, sizeof(struct i915_request *) * 3341 ARRAY_SIZE(eb.requests)); 3342 eb.composite_fence = NULL; 3343 3344 eb.batch_flags = 0; 3345 if (args->flags & I915_EXEC_SECURE) { 3346 if (GRAPHICS_VER(i915) >= 11) 3347 return -ENODEV; 3348 3349 /* Return -EPERM to trigger fallback code on old binaries. */ 3350 if (!HAS_SECURE_BATCHES(i915)) 3351 return -EPERM; 3352 3353 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN)) 3354 return -EPERM; 3355 3356 eb.batch_flags |= I915_DISPATCH_SECURE; 3357 } 3358 if (args->flags & I915_EXEC_IS_PINNED) 3359 eb.batch_flags |= I915_DISPATCH_PINNED; 3360 3361 err = parse_execbuf2_extensions(args, &eb); 3362 if (err) 3363 goto err_ext; 3364 3365 err = add_fence_array(&eb); 3366 if (err) 3367 goto err_ext; 3368 3369 #define IN_FENCES (I915_EXEC_FENCE_IN | I915_EXEC_FENCE_SUBMIT) 3370 if (args->flags & IN_FENCES) { 3371 if ((args->flags & IN_FENCES) == IN_FENCES) 3372 return -EINVAL; 3373 3374 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2)); 3375 if (!in_fence) { 3376 err = -EINVAL; 3377 goto err_ext; 3378 } 3379 } 3380 #undef IN_FENCES 3381 3382 if (args->flags & I915_EXEC_FENCE_OUT) { 3383 out_fence_fd = get_unused_fd_flags(O_CLOEXEC); 3384 if (out_fence_fd < 0) { 3385 err = out_fence_fd; 3386 goto err_in_fence; 3387 } 3388 } 3389 3390 err = eb_create(&eb); 3391 if (err) 3392 goto err_out_fence; 3393 3394 GEM_BUG_ON(!eb.lut_size); 3395 3396 err = eb_select_context(&eb); 3397 if (unlikely(err)) 3398 goto err_destroy; 3399 3400 err = eb_select_engine(&eb); 3401 if (unlikely(err)) 3402 goto err_context; 3403 3404 err = eb_lookup_vmas(&eb); 3405 if (err) { 3406 eb_release_vmas(&eb, true); 3407 goto err_engine; 3408 } 3409 3410 i915_gem_ww_ctx_init(&eb.ww, true); 3411 3412 err = eb_relocate_parse(&eb); 3413 if (err) { 3414 /* 3415 * If the user expects the execobject.offset and 3416 * reloc.presumed_offset to be an exact match, 3417 * as for using NO_RELOC, then we cannot update 3418 * the execobject.offset until we have completed 3419 * relocation. 3420 */ 3421 args->flags &= ~__EXEC_HAS_RELOC; 3422 goto err_vma; 3423 } 3424 3425 ww_acquire_done(&eb.ww.ctx); 3426 err = eb_capture_stage(&eb); 3427 if (err) 3428 goto err_vma; 3429 3430 out_fence = eb_requests_create(&eb, in_fence, out_fence_fd); 3431 if (IS_ERR(out_fence)) { 3432 err = PTR_ERR(out_fence); 3433 out_fence = NULL; 3434 if (eb.requests[0]) 3435 goto err_request; 3436 else 3437 goto err_vma; 3438 } 3439 3440 err = eb_submit(&eb); 3441 3442 err_request: 3443 eb_requests_get(&eb); 3444 err = eb_requests_add(&eb, err); 3445 3446 if (eb.fences) 3447 signal_fence_array(&eb, eb.composite_fence ? 3448 eb.composite_fence : 3449 &eb.requests[0]->fence); 3450 3451 if (out_fence) { 3452 if (err == 0) { 3453 fd_install(out_fence_fd, out_fence->file); 3454 args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */ 3455 args->rsvd2 |= (u64)out_fence_fd << 32; 3456 out_fence_fd = -1; 3457 } else { 3458 fput(out_fence->file); 3459 } 3460 } 3461 3462 if (unlikely(eb.gem_context->syncobj)) { 3463 drm_syncobj_replace_fence(eb.gem_context->syncobj, 3464 eb.composite_fence ? 3465 eb.composite_fence : 3466 &eb.requests[0]->fence); 3467 } 3468 3469 if (!out_fence && eb.composite_fence) 3470 dma_fence_put(eb.composite_fence); 3471 3472 eb_requests_put(&eb); 3473 3474 err_vma: 3475 eb_release_vmas(&eb, true); 3476 WARN_ON(err == -EDEADLK); 3477 i915_gem_ww_ctx_fini(&eb.ww); 3478 3479 if (eb.batch_pool) 3480 intel_gt_buffer_pool_put(eb.batch_pool); 3481 err_engine: 3482 eb_put_engine(&eb); 3483 err_context: 3484 i915_gem_context_put(eb.gem_context); 3485 err_destroy: 3486 eb_destroy(&eb); 3487 err_out_fence: 3488 if (out_fence_fd != -1) 3489 put_unused_fd(out_fence_fd); 3490 err_in_fence: 3491 dma_fence_put(in_fence); 3492 err_ext: 3493 put_fence_array(eb.fences, eb.num_fences); 3494 return err; 3495 } 3496 3497 static size_t eb_element_size(void) 3498 { 3499 return sizeof(struct drm_i915_gem_exec_object2) + sizeof(struct eb_vma); 3500 } 3501 3502 static bool check_buffer_count(size_t count) 3503 { 3504 const size_t sz = eb_element_size(); 3505 3506 /* 3507 * When using LUT_HANDLE, we impose a limit of INT_MAX for the lookup 3508 * array size (see eb_create()). Otherwise, we can accept an array as 3509 * large as can be addressed (though use large arrays at your peril)! 3510 */ 3511 3512 return !(count < 1 || count > INT_MAX || count > SIZE_MAX / sz - 1); 3513 } 3514 3515 int 3516 i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data, 3517 struct drm_file *file) 3518 { 3519 struct drm_i915_private *i915 = to_i915(dev); 3520 struct drm_i915_gem_execbuffer2 *args = data; 3521 struct drm_i915_gem_exec_object2 *exec2_list; 3522 const size_t count = args->buffer_count; 3523 int err; 3524 3525 if (!check_buffer_count(count)) { 3526 drm_dbg(&i915->drm, "execbuf2 with %zd buffers\n", count); 3527 return -EINVAL; 3528 } 3529 3530 err = i915_gem_check_execbuffer(i915, args); 3531 if (err) 3532 return err; 3533 3534 /* Allocate extra slots for use by the command parser */ 3535 exec2_list = kvmalloc_array(count + 2, eb_element_size(), 3536 __GFP_NOWARN | GFP_KERNEL); 3537 if (exec2_list == NULL) { 3538 drm_dbg(&i915->drm, "Failed to allocate exec list for %zd buffers\n", 3539 count); 3540 return -ENOMEM; 3541 } 3542 if (copy_from_user(exec2_list, 3543 u64_to_user_ptr(args->buffers_ptr), 3544 sizeof(*exec2_list) * count)) { 3545 drm_dbg(&i915->drm, "copy %zd exec entries failed\n", count); 3546 kvfree(exec2_list); 3547 return -EFAULT; 3548 } 3549 3550 err = i915_gem_do_execbuffer(dev, file, args, exec2_list); 3551 3552 /* 3553 * Now that we have begun execution of the batchbuffer, we ignore 3554 * any new error after this point. Also given that we have already 3555 * updated the associated relocations, we try to write out the current 3556 * object locations irrespective of any error. 3557 */ 3558 if (args->flags & __EXEC_HAS_RELOC) { 3559 struct drm_i915_gem_exec_object2 __user *user_exec_list = 3560 u64_to_user_ptr(args->buffers_ptr); 3561 unsigned int i; 3562 3563 /* Copy the new buffer offsets back to the user's exec list. */ 3564 /* 3565 * Note: count * sizeof(*user_exec_list) does not overflow, 3566 * because we checked 'count' in check_buffer_count(). 3567 * 3568 * And this range already got effectively checked earlier 3569 * when we did the "copy_from_user()" above. 3570 */ 3571 if (!user_write_access_begin(user_exec_list, 3572 count * sizeof(*user_exec_list))) 3573 goto end; 3574 3575 for (i = 0; i < args->buffer_count; i++) { 3576 if (!(exec2_list[i].offset & UPDATE)) 3577 continue; 3578 3579 exec2_list[i].offset = 3580 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK); 3581 unsafe_put_user(exec2_list[i].offset, 3582 &user_exec_list[i].offset, 3583 end_user); 3584 } 3585 end_user: 3586 user_write_access_end(); 3587 end:; 3588 } 3589 3590 args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS; 3591 kvfree(exec2_list); 3592 return err; 3593 } 3594