1 /*
2  * SPDX-License-Identifier: MIT
3  *
4  * Copyright © 2008,2010 Intel Corporation
5  */
6 
7 #include <linux/dma-resv.h>
8 #include <linux/highmem.h>
9 #include <linux/sync_file.h>
10 #include <linux/uaccess.h>
11 
12 #include <drm/drm_syncobj.h>
13 
14 #include "display/intel_frontbuffer.h"
15 
16 #include "gem/i915_gem_ioctls.h"
17 #include "gt/intel_context.h"
18 #include "gt/intel_gpu_commands.h"
19 #include "gt/intel_gt.h"
20 #include "gt/intel_gt_buffer_pool.h"
21 #include "gt/intel_gt_pm.h"
22 #include "gt/intel_ring.h"
23 
24 #include "pxp/intel_pxp.h"
25 
26 #include "i915_cmd_parser.h"
27 #include "i915_drv.h"
28 #include "i915_file_private.h"
29 #include "i915_gem_clflush.h"
30 #include "i915_gem_context.h"
31 #include "i915_gem_evict.h"
32 #include "i915_gem_ioctls.h"
33 #include "i915_reg.h"
34 #include "i915_trace.h"
35 #include "i915_user_extensions.h"
36 
37 struct eb_vma {
38 	struct i915_vma *vma;
39 	unsigned int flags;
40 
41 	/** This vma's place in the execbuf reservation list */
42 	struct drm_i915_gem_exec_object2 *exec;
43 	struct list_head bind_link;
44 	struct list_head reloc_link;
45 
46 	struct hlist_node node;
47 	u32 handle;
48 };
49 
50 enum {
51 	FORCE_CPU_RELOC = 1,
52 	FORCE_GTT_RELOC,
53 	FORCE_GPU_RELOC,
54 #define DBG_FORCE_RELOC 0 /* choose one of the above! */
55 };
56 
57 /* __EXEC_OBJECT_ flags > BIT(29) defined in i915_vma.h */
58 #define __EXEC_OBJECT_HAS_PIN		BIT(29)
59 #define __EXEC_OBJECT_HAS_FENCE		BIT(28)
60 #define __EXEC_OBJECT_USERPTR_INIT	BIT(27)
61 #define __EXEC_OBJECT_NEEDS_MAP		BIT(26)
62 #define __EXEC_OBJECT_NEEDS_BIAS	BIT(25)
63 #define __EXEC_OBJECT_INTERNAL_FLAGS	(~0u << 25) /* all of the above + */
64 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE)
65 
66 #define __EXEC_HAS_RELOC	BIT(31)
67 #define __EXEC_ENGINE_PINNED	BIT(30)
68 #define __EXEC_USERPTR_USED	BIT(29)
69 #define __EXEC_INTERNAL_FLAGS	(~0u << 29)
70 #define UPDATE			PIN_OFFSET_FIXED
71 
72 #define BATCH_OFFSET_BIAS (256*1024)
73 
74 #define __I915_EXEC_ILLEGAL_FLAGS \
75 	(__I915_EXEC_UNKNOWN_FLAGS | \
76 	 I915_EXEC_CONSTANTS_MASK  | \
77 	 I915_EXEC_RESOURCE_STREAMER)
78 
79 /* Catch emission of unexpected errors for CI! */
80 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
81 #undef EINVAL
82 #define EINVAL ({ \
83 	DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
84 	22; \
85 })
86 #endif
87 
88 /**
89  * DOC: User command execution
90  *
91  * Userspace submits commands to be executed on the GPU as an instruction
92  * stream within a GEM object we call a batchbuffer. This instructions may
93  * refer to other GEM objects containing auxiliary state such as kernels,
94  * samplers, render targets and even secondary batchbuffers. Userspace does
95  * not know where in the GPU memory these objects reside and so before the
96  * batchbuffer is passed to the GPU for execution, those addresses in the
97  * batchbuffer and auxiliary objects are updated. This is known as relocation,
98  * or patching. To try and avoid having to relocate each object on the next
99  * execution, userspace is told the location of those objects in this pass,
100  * but this remains just a hint as the kernel may choose a new location for
101  * any object in the future.
102  *
103  * At the level of talking to the hardware, submitting a batchbuffer for the
104  * GPU to execute is to add content to a buffer from which the HW
105  * command streamer is reading.
106  *
107  * 1. Add a command to load the HW context. For Logical Ring Contexts, i.e.
108  *    Execlists, this command is not placed on the same buffer as the
109  *    remaining items.
110  *
111  * 2. Add a command to invalidate caches to the buffer.
112  *
113  * 3. Add a batchbuffer start command to the buffer; the start command is
114  *    essentially a token together with the GPU address of the batchbuffer
115  *    to be executed.
116  *
117  * 4. Add a pipeline flush to the buffer.
118  *
119  * 5. Add a memory write command to the buffer to record when the GPU
120  *    is done executing the batchbuffer. The memory write writes the
121  *    global sequence number of the request, ``i915_request::global_seqno``;
122  *    the i915 driver uses the current value in the register to determine
123  *    if the GPU has completed the batchbuffer.
124  *
125  * 6. Add a user interrupt command to the buffer. This command instructs
126  *    the GPU to issue an interrupt when the command, pipeline flush and
127  *    memory write are completed.
128  *
129  * 7. Inform the hardware of the additional commands added to the buffer
130  *    (by updating the tail pointer).
131  *
132  * Processing an execbuf ioctl is conceptually split up into a few phases.
133  *
134  * 1. Validation - Ensure all the pointers, handles and flags are valid.
135  * 2. Reservation - Assign GPU address space for every object
136  * 3. Relocation - Update any addresses to point to the final locations
137  * 4. Serialisation - Order the request with respect to its dependencies
138  * 5. Construction - Construct a request to execute the batchbuffer
139  * 6. Submission (at some point in the future execution)
140  *
141  * Reserving resources for the execbuf is the most complicated phase. We
142  * neither want to have to migrate the object in the address space, nor do
143  * we want to have to update any relocations pointing to this object. Ideally,
144  * we want to leave the object where it is and for all the existing relocations
145  * to match. If the object is given a new address, or if userspace thinks the
146  * object is elsewhere, we have to parse all the relocation entries and update
147  * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that
148  * all the target addresses in all of its objects match the value in the
149  * relocation entries and that they all match the presumed offsets given by the
150  * list of execbuffer objects. Using this knowledge, we know that if we haven't
151  * moved any buffers, all the relocation entries are valid and we can skip
152  * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
153  * hang.) The requirement for using I915_EXEC_NO_RELOC are:
154  *
155  *      The addresses written in the objects must match the corresponding
156  *      reloc.presumed_offset which in turn must match the corresponding
157  *      execobject.offset.
158  *
159  *      Any render targets written to in the batch must be flagged with
160  *      EXEC_OBJECT_WRITE.
161  *
162  *      To avoid stalling, execobject.offset should match the current
163  *      address of that object within the active context.
164  *
165  * The reservation is done is multiple phases. First we try and keep any
166  * object already bound in its current location - so as long as meets the
167  * constraints imposed by the new execbuffer. Any object left unbound after the
168  * first pass is then fitted into any available idle space. If an object does
169  * not fit, all objects are removed from the reservation and the process rerun
170  * after sorting the objects into a priority order (more difficult to fit
171  * objects are tried first). Failing that, the entire VM is cleared and we try
172  * to fit the execbuf once last time before concluding that it simply will not
173  * fit.
174  *
175  * A small complication to all of this is that we allow userspace not only to
176  * specify an alignment and a size for the object in the address space, but
177  * we also allow userspace to specify the exact offset. This objects are
178  * simpler to place (the location is known a priori) all we have to do is make
179  * sure the space is available.
180  *
181  * Once all the objects are in place, patching up the buried pointers to point
182  * to the final locations is a fairly simple job of walking over the relocation
183  * entry arrays, looking up the right address and rewriting the value into
184  * the object. Simple! ... The relocation entries are stored in user memory
185  * and so to access them we have to copy them into a local buffer. That copy
186  * has to avoid taking any pagefaults as they may lead back to a GEM object
187  * requiring the struct_mutex (i.e. recursive deadlock). So once again we split
188  * the relocation into multiple passes. First we try to do everything within an
189  * atomic context (avoid the pagefaults) which requires that we never wait. If
190  * we detect that we may wait, or if we need to fault, then we have to fallback
191  * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
192  * bells yet?) Dropping the mutex means that we lose all the state we have
193  * built up so far for the execbuf and we must reset any global data. However,
194  * we do leave the objects pinned in their final locations - which is a
195  * potential issue for concurrent execbufs. Once we have left the mutex, we can
196  * allocate and copy all the relocation entries into a large array at our
197  * leisure, reacquire the mutex, reclaim all the objects and other state and
198  * then proceed to update any incorrect addresses with the objects.
199  *
200  * As we process the relocation entries, we maintain a record of whether the
201  * object is being written to. Using NORELOC, we expect userspace to provide
202  * this information instead. We also check whether we can skip the relocation
203  * by comparing the expected value inside the relocation entry with the target's
204  * final address. If they differ, we have to map the current object and rewrite
205  * the 4 or 8 byte pointer within.
206  *
207  * Serialising an execbuf is quite simple according to the rules of the GEM
208  * ABI. Execution within each context is ordered by the order of submission.
209  * Writes to any GEM object are in order of submission and are exclusive. Reads
210  * from a GEM object are unordered with respect to other reads, but ordered by
211  * writes. A write submitted after a read cannot occur before the read, and
212  * similarly any read submitted after a write cannot occur before the write.
213  * Writes are ordered between engines such that only one write occurs at any
214  * time (completing any reads beforehand) - using semaphores where available
215  * and CPU serialisation otherwise. Other GEM access obey the same rules, any
216  * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
217  * reads before starting, and any read (either using set-domain or pread) must
218  * flush all GPU writes before starting. (Note we only employ a barrier before,
219  * we currently rely on userspace not concurrently starting a new execution
220  * whilst reading or writing to an object. This may be an advantage or not
221  * depending on how much you trust userspace not to shoot themselves in the
222  * foot.) Serialisation may just result in the request being inserted into
223  * a DAG awaiting its turn, but most simple is to wait on the CPU until
224  * all dependencies are resolved.
225  *
226  * After all of that, is just a matter of closing the request and handing it to
227  * the hardware (well, leaving it in a queue to be executed). However, we also
228  * offer the ability for batchbuffers to be run with elevated privileges so
229  * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
230  * Before any batch is given extra privileges we first must check that it
231  * contains no nefarious instructions, we check that each instruction is from
232  * our whitelist and all registers are also from an allowed list. We first
233  * copy the user's batchbuffer to a shadow (so that the user doesn't have
234  * access to it, either by the CPU or GPU as we scan it) and then parse each
235  * instruction. If everything is ok, we set a flag telling the hardware to run
236  * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
237  */
238 
239 struct eb_fence {
240 	struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */
241 	struct dma_fence *dma_fence;
242 	u64 value;
243 	struct dma_fence_chain *chain_fence;
244 };
245 
246 struct i915_execbuffer {
247 	struct drm_i915_private *i915; /** i915 backpointer */
248 	struct drm_file *file; /** per-file lookup tables and limits */
249 	struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */
250 	struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */
251 	struct eb_vma *vma;
252 
253 	struct intel_gt *gt; /* gt for the execbuf */
254 	struct intel_context *context; /* logical state for the request */
255 	struct i915_gem_context *gem_context; /** caller's context */
256 
257 	/** our requests to build */
258 	struct i915_request *requests[MAX_ENGINE_INSTANCE + 1];
259 	/** identity of the batch obj/vma */
260 	struct eb_vma *batches[MAX_ENGINE_INSTANCE + 1];
261 	struct i915_vma *trampoline; /** trampoline used for chaining */
262 
263 	/** used for excl fence in dma_resv objects when > 1 BB submitted */
264 	struct dma_fence *composite_fence;
265 
266 	/** actual size of execobj[] as we may extend it for the cmdparser */
267 	unsigned int buffer_count;
268 
269 	/* number of batches in execbuf IOCTL */
270 	unsigned int num_batches;
271 
272 	/** list of vma not yet bound during reservation phase */
273 	struct list_head unbound;
274 
275 	/** list of vma that have execobj.relocation_count */
276 	struct list_head relocs;
277 
278 	struct i915_gem_ww_ctx ww;
279 
280 	/**
281 	 * Track the most recently used object for relocations, as we
282 	 * frequently have to perform multiple relocations within the same
283 	 * obj/page
284 	 */
285 	struct reloc_cache {
286 		struct drm_mm_node node; /** temporary GTT binding */
287 		unsigned long vaddr; /** Current kmap address */
288 		unsigned long page; /** Currently mapped page index */
289 		unsigned int graphics_ver; /** Cached value of GRAPHICS_VER */
290 		bool use_64bit_reloc : 1;
291 		bool has_llc : 1;
292 		bool has_fence : 1;
293 		bool needs_unfenced : 1;
294 	} reloc_cache;
295 
296 	u64 invalid_flags; /** Set of execobj.flags that are invalid */
297 
298 	/** Length of batch within object */
299 	u64 batch_len[MAX_ENGINE_INSTANCE + 1];
300 	u32 batch_start_offset; /** Location within object of batch */
301 	u32 batch_flags; /** Flags composed for emit_bb_start() */
302 	struct intel_gt_buffer_pool_node *batch_pool; /** pool node for batch buffer */
303 
304 	/**
305 	 * Indicate either the size of the hastable used to resolve
306 	 * relocation handles, or if negative that we are using a direct
307 	 * index into the execobj[].
308 	 */
309 	int lut_size;
310 	struct hlist_head *buckets; /** ht for relocation handles */
311 
312 	struct eb_fence *fences;
313 	unsigned long num_fences;
314 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
315 	struct i915_capture_list *capture_lists[MAX_ENGINE_INSTANCE + 1];
316 #endif
317 };
318 
319 static int eb_parse(struct i915_execbuffer *eb);
320 static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle);
321 static void eb_unpin_engine(struct i915_execbuffer *eb);
322 static void eb_capture_release(struct i915_execbuffer *eb);
323 
324 static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
325 {
326 	return intel_engine_requires_cmd_parser(eb->context->engine) ||
327 		(intel_engine_using_cmd_parser(eb->context->engine) &&
328 		 eb->args->batch_len);
329 }
330 
331 static int eb_create(struct i915_execbuffer *eb)
332 {
333 	if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
334 		unsigned int size = 1 + ilog2(eb->buffer_count);
335 
336 		/*
337 		 * Without a 1:1 association between relocation handles and
338 		 * the execobject[] index, we instead create a hashtable.
339 		 * We size it dynamically based on available memory, starting
340 		 * first with 1:1 assocative hash and scaling back until
341 		 * the allocation succeeds.
342 		 *
343 		 * Later on we use a positive lut_size to indicate we are
344 		 * using this hashtable, and a negative value to indicate a
345 		 * direct lookup.
346 		 */
347 		do {
348 			gfp_t flags;
349 
350 			/* While we can still reduce the allocation size, don't
351 			 * raise a warning and allow the allocation to fail.
352 			 * On the last pass though, we want to try as hard
353 			 * as possible to perform the allocation and warn
354 			 * if it fails.
355 			 */
356 			flags = GFP_KERNEL;
357 			if (size > 1)
358 				flags |= __GFP_NORETRY | __GFP_NOWARN;
359 
360 			eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
361 					      flags);
362 			if (eb->buckets)
363 				break;
364 		} while (--size);
365 
366 		if (unlikely(!size))
367 			return -ENOMEM;
368 
369 		eb->lut_size = size;
370 	} else {
371 		eb->lut_size = -eb->buffer_count;
372 	}
373 
374 	return 0;
375 }
376 
377 static bool
378 eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
379 		 const struct i915_vma *vma,
380 		 unsigned int flags)
381 {
382 	const u64 start = i915_vma_offset(vma);
383 	const u64 size = i915_vma_size(vma);
384 
385 	if (size < entry->pad_to_size)
386 		return true;
387 
388 	if (entry->alignment && !IS_ALIGNED(start, entry->alignment))
389 		return true;
390 
391 	if (flags & EXEC_OBJECT_PINNED &&
392 	    start != entry->offset)
393 		return true;
394 
395 	if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
396 	    start < BATCH_OFFSET_BIAS)
397 		return true;
398 
399 	if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
400 	    (start + size + 4095) >> 32)
401 		return true;
402 
403 	if (flags & __EXEC_OBJECT_NEEDS_MAP &&
404 	    !i915_vma_is_map_and_fenceable(vma))
405 		return true;
406 
407 	return false;
408 }
409 
410 static u64 eb_pin_flags(const struct drm_i915_gem_exec_object2 *entry,
411 			unsigned int exec_flags)
412 {
413 	u64 pin_flags = 0;
414 
415 	if (exec_flags & EXEC_OBJECT_NEEDS_GTT)
416 		pin_flags |= PIN_GLOBAL;
417 
418 	/*
419 	 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
420 	 * limit address to the first 4GBs for unflagged objects.
421 	 */
422 	if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
423 		pin_flags |= PIN_ZONE_4G;
424 
425 	if (exec_flags & __EXEC_OBJECT_NEEDS_MAP)
426 		pin_flags |= PIN_MAPPABLE;
427 
428 	if (exec_flags & EXEC_OBJECT_PINNED)
429 		pin_flags |= entry->offset | PIN_OFFSET_FIXED;
430 	else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS)
431 		pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
432 
433 	return pin_flags;
434 }
435 
436 static inline int
437 eb_pin_vma(struct i915_execbuffer *eb,
438 	   const struct drm_i915_gem_exec_object2 *entry,
439 	   struct eb_vma *ev)
440 {
441 	struct i915_vma *vma = ev->vma;
442 	u64 pin_flags;
443 	int err;
444 
445 	if (vma->node.size)
446 		pin_flags =  __i915_vma_offset(vma);
447 	else
448 		pin_flags = entry->offset & PIN_OFFSET_MASK;
449 
450 	pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED | PIN_VALIDATE;
451 	if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_GTT))
452 		pin_flags |= PIN_GLOBAL;
453 
454 	/* Attempt to reuse the current location if available */
455 	err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, pin_flags);
456 	if (err == -EDEADLK)
457 		return err;
458 
459 	if (unlikely(err)) {
460 		if (entry->flags & EXEC_OBJECT_PINNED)
461 			return err;
462 
463 		/* Failing that pick any _free_ space if suitable */
464 		err = i915_vma_pin_ww(vma, &eb->ww,
465 					     entry->pad_to_size,
466 					     entry->alignment,
467 					     eb_pin_flags(entry, ev->flags) |
468 					     PIN_USER | PIN_NOEVICT | PIN_VALIDATE);
469 		if (unlikely(err))
470 			return err;
471 	}
472 
473 	if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
474 		err = i915_vma_pin_fence(vma);
475 		if (unlikely(err))
476 			return err;
477 
478 		if (vma->fence)
479 			ev->flags |= __EXEC_OBJECT_HAS_FENCE;
480 	}
481 
482 	ev->flags |= __EXEC_OBJECT_HAS_PIN;
483 	if (eb_vma_misplaced(entry, vma, ev->flags))
484 		return -EBADSLT;
485 
486 	return 0;
487 }
488 
489 static inline void
490 eb_unreserve_vma(struct eb_vma *ev)
491 {
492 	if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE))
493 		__i915_vma_unpin_fence(ev->vma);
494 
495 	ev->flags &= ~__EXEC_OBJECT_RESERVED;
496 }
497 
498 static int
499 eb_validate_vma(struct i915_execbuffer *eb,
500 		struct drm_i915_gem_exec_object2 *entry,
501 		struct i915_vma *vma)
502 {
503 	/* Relocations are disallowed for all platforms after TGL-LP.  This
504 	 * also covers all platforms with local memory.
505 	 */
506 	if (entry->relocation_count &&
507 	    GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
508 		return -EINVAL;
509 
510 	if (unlikely(entry->flags & eb->invalid_flags))
511 		return -EINVAL;
512 
513 	if (unlikely(entry->alignment &&
514 		     !is_power_of_2_u64(entry->alignment)))
515 		return -EINVAL;
516 
517 	/*
518 	 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
519 	 * any non-page-aligned or non-canonical addresses.
520 	 */
521 	if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
522 		     entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
523 		return -EINVAL;
524 
525 	/* pad_to_size was once a reserved field, so sanitize it */
526 	if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
527 		if (unlikely(offset_in_page(entry->pad_to_size)))
528 			return -EINVAL;
529 	} else {
530 		entry->pad_to_size = 0;
531 	}
532 	/*
533 	 * From drm_mm perspective address space is continuous,
534 	 * so from this point we're always using non-canonical
535 	 * form internally.
536 	 */
537 	entry->offset = gen8_noncanonical_addr(entry->offset);
538 
539 	if (!eb->reloc_cache.has_fence) {
540 		entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
541 	} else {
542 		if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
543 		     eb->reloc_cache.needs_unfenced) &&
544 		    i915_gem_object_is_tiled(vma->obj))
545 			entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP;
546 	}
547 
548 	return 0;
549 }
550 
551 static inline bool
552 is_batch_buffer(struct i915_execbuffer *eb, unsigned int buffer_idx)
553 {
554 	return eb->args->flags & I915_EXEC_BATCH_FIRST ?
555 		buffer_idx < eb->num_batches :
556 		buffer_idx >= eb->args->buffer_count - eb->num_batches;
557 }
558 
559 static int
560 eb_add_vma(struct i915_execbuffer *eb,
561 	   unsigned int *current_batch,
562 	   unsigned int i,
563 	   struct i915_vma *vma)
564 {
565 	struct drm_i915_private *i915 = eb->i915;
566 	struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
567 	struct eb_vma *ev = &eb->vma[i];
568 
569 	ev->vma = vma;
570 	ev->exec = entry;
571 	ev->flags = entry->flags;
572 
573 	if (eb->lut_size > 0) {
574 		ev->handle = entry->handle;
575 		hlist_add_head(&ev->node,
576 			       &eb->buckets[hash_32(entry->handle,
577 						    eb->lut_size)]);
578 	}
579 
580 	if (entry->relocation_count)
581 		list_add_tail(&ev->reloc_link, &eb->relocs);
582 
583 	/*
584 	 * SNA is doing fancy tricks with compressing batch buffers, which leads
585 	 * to negative relocation deltas. Usually that works out ok since the
586 	 * relocate address is still positive, except when the batch is placed
587 	 * very low in the GTT. Ensure this doesn't happen.
588 	 *
589 	 * Note that actual hangs have only been observed on gen7, but for
590 	 * paranoia do it everywhere.
591 	 */
592 	if (is_batch_buffer(eb, i)) {
593 		if (entry->relocation_count &&
594 		    !(ev->flags & EXEC_OBJECT_PINNED))
595 			ev->flags |= __EXEC_OBJECT_NEEDS_BIAS;
596 		if (eb->reloc_cache.has_fence)
597 			ev->flags |= EXEC_OBJECT_NEEDS_FENCE;
598 
599 		eb->batches[*current_batch] = ev;
600 
601 		if (unlikely(ev->flags & EXEC_OBJECT_WRITE)) {
602 			drm_dbg(&i915->drm,
603 				"Attempting to use self-modifying batch buffer\n");
604 			return -EINVAL;
605 		}
606 
607 		if (range_overflows_t(u64,
608 				      eb->batch_start_offset,
609 				      eb->args->batch_len,
610 				      ev->vma->size)) {
611 			drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n");
612 			return -EINVAL;
613 		}
614 
615 		if (eb->args->batch_len == 0)
616 			eb->batch_len[*current_batch] = ev->vma->size -
617 				eb->batch_start_offset;
618 		else
619 			eb->batch_len[*current_batch] = eb->args->batch_len;
620 		if (unlikely(eb->batch_len[*current_batch] == 0)) { /* impossible! */
621 			drm_dbg(&i915->drm, "Invalid batch length\n");
622 			return -EINVAL;
623 		}
624 
625 		++*current_batch;
626 	}
627 
628 	return 0;
629 }
630 
631 static inline int use_cpu_reloc(const struct reloc_cache *cache,
632 				const struct drm_i915_gem_object *obj)
633 {
634 	if (!i915_gem_object_has_struct_page(obj))
635 		return false;
636 
637 	if (DBG_FORCE_RELOC == FORCE_CPU_RELOC)
638 		return true;
639 
640 	if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
641 		return false;
642 
643 	return (cache->has_llc ||
644 		obj->cache_dirty ||
645 		obj->cache_level != I915_CACHE_NONE);
646 }
647 
648 static int eb_reserve_vma(struct i915_execbuffer *eb,
649 			  struct eb_vma *ev,
650 			  u64 pin_flags)
651 {
652 	struct drm_i915_gem_exec_object2 *entry = ev->exec;
653 	struct i915_vma *vma = ev->vma;
654 	int err;
655 
656 	if (drm_mm_node_allocated(&vma->node) &&
657 	    eb_vma_misplaced(entry, vma, ev->flags)) {
658 		err = i915_vma_unbind(vma);
659 		if (err)
660 			return err;
661 	}
662 
663 	err = i915_vma_pin_ww(vma, &eb->ww,
664 			   entry->pad_to_size, entry->alignment,
665 			   eb_pin_flags(entry, ev->flags) | pin_flags);
666 	if (err)
667 		return err;
668 
669 	if (entry->offset != i915_vma_offset(vma)) {
670 		entry->offset = i915_vma_offset(vma) | UPDATE;
671 		eb->args->flags |= __EXEC_HAS_RELOC;
672 	}
673 
674 	if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
675 		err = i915_vma_pin_fence(vma);
676 		if (unlikely(err))
677 			return err;
678 
679 		if (vma->fence)
680 			ev->flags |= __EXEC_OBJECT_HAS_FENCE;
681 	}
682 
683 	ev->flags |= __EXEC_OBJECT_HAS_PIN;
684 	GEM_BUG_ON(eb_vma_misplaced(entry, vma, ev->flags));
685 
686 	return 0;
687 }
688 
689 static bool eb_unbind(struct i915_execbuffer *eb, bool force)
690 {
691 	const unsigned int count = eb->buffer_count;
692 	unsigned int i;
693 	struct list_head last;
694 	bool unpinned = false;
695 
696 	/* Resort *all* the objects into priority order */
697 	INIT_LIST_HEAD(&eb->unbound);
698 	INIT_LIST_HEAD(&last);
699 
700 	for (i = 0; i < count; i++) {
701 		struct eb_vma *ev = &eb->vma[i];
702 		unsigned int flags = ev->flags;
703 
704 		if (!force && flags & EXEC_OBJECT_PINNED &&
705 		    flags & __EXEC_OBJECT_HAS_PIN)
706 			continue;
707 
708 		unpinned = true;
709 		eb_unreserve_vma(ev);
710 
711 		if (flags & EXEC_OBJECT_PINNED)
712 			/* Pinned must have their slot */
713 			list_add(&ev->bind_link, &eb->unbound);
714 		else if (flags & __EXEC_OBJECT_NEEDS_MAP)
715 			/* Map require the lowest 256MiB (aperture) */
716 			list_add_tail(&ev->bind_link, &eb->unbound);
717 		else if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
718 			/* Prioritise 4GiB region for restricted bo */
719 			list_add(&ev->bind_link, &last);
720 		else
721 			list_add_tail(&ev->bind_link, &last);
722 	}
723 
724 	list_splice_tail(&last, &eb->unbound);
725 	return unpinned;
726 }
727 
728 static int eb_reserve(struct i915_execbuffer *eb)
729 {
730 	struct eb_vma *ev;
731 	unsigned int pass;
732 	int err = 0;
733 	bool unpinned;
734 
735 	/*
736 	 * We have one more buffers that we couldn't bind, which could be due to
737 	 * various reasons. To resolve this we have 4 passes, with every next
738 	 * level turning the screws tighter:
739 	 *
740 	 * 0. Unbind all objects that do not match the GTT constraints for the
741 	 * execbuffer (fenceable, mappable, alignment etc). Bind all new
742 	 * objects.  This avoids unnecessary unbinding of later objects in order
743 	 * to make room for the earlier objects *unless* we need to defragment.
744 	 *
745 	 * 1. Reorder the buffers, where objects with the most restrictive
746 	 * placement requirements go first (ignoring fixed location buffers for
747 	 * now).  For example, objects needing the mappable aperture (the first
748 	 * 256M of GTT), should go first vs objects that can be placed just
749 	 * about anywhere. Repeat the previous pass.
750 	 *
751 	 * 2. Consider buffers that are pinned at a fixed location. Also try to
752 	 * evict the entire VM this time, leaving only objects that we were
753 	 * unable to lock. Try again to bind the buffers. (still using the new
754 	 * buffer order).
755 	 *
756 	 * 3. We likely have object lock contention for one or more stubborn
757 	 * objects in the VM, for which we need to evict to make forward
758 	 * progress (perhaps we are fighting the shrinker?). When evicting the
759 	 * VM this time around, anything that we can't lock we now track using
760 	 * the busy_bo, using the full lock (after dropping the vm->mutex to
761 	 * prevent deadlocks), instead of trylock. We then continue to evict the
762 	 * VM, this time with the stubborn object locked, which we can now
763 	 * hopefully unbind (if still bound in the VM). Repeat until the VM is
764 	 * evicted. Finally we should be able bind everything.
765 	 */
766 	for (pass = 0; pass <= 3; pass++) {
767 		int pin_flags = PIN_USER | PIN_VALIDATE;
768 
769 		if (pass == 0)
770 			pin_flags |= PIN_NONBLOCK;
771 
772 		if (pass >= 1)
773 			unpinned = eb_unbind(eb, pass >= 2);
774 
775 		if (pass == 2) {
776 			err = mutex_lock_interruptible(&eb->context->vm->mutex);
777 			if (!err) {
778 				err = i915_gem_evict_vm(eb->context->vm, &eb->ww, NULL);
779 				mutex_unlock(&eb->context->vm->mutex);
780 			}
781 			if (err)
782 				return err;
783 		}
784 
785 		if (pass == 3) {
786 retry:
787 			err = mutex_lock_interruptible(&eb->context->vm->mutex);
788 			if (!err) {
789 				struct drm_i915_gem_object *busy_bo = NULL;
790 
791 				err = i915_gem_evict_vm(eb->context->vm, &eb->ww, &busy_bo);
792 				mutex_unlock(&eb->context->vm->mutex);
793 				if (err && busy_bo) {
794 					err = i915_gem_object_lock(busy_bo, &eb->ww);
795 					i915_gem_object_put(busy_bo);
796 					if (!err)
797 						goto retry;
798 				}
799 			}
800 			if (err)
801 				return err;
802 		}
803 
804 		list_for_each_entry(ev, &eb->unbound, bind_link) {
805 			err = eb_reserve_vma(eb, ev, pin_flags);
806 			if (err)
807 				break;
808 		}
809 
810 		if (err != -ENOSPC)
811 			break;
812 	}
813 
814 	return err;
815 }
816 
817 static int eb_select_context(struct i915_execbuffer *eb)
818 {
819 	struct i915_gem_context *ctx;
820 
821 	ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1);
822 	if (unlikely(IS_ERR(ctx)))
823 		return PTR_ERR(ctx);
824 
825 	eb->gem_context = ctx;
826 	if (i915_gem_context_has_full_ppgtt(ctx))
827 		eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
828 
829 	return 0;
830 }
831 
832 static int __eb_add_lut(struct i915_execbuffer *eb,
833 			u32 handle, struct i915_vma *vma)
834 {
835 	struct i915_gem_context *ctx = eb->gem_context;
836 	struct i915_lut_handle *lut;
837 	int err;
838 
839 	lut = i915_lut_handle_alloc();
840 	if (unlikely(!lut))
841 		return -ENOMEM;
842 
843 	i915_vma_get(vma);
844 	if (!atomic_fetch_inc(&vma->open_count))
845 		i915_vma_reopen(vma);
846 	lut->handle = handle;
847 	lut->ctx = ctx;
848 
849 	/* Check that the context hasn't been closed in the meantime */
850 	err = -EINTR;
851 	if (!mutex_lock_interruptible(&ctx->lut_mutex)) {
852 		if (likely(!i915_gem_context_is_closed(ctx)))
853 			err = radix_tree_insert(&ctx->handles_vma, handle, vma);
854 		else
855 			err = -ENOENT;
856 		if (err == 0) { /* And nor has this handle */
857 			struct drm_i915_gem_object *obj = vma->obj;
858 
859 			spin_lock(&obj->lut_lock);
860 			if (idr_find(&eb->file->object_idr, handle) == obj) {
861 				list_add(&lut->obj_link, &obj->lut_list);
862 			} else {
863 				radix_tree_delete(&ctx->handles_vma, handle);
864 				err = -ENOENT;
865 			}
866 			spin_unlock(&obj->lut_lock);
867 		}
868 		mutex_unlock(&ctx->lut_mutex);
869 	}
870 	if (unlikely(err))
871 		goto err;
872 
873 	return 0;
874 
875 err:
876 	i915_vma_close(vma);
877 	i915_vma_put(vma);
878 	i915_lut_handle_free(lut);
879 	return err;
880 }
881 
882 static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle)
883 {
884 	struct i915_address_space *vm = eb->context->vm;
885 
886 	do {
887 		struct drm_i915_gem_object *obj;
888 		struct i915_vma *vma;
889 		int err;
890 
891 		rcu_read_lock();
892 		vma = radix_tree_lookup(&eb->gem_context->handles_vma, handle);
893 		if (likely(vma && vma->vm == vm))
894 			vma = i915_vma_tryget(vma);
895 		rcu_read_unlock();
896 		if (likely(vma))
897 			return vma;
898 
899 		obj = i915_gem_object_lookup(eb->file, handle);
900 		if (unlikely(!obj))
901 			return ERR_PTR(-ENOENT);
902 
903 		/*
904 		 * If the user has opted-in for protected-object tracking, make
905 		 * sure the object encryption can be used.
906 		 * We only need to do this when the object is first used with
907 		 * this context, because the context itself will be banned when
908 		 * the protected objects become invalid.
909 		 */
910 		if (i915_gem_context_uses_protected_content(eb->gem_context) &&
911 		    i915_gem_object_is_protected(obj)) {
912 			err = intel_pxp_key_check(eb->i915->pxp, obj, true);
913 			if (err) {
914 				i915_gem_object_put(obj);
915 				return ERR_PTR(err);
916 			}
917 		}
918 
919 		vma = i915_vma_instance(obj, vm, NULL);
920 		if (IS_ERR(vma)) {
921 			i915_gem_object_put(obj);
922 			return vma;
923 		}
924 
925 		err = __eb_add_lut(eb, handle, vma);
926 		if (likely(!err))
927 			return vma;
928 
929 		i915_gem_object_put(obj);
930 		if (err != -EEXIST)
931 			return ERR_PTR(err);
932 	} while (1);
933 }
934 
935 static int eb_lookup_vmas(struct i915_execbuffer *eb)
936 {
937 	unsigned int i, current_batch = 0;
938 	int err = 0;
939 
940 	INIT_LIST_HEAD(&eb->relocs);
941 
942 	for (i = 0; i < eb->buffer_count; i++) {
943 		struct i915_vma *vma;
944 
945 		vma = eb_lookup_vma(eb, eb->exec[i].handle);
946 		if (IS_ERR(vma)) {
947 			err = PTR_ERR(vma);
948 			goto err;
949 		}
950 
951 		err = eb_validate_vma(eb, &eb->exec[i], vma);
952 		if (unlikely(err)) {
953 			i915_vma_put(vma);
954 			goto err;
955 		}
956 
957 		err = eb_add_vma(eb, &current_batch, i, vma);
958 		if (err)
959 			return err;
960 
961 		if (i915_gem_object_is_userptr(vma->obj)) {
962 			err = i915_gem_object_userptr_submit_init(vma->obj);
963 			if (err) {
964 				if (i + 1 < eb->buffer_count) {
965 					/*
966 					 * Execbuffer code expects last vma entry to be NULL,
967 					 * since we already initialized this entry,
968 					 * set the next value to NULL or we mess up
969 					 * cleanup handling.
970 					 */
971 					eb->vma[i + 1].vma = NULL;
972 				}
973 
974 				return err;
975 			}
976 
977 			eb->vma[i].flags |= __EXEC_OBJECT_USERPTR_INIT;
978 			eb->args->flags |= __EXEC_USERPTR_USED;
979 		}
980 	}
981 
982 	return 0;
983 
984 err:
985 	eb->vma[i].vma = NULL;
986 	return err;
987 }
988 
989 static int eb_lock_vmas(struct i915_execbuffer *eb)
990 {
991 	unsigned int i;
992 	int err;
993 
994 	for (i = 0; i < eb->buffer_count; i++) {
995 		struct eb_vma *ev = &eb->vma[i];
996 		struct i915_vma *vma = ev->vma;
997 
998 		err = i915_gem_object_lock(vma->obj, &eb->ww);
999 		if (err)
1000 			return err;
1001 	}
1002 
1003 	return 0;
1004 }
1005 
1006 static int eb_validate_vmas(struct i915_execbuffer *eb)
1007 {
1008 	unsigned int i;
1009 	int err;
1010 
1011 	INIT_LIST_HEAD(&eb->unbound);
1012 
1013 	err = eb_lock_vmas(eb);
1014 	if (err)
1015 		return err;
1016 
1017 	for (i = 0; i < eb->buffer_count; i++) {
1018 		struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
1019 		struct eb_vma *ev = &eb->vma[i];
1020 		struct i915_vma *vma = ev->vma;
1021 
1022 		err = eb_pin_vma(eb, entry, ev);
1023 		if (err == -EDEADLK)
1024 			return err;
1025 
1026 		if (!err) {
1027 			if (entry->offset != i915_vma_offset(vma)) {
1028 				entry->offset = i915_vma_offset(vma) | UPDATE;
1029 				eb->args->flags |= __EXEC_HAS_RELOC;
1030 			}
1031 		} else {
1032 			eb_unreserve_vma(ev);
1033 
1034 			list_add_tail(&ev->bind_link, &eb->unbound);
1035 			if (drm_mm_node_allocated(&vma->node)) {
1036 				err = i915_vma_unbind(vma);
1037 				if (err)
1038 					return err;
1039 			}
1040 		}
1041 
1042 		/* Reserve enough slots to accommodate composite fences */
1043 		err = dma_resv_reserve_fences(vma->obj->base.resv, eb->num_batches);
1044 		if (err)
1045 			return err;
1046 
1047 		GEM_BUG_ON(drm_mm_node_allocated(&vma->node) &&
1048 			   eb_vma_misplaced(&eb->exec[i], vma, ev->flags));
1049 	}
1050 
1051 	if (!list_empty(&eb->unbound))
1052 		return eb_reserve(eb);
1053 
1054 	return 0;
1055 }
1056 
1057 static struct eb_vma *
1058 eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle)
1059 {
1060 	if (eb->lut_size < 0) {
1061 		if (handle >= -eb->lut_size)
1062 			return NULL;
1063 		return &eb->vma[handle];
1064 	} else {
1065 		struct hlist_head *head;
1066 		struct eb_vma *ev;
1067 
1068 		head = &eb->buckets[hash_32(handle, eb->lut_size)];
1069 		hlist_for_each_entry(ev, head, node) {
1070 			if (ev->handle == handle)
1071 				return ev;
1072 		}
1073 		return NULL;
1074 	}
1075 }
1076 
1077 static void eb_release_vmas(struct i915_execbuffer *eb, bool final)
1078 {
1079 	const unsigned int count = eb->buffer_count;
1080 	unsigned int i;
1081 
1082 	for (i = 0; i < count; i++) {
1083 		struct eb_vma *ev = &eb->vma[i];
1084 		struct i915_vma *vma = ev->vma;
1085 
1086 		if (!vma)
1087 			break;
1088 
1089 		eb_unreserve_vma(ev);
1090 
1091 		if (final)
1092 			i915_vma_put(vma);
1093 	}
1094 
1095 	eb_capture_release(eb);
1096 	eb_unpin_engine(eb);
1097 }
1098 
1099 static void eb_destroy(const struct i915_execbuffer *eb)
1100 {
1101 	if (eb->lut_size > 0)
1102 		kfree(eb->buckets);
1103 }
1104 
1105 static inline u64
1106 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
1107 		  const struct i915_vma *target)
1108 {
1109 	return gen8_canonical_addr((int)reloc->delta + i915_vma_offset(target));
1110 }
1111 
1112 static void reloc_cache_init(struct reloc_cache *cache,
1113 			     struct drm_i915_private *i915)
1114 {
1115 	cache->page = -1;
1116 	cache->vaddr = 0;
1117 	/* Must be a variable in the struct to allow GCC to unroll. */
1118 	cache->graphics_ver = GRAPHICS_VER(i915);
1119 	cache->has_llc = HAS_LLC(i915);
1120 	cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
1121 	cache->has_fence = cache->graphics_ver < 4;
1122 	cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
1123 	cache->node.flags = 0;
1124 }
1125 
1126 static inline void *unmask_page(unsigned long p)
1127 {
1128 	return (void *)(uintptr_t)(p & PAGE_MASK);
1129 }
1130 
1131 static inline unsigned int unmask_flags(unsigned long p)
1132 {
1133 	return p & ~PAGE_MASK;
1134 }
1135 
1136 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
1137 
1138 static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
1139 {
1140 	struct drm_i915_private *i915 =
1141 		container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
1142 	return to_gt(i915)->ggtt;
1143 }
1144 
1145 static void reloc_cache_unmap(struct reloc_cache *cache)
1146 {
1147 	void *vaddr;
1148 
1149 	if (!cache->vaddr)
1150 		return;
1151 
1152 	vaddr = unmask_page(cache->vaddr);
1153 	if (cache->vaddr & KMAP)
1154 		kunmap_atomic(vaddr);
1155 	else
1156 		io_mapping_unmap_atomic((void __iomem *)vaddr);
1157 }
1158 
1159 static void reloc_cache_remap(struct reloc_cache *cache,
1160 			      struct drm_i915_gem_object *obj)
1161 {
1162 	void *vaddr;
1163 
1164 	if (!cache->vaddr)
1165 		return;
1166 
1167 	if (cache->vaddr & KMAP) {
1168 		struct page *page = i915_gem_object_get_page(obj, cache->page);
1169 
1170 		vaddr = kmap_atomic(page);
1171 		cache->vaddr = unmask_flags(cache->vaddr) |
1172 			(unsigned long)vaddr;
1173 	} else {
1174 		struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1175 		unsigned long offset;
1176 
1177 		offset = cache->node.start;
1178 		if (!drm_mm_node_allocated(&cache->node))
1179 			offset += cache->page << PAGE_SHIFT;
1180 
1181 		cache->vaddr = (unsigned long)
1182 			io_mapping_map_atomic_wc(&ggtt->iomap, offset);
1183 	}
1184 }
1185 
1186 static void reloc_cache_reset(struct reloc_cache *cache, struct i915_execbuffer *eb)
1187 {
1188 	void *vaddr;
1189 
1190 	if (!cache->vaddr)
1191 		return;
1192 
1193 	vaddr = unmask_page(cache->vaddr);
1194 	if (cache->vaddr & KMAP) {
1195 		struct drm_i915_gem_object *obj =
1196 			(struct drm_i915_gem_object *)cache->node.mm;
1197 		if (cache->vaddr & CLFLUSH_AFTER)
1198 			mb();
1199 
1200 		kunmap_atomic(vaddr);
1201 		i915_gem_object_finish_access(obj);
1202 	} else {
1203 		struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1204 
1205 		intel_gt_flush_ggtt_writes(ggtt->vm.gt);
1206 		io_mapping_unmap_atomic((void __iomem *)vaddr);
1207 
1208 		if (drm_mm_node_allocated(&cache->node)) {
1209 			ggtt->vm.clear_range(&ggtt->vm,
1210 					     cache->node.start,
1211 					     cache->node.size);
1212 			mutex_lock(&ggtt->vm.mutex);
1213 			drm_mm_remove_node(&cache->node);
1214 			mutex_unlock(&ggtt->vm.mutex);
1215 		} else {
1216 			i915_vma_unpin((struct i915_vma *)cache->node.mm);
1217 		}
1218 	}
1219 
1220 	cache->vaddr = 0;
1221 	cache->page = -1;
1222 }
1223 
1224 static void *reloc_kmap(struct drm_i915_gem_object *obj,
1225 			struct reloc_cache *cache,
1226 			unsigned long pageno)
1227 {
1228 	void *vaddr;
1229 	struct page *page;
1230 
1231 	if (cache->vaddr) {
1232 		kunmap_atomic(unmask_page(cache->vaddr));
1233 	} else {
1234 		unsigned int flushes;
1235 		int err;
1236 
1237 		err = i915_gem_object_prepare_write(obj, &flushes);
1238 		if (err)
1239 			return ERR_PTR(err);
1240 
1241 		BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
1242 		BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
1243 
1244 		cache->vaddr = flushes | KMAP;
1245 		cache->node.mm = (void *)obj;
1246 		if (flushes)
1247 			mb();
1248 	}
1249 
1250 	page = i915_gem_object_get_page(obj, pageno);
1251 	if (!obj->mm.dirty)
1252 		set_page_dirty(page);
1253 
1254 	vaddr = kmap_atomic(page);
1255 	cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
1256 	cache->page = pageno;
1257 
1258 	return vaddr;
1259 }
1260 
1261 static void *reloc_iomap(struct i915_vma *batch,
1262 			 struct i915_execbuffer *eb,
1263 			 unsigned long page)
1264 {
1265 	struct drm_i915_gem_object *obj = batch->obj;
1266 	struct reloc_cache *cache = &eb->reloc_cache;
1267 	struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1268 	unsigned long offset;
1269 	void *vaddr;
1270 
1271 	if (cache->vaddr) {
1272 		intel_gt_flush_ggtt_writes(ggtt->vm.gt);
1273 		io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
1274 	} else {
1275 		struct i915_vma *vma = ERR_PTR(-ENODEV);
1276 		int err;
1277 
1278 		if (i915_gem_object_is_tiled(obj))
1279 			return ERR_PTR(-EINVAL);
1280 
1281 		if (use_cpu_reloc(cache, obj))
1282 			return NULL;
1283 
1284 		err = i915_gem_object_set_to_gtt_domain(obj, true);
1285 		if (err)
1286 			return ERR_PTR(err);
1287 
1288 		/*
1289 		 * i915_gem_object_ggtt_pin_ww may attempt to remove the batch
1290 		 * VMA from the object list because we no longer pin.
1291 		 *
1292 		 * Only attempt to pin the batch buffer to ggtt if the current batch
1293 		 * is not inside ggtt, or the batch buffer is not misplaced.
1294 		 */
1295 		if (!i915_is_ggtt(batch->vm) ||
1296 		    !i915_vma_misplaced(batch, 0, 0, PIN_MAPPABLE)) {
1297 			vma = i915_gem_object_ggtt_pin_ww(obj, &eb->ww, NULL, 0, 0,
1298 							  PIN_MAPPABLE |
1299 							  PIN_NONBLOCK /* NOWARN */ |
1300 							  PIN_NOEVICT);
1301 		}
1302 
1303 		if (vma == ERR_PTR(-EDEADLK))
1304 			return vma;
1305 
1306 		if (IS_ERR(vma)) {
1307 			memset(&cache->node, 0, sizeof(cache->node));
1308 			mutex_lock(&ggtt->vm.mutex);
1309 			err = drm_mm_insert_node_in_range
1310 				(&ggtt->vm.mm, &cache->node,
1311 				 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
1312 				 0, ggtt->mappable_end,
1313 				 DRM_MM_INSERT_LOW);
1314 			mutex_unlock(&ggtt->vm.mutex);
1315 			if (err) /* no inactive aperture space, use cpu reloc */
1316 				return NULL;
1317 		} else {
1318 			cache->node.start = i915_ggtt_offset(vma);
1319 			cache->node.mm = (void *)vma;
1320 		}
1321 	}
1322 
1323 	offset = cache->node.start;
1324 	if (drm_mm_node_allocated(&cache->node)) {
1325 		ggtt->vm.insert_page(&ggtt->vm,
1326 				     i915_gem_object_get_dma_address(obj, page),
1327 				     offset, I915_CACHE_NONE, 0);
1328 	} else {
1329 		offset += page << PAGE_SHIFT;
1330 	}
1331 
1332 	vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap,
1333 							 offset);
1334 	cache->page = page;
1335 	cache->vaddr = (unsigned long)vaddr;
1336 
1337 	return vaddr;
1338 }
1339 
1340 static void *reloc_vaddr(struct i915_vma *vma,
1341 			 struct i915_execbuffer *eb,
1342 			 unsigned long page)
1343 {
1344 	struct reloc_cache *cache = &eb->reloc_cache;
1345 	void *vaddr;
1346 
1347 	if (cache->page == page) {
1348 		vaddr = unmask_page(cache->vaddr);
1349 	} else {
1350 		vaddr = NULL;
1351 		if ((cache->vaddr & KMAP) == 0)
1352 			vaddr = reloc_iomap(vma, eb, page);
1353 		if (!vaddr)
1354 			vaddr = reloc_kmap(vma->obj, cache, page);
1355 	}
1356 
1357 	return vaddr;
1358 }
1359 
1360 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
1361 {
1362 	if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
1363 		if (flushes & CLFLUSH_BEFORE)
1364 			drm_clflush_virt_range(addr, sizeof(*addr));
1365 
1366 		*addr = value;
1367 
1368 		/*
1369 		 * Writes to the same cacheline are serialised by the CPU
1370 		 * (including clflush). On the write path, we only require
1371 		 * that it hits memory in an orderly fashion and place
1372 		 * mb barriers at the start and end of the relocation phase
1373 		 * to ensure ordering of clflush wrt to the system.
1374 		 */
1375 		if (flushes & CLFLUSH_AFTER)
1376 			drm_clflush_virt_range(addr, sizeof(*addr));
1377 	} else
1378 		*addr = value;
1379 }
1380 
1381 static u64
1382 relocate_entry(struct i915_vma *vma,
1383 	       const struct drm_i915_gem_relocation_entry *reloc,
1384 	       struct i915_execbuffer *eb,
1385 	       const struct i915_vma *target)
1386 {
1387 	u64 target_addr = relocation_target(reloc, target);
1388 	u64 offset = reloc->offset;
1389 	bool wide = eb->reloc_cache.use_64bit_reloc;
1390 	void *vaddr;
1391 
1392 repeat:
1393 	vaddr = reloc_vaddr(vma, eb,
1394 			    offset >> PAGE_SHIFT);
1395 	if (IS_ERR(vaddr))
1396 		return PTR_ERR(vaddr);
1397 
1398 	GEM_BUG_ON(!IS_ALIGNED(offset, sizeof(u32)));
1399 	clflush_write32(vaddr + offset_in_page(offset),
1400 			lower_32_bits(target_addr),
1401 			eb->reloc_cache.vaddr);
1402 
1403 	if (wide) {
1404 		offset += sizeof(u32);
1405 		target_addr >>= 32;
1406 		wide = false;
1407 		goto repeat;
1408 	}
1409 
1410 	return target->node.start | UPDATE;
1411 }
1412 
1413 static u64
1414 eb_relocate_entry(struct i915_execbuffer *eb,
1415 		  struct eb_vma *ev,
1416 		  const struct drm_i915_gem_relocation_entry *reloc)
1417 {
1418 	struct drm_i915_private *i915 = eb->i915;
1419 	struct eb_vma *target;
1420 	int err;
1421 
1422 	/* we've already hold a reference to all valid objects */
1423 	target = eb_get_vma(eb, reloc->target_handle);
1424 	if (unlikely(!target))
1425 		return -ENOENT;
1426 
1427 	/* Validate that the target is in a valid r/w GPU domain */
1428 	if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
1429 		drm_dbg(&i915->drm, "reloc with multiple write domains: "
1430 			  "target %d offset %d "
1431 			  "read %08x write %08x",
1432 			  reloc->target_handle,
1433 			  (int) reloc->offset,
1434 			  reloc->read_domains,
1435 			  reloc->write_domain);
1436 		return -EINVAL;
1437 	}
1438 	if (unlikely((reloc->write_domain | reloc->read_domains)
1439 		     & ~I915_GEM_GPU_DOMAINS)) {
1440 		drm_dbg(&i915->drm, "reloc with read/write non-GPU domains: "
1441 			  "target %d offset %d "
1442 			  "read %08x write %08x",
1443 			  reloc->target_handle,
1444 			  (int) reloc->offset,
1445 			  reloc->read_domains,
1446 			  reloc->write_domain);
1447 		return -EINVAL;
1448 	}
1449 
1450 	if (reloc->write_domain) {
1451 		target->flags |= EXEC_OBJECT_WRITE;
1452 
1453 		/*
1454 		 * Sandybridge PPGTT errata: We need a global gtt mapping
1455 		 * for MI and pipe_control writes because the gpu doesn't
1456 		 * properly redirect them through the ppgtt for non_secure
1457 		 * batchbuffers.
1458 		 */
1459 		if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1460 		    GRAPHICS_VER(eb->i915) == 6 &&
1461 		    !i915_vma_is_bound(target->vma, I915_VMA_GLOBAL_BIND)) {
1462 			struct i915_vma *vma = target->vma;
1463 
1464 			reloc_cache_unmap(&eb->reloc_cache);
1465 			mutex_lock(&vma->vm->mutex);
1466 			err = i915_vma_bind(target->vma,
1467 					    target->vma->obj->cache_level,
1468 					    PIN_GLOBAL, NULL, NULL);
1469 			mutex_unlock(&vma->vm->mutex);
1470 			reloc_cache_remap(&eb->reloc_cache, ev->vma->obj);
1471 			if (err)
1472 				return err;
1473 		}
1474 	}
1475 
1476 	/*
1477 	 * If the relocation already has the right value in it, no
1478 	 * more work needs to be done.
1479 	 */
1480 	if (!DBG_FORCE_RELOC &&
1481 	    gen8_canonical_addr(i915_vma_offset(target->vma)) == reloc->presumed_offset)
1482 		return 0;
1483 
1484 	/* Check that the relocation address is valid... */
1485 	if (unlikely(reloc->offset >
1486 		     ev->vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) {
1487 		drm_dbg(&i915->drm, "Relocation beyond object bounds: "
1488 			  "target %d offset %d size %d.\n",
1489 			  reloc->target_handle,
1490 			  (int)reloc->offset,
1491 			  (int)ev->vma->size);
1492 		return -EINVAL;
1493 	}
1494 	if (unlikely(reloc->offset & 3)) {
1495 		drm_dbg(&i915->drm, "Relocation not 4-byte aligned: "
1496 			  "target %d offset %d.\n",
1497 			  reloc->target_handle,
1498 			  (int)reloc->offset);
1499 		return -EINVAL;
1500 	}
1501 
1502 	/*
1503 	 * If we write into the object, we need to force the synchronisation
1504 	 * barrier, either with an asynchronous clflush or if we executed the
1505 	 * patching using the GPU (though that should be serialised by the
1506 	 * timeline). To be completely sure, and since we are required to
1507 	 * do relocations we are already stalling, disable the user's opt
1508 	 * out of our synchronisation.
1509 	 */
1510 	ev->flags &= ~EXEC_OBJECT_ASYNC;
1511 
1512 	/* and update the user's relocation entry */
1513 	return relocate_entry(ev->vma, reloc, eb, target->vma);
1514 }
1515 
1516 static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev)
1517 {
1518 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1519 	struct drm_i915_gem_relocation_entry stack[N_RELOC(512)];
1520 	const struct drm_i915_gem_exec_object2 *entry = ev->exec;
1521 	struct drm_i915_gem_relocation_entry __user *urelocs =
1522 		u64_to_user_ptr(entry->relocs_ptr);
1523 	unsigned long remain = entry->relocation_count;
1524 
1525 	if (unlikely(remain > N_RELOC(ULONG_MAX)))
1526 		return -EINVAL;
1527 
1528 	/*
1529 	 * We must check that the entire relocation array is safe
1530 	 * to read. However, if the array is not writable the user loses
1531 	 * the updated relocation values.
1532 	 */
1533 	if (unlikely(!access_ok(urelocs, remain * sizeof(*urelocs))))
1534 		return -EFAULT;
1535 
1536 	do {
1537 		struct drm_i915_gem_relocation_entry *r = stack;
1538 		unsigned int count =
1539 			min_t(unsigned long, remain, ARRAY_SIZE(stack));
1540 		unsigned int copied;
1541 
1542 		/*
1543 		 * This is the fast path and we cannot handle a pagefault
1544 		 * whilst holding the struct mutex lest the user pass in the
1545 		 * relocations contained within a mmaped bo. For in such a case
1546 		 * we, the page fault handler would call i915_gem_fault() and
1547 		 * we would try to acquire the struct mutex again. Obviously
1548 		 * this is bad and so lockdep complains vehemently.
1549 		 */
1550 		pagefault_disable();
1551 		copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0]));
1552 		pagefault_enable();
1553 		if (unlikely(copied)) {
1554 			remain = -EFAULT;
1555 			goto out;
1556 		}
1557 
1558 		remain -= count;
1559 		do {
1560 			u64 offset = eb_relocate_entry(eb, ev, r);
1561 
1562 			if (likely(offset == 0)) {
1563 			} else if ((s64)offset < 0) {
1564 				remain = (int)offset;
1565 				goto out;
1566 			} else {
1567 				/*
1568 				 * Note that reporting an error now
1569 				 * leaves everything in an inconsistent
1570 				 * state as we have *already* changed
1571 				 * the relocation value inside the
1572 				 * object. As we have not changed the
1573 				 * reloc.presumed_offset or will not
1574 				 * change the execobject.offset, on the
1575 				 * call we may not rewrite the value
1576 				 * inside the object, leaving it
1577 				 * dangling and causing a GPU hang. Unless
1578 				 * userspace dynamically rebuilds the
1579 				 * relocations on each execbuf rather than
1580 				 * presume a static tree.
1581 				 *
1582 				 * We did previously check if the relocations
1583 				 * were writable (access_ok), an error now
1584 				 * would be a strange race with mprotect,
1585 				 * having already demonstrated that we
1586 				 * can read from this userspace address.
1587 				 */
1588 				offset = gen8_canonical_addr(offset & ~UPDATE);
1589 				__put_user(offset,
1590 					   &urelocs[r - stack].presumed_offset);
1591 			}
1592 		} while (r++, --count);
1593 		urelocs += ARRAY_SIZE(stack);
1594 	} while (remain);
1595 out:
1596 	reloc_cache_reset(&eb->reloc_cache, eb);
1597 	return remain;
1598 }
1599 
1600 static int
1601 eb_relocate_vma_slow(struct i915_execbuffer *eb, struct eb_vma *ev)
1602 {
1603 	const struct drm_i915_gem_exec_object2 *entry = ev->exec;
1604 	struct drm_i915_gem_relocation_entry *relocs =
1605 		u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1606 	unsigned int i;
1607 	int err;
1608 
1609 	for (i = 0; i < entry->relocation_count; i++) {
1610 		u64 offset = eb_relocate_entry(eb, ev, &relocs[i]);
1611 
1612 		if ((s64)offset < 0) {
1613 			err = (int)offset;
1614 			goto err;
1615 		}
1616 	}
1617 	err = 0;
1618 err:
1619 	reloc_cache_reset(&eb->reloc_cache, eb);
1620 	return err;
1621 }
1622 
1623 static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
1624 {
1625 	const char __user *addr, *end;
1626 	unsigned long size;
1627 	char __maybe_unused c;
1628 
1629 	size = entry->relocation_count;
1630 	if (size == 0)
1631 		return 0;
1632 
1633 	if (size > N_RELOC(ULONG_MAX))
1634 		return -EINVAL;
1635 
1636 	addr = u64_to_user_ptr(entry->relocs_ptr);
1637 	size *= sizeof(struct drm_i915_gem_relocation_entry);
1638 	if (!access_ok(addr, size))
1639 		return -EFAULT;
1640 
1641 	end = addr + size;
1642 	for (; addr < end; addr += PAGE_SIZE) {
1643 		int err = __get_user(c, addr);
1644 		if (err)
1645 			return err;
1646 	}
1647 	return __get_user(c, end - 1);
1648 }
1649 
1650 static int eb_copy_relocations(const struct i915_execbuffer *eb)
1651 {
1652 	struct drm_i915_gem_relocation_entry *relocs;
1653 	const unsigned int count = eb->buffer_count;
1654 	unsigned int i;
1655 	int err;
1656 
1657 	for (i = 0; i < count; i++) {
1658 		const unsigned int nreloc = eb->exec[i].relocation_count;
1659 		struct drm_i915_gem_relocation_entry __user *urelocs;
1660 		unsigned long size;
1661 		unsigned long copied;
1662 
1663 		if (nreloc == 0)
1664 			continue;
1665 
1666 		err = check_relocations(&eb->exec[i]);
1667 		if (err)
1668 			goto err;
1669 
1670 		urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
1671 		size = nreloc * sizeof(*relocs);
1672 
1673 		relocs = kvmalloc_array(size, 1, GFP_KERNEL);
1674 		if (!relocs) {
1675 			err = -ENOMEM;
1676 			goto err;
1677 		}
1678 
1679 		/* copy_from_user is limited to < 4GiB */
1680 		copied = 0;
1681 		do {
1682 			unsigned int len =
1683 				min_t(u64, BIT_ULL(31), size - copied);
1684 
1685 			if (__copy_from_user((char *)relocs + copied,
1686 					     (char __user *)urelocs + copied,
1687 					     len))
1688 				goto end;
1689 
1690 			copied += len;
1691 		} while (copied < size);
1692 
1693 		/*
1694 		 * As we do not update the known relocation offsets after
1695 		 * relocating (due to the complexities in lock handling),
1696 		 * we need to mark them as invalid now so that we force the
1697 		 * relocation processing next time. Just in case the target
1698 		 * object is evicted and then rebound into its old
1699 		 * presumed_offset before the next execbuffer - if that
1700 		 * happened we would make the mistake of assuming that the
1701 		 * relocations were valid.
1702 		 */
1703 		if (!user_access_begin(urelocs, size))
1704 			goto end;
1705 
1706 		for (copied = 0; copied < nreloc; copied++)
1707 			unsafe_put_user(-1,
1708 					&urelocs[copied].presumed_offset,
1709 					end_user);
1710 		user_access_end();
1711 
1712 		eb->exec[i].relocs_ptr = (uintptr_t)relocs;
1713 	}
1714 
1715 	return 0;
1716 
1717 end_user:
1718 	user_access_end();
1719 end:
1720 	kvfree(relocs);
1721 	err = -EFAULT;
1722 err:
1723 	while (i--) {
1724 		relocs = u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
1725 		if (eb->exec[i].relocation_count)
1726 			kvfree(relocs);
1727 	}
1728 	return err;
1729 }
1730 
1731 static int eb_prefault_relocations(const struct i915_execbuffer *eb)
1732 {
1733 	const unsigned int count = eb->buffer_count;
1734 	unsigned int i;
1735 
1736 	for (i = 0; i < count; i++) {
1737 		int err;
1738 
1739 		err = check_relocations(&eb->exec[i]);
1740 		if (err)
1741 			return err;
1742 	}
1743 
1744 	return 0;
1745 }
1746 
1747 static int eb_reinit_userptr(struct i915_execbuffer *eb)
1748 {
1749 	const unsigned int count = eb->buffer_count;
1750 	unsigned int i;
1751 	int ret;
1752 
1753 	if (likely(!(eb->args->flags & __EXEC_USERPTR_USED)))
1754 		return 0;
1755 
1756 	for (i = 0; i < count; i++) {
1757 		struct eb_vma *ev = &eb->vma[i];
1758 
1759 		if (!i915_gem_object_is_userptr(ev->vma->obj))
1760 			continue;
1761 
1762 		ret = i915_gem_object_userptr_submit_init(ev->vma->obj);
1763 		if (ret)
1764 			return ret;
1765 
1766 		ev->flags |= __EXEC_OBJECT_USERPTR_INIT;
1767 	}
1768 
1769 	return 0;
1770 }
1771 
1772 static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb)
1773 {
1774 	bool have_copy = false;
1775 	struct eb_vma *ev;
1776 	int err = 0;
1777 
1778 repeat:
1779 	if (signal_pending(current)) {
1780 		err = -ERESTARTSYS;
1781 		goto out;
1782 	}
1783 
1784 	/* We may process another execbuffer during the unlock... */
1785 	eb_release_vmas(eb, false);
1786 	i915_gem_ww_ctx_fini(&eb->ww);
1787 
1788 	/*
1789 	 * We take 3 passes through the slowpatch.
1790 	 *
1791 	 * 1 - we try to just prefault all the user relocation entries and
1792 	 * then attempt to reuse the atomic pagefault disabled fast path again.
1793 	 *
1794 	 * 2 - we copy the user entries to a local buffer here outside of the
1795 	 * local and allow ourselves to wait upon any rendering before
1796 	 * relocations
1797 	 *
1798 	 * 3 - we already have a local copy of the relocation entries, but
1799 	 * were interrupted (EAGAIN) whilst waiting for the objects, try again.
1800 	 */
1801 	if (!err) {
1802 		err = eb_prefault_relocations(eb);
1803 	} else if (!have_copy) {
1804 		err = eb_copy_relocations(eb);
1805 		have_copy = err == 0;
1806 	} else {
1807 		cond_resched();
1808 		err = 0;
1809 	}
1810 
1811 	if (!err)
1812 		err = eb_reinit_userptr(eb);
1813 
1814 	i915_gem_ww_ctx_init(&eb->ww, true);
1815 	if (err)
1816 		goto out;
1817 
1818 	/* reacquire the objects */
1819 repeat_validate:
1820 	err = eb_pin_engine(eb, false);
1821 	if (err)
1822 		goto err;
1823 
1824 	err = eb_validate_vmas(eb);
1825 	if (err)
1826 		goto err;
1827 
1828 	GEM_BUG_ON(!eb->batches[0]);
1829 
1830 	list_for_each_entry(ev, &eb->relocs, reloc_link) {
1831 		if (!have_copy) {
1832 			err = eb_relocate_vma(eb, ev);
1833 			if (err)
1834 				break;
1835 		} else {
1836 			err = eb_relocate_vma_slow(eb, ev);
1837 			if (err)
1838 				break;
1839 		}
1840 	}
1841 
1842 	if (err == -EDEADLK)
1843 		goto err;
1844 
1845 	if (err && !have_copy)
1846 		goto repeat;
1847 
1848 	if (err)
1849 		goto err;
1850 
1851 	/* as last step, parse the command buffer */
1852 	err = eb_parse(eb);
1853 	if (err)
1854 		goto err;
1855 
1856 	/*
1857 	 * Leave the user relocations as are, this is the painfully slow path,
1858 	 * and we want to avoid the complication of dropping the lock whilst
1859 	 * having buffers reserved in the aperture and so causing spurious
1860 	 * ENOSPC for random operations.
1861 	 */
1862 
1863 err:
1864 	if (err == -EDEADLK) {
1865 		eb_release_vmas(eb, false);
1866 		err = i915_gem_ww_ctx_backoff(&eb->ww);
1867 		if (!err)
1868 			goto repeat_validate;
1869 	}
1870 
1871 	if (err == -EAGAIN)
1872 		goto repeat;
1873 
1874 out:
1875 	if (have_copy) {
1876 		const unsigned int count = eb->buffer_count;
1877 		unsigned int i;
1878 
1879 		for (i = 0; i < count; i++) {
1880 			const struct drm_i915_gem_exec_object2 *entry =
1881 				&eb->exec[i];
1882 			struct drm_i915_gem_relocation_entry *relocs;
1883 
1884 			if (!entry->relocation_count)
1885 				continue;
1886 
1887 			relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1888 			kvfree(relocs);
1889 		}
1890 	}
1891 
1892 	return err;
1893 }
1894 
1895 static int eb_relocate_parse(struct i915_execbuffer *eb)
1896 {
1897 	int err;
1898 	bool throttle = true;
1899 
1900 retry:
1901 	err = eb_pin_engine(eb, throttle);
1902 	if (err) {
1903 		if (err != -EDEADLK)
1904 			return err;
1905 
1906 		goto err;
1907 	}
1908 
1909 	/* only throttle once, even if we didn't need to throttle */
1910 	throttle = false;
1911 
1912 	err = eb_validate_vmas(eb);
1913 	if (err == -EAGAIN)
1914 		goto slow;
1915 	else if (err)
1916 		goto err;
1917 
1918 	/* The objects are in their final locations, apply the relocations. */
1919 	if (eb->args->flags & __EXEC_HAS_RELOC) {
1920 		struct eb_vma *ev;
1921 
1922 		list_for_each_entry(ev, &eb->relocs, reloc_link) {
1923 			err = eb_relocate_vma(eb, ev);
1924 			if (err)
1925 				break;
1926 		}
1927 
1928 		if (err == -EDEADLK)
1929 			goto err;
1930 		else if (err)
1931 			goto slow;
1932 	}
1933 
1934 	if (!err)
1935 		err = eb_parse(eb);
1936 
1937 err:
1938 	if (err == -EDEADLK) {
1939 		eb_release_vmas(eb, false);
1940 		err = i915_gem_ww_ctx_backoff(&eb->ww);
1941 		if (!err)
1942 			goto retry;
1943 	}
1944 
1945 	return err;
1946 
1947 slow:
1948 	err = eb_relocate_parse_slow(eb);
1949 	if (err)
1950 		/*
1951 		 * If the user expects the execobject.offset and
1952 		 * reloc.presumed_offset to be an exact match,
1953 		 * as for using NO_RELOC, then we cannot update
1954 		 * the execobject.offset until we have completed
1955 		 * relocation.
1956 		 */
1957 		eb->args->flags &= ~__EXEC_HAS_RELOC;
1958 
1959 	return err;
1960 }
1961 
1962 /*
1963  * Using two helper loops for the order of which requests / batches are created
1964  * and added the to backend. Requests are created in order from the parent to
1965  * the last child. Requests are added in the reverse order, from the last child
1966  * to parent. This is done for locking reasons as the timeline lock is acquired
1967  * during request creation and released when the request is added to the
1968  * backend. To make lockdep happy (see intel_context_timeline_lock) this must be
1969  * the ordering.
1970  */
1971 #define for_each_batch_create_order(_eb, _i) \
1972 	for ((_i) = 0; (_i) < (_eb)->num_batches; ++(_i))
1973 #define for_each_batch_add_order(_eb, _i) \
1974 	BUILD_BUG_ON(!typecheck(int, _i)); \
1975 	for ((_i) = (_eb)->num_batches - 1; (_i) >= 0; --(_i))
1976 
1977 static struct i915_request *
1978 eb_find_first_request_added(struct i915_execbuffer *eb)
1979 {
1980 	int i;
1981 
1982 	for_each_batch_add_order(eb, i)
1983 		if (eb->requests[i])
1984 			return eb->requests[i];
1985 
1986 	GEM_BUG_ON("Request not found");
1987 
1988 	return NULL;
1989 }
1990 
1991 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1992 
1993 /* Stage with GFP_KERNEL allocations before we enter the signaling critical path */
1994 static int eb_capture_stage(struct i915_execbuffer *eb)
1995 {
1996 	const unsigned int count = eb->buffer_count;
1997 	unsigned int i = count, j;
1998 
1999 	while (i--) {
2000 		struct eb_vma *ev = &eb->vma[i];
2001 		struct i915_vma *vma = ev->vma;
2002 		unsigned int flags = ev->flags;
2003 
2004 		if (!(flags & EXEC_OBJECT_CAPTURE))
2005 			continue;
2006 
2007 		if (i915_gem_context_is_recoverable(eb->gem_context) &&
2008 		    (IS_DGFX(eb->i915) || GRAPHICS_VER_FULL(eb->i915) > IP_VER(12, 0)))
2009 			return -EINVAL;
2010 
2011 		for_each_batch_create_order(eb, j) {
2012 			struct i915_capture_list *capture;
2013 
2014 			capture = kmalloc(sizeof(*capture), GFP_KERNEL);
2015 			if (!capture)
2016 				continue;
2017 
2018 			capture->next = eb->capture_lists[j];
2019 			capture->vma_res = i915_vma_resource_get(vma->resource);
2020 			eb->capture_lists[j] = capture;
2021 		}
2022 	}
2023 
2024 	return 0;
2025 }
2026 
2027 /* Commit once we're in the critical path */
2028 static void eb_capture_commit(struct i915_execbuffer *eb)
2029 {
2030 	unsigned int j;
2031 
2032 	for_each_batch_create_order(eb, j) {
2033 		struct i915_request *rq = eb->requests[j];
2034 
2035 		if (!rq)
2036 			break;
2037 
2038 		rq->capture_list = eb->capture_lists[j];
2039 		eb->capture_lists[j] = NULL;
2040 	}
2041 }
2042 
2043 /*
2044  * Release anything that didn't get committed due to errors.
2045  * The capture_list will otherwise be freed at request retire.
2046  */
2047 static void eb_capture_release(struct i915_execbuffer *eb)
2048 {
2049 	unsigned int j;
2050 
2051 	for_each_batch_create_order(eb, j) {
2052 		if (eb->capture_lists[j]) {
2053 			i915_request_free_capture_list(eb->capture_lists[j]);
2054 			eb->capture_lists[j] = NULL;
2055 		}
2056 	}
2057 }
2058 
2059 static void eb_capture_list_clear(struct i915_execbuffer *eb)
2060 {
2061 	memset(eb->capture_lists, 0, sizeof(eb->capture_lists));
2062 }
2063 
2064 #else
2065 
2066 static int eb_capture_stage(struct i915_execbuffer *eb)
2067 {
2068 	return 0;
2069 }
2070 
2071 static void eb_capture_commit(struct i915_execbuffer *eb)
2072 {
2073 }
2074 
2075 static void eb_capture_release(struct i915_execbuffer *eb)
2076 {
2077 }
2078 
2079 static void eb_capture_list_clear(struct i915_execbuffer *eb)
2080 {
2081 }
2082 
2083 #endif
2084 
2085 static int eb_move_to_gpu(struct i915_execbuffer *eb)
2086 {
2087 	const unsigned int count = eb->buffer_count;
2088 	unsigned int i = count;
2089 	int err = 0, j;
2090 
2091 	while (i--) {
2092 		struct eb_vma *ev = &eb->vma[i];
2093 		struct i915_vma *vma = ev->vma;
2094 		unsigned int flags = ev->flags;
2095 		struct drm_i915_gem_object *obj = vma->obj;
2096 
2097 		assert_vma_held(vma);
2098 
2099 		/*
2100 		 * If the GPU is not _reading_ through the CPU cache, we need
2101 		 * to make sure that any writes (both previous GPU writes from
2102 		 * before a change in snooping levels and normal CPU writes)
2103 		 * caught in that cache are flushed to main memory.
2104 		 *
2105 		 * We want to say
2106 		 *   obj->cache_dirty &&
2107 		 *   !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
2108 		 * but gcc's optimiser doesn't handle that as well and emits
2109 		 * two jumps instead of one. Maybe one day...
2110 		 *
2111 		 * FIXME: There is also sync flushing in set_pages(), which
2112 		 * serves a different purpose(some of the time at least).
2113 		 *
2114 		 * We should consider:
2115 		 *
2116 		 *   1. Rip out the async flush code.
2117 		 *
2118 		 *   2. Or make the sync flushing use the async clflush path
2119 		 *   using mandatory fences underneath. Currently the below
2120 		 *   async flush happens after we bind the object.
2121 		 */
2122 		if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) {
2123 			if (i915_gem_clflush_object(obj, 0))
2124 				flags &= ~EXEC_OBJECT_ASYNC;
2125 		}
2126 
2127 		/* We only need to await on the first request */
2128 		if (err == 0 && !(flags & EXEC_OBJECT_ASYNC)) {
2129 			err = i915_request_await_object
2130 				(eb_find_first_request_added(eb), obj,
2131 				 flags & EXEC_OBJECT_WRITE);
2132 		}
2133 
2134 		for_each_batch_add_order(eb, j) {
2135 			if (err)
2136 				break;
2137 			if (!eb->requests[j])
2138 				continue;
2139 
2140 			err = _i915_vma_move_to_active(vma, eb->requests[j],
2141 						       j ? NULL :
2142 						       eb->composite_fence ?
2143 						       eb->composite_fence :
2144 						       &eb->requests[j]->fence,
2145 						       flags | __EXEC_OBJECT_NO_RESERVE |
2146 						       __EXEC_OBJECT_NO_REQUEST_AWAIT);
2147 		}
2148 	}
2149 
2150 #ifdef CONFIG_MMU_NOTIFIER
2151 	if (!err && (eb->args->flags & __EXEC_USERPTR_USED)) {
2152 		read_lock(&eb->i915->mm.notifier_lock);
2153 
2154 		/*
2155 		 * count is always at least 1, otherwise __EXEC_USERPTR_USED
2156 		 * could not have been set
2157 		 */
2158 		for (i = 0; i < count; i++) {
2159 			struct eb_vma *ev = &eb->vma[i];
2160 			struct drm_i915_gem_object *obj = ev->vma->obj;
2161 
2162 			if (!i915_gem_object_is_userptr(obj))
2163 				continue;
2164 
2165 			err = i915_gem_object_userptr_submit_done(obj);
2166 			if (err)
2167 				break;
2168 		}
2169 
2170 		read_unlock(&eb->i915->mm.notifier_lock);
2171 	}
2172 #endif
2173 
2174 	if (unlikely(err))
2175 		goto err_skip;
2176 
2177 	/* Unconditionally flush any chipset caches (for streaming writes). */
2178 	intel_gt_chipset_flush(eb->gt);
2179 	eb_capture_commit(eb);
2180 
2181 	return 0;
2182 
2183 err_skip:
2184 	for_each_batch_create_order(eb, j) {
2185 		if (!eb->requests[j])
2186 			break;
2187 
2188 		i915_request_set_error_once(eb->requests[j], err);
2189 	}
2190 	return err;
2191 }
2192 
2193 static int i915_gem_check_execbuffer(struct drm_i915_private *i915,
2194 				     struct drm_i915_gem_execbuffer2 *exec)
2195 {
2196 	if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS)
2197 		return -EINVAL;
2198 
2199 	/* Kernel clipping was a DRI1 misfeature */
2200 	if (!(exec->flags & (I915_EXEC_FENCE_ARRAY |
2201 			     I915_EXEC_USE_EXTENSIONS))) {
2202 		if (exec->num_cliprects || exec->cliprects_ptr)
2203 			return -EINVAL;
2204 	}
2205 
2206 	if (exec->DR4 == 0xffffffff) {
2207 		drm_dbg(&i915->drm, "UXA submitting garbage DR4, fixing up\n");
2208 		exec->DR4 = 0;
2209 	}
2210 	if (exec->DR1 || exec->DR4)
2211 		return -EINVAL;
2212 
2213 	if ((exec->batch_start_offset | exec->batch_len) & 0x7)
2214 		return -EINVAL;
2215 
2216 	return 0;
2217 }
2218 
2219 static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
2220 {
2221 	u32 *cs;
2222 	int i;
2223 
2224 	if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {
2225 		drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");
2226 		return -EINVAL;
2227 	}
2228 
2229 	cs = intel_ring_begin(rq, 4 * 2 + 2);
2230 	if (IS_ERR(cs))
2231 		return PTR_ERR(cs);
2232 
2233 	*cs++ = MI_LOAD_REGISTER_IMM(4);
2234 	for (i = 0; i < 4; i++) {
2235 		*cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));
2236 		*cs++ = 0;
2237 	}
2238 	*cs++ = MI_NOOP;
2239 	intel_ring_advance(rq, cs);
2240 
2241 	return 0;
2242 }
2243 
2244 static struct i915_vma *
2245 shadow_batch_pin(struct i915_execbuffer *eb,
2246 		 struct drm_i915_gem_object *obj,
2247 		 struct i915_address_space *vm,
2248 		 unsigned int flags)
2249 {
2250 	struct i915_vma *vma;
2251 	int err;
2252 
2253 	vma = i915_vma_instance(obj, vm, NULL);
2254 	if (IS_ERR(vma))
2255 		return vma;
2256 
2257 	err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, flags | PIN_VALIDATE);
2258 	if (err)
2259 		return ERR_PTR(err);
2260 
2261 	return vma;
2262 }
2263 
2264 static struct i915_vma *eb_dispatch_secure(struct i915_execbuffer *eb, struct i915_vma *vma)
2265 {
2266 	/*
2267 	 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2268 	 * batch" bit. Hence we need to pin secure batches into the global gtt.
2269 	 * hsw should have this fixed, but bdw mucks it up again. */
2270 	if (eb->batch_flags & I915_DISPATCH_SECURE)
2271 		return i915_gem_object_ggtt_pin_ww(vma->obj, &eb->ww, NULL, 0, 0, PIN_VALIDATE);
2272 
2273 	return NULL;
2274 }
2275 
2276 static int eb_parse(struct i915_execbuffer *eb)
2277 {
2278 	struct drm_i915_private *i915 = eb->i915;
2279 	struct intel_gt_buffer_pool_node *pool = eb->batch_pool;
2280 	struct i915_vma *shadow, *trampoline, *batch;
2281 	unsigned long len;
2282 	int err;
2283 
2284 	if (!eb_use_cmdparser(eb)) {
2285 		batch = eb_dispatch_secure(eb, eb->batches[0]->vma);
2286 		if (IS_ERR(batch))
2287 			return PTR_ERR(batch);
2288 
2289 		goto secure_batch;
2290 	}
2291 
2292 	if (intel_context_is_parallel(eb->context))
2293 		return -EINVAL;
2294 
2295 	len = eb->batch_len[0];
2296 	if (!CMDPARSER_USES_GGTT(eb->i915)) {
2297 		/*
2298 		 * ppGTT backed shadow buffers must be mapped RO, to prevent
2299 		 * post-scan tampering
2300 		 */
2301 		if (!eb->context->vm->has_read_only) {
2302 			drm_dbg(&i915->drm,
2303 				"Cannot prevent post-scan tampering without RO capable vm\n");
2304 			return -EINVAL;
2305 		}
2306 	} else {
2307 		len += I915_CMD_PARSER_TRAMPOLINE_SIZE;
2308 	}
2309 	if (unlikely(len < eb->batch_len[0])) /* last paranoid check of overflow */
2310 		return -EINVAL;
2311 
2312 	if (!pool) {
2313 		pool = intel_gt_get_buffer_pool(eb->gt, len,
2314 						I915_MAP_WB);
2315 		if (IS_ERR(pool))
2316 			return PTR_ERR(pool);
2317 		eb->batch_pool = pool;
2318 	}
2319 
2320 	err = i915_gem_object_lock(pool->obj, &eb->ww);
2321 	if (err)
2322 		return err;
2323 
2324 	shadow = shadow_batch_pin(eb, pool->obj, eb->context->vm, PIN_USER);
2325 	if (IS_ERR(shadow))
2326 		return PTR_ERR(shadow);
2327 
2328 	intel_gt_buffer_pool_mark_used(pool);
2329 	i915_gem_object_set_readonly(shadow->obj);
2330 	shadow->private = pool;
2331 
2332 	trampoline = NULL;
2333 	if (CMDPARSER_USES_GGTT(eb->i915)) {
2334 		trampoline = shadow;
2335 
2336 		shadow = shadow_batch_pin(eb, pool->obj,
2337 					  &eb->gt->ggtt->vm,
2338 					  PIN_GLOBAL);
2339 		if (IS_ERR(shadow))
2340 			return PTR_ERR(shadow);
2341 
2342 		shadow->private = pool;
2343 
2344 		eb->batch_flags |= I915_DISPATCH_SECURE;
2345 	}
2346 
2347 	batch = eb_dispatch_secure(eb, shadow);
2348 	if (IS_ERR(batch))
2349 		return PTR_ERR(batch);
2350 
2351 	err = dma_resv_reserve_fences(shadow->obj->base.resv, 1);
2352 	if (err)
2353 		return err;
2354 
2355 	err = intel_engine_cmd_parser(eb->context->engine,
2356 				      eb->batches[0]->vma,
2357 				      eb->batch_start_offset,
2358 				      eb->batch_len[0],
2359 				      shadow, trampoline);
2360 	if (err)
2361 		return err;
2362 
2363 	eb->batches[0] = &eb->vma[eb->buffer_count++];
2364 	eb->batches[0]->vma = i915_vma_get(shadow);
2365 	eb->batches[0]->flags = __EXEC_OBJECT_HAS_PIN;
2366 
2367 	eb->trampoline = trampoline;
2368 	eb->batch_start_offset = 0;
2369 
2370 secure_batch:
2371 	if (batch) {
2372 		if (intel_context_is_parallel(eb->context))
2373 			return -EINVAL;
2374 
2375 		eb->batches[0] = &eb->vma[eb->buffer_count++];
2376 		eb->batches[0]->flags = __EXEC_OBJECT_HAS_PIN;
2377 		eb->batches[0]->vma = i915_vma_get(batch);
2378 	}
2379 	return 0;
2380 }
2381 
2382 static int eb_request_submit(struct i915_execbuffer *eb,
2383 			     struct i915_request *rq,
2384 			     struct i915_vma *batch,
2385 			     u64 batch_len)
2386 {
2387 	int err;
2388 
2389 	if (intel_context_nopreempt(rq->context))
2390 		__set_bit(I915_FENCE_FLAG_NOPREEMPT, &rq->fence.flags);
2391 
2392 	if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
2393 		err = i915_reset_gen7_sol_offsets(rq);
2394 		if (err)
2395 			return err;
2396 	}
2397 
2398 	/*
2399 	 * After we completed waiting for other engines (using HW semaphores)
2400 	 * then we can signal that this request/batch is ready to run. This
2401 	 * allows us to determine if the batch is still waiting on the GPU
2402 	 * or actually running by checking the breadcrumb.
2403 	 */
2404 	if (rq->context->engine->emit_init_breadcrumb) {
2405 		err = rq->context->engine->emit_init_breadcrumb(rq);
2406 		if (err)
2407 			return err;
2408 	}
2409 
2410 	err = rq->context->engine->emit_bb_start(rq,
2411 						 i915_vma_offset(batch) +
2412 						 eb->batch_start_offset,
2413 						 batch_len,
2414 						 eb->batch_flags);
2415 	if (err)
2416 		return err;
2417 
2418 	if (eb->trampoline) {
2419 		GEM_BUG_ON(intel_context_is_parallel(rq->context));
2420 		GEM_BUG_ON(eb->batch_start_offset);
2421 		err = rq->context->engine->emit_bb_start(rq,
2422 							 i915_vma_offset(eb->trampoline) +
2423 							 batch_len, 0, 0);
2424 		if (err)
2425 			return err;
2426 	}
2427 
2428 	return 0;
2429 }
2430 
2431 static int eb_submit(struct i915_execbuffer *eb)
2432 {
2433 	unsigned int i;
2434 	int err;
2435 
2436 	err = eb_move_to_gpu(eb);
2437 
2438 	for_each_batch_create_order(eb, i) {
2439 		if (!eb->requests[i])
2440 			break;
2441 
2442 		trace_i915_request_queue(eb->requests[i], eb->batch_flags);
2443 		if (!err)
2444 			err = eb_request_submit(eb, eb->requests[i],
2445 						eb->batches[i]->vma,
2446 						eb->batch_len[i]);
2447 	}
2448 
2449 	return err;
2450 }
2451 
2452 static int num_vcs_engines(struct drm_i915_private *i915)
2453 {
2454 	return hweight_long(VDBOX_MASK(to_gt(i915)));
2455 }
2456 
2457 /*
2458  * Find one BSD ring to dispatch the corresponding BSD command.
2459  * The engine index is returned.
2460  */
2461 static unsigned int
2462 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
2463 			 struct drm_file *file)
2464 {
2465 	struct drm_i915_file_private *file_priv = file->driver_priv;
2466 
2467 	/* Check whether the file_priv has already selected one ring. */
2468 	if ((int)file_priv->bsd_engine < 0)
2469 		file_priv->bsd_engine =
2470 			get_random_u32_below(num_vcs_engines(dev_priv));
2471 
2472 	return file_priv->bsd_engine;
2473 }
2474 
2475 static const enum intel_engine_id user_ring_map[] = {
2476 	[I915_EXEC_DEFAULT]	= RCS0,
2477 	[I915_EXEC_RENDER]	= RCS0,
2478 	[I915_EXEC_BLT]		= BCS0,
2479 	[I915_EXEC_BSD]		= VCS0,
2480 	[I915_EXEC_VEBOX]	= VECS0
2481 };
2482 
2483 static struct i915_request *eb_throttle(struct i915_execbuffer *eb, struct intel_context *ce)
2484 {
2485 	struct intel_ring *ring = ce->ring;
2486 	struct intel_timeline *tl = ce->timeline;
2487 	struct i915_request *rq;
2488 
2489 	/*
2490 	 * Completely unscientific finger-in-the-air estimates for suitable
2491 	 * maximum user request size (to avoid blocking) and then backoff.
2492 	 */
2493 	if (intel_ring_update_space(ring) >= PAGE_SIZE)
2494 		return NULL;
2495 
2496 	/*
2497 	 * Find a request that after waiting upon, there will be at least half
2498 	 * the ring available. The hysteresis allows us to compete for the
2499 	 * shared ring and should mean that we sleep less often prior to
2500 	 * claiming our resources, but not so long that the ring completely
2501 	 * drains before we can submit our next request.
2502 	 */
2503 	list_for_each_entry(rq, &tl->requests, link) {
2504 		if (rq->ring != ring)
2505 			continue;
2506 
2507 		if (__intel_ring_space(rq->postfix,
2508 				       ring->emit, ring->size) > ring->size / 2)
2509 			break;
2510 	}
2511 	if (&rq->link == &tl->requests)
2512 		return NULL; /* weird, we will check again later for real */
2513 
2514 	return i915_request_get(rq);
2515 }
2516 
2517 static int eb_pin_timeline(struct i915_execbuffer *eb, struct intel_context *ce,
2518 			   bool throttle)
2519 {
2520 	struct intel_timeline *tl;
2521 	struct i915_request *rq = NULL;
2522 
2523 	/*
2524 	 * Take a local wakeref for preparing to dispatch the execbuf as
2525 	 * we expect to access the hardware fairly frequently in the
2526 	 * process, and require the engine to be kept awake between accesses.
2527 	 * Upon dispatch, we acquire another prolonged wakeref that we hold
2528 	 * until the timeline is idle, which in turn releases the wakeref
2529 	 * taken on the engine, and the parent device.
2530 	 */
2531 	tl = intel_context_timeline_lock(ce);
2532 	if (IS_ERR(tl))
2533 		return PTR_ERR(tl);
2534 
2535 	intel_context_enter(ce);
2536 	if (throttle)
2537 		rq = eb_throttle(eb, ce);
2538 	intel_context_timeline_unlock(tl);
2539 
2540 	if (rq) {
2541 		bool nonblock = eb->file->filp->f_flags & O_NONBLOCK;
2542 		long timeout = nonblock ? 0 : MAX_SCHEDULE_TIMEOUT;
2543 
2544 		if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
2545 				      timeout) < 0) {
2546 			i915_request_put(rq);
2547 
2548 			/*
2549 			 * Error path, cannot use intel_context_timeline_lock as
2550 			 * that is user interruptable and this clean up step
2551 			 * must be done.
2552 			 */
2553 			mutex_lock(&ce->timeline->mutex);
2554 			intel_context_exit(ce);
2555 			mutex_unlock(&ce->timeline->mutex);
2556 
2557 			if (nonblock)
2558 				return -EWOULDBLOCK;
2559 			else
2560 				return -EINTR;
2561 		}
2562 		i915_request_put(rq);
2563 	}
2564 
2565 	return 0;
2566 }
2567 
2568 static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle)
2569 {
2570 	struct intel_context *ce = eb->context, *child;
2571 	int err;
2572 	int i = 0, j = 0;
2573 
2574 	GEM_BUG_ON(eb->args->flags & __EXEC_ENGINE_PINNED);
2575 
2576 	if (unlikely(intel_context_is_banned(ce)))
2577 		return -EIO;
2578 
2579 	/*
2580 	 * Pinning the contexts may generate requests in order to acquire
2581 	 * GGTT space, so do this first before we reserve a seqno for
2582 	 * ourselves.
2583 	 */
2584 	err = intel_context_pin_ww(ce, &eb->ww);
2585 	if (err)
2586 		return err;
2587 	for_each_child(ce, child) {
2588 		err = intel_context_pin_ww(child, &eb->ww);
2589 		GEM_BUG_ON(err);	/* perma-pinned should incr a counter */
2590 	}
2591 
2592 	for_each_child(ce, child) {
2593 		err = eb_pin_timeline(eb, child, throttle);
2594 		if (err)
2595 			goto unwind;
2596 		++i;
2597 	}
2598 	err = eb_pin_timeline(eb, ce, throttle);
2599 	if (err)
2600 		goto unwind;
2601 
2602 	eb->args->flags |= __EXEC_ENGINE_PINNED;
2603 	return 0;
2604 
2605 unwind:
2606 	for_each_child(ce, child) {
2607 		if (j++ < i) {
2608 			mutex_lock(&child->timeline->mutex);
2609 			intel_context_exit(child);
2610 			mutex_unlock(&child->timeline->mutex);
2611 		}
2612 	}
2613 	for_each_child(ce, child)
2614 		intel_context_unpin(child);
2615 	intel_context_unpin(ce);
2616 	return err;
2617 }
2618 
2619 static void eb_unpin_engine(struct i915_execbuffer *eb)
2620 {
2621 	struct intel_context *ce = eb->context, *child;
2622 
2623 	if (!(eb->args->flags & __EXEC_ENGINE_PINNED))
2624 		return;
2625 
2626 	eb->args->flags &= ~__EXEC_ENGINE_PINNED;
2627 
2628 	for_each_child(ce, child) {
2629 		mutex_lock(&child->timeline->mutex);
2630 		intel_context_exit(child);
2631 		mutex_unlock(&child->timeline->mutex);
2632 
2633 		intel_context_unpin(child);
2634 	}
2635 
2636 	mutex_lock(&ce->timeline->mutex);
2637 	intel_context_exit(ce);
2638 	mutex_unlock(&ce->timeline->mutex);
2639 
2640 	intel_context_unpin(ce);
2641 }
2642 
2643 static unsigned int
2644 eb_select_legacy_ring(struct i915_execbuffer *eb)
2645 {
2646 	struct drm_i915_private *i915 = eb->i915;
2647 	struct drm_i915_gem_execbuffer2 *args = eb->args;
2648 	unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
2649 
2650 	if (user_ring_id != I915_EXEC_BSD &&
2651 	    (args->flags & I915_EXEC_BSD_MASK)) {
2652 		drm_dbg(&i915->drm,
2653 			"execbuf with non bsd ring but with invalid "
2654 			"bsd dispatch flags: %d\n", (int)(args->flags));
2655 		return -1;
2656 	}
2657 
2658 	if (user_ring_id == I915_EXEC_BSD && num_vcs_engines(i915) > 1) {
2659 		unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
2660 
2661 		if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
2662 			bsd_idx = gen8_dispatch_bsd_engine(i915, eb->file);
2663 		} else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
2664 			   bsd_idx <= I915_EXEC_BSD_RING2) {
2665 			bsd_idx >>= I915_EXEC_BSD_SHIFT;
2666 			bsd_idx--;
2667 		} else {
2668 			drm_dbg(&i915->drm,
2669 				"execbuf with unknown bsd ring: %u\n",
2670 				bsd_idx);
2671 			return -1;
2672 		}
2673 
2674 		return _VCS(bsd_idx);
2675 	}
2676 
2677 	if (user_ring_id >= ARRAY_SIZE(user_ring_map)) {
2678 		drm_dbg(&i915->drm, "execbuf with unknown ring: %u\n",
2679 			user_ring_id);
2680 		return -1;
2681 	}
2682 
2683 	return user_ring_map[user_ring_id];
2684 }
2685 
2686 static int
2687 eb_select_engine(struct i915_execbuffer *eb)
2688 {
2689 	struct intel_context *ce, *child;
2690 	unsigned int idx;
2691 	int err;
2692 
2693 	if (i915_gem_context_user_engines(eb->gem_context))
2694 		idx = eb->args->flags & I915_EXEC_RING_MASK;
2695 	else
2696 		idx = eb_select_legacy_ring(eb);
2697 
2698 	ce = i915_gem_context_get_engine(eb->gem_context, idx);
2699 	if (IS_ERR(ce))
2700 		return PTR_ERR(ce);
2701 
2702 	if (intel_context_is_parallel(ce)) {
2703 		if (eb->buffer_count < ce->parallel.number_children + 1) {
2704 			intel_context_put(ce);
2705 			return -EINVAL;
2706 		}
2707 		if (eb->batch_start_offset || eb->args->batch_len) {
2708 			intel_context_put(ce);
2709 			return -EINVAL;
2710 		}
2711 	}
2712 	eb->num_batches = ce->parallel.number_children + 1;
2713 
2714 	for_each_child(ce, child)
2715 		intel_context_get(child);
2716 	intel_gt_pm_get(ce->engine->gt);
2717 
2718 	if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
2719 		err = intel_context_alloc_state(ce);
2720 		if (err)
2721 			goto err;
2722 	}
2723 	for_each_child(ce, child) {
2724 		if (!test_bit(CONTEXT_ALLOC_BIT, &child->flags)) {
2725 			err = intel_context_alloc_state(child);
2726 			if (err)
2727 				goto err;
2728 		}
2729 	}
2730 
2731 	/*
2732 	 * ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2733 	 * EIO if the GPU is already wedged.
2734 	 */
2735 	err = intel_gt_terminally_wedged(ce->engine->gt);
2736 	if (err)
2737 		goto err;
2738 
2739 	if (!i915_vm_tryget(ce->vm)) {
2740 		err = -ENOENT;
2741 		goto err;
2742 	}
2743 
2744 	eb->context = ce;
2745 	eb->gt = ce->engine->gt;
2746 
2747 	/*
2748 	 * Make sure engine pool stays alive even if we call intel_context_put
2749 	 * during ww handling. The pool is destroyed when last pm reference
2750 	 * is dropped, which breaks our -EDEADLK handling.
2751 	 */
2752 	return err;
2753 
2754 err:
2755 	intel_gt_pm_put(ce->engine->gt);
2756 	for_each_child(ce, child)
2757 		intel_context_put(child);
2758 	intel_context_put(ce);
2759 	return err;
2760 }
2761 
2762 static void
2763 eb_put_engine(struct i915_execbuffer *eb)
2764 {
2765 	struct intel_context *child;
2766 
2767 	i915_vm_put(eb->context->vm);
2768 	intel_gt_pm_put(eb->gt);
2769 	for_each_child(eb->context, child)
2770 		intel_context_put(child);
2771 	intel_context_put(eb->context);
2772 }
2773 
2774 static void
2775 __free_fence_array(struct eb_fence *fences, unsigned int n)
2776 {
2777 	while (n--) {
2778 		drm_syncobj_put(ptr_mask_bits(fences[n].syncobj, 2));
2779 		dma_fence_put(fences[n].dma_fence);
2780 		dma_fence_chain_free(fences[n].chain_fence);
2781 	}
2782 	kvfree(fences);
2783 }
2784 
2785 static int
2786 add_timeline_fence_array(struct i915_execbuffer *eb,
2787 			 const struct drm_i915_gem_execbuffer_ext_timeline_fences *timeline_fences)
2788 {
2789 	struct drm_i915_gem_exec_fence __user *user_fences;
2790 	u64 __user *user_values;
2791 	struct eb_fence *f;
2792 	u64 nfences;
2793 	int err = 0;
2794 
2795 	nfences = timeline_fences->fence_count;
2796 	if (!nfences)
2797 		return 0;
2798 
2799 	/* Check multiplication overflow for access_ok() and kvmalloc_array() */
2800 	BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2801 	if (nfences > min_t(unsigned long,
2802 			    ULONG_MAX / sizeof(*user_fences),
2803 			    SIZE_MAX / sizeof(*f)) - eb->num_fences)
2804 		return -EINVAL;
2805 
2806 	user_fences = u64_to_user_ptr(timeline_fences->handles_ptr);
2807 	if (!access_ok(user_fences, nfences * sizeof(*user_fences)))
2808 		return -EFAULT;
2809 
2810 	user_values = u64_to_user_ptr(timeline_fences->values_ptr);
2811 	if (!access_ok(user_values, nfences * sizeof(*user_values)))
2812 		return -EFAULT;
2813 
2814 	f = krealloc(eb->fences,
2815 		     (eb->num_fences + nfences) * sizeof(*f),
2816 		     __GFP_NOWARN | GFP_KERNEL);
2817 	if (!f)
2818 		return -ENOMEM;
2819 
2820 	eb->fences = f;
2821 	f += eb->num_fences;
2822 
2823 	BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
2824 		     ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
2825 
2826 	while (nfences--) {
2827 		struct drm_i915_gem_exec_fence user_fence;
2828 		struct drm_syncobj *syncobj;
2829 		struct dma_fence *fence = NULL;
2830 		u64 point;
2831 
2832 		if (__copy_from_user(&user_fence,
2833 				     user_fences++,
2834 				     sizeof(user_fence)))
2835 			return -EFAULT;
2836 
2837 		if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS)
2838 			return -EINVAL;
2839 
2840 		if (__get_user(point, user_values++))
2841 			return -EFAULT;
2842 
2843 		syncobj = drm_syncobj_find(eb->file, user_fence.handle);
2844 		if (!syncobj) {
2845 			drm_dbg(&eb->i915->drm,
2846 				"Invalid syncobj handle provided\n");
2847 			return -ENOENT;
2848 		}
2849 
2850 		fence = drm_syncobj_fence_get(syncobj);
2851 
2852 		if (!fence && user_fence.flags &&
2853 		    !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2854 			drm_dbg(&eb->i915->drm,
2855 				"Syncobj handle has no fence\n");
2856 			drm_syncobj_put(syncobj);
2857 			return -EINVAL;
2858 		}
2859 
2860 		if (fence)
2861 			err = dma_fence_chain_find_seqno(&fence, point);
2862 
2863 		if (err && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2864 			drm_dbg(&eb->i915->drm,
2865 				"Syncobj handle missing requested point %llu\n",
2866 				point);
2867 			dma_fence_put(fence);
2868 			drm_syncobj_put(syncobj);
2869 			return err;
2870 		}
2871 
2872 		/*
2873 		 * A point might have been signaled already and
2874 		 * garbage collected from the timeline. In this case
2875 		 * just ignore the point and carry on.
2876 		 */
2877 		if (!fence && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2878 			drm_syncobj_put(syncobj);
2879 			continue;
2880 		}
2881 
2882 		/*
2883 		 * For timeline syncobjs we need to preallocate chains for
2884 		 * later signaling.
2885 		 */
2886 		if (point != 0 && user_fence.flags & I915_EXEC_FENCE_SIGNAL) {
2887 			/*
2888 			 * Waiting and signaling the same point (when point !=
2889 			 * 0) would break the timeline.
2890 			 */
2891 			if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
2892 				drm_dbg(&eb->i915->drm,
2893 					"Trying to wait & signal the same timeline point.\n");
2894 				dma_fence_put(fence);
2895 				drm_syncobj_put(syncobj);
2896 				return -EINVAL;
2897 			}
2898 
2899 			f->chain_fence = dma_fence_chain_alloc();
2900 			if (!f->chain_fence) {
2901 				drm_syncobj_put(syncobj);
2902 				dma_fence_put(fence);
2903 				return -ENOMEM;
2904 			}
2905 		} else {
2906 			f->chain_fence = NULL;
2907 		}
2908 
2909 		f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
2910 		f->dma_fence = fence;
2911 		f->value = point;
2912 		f++;
2913 		eb->num_fences++;
2914 	}
2915 
2916 	return 0;
2917 }
2918 
2919 static int add_fence_array(struct i915_execbuffer *eb)
2920 {
2921 	struct drm_i915_gem_execbuffer2 *args = eb->args;
2922 	struct drm_i915_gem_exec_fence __user *user;
2923 	unsigned long num_fences = args->num_cliprects;
2924 	struct eb_fence *f;
2925 
2926 	if (!(args->flags & I915_EXEC_FENCE_ARRAY))
2927 		return 0;
2928 
2929 	if (!num_fences)
2930 		return 0;
2931 
2932 	/* Check multiplication overflow for access_ok() and kvmalloc_array() */
2933 	BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2934 	if (num_fences > min_t(unsigned long,
2935 			       ULONG_MAX / sizeof(*user),
2936 			       SIZE_MAX / sizeof(*f) - eb->num_fences))
2937 		return -EINVAL;
2938 
2939 	user = u64_to_user_ptr(args->cliprects_ptr);
2940 	if (!access_ok(user, num_fences * sizeof(*user)))
2941 		return -EFAULT;
2942 
2943 	f = krealloc(eb->fences,
2944 		     (eb->num_fences + num_fences) * sizeof(*f),
2945 		     __GFP_NOWARN | GFP_KERNEL);
2946 	if (!f)
2947 		return -ENOMEM;
2948 
2949 	eb->fences = f;
2950 	f += eb->num_fences;
2951 	while (num_fences--) {
2952 		struct drm_i915_gem_exec_fence user_fence;
2953 		struct drm_syncobj *syncobj;
2954 		struct dma_fence *fence = NULL;
2955 
2956 		if (__copy_from_user(&user_fence, user++, sizeof(user_fence)))
2957 			return -EFAULT;
2958 
2959 		if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS)
2960 			return -EINVAL;
2961 
2962 		syncobj = drm_syncobj_find(eb->file, user_fence.handle);
2963 		if (!syncobj) {
2964 			drm_dbg(&eb->i915->drm,
2965 				"Invalid syncobj handle provided\n");
2966 			return -ENOENT;
2967 		}
2968 
2969 		if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
2970 			fence = drm_syncobj_fence_get(syncobj);
2971 			if (!fence) {
2972 				drm_dbg(&eb->i915->drm,
2973 					"Syncobj handle has no fence\n");
2974 				drm_syncobj_put(syncobj);
2975 				return -EINVAL;
2976 			}
2977 		}
2978 
2979 		BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
2980 			     ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
2981 
2982 		f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
2983 		f->dma_fence = fence;
2984 		f->value = 0;
2985 		f->chain_fence = NULL;
2986 		f++;
2987 		eb->num_fences++;
2988 	}
2989 
2990 	return 0;
2991 }
2992 
2993 static void put_fence_array(struct eb_fence *fences, int num_fences)
2994 {
2995 	if (fences)
2996 		__free_fence_array(fences, num_fences);
2997 }
2998 
2999 static int
3000 await_fence_array(struct i915_execbuffer *eb,
3001 		  struct i915_request *rq)
3002 {
3003 	unsigned int n;
3004 	int err;
3005 
3006 	for (n = 0; n < eb->num_fences; n++) {
3007 		if (!eb->fences[n].dma_fence)
3008 			continue;
3009 
3010 		err = i915_request_await_dma_fence(rq, eb->fences[n].dma_fence);
3011 		if (err < 0)
3012 			return err;
3013 	}
3014 
3015 	return 0;
3016 }
3017 
3018 static void signal_fence_array(const struct i915_execbuffer *eb,
3019 			       struct dma_fence * const fence)
3020 {
3021 	unsigned int n;
3022 
3023 	for (n = 0; n < eb->num_fences; n++) {
3024 		struct drm_syncobj *syncobj;
3025 		unsigned int flags;
3026 
3027 		syncobj = ptr_unpack_bits(eb->fences[n].syncobj, &flags, 2);
3028 		if (!(flags & I915_EXEC_FENCE_SIGNAL))
3029 			continue;
3030 
3031 		if (eb->fences[n].chain_fence) {
3032 			drm_syncobj_add_point(syncobj,
3033 					      eb->fences[n].chain_fence,
3034 					      fence,
3035 					      eb->fences[n].value);
3036 			/*
3037 			 * The chain's ownership is transferred to the
3038 			 * timeline.
3039 			 */
3040 			eb->fences[n].chain_fence = NULL;
3041 		} else {
3042 			drm_syncobj_replace_fence(syncobj, fence);
3043 		}
3044 	}
3045 }
3046 
3047 static int
3048 parse_timeline_fences(struct i915_user_extension __user *ext, void *data)
3049 {
3050 	struct i915_execbuffer *eb = data;
3051 	struct drm_i915_gem_execbuffer_ext_timeline_fences timeline_fences;
3052 
3053 	if (copy_from_user(&timeline_fences, ext, sizeof(timeline_fences)))
3054 		return -EFAULT;
3055 
3056 	return add_timeline_fence_array(eb, &timeline_fences);
3057 }
3058 
3059 static void retire_requests(struct intel_timeline *tl, struct i915_request *end)
3060 {
3061 	struct i915_request *rq, *rn;
3062 
3063 	list_for_each_entry_safe(rq, rn, &tl->requests, link)
3064 		if (rq == end || !i915_request_retire(rq))
3065 			break;
3066 }
3067 
3068 static int eb_request_add(struct i915_execbuffer *eb, struct i915_request *rq,
3069 			  int err, bool last_parallel)
3070 {
3071 	struct intel_timeline * const tl = i915_request_timeline(rq);
3072 	struct i915_sched_attr attr = {};
3073 	struct i915_request *prev;
3074 
3075 	lockdep_assert_held(&tl->mutex);
3076 	lockdep_unpin_lock(&tl->mutex, rq->cookie);
3077 
3078 	trace_i915_request_add(rq);
3079 
3080 	prev = __i915_request_commit(rq);
3081 
3082 	/* Check that the context wasn't destroyed before submission */
3083 	if (likely(!intel_context_is_closed(eb->context))) {
3084 		attr = eb->gem_context->sched;
3085 	} else {
3086 		/* Serialise with context_close via the add_to_timeline */
3087 		i915_request_set_error_once(rq, -ENOENT);
3088 		__i915_request_skip(rq);
3089 		err = -ENOENT; /* override any transient errors */
3090 	}
3091 
3092 	if (intel_context_is_parallel(eb->context)) {
3093 		if (err) {
3094 			__i915_request_skip(rq);
3095 			set_bit(I915_FENCE_FLAG_SKIP_PARALLEL,
3096 				&rq->fence.flags);
3097 		}
3098 		if (last_parallel)
3099 			set_bit(I915_FENCE_FLAG_SUBMIT_PARALLEL,
3100 				&rq->fence.flags);
3101 	}
3102 
3103 	__i915_request_queue(rq, &attr);
3104 
3105 	/* Try to clean up the client's timeline after submitting the request */
3106 	if (prev)
3107 		retire_requests(tl, prev);
3108 
3109 	mutex_unlock(&tl->mutex);
3110 
3111 	return err;
3112 }
3113 
3114 static int eb_requests_add(struct i915_execbuffer *eb, int err)
3115 {
3116 	int i;
3117 
3118 	/*
3119 	 * We iterate in reverse order of creation to release timeline mutexes in
3120 	 * same order.
3121 	 */
3122 	for_each_batch_add_order(eb, i) {
3123 		struct i915_request *rq = eb->requests[i];
3124 
3125 		if (!rq)
3126 			continue;
3127 		err |= eb_request_add(eb, rq, err, i == 0);
3128 	}
3129 
3130 	return err;
3131 }
3132 
3133 static const i915_user_extension_fn execbuf_extensions[] = {
3134 	[DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES] = parse_timeline_fences,
3135 };
3136 
3137 static int
3138 parse_execbuf2_extensions(struct drm_i915_gem_execbuffer2 *args,
3139 			  struct i915_execbuffer *eb)
3140 {
3141 	if (!(args->flags & I915_EXEC_USE_EXTENSIONS))
3142 		return 0;
3143 
3144 	/* The execbuf2 extension mechanism reuses cliprects_ptr. So we cannot
3145 	 * have another flag also using it at the same time.
3146 	 */
3147 	if (eb->args->flags & I915_EXEC_FENCE_ARRAY)
3148 		return -EINVAL;
3149 
3150 	if (args->num_cliprects != 0)
3151 		return -EINVAL;
3152 
3153 	return i915_user_extensions(u64_to_user_ptr(args->cliprects_ptr),
3154 				    execbuf_extensions,
3155 				    ARRAY_SIZE(execbuf_extensions),
3156 				    eb);
3157 }
3158 
3159 static void eb_requests_get(struct i915_execbuffer *eb)
3160 {
3161 	unsigned int i;
3162 
3163 	for_each_batch_create_order(eb, i) {
3164 		if (!eb->requests[i])
3165 			break;
3166 
3167 		i915_request_get(eb->requests[i]);
3168 	}
3169 }
3170 
3171 static void eb_requests_put(struct i915_execbuffer *eb)
3172 {
3173 	unsigned int i;
3174 
3175 	for_each_batch_create_order(eb, i) {
3176 		if (!eb->requests[i])
3177 			break;
3178 
3179 		i915_request_put(eb->requests[i]);
3180 	}
3181 }
3182 
3183 static struct sync_file *
3184 eb_composite_fence_create(struct i915_execbuffer *eb, int out_fence_fd)
3185 {
3186 	struct sync_file *out_fence = NULL;
3187 	struct dma_fence_array *fence_array;
3188 	struct dma_fence **fences;
3189 	unsigned int i;
3190 
3191 	GEM_BUG_ON(!intel_context_is_parent(eb->context));
3192 
3193 	fences = kmalloc_array(eb->num_batches, sizeof(*fences), GFP_KERNEL);
3194 	if (!fences)
3195 		return ERR_PTR(-ENOMEM);
3196 
3197 	for_each_batch_create_order(eb, i) {
3198 		fences[i] = &eb->requests[i]->fence;
3199 		__set_bit(I915_FENCE_FLAG_COMPOSITE,
3200 			  &eb->requests[i]->fence.flags);
3201 	}
3202 
3203 	fence_array = dma_fence_array_create(eb->num_batches,
3204 					     fences,
3205 					     eb->context->parallel.fence_context,
3206 					     eb->context->parallel.seqno++,
3207 					     false);
3208 	if (!fence_array) {
3209 		kfree(fences);
3210 		return ERR_PTR(-ENOMEM);
3211 	}
3212 
3213 	/* Move ownership to the dma_fence_array created above */
3214 	for_each_batch_create_order(eb, i)
3215 		dma_fence_get(fences[i]);
3216 
3217 	if (out_fence_fd != -1) {
3218 		out_fence = sync_file_create(&fence_array->base);
3219 		/* sync_file now owns fence_arry, drop creation ref */
3220 		dma_fence_put(&fence_array->base);
3221 		if (!out_fence)
3222 			return ERR_PTR(-ENOMEM);
3223 	}
3224 
3225 	eb->composite_fence = &fence_array->base;
3226 
3227 	return out_fence;
3228 }
3229 
3230 static struct sync_file *
3231 eb_fences_add(struct i915_execbuffer *eb, struct i915_request *rq,
3232 	      struct dma_fence *in_fence, int out_fence_fd)
3233 {
3234 	struct sync_file *out_fence = NULL;
3235 	int err;
3236 
3237 	if (unlikely(eb->gem_context->syncobj)) {
3238 		struct dma_fence *fence;
3239 
3240 		fence = drm_syncobj_fence_get(eb->gem_context->syncobj);
3241 		err = i915_request_await_dma_fence(rq, fence);
3242 		dma_fence_put(fence);
3243 		if (err)
3244 			return ERR_PTR(err);
3245 	}
3246 
3247 	if (in_fence) {
3248 		if (eb->args->flags & I915_EXEC_FENCE_SUBMIT)
3249 			err = i915_request_await_execution(rq, in_fence);
3250 		else
3251 			err = i915_request_await_dma_fence(rq, in_fence);
3252 		if (err < 0)
3253 			return ERR_PTR(err);
3254 	}
3255 
3256 	if (eb->fences) {
3257 		err = await_fence_array(eb, rq);
3258 		if (err)
3259 			return ERR_PTR(err);
3260 	}
3261 
3262 	if (intel_context_is_parallel(eb->context)) {
3263 		out_fence = eb_composite_fence_create(eb, out_fence_fd);
3264 		if (IS_ERR(out_fence))
3265 			return ERR_PTR(-ENOMEM);
3266 	} else if (out_fence_fd != -1) {
3267 		out_fence = sync_file_create(&rq->fence);
3268 		if (!out_fence)
3269 			return ERR_PTR(-ENOMEM);
3270 	}
3271 
3272 	return out_fence;
3273 }
3274 
3275 static struct intel_context *
3276 eb_find_context(struct i915_execbuffer *eb, unsigned int context_number)
3277 {
3278 	struct intel_context *child;
3279 
3280 	if (likely(context_number == 0))
3281 		return eb->context;
3282 
3283 	for_each_child(eb->context, child)
3284 		if (!--context_number)
3285 			return child;
3286 
3287 	GEM_BUG_ON("Context not found");
3288 
3289 	return NULL;
3290 }
3291 
3292 static struct sync_file *
3293 eb_requests_create(struct i915_execbuffer *eb, struct dma_fence *in_fence,
3294 		   int out_fence_fd)
3295 {
3296 	struct sync_file *out_fence = NULL;
3297 	unsigned int i;
3298 
3299 	for_each_batch_create_order(eb, i) {
3300 		/* Allocate a request for this batch buffer nice and early. */
3301 		eb->requests[i] = i915_request_create(eb_find_context(eb, i));
3302 		if (IS_ERR(eb->requests[i])) {
3303 			out_fence = ERR_CAST(eb->requests[i]);
3304 			eb->requests[i] = NULL;
3305 			return out_fence;
3306 		}
3307 
3308 		/*
3309 		 * Only the first request added (committed to backend) has to
3310 		 * take the in fences into account as all subsequent requests
3311 		 * will have fences inserted inbetween them.
3312 		 */
3313 		if (i + 1 == eb->num_batches) {
3314 			out_fence = eb_fences_add(eb, eb->requests[i],
3315 						  in_fence, out_fence_fd);
3316 			if (IS_ERR(out_fence))
3317 				return out_fence;
3318 		}
3319 
3320 		/*
3321 		 * Not really on stack, but we don't want to call
3322 		 * kfree on the batch_snapshot when we put it, so use the
3323 		 * _onstack interface.
3324 		 */
3325 		if (eb->batches[i]->vma)
3326 			eb->requests[i]->batch_res =
3327 				i915_vma_resource_get(eb->batches[i]->vma->resource);
3328 		if (eb->batch_pool) {
3329 			GEM_BUG_ON(intel_context_is_parallel(eb->context));
3330 			intel_gt_buffer_pool_mark_active(eb->batch_pool,
3331 							 eb->requests[i]);
3332 		}
3333 	}
3334 
3335 	return out_fence;
3336 }
3337 
3338 static int
3339 i915_gem_do_execbuffer(struct drm_device *dev,
3340 		       struct drm_file *file,
3341 		       struct drm_i915_gem_execbuffer2 *args,
3342 		       struct drm_i915_gem_exec_object2 *exec)
3343 {
3344 	struct drm_i915_private *i915 = to_i915(dev);
3345 	struct i915_execbuffer eb;
3346 	struct dma_fence *in_fence = NULL;
3347 	struct sync_file *out_fence = NULL;
3348 	int out_fence_fd = -1;
3349 	int err;
3350 
3351 	BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
3352 	BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
3353 		     ~__EXEC_OBJECT_UNKNOWN_FLAGS);
3354 
3355 	eb.i915 = i915;
3356 	eb.file = file;
3357 	eb.args = args;
3358 	if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC))
3359 		args->flags |= __EXEC_HAS_RELOC;
3360 
3361 	eb.exec = exec;
3362 	eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1);
3363 	eb.vma[0].vma = NULL;
3364 	eb.batch_pool = NULL;
3365 
3366 	eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
3367 	reloc_cache_init(&eb.reloc_cache, eb.i915);
3368 
3369 	eb.buffer_count = args->buffer_count;
3370 	eb.batch_start_offset = args->batch_start_offset;
3371 	eb.trampoline = NULL;
3372 
3373 	eb.fences = NULL;
3374 	eb.num_fences = 0;
3375 
3376 	eb_capture_list_clear(&eb);
3377 
3378 	memset(eb.requests, 0, sizeof(struct i915_request *) *
3379 	       ARRAY_SIZE(eb.requests));
3380 	eb.composite_fence = NULL;
3381 
3382 	eb.batch_flags = 0;
3383 	if (args->flags & I915_EXEC_SECURE) {
3384 		if (GRAPHICS_VER(i915) >= 11)
3385 			return -ENODEV;
3386 
3387 		/* Return -EPERM to trigger fallback code on old binaries. */
3388 		if (!HAS_SECURE_BATCHES(i915))
3389 			return -EPERM;
3390 
3391 		if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
3392 			return -EPERM;
3393 
3394 		eb.batch_flags |= I915_DISPATCH_SECURE;
3395 	}
3396 	if (args->flags & I915_EXEC_IS_PINNED)
3397 		eb.batch_flags |= I915_DISPATCH_PINNED;
3398 
3399 	err = parse_execbuf2_extensions(args, &eb);
3400 	if (err)
3401 		goto err_ext;
3402 
3403 	err = add_fence_array(&eb);
3404 	if (err)
3405 		goto err_ext;
3406 
3407 #define IN_FENCES (I915_EXEC_FENCE_IN | I915_EXEC_FENCE_SUBMIT)
3408 	if (args->flags & IN_FENCES) {
3409 		if ((args->flags & IN_FENCES) == IN_FENCES)
3410 			return -EINVAL;
3411 
3412 		in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
3413 		if (!in_fence) {
3414 			err = -EINVAL;
3415 			goto err_ext;
3416 		}
3417 	}
3418 #undef IN_FENCES
3419 
3420 	if (args->flags & I915_EXEC_FENCE_OUT) {
3421 		out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
3422 		if (out_fence_fd < 0) {
3423 			err = out_fence_fd;
3424 			goto err_in_fence;
3425 		}
3426 	}
3427 
3428 	err = eb_create(&eb);
3429 	if (err)
3430 		goto err_out_fence;
3431 
3432 	GEM_BUG_ON(!eb.lut_size);
3433 
3434 	err = eb_select_context(&eb);
3435 	if (unlikely(err))
3436 		goto err_destroy;
3437 
3438 	err = eb_select_engine(&eb);
3439 	if (unlikely(err))
3440 		goto err_context;
3441 
3442 	err = eb_lookup_vmas(&eb);
3443 	if (err) {
3444 		eb_release_vmas(&eb, true);
3445 		goto err_engine;
3446 	}
3447 
3448 	i915_gem_ww_ctx_init(&eb.ww, true);
3449 
3450 	err = eb_relocate_parse(&eb);
3451 	if (err) {
3452 		/*
3453 		 * If the user expects the execobject.offset and
3454 		 * reloc.presumed_offset to be an exact match,
3455 		 * as for using NO_RELOC, then we cannot update
3456 		 * the execobject.offset until we have completed
3457 		 * relocation.
3458 		 */
3459 		args->flags &= ~__EXEC_HAS_RELOC;
3460 		goto err_vma;
3461 	}
3462 
3463 	ww_acquire_done(&eb.ww.ctx);
3464 	err = eb_capture_stage(&eb);
3465 	if (err)
3466 		goto err_vma;
3467 
3468 	out_fence = eb_requests_create(&eb, in_fence, out_fence_fd);
3469 	if (IS_ERR(out_fence)) {
3470 		err = PTR_ERR(out_fence);
3471 		out_fence = NULL;
3472 		if (eb.requests[0])
3473 			goto err_request;
3474 		else
3475 			goto err_vma;
3476 	}
3477 
3478 	err = eb_submit(&eb);
3479 
3480 err_request:
3481 	eb_requests_get(&eb);
3482 	err = eb_requests_add(&eb, err);
3483 
3484 	if (eb.fences)
3485 		signal_fence_array(&eb, eb.composite_fence ?
3486 				   eb.composite_fence :
3487 				   &eb.requests[0]->fence);
3488 
3489 	if (unlikely(eb.gem_context->syncobj)) {
3490 		drm_syncobj_replace_fence(eb.gem_context->syncobj,
3491 					  eb.composite_fence ?
3492 					  eb.composite_fence :
3493 					  &eb.requests[0]->fence);
3494 	}
3495 
3496 	if (out_fence) {
3497 		if (err == 0) {
3498 			fd_install(out_fence_fd, out_fence->file);
3499 			args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */
3500 			args->rsvd2 |= (u64)out_fence_fd << 32;
3501 			out_fence_fd = -1;
3502 		} else {
3503 			fput(out_fence->file);
3504 		}
3505 	}
3506 
3507 	if (!out_fence && eb.composite_fence)
3508 		dma_fence_put(eb.composite_fence);
3509 
3510 	eb_requests_put(&eb);
3511 
3512 err_vma:
3513 	eb_release_vmas(&eb, true);
3514 	WARN_ON(err == -EDEADLK);
3515 	i915_gem_ww_ctx_fini(&eb.ww);
3516 
3517 	if (eb.batch_pool)
3518 		intel_gt_buffer_pool_put(eb.batch_pool);
3519 err_engine:
3520 	eb_put_engine(&eb);
3521 err_context:
3522 	i915_gem_context_put(eb.gem_context);
3523 err_destroy:
3524 	eb_destroy(&eb);
3525 err_out_fence:
3526 	if (out_fence_fd != -1)
3527 		put_unused_fd(out_fence_fd);
3528 err_in_fence:
3529 	dma_fence_put(in_fence);
3530 err_ext:
3531 	put_fence_array(eb.fences, eb.num_fences);
3532 	return err;
3533 }
3534 
3535 static size_t eb_element_size(void)
3536 {
3537 	return sizeof(struct drm_i915_gem_exec_object2) + sizeof(struct eb_vma);
3538 }
3539 
3540 static bool check_buffer_count(size_t count)
3541 {
3542 	const size_t sz = eb_element_size();
3543 
3544 	/*
3545 	 * When using LUT_HANDLE, we impose a limit of INT_MAX for the lookup
3546 	 * array size (see eb_create()). Otherwise, we can accept an array as
3547 	 * large as can be addressed (though use large arrays at your peril)!
3548 	 */
3549 
3550 	return !(count < 1 || count > INT_MAX || count > SIZE_MAX / sz - 1);
3551 }
3552 
3553 int
3554 i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
3555 			   struct drm_file *file)
3556 {
3557 	struct drm_i915_private *i915 = to_i915(dev);
3558 	struct drm_i915_gem_execbuffer2 *args = data;
3559 	struct drm_i915_gem_exec_object2 *exec2_list;
3560 	const size_t count = args->buffer_count;
3561 	int err;
3562 
3563 	if (!check_buffer_count(count)) {
3564 		drm_dbg(&i915->drm, "execbuf2 with %zd buffers\n", count);
3565 		return -EINVAL;
3566 	}
3567 
3568 	err = i915_gem_check_execbuffer(i915, args);
3569 	if (err)
3570 		return err;
3571 
3572 	/* Allocate extra slots for use by the command parser */
3573 	exec2_list = kvmalloc_array(count + 2, eb_element_size(),
3574 				    __GFP_NOWARN | GFP_KERNEL);
3575 	if (exec2_list == NULL) {
3576 		drm_dbg(&i915->drm, "Failed to allocate exec list for %zd buffers\n",
3577 			count);
3578 		return -ENOMEM;
3579 	}
3580 	if (copy_from_user(exec2_list,
3581 			   u64_to_user_ptr(args->buffers_ptr),
3582 			   sizeof(*exec2_list) * count)) {
3583 		drm_dbg(&i915->drm, "copy %zd exec entries failed\n", count);
3584 		kvfree(exec2_list);
3585 		return -EFAULT;
3586 	}
3587 
3588 	err = i915_gem_do_execbuffer(dev, file, args, exec2_list);
3589 
3590 	/*
3591 	 * Now that we have begun execution of the batchbuffer, we ignore
3592 	 * any new error after this point. Also given that we have already
3593 	 * updated the associated relocations, we try to write out the current
3594 	 * object locations irrespective of any error.
3595 	 */
3596 	if (args->flags & __EXEC_HAS_RELOC) {
3597 		struct drm_i915_gem_exec_object2 __user *user_exec_list =
3598 			u64_to_user_ptr(args->buffers_ptr);
3599 		unsigned int i;
3600 
3601 		/* Copy the new buffer offsets back to the user's exec list. */
3602 		/*
3603 		 * Note: count * sizeof(*user_exec_list) does not overflow,
3604 		 * because we checked 'count' in check_buffer_count().
3605 		 *
3606 		 * And this range already got effectively checked earlier
3607 		 * when we did the "copy_from_user()" above.
3608 		 */
3609 		if (!user_write_access_begin(user_exec_list,
3610 					     count * sizeof(*user_exec_list)))
3611 			goto end;
3612 
3613 		for (i = 0; i < args->buffer_count; i++) {
3614 			if (!(exec2_list[i].offset & UPDATE))
3615 				continue;
3616 
3617 			exec2_list[i].offset =
3618 				gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
3619 			unsafe_put_user(exec2_list[i].offset,
3620 					&user_exec_list[i].offset,
3621 					end_user);
3622 		}
3623 end_user:
3624 		user_write_access_end();
3625 end:;
3626 	}
3627 
3628 	args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;
3629 	kvfree(exec2_list);
3630 	return err;
3631 }
3632