1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright 2012 Red Hat Inc 5 */ 6 7 #include <linux/dma-buf.h> 8 #include <linux/highmem.h> 9 #include <linux/dma-resv.h> 10 #include <linux/module.h> 11 12 #include <asm/smp.h> 13 14 #include "gem/i915_gem_dmabuf.h" 15 #include "i915_drv.h" 16 #include "i915_gem_object.h" 17 #include "i915_scatterlist.h" 18 19 MODULE_IMPORT_NS(DMA_BUF); 20 21 I915_SELFTEST_DECLARE(static bool force_different_devices;) 22 23 static struct drm_i915_gem_object *dma_buf_to_obj(struct dma_buf *buf) 24 { 25 return to_intel_bo(buf->priv); 26 } 27 28 static struct sg_table *i915_gem_map_dma_buf(struct dma_buf_attachment *attachment, 29 enum dma_data_direction dir) 30 { 31 struct drm_i915_gem_object *obj = dma_buf_to_obj(attachment->dmabuf); 32 struct sg_table *st; 33 struct scatterlist *src, *dst; 34 int ret, i; 35 36 /* Copy sg so that we make an independent mapping */ 37 st = kmalloc(sizeof(struct sg_table), GFP_KERNEL); 38 if (st == NULL) { 39 ret = -ENOMEM; 40 goto err; 41 } 42 43 ret = sg_alloc_table(st, obj->mm.pages->nents, GFP_KERNEL); 44 if (ret) 45 goto err_free; 46 47 src = obj->mm.pages->sgl; 48 dst = st->sgl; 49 for (i = 0; i < obj->mm.pages->nents; i++) { 50 sg_set_page(dst, sg_page(src), src->length, 0); 51 dst = sg_next(dst); 52 src = sg_next(src); 53 } 54 55 ret = dma_map_sgtable(attachment->dev, st, dir, DMA_ATTR_SKIP_CPU_SYNC); 56 if (ret) 57 goto err_free_sg; 58 59 return st; 60 61 err_free_sg: 62 sg_free_table(st); 63 err_free: 64 kfree(st); 65 err: 66 return ERR_PTR(ret); 67 } 68 69 static int i915_gem_dmabuf_vmap(struct dma_buf *dma_buf, 70 struct iosys_map *map) 71 { 72 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf); 73 void *vaddr; 74 75 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); 76 if (IS_ERR(vaddr)) 77 return PTR_ERR(vaddr); 78 79 iosys_map_set_vaddr(map, vaddr); 80 81 return 0; 82 } 83 84 static void i915_gem_dmabuf_vunmap(struct dma_buf *dma_buf, 85 struct iosys_map *map) 86 { 87 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf); 88 89 i915_gem_object_flush_map(obj); 90 i915_gem_object_unpin_map(obj); 91 } 92 93 static int i915_gem_dmabuf_mmap(struct dma_buf *dma_buf, struct vm_area_struct *vma) 94 { 95 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf); 96 struct drm_i915_private *i915 = to_i915(obj->base.dev); 97 int ret; 98 99 if (obj->base.size < vma->vm_end - vma->vm_start) 100 return -EINVAL; 101 102 if (HAS_LMEM(i915)) 103 return drm_gem_prime_mmap(&obj->base, vma); 104 105 if (!obj->base.filp) 106 return -ENODEV; 107 108 ret = call_mmap(obj->base.filp, vma); 109 if (ret) 110 return ret; 111 112 vma_set_file(vma, obj->base.filp); 113 114 return 0; 115 } 116 117 static int i915_gem_begin_cpu_access(struct dma_buf *dma_buf, enum dma_data_direction direction) 118 { 119 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf); 120 bool write = (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE); 121 struct i915_gem_ww_ctx ww; 122 int err; 123 124 i915_gem_ww_ctx_init(&ww, true); 125 retry: 126 err = i915_gem_object_lock(obj, &ww); 127 if (!err) 128 err = i915_gem_object_pin_pages(obj); 129 if (!err) { 130 err = i915_gem_object_set_to_cpu_domain(obj, write); 131 i915_gem_object_unpin_pages(obj); 132 } 133 if (err == -EDEADLK) { 134 err = i915_gem_ww_ctx_backoff(&ww); 135 if (!err) 136 goto retry; 137 } 138 i915_gem_ww_ctx_fini(&ww); 139 return err; 140 } 141 142 static int i915_gem_end_cpu_access(struct dma_buf *dma_buf, enum dma_data_direction direction) 143 { 144 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf); 145 struct i915_gem_ww_ctx ww; 146 int err; 147 148 i915_gem_ww_ctx_init(&ww, true); 149 retry: 150 err = i915_gem_object_lock(obj, &ww); 151 if (!err) 152 err = i915_gem_object_pin_pages(obj); 153 if (!err) { 154 err = i915_gem_object_set_to_gtt_domain(obj, false); 155 i915_gem_object_unpin_pages(obj); 156 } 157 if (err == -EDEADLK) { 158 err = i915_gem_ww_ctx_backoff(&ww); 159 if (!err) 160 goto retry; 161 } 162 i915_gem_ww_ctx_fini(&ww); 163 return err; 164 } 165 166 static int i915_gem_dmabuf_attach(struct dma_buf *dmabuf, 167 struct dma_buf_attachment *attach) 168 { 169 struct drm_i915_gem_object *obj = dma_buf_to_obj(dmabuf); 170 struct i915_gem_ww_ctx ww; 171 int err; 172 173 if (!i915_gem_object_can_migrate(obj, INTEL_REGION_SMEM)) 174 return -EOPNOTSUPP; 175 176 for_i915_gem_ww(&ww, err, true) { 177 err = i915_gem_object_lock(obj, &ww); 178 if (err) 179 continue; 180 181 err = i915_gem_object_migrate(obj, &ww, INTEL_REGION_SMEM); 182 if (err) 183 continue; 184 185 err = i915_gem_object_wait_migration(obj, 0); 186 if (err) 187 continue; 188 189 err = i915_gem_object_pin_pages(obj); 190 } 191 192 return err; 193 } 194 195 static void i915_gem_dmabuf_detach(struct dma_buf *dmabuf, 196 struct dma_buf_attachment *attach) 197 { 198 struct drm_i915_gem_object *obj = dma_buf_to_obj(dmabuf); 199 200 i915_gem_object_unpin_pages(obj); 201 } 202 203 static const struct dma_buf_ops i915_dmabuf_ops = { 204 .attach = i915_gem_dmabuf_attach, 205 .detach = i915_gem_dmabuf_detach, 206 .map_dma_buf = i915_gem_map_dma_buf, 207 .unmap_dma_buf = drm_gem_unmap_dma_buf, 208 .release = drm_gem_dmabuf_release, 209 .mmap = i915_gem_dmabuf_mmap, 210 .vmap = i915_gem_dmabuf_vmap, 211 .vunmap = i915_gem_dmabuf_vunmap, 212 .begin_cpu_access = i915_gem_begin_cpu_access, 213 .end_cpu_access = i915_gem_end_cpu_access, 214 }; 215 216 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags) 217 { 218 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); 219 DEFINE_DMA_BUF_EXPORT_INFO(exp_info); 220 221 exp_info.ops = &i915_dmabuf_ops; 222 exp_info.size = gem_obj->size; 223 exp_info.flags = flags; 224 exp_info.priv = gem_obj; 225 exp_info.resv = obj->base.resv; 226 227 if (obj->ops->dmabuf_export) { 228 int ret = obj->ops->dmabuf_export(obj); 229 if (ret) 230 return ERR_PTR(ret); 231 } 232 233 return drm_gem_dmabuf_export(gem_obj->dev, &exp_info); 234 } 235 236 static int i915_gem_object_get_pages_dmabuf(struct drm_i915_gem_object *obj) 237 { 238 struct drm_i915_private *i915 = to_i915(obj->base.dev); 239 struct sg_table *pages; 240 unsigned int sg_page_sizes; 241 242 assert_object_held(obj); 243 244 pages = dma_buf_map_attachment(obj->base.import_attach, 245 DMA_BIDIRECTIONAL); 246 if (IS_ERR(pages)) 247 return PTR_ERR(pages); 248 249 /* 250 * DG1 is special here since it still snoops transactions even with 251 * CACHE_NONE. This is not the case with other HAS_SNOOP platforms. We 252 * might need to revisit this as we add new discrete platforms. 253 * 254 * XXX: Consider doing a vmap flush or something, where possible. 255 * Currently we just do a heavy handed wbinvd_on_all_cpus() here since 256 * the underlying sg_table might not even point to struct pages, so we 257 * can't just call drm_clflush_sg or similar, like we do elsewhere in 258 * the driver. 259 */ 260 if (i915_gem_object_can_bypass_llc(obj) || 261 (!HAS_LLC(i915) && !IS_DG1(i915))) 262 wbinvd_on_all_cpus(); 263 264 sg_page_sizes = i915_sg_dma_sizes(pages->sgl); 265 __i915_gem_object_set_pages(obj, pages, sg_page_sizes); 266 267 return 0; 268 } 269 270 static void i915_gem_object_put_pages_dmabuf(struct drm_i915_gem_object *obj, 271 struct sg_table *pages) 272 { 273 dma_buf_unmap_attachment(obj->base.import_attach, pages, 274 DMA_BIDIRECTIONAL); 275 } 276 277 static const struct drm_i915_gem_object_ops i915_gem_object_dmabuf_ops = { 278 .name = "i915_gem_object_dmabuf", 279 .get_pages = i915_gem_object_get_pages_dmabuf, 280 .put_pages = i915_gem_object_put_pages_dmabuf, 281 }; 282 283 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 284 struct dma_buf *dma_buf) 285 { 286 static struct lock_class_key lock_class; 287 struct dma_buf_attachment *attach; 288 struct drm_i915_gem_object *obj; 289 int ret; 290 291 /* is this one of own objects? */ 292 if (dma_buf->ops == &i915_dmabuf_ops) { 293 obj = dma_buf_to_obj(dma_buf); 294 /* is it from our device? */ 295 if (obj->base.dev == dev && 296 !I915_SELFTEST_ONLY(force_different_devices)) { 297 /* 298 * Importing dmabuf exported from out own gem increases 299 * refcount on gem itself instead of f_count of dmabuf. 300 */ 301 return &i915_gem_object_get(obj)->base; 302 } 303 } 304 305 if (i915_gem_object_size_2big(dma_buf->size)) 306 return ERR_PTR(-E2BIG); 307 308 /* need to attach */ 309 attach = dma_buf_attach(dma_buf, dev->dev); 310 if (IS_ERR(attach)) 311 return ERR_CAST(attach); 312 313 get_dma_buf(dma_buf); 314 315 obj = i915_gem_object_alloc(); 316 if (obj == NULL) { 317 ret = -ENOMEM; 318 goto fail_detach; 319 } 320 321 drm_gem_private_object_init(dev, &obj->base, dma_buf->size); 322 i915_gem_object_init(obj, &i915_gem_object_dmabuf_ops, &lock_class, 323 I915_BO_ALLOC_USER); 324 obj->base.import_attach = attach; 325 obj->base.resv = dma_buf->resv; 326 327 /* We use GTT as shorthand for a coherent domain, one that is 328 * neither in the GPU cache nor in the CPU cache, where all 329 * writes are immediately visible in memory. (That's not strictly 330 * true, but it's close! There are internal buffers such as the 331 * write-combined buffer or a delay through the chipset for GTT 332 * writes that do require us to treat GTT as a separate cache domain.) 333 */ 334 obj->read_domains = I915_GEM_DOMAIN_GTT; 335 obj->write_domain = 0; 336 337 return &obj->base; 338 339 fail_detach: 340 dma_buf_detach(dma_buf, attach); 341 dma_buf_put(dma_buf); 342 343 return ERR_PTR(ret); 344 } 345 346 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 347 #include "selftests/mock_dmabuf.c" 348 #include "selftests/i915_gem_dmabuf.c" 349 #endif 350