1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright 2012 Red Hat Inc 5 */ 6 7 #include <linux/dma-buf.h> 8 #include <linux/highmem.h> 9 #include <linux/dma-resv.h> 10 #include <linux/module.h> 11 12 #include <asm/smp.h> 13 14 #include "gem/i915_gem_dmabuf.h" 15 #include "i915_drv.h" 16 #include "i915_gem_object.h" 17 #include "i915_scatterlist.h" 18 19 MODULE_IMPORT_NS(DMA_BUF); 20 21 I915_SELFTEST_DECLARE(static bool force_different_devices;) 22 23 static struct drm_i915_gem_object *dma_buf_to_obj(struct dma_buf *buf) 24 { 25 return to_intel_bo(buf->priv); 26 } 27 28 static struct sg_table *i915_gem_map_dma_buf(struct dma_buf_attachment *attachment, 29 enum dma_data_direction dir) 30 { 31 struct drm_i915_gem_object *obj = dma_buf_to_obj(attachment->dmabuf); 32 struct sg_table *st; 33 struct scatterlist *src, *dst; 34 int ret, i; 35 36 /* Copy sg so that we make an independent mapping */ 37 st = kmalloc(sizeof(struct sg_table), GFP_KERNEL); 38 if (st == NULL) { 39 ret = -ENOMEM; 40 goto err; 41 } 42 43 ret = sg_alloc_table(st, obj->mm.pages->nents, GFP_KERNEL); 44 if (ret) 45 goto err_free; 46 47 src = obj->mm.pages->sgl; 48 dst = st->sgl; 49 for (i = 0; i < obj->mm.pages->nents; i++) { 50 sg_set_page(dst, sg_page(src), src->length, 0); 51 dst = sg_next(dst); 52 src = sg_next(src); 53 } 54 55 ret = dma_map_sgtable(attachment->dev, st, dir, DMA_ATTR_SKIP_CPU_SYNC); 56 if (ret) 57 goto err_free_sg; 58 59 return st; 60 61 err_free_sg: 62 sg_free_table(st); 63 err_free: 64 kfree(st); 65 err: 66 return ERR_PTR(ret); 67 } 68 69 static void i915_gem_unmap_dma_buf(struct dma_buf_attachment *attachment, 70 struct sg_table *sg, 71 enum dma_data_direction dir) 72 { 73 dma_unmap_sgtable(attachment->dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC); 74 sg_free_table(sg); 75 kfree(sg); 76 } 77 78 static int i915_gem_dmabuf_vmap(struct dma_buf *dma_buf, 79 struct iosys_map *map) 80 { 81 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf); 82 void *vaddr; 83 84 vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB); 85 if (IS_ERR(vaddr)) 86 return PTR_ERR(vaddr); 87 88 iosys_map_set_vaddr(map, vaddr); 89 90 return 0; 91 } 92 93 static void i915_gem_dmabuf_vunmap(struct dma_buf *dma_buf, 94 struct iosys_map *map) 95 { 96 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf); 97 98 i915_gem_object_flush_map(obj); 99 i915_gem_object_unpin_map(obj); 100 } 101 102 static int i915_gem_dmabuf_mmap(struct dma_buf *dma_buf, struct vm_area_struct *vma) 103 { 104 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf); 105 int ret; 106 107 if (obj->base.size < vma->vm_end - vma->vm_start) 108 return -EINVAL; 109 110 if (!obj->base.filp) 111 return -ENODEV; 112 113 ret = call_mmap(obj->base.filp, vma); 114 if (ret) 115 return ret; 116 117 vma_set_file(vma, obj->base.filp); 118 119 return 0; 120 } 121 122 static int i915_gem_begin_cpu_access(struct dma_buf *dma_buf, enum dma_data_direction direction) 123 { 124 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf); 125 bool write = (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE); 126 struct i915_gem_ww_ctx ww; 127 int err; 128 129 i915_gem_ww_ctx_init(&ww, true); 130 retry: 131 err = i915_gem_object_lock(obj, &ww); 132 if (!err) 133 err = i915_gem_object_pin_pages(obj); 134 if (!err) { 135 err = i915_gem_object_set_to_cpu_domain(obj, write); 136 i915_gem_object_unpin_pages(obj); 137 } 138 if (err == -EDEADLK) { 139 err = i915_gem_ww_ctx_backoff(&ww); 140 if (!err) 141 goto retry; 142 } 143 i915_gem_ww_ctx_fini(&ww); 144 return err; 145 } 146 147 static int i915_gem_end_cpu_access(struct dma_buf *dma_buf, enum dma_data_direction direction) 148 { 149 struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf); 150 struct i915_gem_ww_ctx ww; 151 int err; 152 153 i915_gem_ww_ctx_init(&ww, true); 154 retry: 155 err = i915_gem_object_lock(obj, &ww); 156 if (!err) 157 err = i915_gem_object_pin_pages(obj); 158 if (!err) { 159 err = i915_gem_object_set_to_gtt_domain(obj, false); 160 i915_gem_object_unpin_pages(obj); 161 } 162 if (err == -EDEADLK) { 163 err = i915_gem_ww_ctx_backoff(&ww); 164 if (!err) 165 goto retry; 166 } 167 i915_gem_ww_ctx_fini(&ww); 168 return err; 169 } 170 171 static int i915_gem_dmabuf_attach(struct dma_buf *dmabuf, 172 struct dma_buf_attachment *attach) 173 { 174 struct drm_i915_gem_object *obj = dma_buf_to_obj(dmabuf); 175 struct i915_gem_ww_ctx ww; 176 int err; 177 178 if (!i915_gem_object_can_migrate(obj, INTEL_REGION_SMEM)) 179 return -EOPNOTSUPP; 180 181 for_i915_gem_ww(&ww, err, true) { 182 err = i915_gem_object_lock(obj, &ww); 183 if (err) 184 continue; 185 186 err = i915_gem_object_migrate(obj, &ww, INTEL_REGION_SMEM); 187 if (err) 188 continue; 189 190 err = i915_gem_object_wait_migration(obj, 0); 191 if (err) 192 continue; 193 194 err = i915_gem_object_pin_pages(obj); 195 } 196 197 return err; 198 } 199 200 static void i915_gem_dmabuf_detach(struct dma_buf *dmabuf, 201 struct dma_buf_attachment *attach) 202 { 203 struct drm_i915_gem_object *obj = dma_buf_to_obj(dmabuf); 204 205 i915_gem_object_unpin_pages(obj); 206 } 207 208 static const struct dma_buf_ops i915_dmabuf_ops = { 209 .attach = i915_gem_dmabuf_attach, 210 .detach = i915_gem_dmabuf_detach, 211 .map_dma_buf = i915_gem_map_dma_buf, 212 .unmap_dma_buf = i915_gem_unmap_dma_buf, 213 .release = drm_gem_dmabuf_release, 214 .mmap = i915_gem_dmabuf_mmap, 215 .vmap = i915_gem_dmabuf_vmap, 216 .vunmap = i915_gem_dmabuf_vunmap, 217 .begin_cpu_access = i915_gem_begin_cpu_access, 218 .end_cpu_access = i915_gem_end_cpu_access, 219 }; 220 221 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags) 222 { 223 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); 224 DEFINE_DMA_BUF_EXPORT_INFO(exp_info); 225 226 exp_info.ops = &i915_dmabuf_ops; 227 exp_info.size = gem_obj->size; 228 exp_info.flags = flags; 229 exp_info.priv = gem_obj; 230 exp_info.resv = obj->base.resv; 231 232 if (obj->ops->dmabuf_export) { 233 int ret = obj->ops->dmabuf_export(obj); 234 if (ret) 235 return ERR_PTR(ret); 236 } 237 238 return drm_gem_dmabuf_export(gem_obj->dev, &exp_info); 239 } 240 241 static int i915_gem_object_get_pages_dmabuf(struct drm_i915_gem_object *obj) 242 { 243 struct drm_i915_private *i915 = to_i915(obj->base.dev); 244 struct sg_table *pages; 245 unsigned int sg_page_sizes; 246 247 assert_object_held(obj); 248 249 pages = dma_buf_map_attachment(obj->base.import_attach, 250 DMA_BIDIRECTIONAL); 251 if (IS_ERR(pages)) 252 return PTR_ERR(pages); 253 254 /* 255 * DG1 is special here since it still snoops transactions even with 256 * CACHE_NONE. This is not the case with other HAS_SNOOP platforms. We 257 * might need to revisit this as we add new discrete platforms. 258 * 259 * XXX: Consider doing a vmap flush or something, where possible. 260 * Currently we just do a heavy handed wbinvd_on_all_cpus() here since 261 * the underlying sg_table might not even point to struct pages, so we 262 * can't just call drm_clflush_sg or similar, like we do elsewhere in 263 * the driver. 264 */ 265 if (i915_gem_object_can_bypass_llc(obj) || 266 (!HAS_LLC(i915) && !IS_DG1(i915))) 267 wbinvd_on_all_cpus(); 268 269 sg_page_sizes = i915_sg_dma_sizes(pages->sgl); 270 __i915_gem_object_set_pages(obj, pages, sg_page_sizes); 271 272 return 0; 273 } 274 275 static void i915_gem_object_put_pages_dmabuf(struct drm_i915_gem_object *obj, 276 struct sg_table *pages) 277 { 278 dma_buf_unmap_attachment(obj->base.import_attach, pages, 279 DMA_BIDIRECTIONAL); 280 } 281 282 static const struct drm_i915_gem_object_ops i915_gem_object_dmabuf_ops = { 283 .name = "i915_gem_object_dmabuf", 284 .get_pages = i915_gem_object_get_pages_dmabuf, 285 .put_pages = i915_gem_object_put_pages_dmabuf, 286 }; 287 288 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 289 struct dma_buf *dma_buf) 290 { 291 static struct lock_class_key lock_class; 292 struct dma_buf_attachment *attach; 293 struct drm_i915_gem_object *obj; 294 int ret; 295 296 /* is this one of own objects? */ 297 if (dma_buf->ops == &i915_dmabuf_ops) { 298 obj = dma_buf_to_obj(dma_buf); 299 /* is it from our device? */ 300 if (obj->base.dev == dev && 301 !I915_SELFTEST_ONLY(force_different_devices)) { 302 /* 303 * Importing dmabuf exported from out own gem increases 304 * refcount on gem itself instead of f_count of dmabuf. 305 */ 306 return &i915_gem_object_get(obj)->base; 307 } 308 } 309 310 if (i915_gem_object_size_2big(dma_buf->size)) 311 return ERR_PTR(-E2BIG); 312 313 /* need to attach */ 314 attach = dma_buf_attach(dma_buf, dev->dev); 315 if (IS_ERR(attach)) 316 return ERR_CAST(attach); 317 318 get_dma_buf(dma_buf); 319 320 obj = i915_gem_object_alloc(); 321 if (obj == NULL) { 322 ret = -ENOMEM; 323 goto fail_detach; 324 } 325 326 drm_gem_private_object_init(dev, &obj->base, dma_buf->size); 327 i915_gem_object_init(obj, &i915_gem_object_dmabuf_ops, &lock_class, 328 I915_BO_ALLOC_USER); 329 obj->base.import_attach = attach; 330 obj->base.resv = dma_buf->resv; 331 332 /* We use GTT as shorthand for a coherent domain, one that is 333 * neither in the GPU cache nor in the CPU cache, where all 334 * writes are immediately visible in memory. (That's not strictly 335 * true, but it's close! There are internal buffers such as the 336 * write-combined buffer or a delay through the chipset for GTT 337 * writes that do require us to treat GTT as a separate cache domain.) 338 */ 339 obj->read_domains = I915_GEM_DOMAIN_GTT; 340 obj->write_domain = 0; 341 342 return &obj->base; 343 344 fail_detach: 345 dma_buf_detach(dma_buf, attach); 346 dma_buf_put(dma_buf); 347 348 return ERR_PTR(ret); 349 } 350 351 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 352 #include "selftests/mock_dmabuf.c" 353 #include "selftests/i915_gem_dmabuf.c" 354 #endif 355