1 /*
2  * SPDX-License-Identifier: MIT
3  *
4  * Copyright © 2011-2012 Intel Corporation
5  */
6 
7 /*
8  * This file implements HW context support. On gen5+ a HW context consists of an
9  * opaque GPU object which is referenced at times of context saves and restores.
10  * With RC6 enabled, the context is also referenced as the GPU enters and exists
11  * from RC6 (GPU has it's own internal power context, except on gen5). Though
12  * something like a context does exist for the media ring, the code only
13  * supports contexts for the render ring.
14  *
15  * In software, there is a distinction between contexts created by the user,
16  * and the default HW context. The default HW context is used by GPU clients
17  * that do not request setup of their own hardware context. The default
18  * context's state is never restored to help prevent programming errors. This
19  * would happen if a client ran and piggy-backed off another clients GPU state.
20  * The default context only exists to give the GPU some offset to load as the
21  * current to invoke a save of the context we actually care about. In fact, the
22  * code could likely be constructed, albeit in a more complicated fashion, to
23  * never use the default context, though that limits the driver's ability to
24  * swap out, and/or destroy other contexts.
25  *
26  * All other contexts are created as a request by the GPU client. These contexts
27  * store GPU state, and thus allow GPU clients to not re-emit state (and
28  * potentially query certain state) at any time. The kernel driver makes
29  * certain that the appropriate commands are inserted.
30  *
31  * The context life cycle is semi-complicated in that context BOs may live
32  * longer than the context itself because of the way the hardware, and object
33  * tracking works. Below is a very crude representation of the state machine
34  * describing the context life.
35  *                                         refcount     pincount     active
36  * S0: initial state                          0            0           0
37  * S1: context created                        1            0           0
38  * S2: context is currently running           2            1           X
39  * S3: GPU referenced, but not current        2            0           1
40  * S4: context is current, but destroyed      1            1           0
41  * S5: like S3, but destroyed                 1            0           1
42  *
43  * The most common (but not all) transitions:
44  * S0->S1: client creates a context
45  * S1->S2: client submits execbuf with context
46  * S2->S3: other clients submits execbuf with context
47  * S3->S1: context object was retired
48  * S3->S2: clients submits another execbuf
49  * S2->S4: context destroy called with current context
50  * S3->S5->S0: destroy path
51  * S4->S5->S0: destroy path on current context
52  *
53  * There are two confusing terms used above:
54  *  The "current context" means the context which is currently running on the
55  *  GPU. The GPU has loaded its state already and has stored away the gtt
56  *  offset of the BO. The GPU is not actively referencing the data at this
57  *  offset, but it will on the next context switch. The only way to avoid this
58  *  is to do a GPU reset.
59  *
60  *  An "active context' is one which was previously the "current context" and is
61  *  on the active list waiting for the next context switch to occur. Until this
62  *  happens, the object must remain at the same gtt offset. It is therefore
63  *  possible to destroy a context, but it is still active.
64  *
65  */
66 
67 #include <linux/log2.h>
68 #include <linux/nospec.h>
69 
70 #include <drm/i915_drm.h>
71 
72 #include "gt/intel_lrc_reg.h"
73 
74 #include "i915_gem_context.h"
75 #include "i915_globals.h"
76 #include "i915_trace.h"
77 #include "i915_user_extensions.h"
78 
79 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
80 
81 static struct i915_global_gem_context {
82 	struct i915_global base;
83 	struct kmem_cache *slab_luts;
84 } global;
85 
86 struct i915_lut_handle *i915_lut_handle_alloc(void)
87 {
88 	return kmem_cache_alloc(global.slab_luts, GFP_KERNEL);
89 }
90 
91 void i915_lut_handle_free(struct i915_lut_handle *lut)
92 {
93 	return kmem_cache_free(global.slab_luts, lut);
94 }
95 
96 static void lut_close(struct i915_gem_context *ctx)
97 {
98 	struct radix_tree_iter iter;
99 	void __rcu **slot;
100 
101 	lockdep_assert_held(&ctx->mutex);
102 
103 	rcu_read_lock();
104 	radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) {
105 		struct i915_vma *vma = rcu_dereference_raw(*slot);
106 		struct drm_i915_gem_object *obj = vma->obj;
107 		struct i915_lut_handle *lut;
108 
109 		if (!kref_get_unless_zero(&obj->base.refcount))
110 			continue;
111 
112 		rcu_read_unlock();
113 		i915_gem_object_lock(obj);
114 		list_for_each_entry(lut, &obj->lut_list, obj_link) {
115 			if (lut->ctx != ctx)
116 				continue;
117 
118 			if (lut->handle != iter.index)
119 				continue;
120 
121 			list_del(&lut->obj_link);
122 			break;
123 		}
124 		i915_gem_object_unlock(obj);
125 		rcu_read_lock();
126 
127 		if (&lut->obj_link != &obj->lut_list) {
128 			i915_lut_handle_free(lut);
129 			radix_tree_iter_delete(&ctx->handles_vma, &iter, slot);
130 			if (atomic_dec_and_test(&vma->open_count) &&
131 			    !i915_vma_is_ggtt(vma))
132 				i915_vma_close(vma);
133 			i915_gem_object_put(obj);
134 		}
135 
136 		i915_gem_object_put(obj);
137 	}
138 	rcu_read_unlock();
139 }
140 
141 static struct intel_context *
142 lookup_user_engine(struct i915_gem_context *ctx,
143 		   unsigned long flags,
144 		   const struct i915_engine_class_instance *ci)
145 #define LOOKUP_USER_INDEX BIT(0)
146 {
147 	int idx;
148 
149 	if (!!(flags & LOOKUP_USER_INDEX) != i915_gem_context_user_engines(ctx))
150 		return ERR_PTR(-EINVAL);
151 
152 	if (!i915_gem_context_user_engines(ctx)) {
153 		struct intel_engine_cs *engine;
154 
155 		engine = intel_engine_lookup_user(ctx->i915,
156 						  ci->engine_class,
157 						  ci->engine_instance);
158 		if (!engine)
159 			return ERR_PTR(-EINVAL);
160 
161 		idx = engine->id;
162 	} else {
163 		idx = ci->engine_instance;
164 	}
165 
166 	return i915_gem_context_get_engine(ctx, idx);
167 }
168 
169 static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp)
170 {
171 	unsigned int max;
172 
173 	lockdep_assert_held(&i915->contexts.mutex);
174 
175 	if (INTEL_GEN(i915) >= 11)
176 		max = GEN11_MAX_CONTEXT_HW_ID;
177 	else if (USES_GUC_SUBMISSION(i915))
178 		/*
179 		 * When using GuC in proxy submission, GuC consumes the
180 		 * highest bit in the context id to indicate proxy submission.
181 		 */
182 		max = MAX_GUC_CONTEXT_HW_ID;
183 	else
184 		max = MAX_CONTEXT_HW_ID;
185 
186 	return ida_simple_get(&i915->contexts.hw_ida, 0, max, gfp);
187 }
188 
189 static int steal_hw_id(struct drm_i915_private *i915)
190 {
191 	struct i915_gem_context *ctx, *cn;
192 	LIST_HEAD(pinned);
193 	int id = -ENOSPC;
194 
195 	lockdep_assert_held(&i915->contexts.mutex);
196 
197 	list_for_each_entry_safe(ctx, cn,
198 				 &i915->contexts.hw_id_list, hw_id_link) {
199 		if (atomic_read(&ctx->hw_id_pin_count)) {
200 			list_move_tail(&ctx->hw_id_link, &pinned);
201 			continue;
202 		}
203 
204 		GEM_BUG_ON(!ctx->hw_id); /* perma-pinned kernel context */
205 		list_del_init(&ctx->hw_id_link);
206 		id = ctx->hw_id;
207 		break;
208 	}
209 
210 	/*
211 	 * Remember how far we got up on the last repossesion scan, so the
212 	 * list is kept in a "least recently scanned" order.
213 	 */
214 	list_splice_tail(&pinned, &i915->contexts.hw_id_list);
215 	return id;
216 }
217 
218 static int assign_hw_id(struct drm_i915_private *i915, unsigned int *out)
219 {
220 	int ret;
221 
222 	lockdep_assert_held(&i915->contexts.mutex);
223 
224 	/*
225 	 * We prefer to steal/stall ourselves and our users over that of the
226 	 * entire system. That may be a little unfair to our users, and
227 	 * even hurt high priority clients. The choice is whether to oomkill
228 	 * something else, or steal a context id.
229 	 */
230 	ret = new_hw_id(i915, GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
231 	if (unlikely(ret < 0)) {
232 		ret = steal_hw_id(i915);
233 		if (ret < 0) /* once again for the correct errno code */
234 			ret = new_hw_id(i915, GFP_KERNEL);
235 		if (ret < 0)
236 			return ret;
237 	}
238 
239 	*out = ret;
240 	return 0;
241 }
242 
243 static void release_hw_id(struct i915_gem_context *ctx)
244 {
245 	struct drm_i915_private *i915 = ctx->i915;
246 
247 	if (list_empty(&ctx->hw_id_link))
248 		return;
249 
250 	mutex_lock(&i915->contexts.mutex);
251 	if (!list_empty(&ctx->hw_id_link)) {
252 		ida_simple_remove(&i915->contexts.hw_ida, ctx->hw_id);
253 		list_del_init(&ctx->hw_id_link);
254 	}
255 	mutex_unlock(&i915->contexts.mutex);
256 }
257 
258 static void __free_engines(struct i915_gem_engines *e, unsigned int count)
259 {
260 	while (count--) {
261 		if (!e->engines[count])
262 			continue;
263 
264 		intel_context_put(e->engines[count]);
265 	}
266 	kfree(e);
267 }
268 
269 static void free_engines(struct i915_gem_engines *e)
270 {
271 	__free_engines(e, e->num_engines);
272 }
273 
274 static void free_engines_rcu(struct rcu_head *rcu)
275 {
276 	free_engines(container_of(rcu, struct i915_gem_engines, rcu));
277 }
278 
279 static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
280 {
281 	struct intel_engine_cs *engine;
282 	struct i915_gem_engines *e;
283 	enum intel_engine_id id;
284 
285 	e = kzalloc(struct_size(e, engines, I915_NUM_ENGINES), GFP_KERNEL);
286 	if (!e)
287 		return ERR_PTR(-ENOMEM);
288 
289 	init_rcu_head(&e->rcu);
290 	for_each_engine(engine, ctx->i915, id) {
291 		struct intel_context *ce;
292 
293 		ce = intel_context_create(ctx, engine);
294 		if (IS_ERR(ce)) {
295 			__free_engines(e, id);
296 			return ERR_CAST(ce);
297 		}
298 
299 		e->engines[id] = ce;
300 	}
301 	e->num_engines = id;
302 
303 	return e;
304 }
305 
306 static void i915_gem_context_free(struct i915_gem_context *ctx)
307 {
308 	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
309 	GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
310 
311 	release_hw_id(ctx);
312 	if (ctx->vm)
313 		i915_vm_put(ctx->vm);
314 
315 	free_engines(rcu_access_pointer(ctx->engines));
316 	mutex_destroy(&ctx->engines_mutex);
317 
318 	if (ctx->timeline)
319 		intel_timeline_put(ctx->timeline);
320 
321 	kfree(ctx->name);
322 	put_pid(ctx->pid);
323 
324 	list_del(&ctx->link);
325 	mutex_destroy(&ctx->mutex);
326 
327 	kfree_rcu(ctx, rcu);
328 }
329 
330 static void contexts_free(struct drm_i915_private *i915)
331 {
332 	struct llist_node *freed = llist_del_all(&i915->contexts.free_list);
333 	struct i915_gem_context *ctx, *cn;
334 
335 	lockdep_assert_held(&i915->drm.struct_mutex);
336 
337 	llist_for_each_entry_safe(ctx, cn, freed, free_link)
338 		i915_gem_context_free(ctx);
339 }
340 
341 static void contexts_free_first(struct drm_i915_private *i915)
342 {
343 	struct i915_gem_context *ctx;
344 	struct llist_node *freed;
345 
346 	lockdep_assert_held(&i915->drm.struct_mutex);
347 
348 	freed = llist_del_first(&i915->contexts.free_list);
349 	if (!freed)
350 		return;
351 
352 	ctx = container_of(freed, typeof(*ctx), free_link);
353 	i915_gem_context_free(ctx);
354 }
355 
356 static void contexts_free_worker(struct work_struct *work)
357 {
358 	struct drm_i915_private *i915 =
359 		container_of(work, typeof(*i915), contexts.free_work);
360 
361 	mutex_lock(&i915->drm.struct_mutex);
362 	contexts_free(i915);
363 	mutex_unlock(&i915->drm.struct_mutex);
364 }
365 
366 void i915_gem_context_release(struct kref *ref)
367 {
368 	struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
369 	struct drm_i915_private *i915 = ctx->i915;
370 
371 	trace_i915_context_free(ctx);
372 	if (llist_add(&ctx->free_link, &i915->contexts.free_list))
373 		queue_work(i915->wq, &i915->contexts.free_work);
374 }
375 
376 static void context_close(struct i915_gem_context *ctx)
377 {
378 	mutex_lock(&ctx->mutex);
379 
380 	i915_gem_context_set_closed(ctx);
381 	ctx->file_priv = ERR_PTR(-EBADF);
382 
383 	/*
384 	 * This context will never again be assinged to HW, so we can
385 	 * reuse its ID for the next context.
386 	 */
387 	release_hw_id(ctx);
388 
389 	/*
390 	 * The LUT uses the VMA as a backpointer to unref the object,
391 	 * so we need to clear the LUT before we close all the VMA (inside
392 	 * the ppgtt).
393 	 */
394 	lut_close(ctx);
395 
396 	mutex_unlock(&ctx->mutex);
397 	i915_gem_context_put(ctx);
398 }
399 
400 static u32 default_desc_template(const struct drm_i915_private *i915,
401 				 const struct i915_address_space *vm)
402 {
403 	u32 address_mode;
404 	u32 desc;
405 
406 	desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
407 
408 	address_mode = INTEL_LEGACY_32B_CONTEXT;
409 	if (vm && i915_vm_is_4lvl(vm))
410 		address_mode = INTEL_LEGACY_64B_CONTEXT;
411 	desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
412 
413 	if (IS_GEN(i915, 8))
414 		desc |= GEN8_CTX_L3LLC_COHERENT;
415 
416 	/* TODO: WaDisableLiteRestore when we start using semaphore
417 	 * signalling between Command Streamers
418 	 * ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
419 	 */
420 
421 	return desc;
422 }
423 
424 static struct i915_gem_context *
425 __create_context(struct drm_i915_private *i915)
426 {
427 	struct i915_gem_context *ctx;
428 	struct i915_gem_engines *e;
429 	int err;
430 	int i;
431 
432 	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
433 	if (!ctx)
434 		return ERR_PTR(-ENOMEM);
435 
436 	kref_init(&ctx->ref);
437 	list_add_tail(&ctx->link, &i915->contexts.list);
438 	ctx->i915 = i915;
439 	ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL);
440 	mutex_init(&ctx->mutex);
441 
442 	mutex_init(&ctx->engines_mutex);
443 	e = default_engines(ctx);
444 	if (IS_ERR(e)) {
445 		err = PTR_ERR(e);
446 		goto err_free;
447 	}
448 	RCU_INIT_POINTER(ctx->engines, e);
449 
450 	INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL);
451 	INIT_LIST_HEAD(&ctx->hw_id_link);
452 
453 	/* NB: Mark all slices as needing a remap so that when the context first
454 	 * loads it will restore whatever remap state already exists. If there
455 	 * is no remap info, it will be a NOP. */
456 	ctx->remap_slice = ALL_L3_SLICES(i915);
457 
458 	i915_gem_context_set_bannable(ctx);
459 	i915_gem_context_set_recoverable(ctx);
460 
461 	ctx->ring_size = 4 * PAGE_SIZE;
462 	ctx->desc_template = default_desc_template(i915, NULL);
463 
464 	for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
465 		ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
466 
467 	return ctx;
468 
469 err_free:
470 	kfree(ctx);
471 	return ERR_PTR(err);
472 }
473 
474 static struct i915_address_space *
475 __set_ppgtt(struct i915_gem_context *ctx, struct i915_address_space *vm)
476 {
477 	struct i915_address_space *old = ctx->vm;
478 	struct i915_gem_engines_iter it;
479 	struct intel_context *ce;
480 
481 	ctx->vm = i915_vm_get(vm);
482 	ctx->desc_template = default_desc_template(ctx->i915, vm);
483 
484 	for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
485 		i915_vm_put(ce->vm);
486 		ce->vm = i915_vm_get(vm);
487 	}
488 	i915_gem_context_unlock_engines(ctx);
489 
490 	return old;
491 }
492 
493 static void __assign_ppgtt(struct i915_gem_context *ctx,
494 			   struct i915_address_space *vm)
495 {
496 	if (vm == ctx->vm)
497 		return;
498 
499 	vm = __set_ppgtt(ctx, vm);
500 	if (vm)
501 		i915_vm_put(vm);
502 }
503 
504 static struct i915_gem_context *
505 i915_gem_create_context(struct drm_i915_private *dev_priv, unsigned int flags)
506 {
507 	struct i915_gem_context *ctx;
508 
509 	lockdep_assert_held(&dev_priv->drm.struct_mutex);
510 
511 	if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE &&
512 	    !HAS_EXECLISTS(dev_priv))
513 		return ERR_PTR(-EINVAL);
514 
515 	/* Reap the most stale context */
516 	contexts_free_first(dev_priv);
517 
518 	ctx = __create_context(dev_priv);
519 	if (IS_ERR(ctx))
520 		return ctx;
521 
522 	if (HAS_FULL_PPGTT(dev_priv)) {
523 		struct i915_ppgtt *ppgtt;
524 
525 		ppgtt = i915_ppgtt_create(dev_priv);
526 		if (IS_ERR(ppgtt)) {
527 			DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
528 					 PTR_ERR(ppgtt));
529 			context_close(ctx);
530 			return ERR_CAST(ppgtt);
531 		}
532 
533 		__assign_ppgtt(ctx, &ppgtt->vm);
534 		i915_vm_put(&ppgtt->vm);
535 	}
536 
537 	if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) {
538 		struct intel_timeline *timeline;
539 
540 		timeline = intel_timeline_create(&dev_priv->gt, NULL);
541 		if (IS_ERR(timeline)) {
542 			context_close(ctx);
543 			return ERR_CAST(timeline);
544 		}
545 
546 		ctx->timeline = timeline;
547 	}
548 
549 	trace_i915_context_create(ctx);
550 
551 	return ctx;
552 }
553 
554 /**
555  * i915_gem_context_create_gvt - create a GVT GEM context
556  * @dev: drm device *
557  *
558  * This function is used to create a GVT specific GEM context.
559  *
560  * Returns:
561  * pointer to i915_gem_context on success, error pointer if failed
562  *
563  */
564 struct i915_gem_context *
565 i915_gem_context_create_gvt(struct drm_device *dev)
566 {
567 	struct i915_gem_context *ctx;
568 	int ret;
569 
570 	if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
571 		return ERR_PTR(-ENODEV);
572 
573 	ret = i915_mutex_lock_interruptible(dev);
574 	if (ret)
575 		return ERR_PTR(ret);
576 
577 	ctx = i915_gem_create_context(to_i915(dev), 0);
578 	if (IS_ERR(ctx))
579 		goto out;
580 
581 	ret = i915_gem_context_pin_hw_id(ctx);
582 	if (ret) {
583 		context_close(ctx);
584 		ctx = ERR_PTR(ret);
585 		goto out;
586 	}
587 
588 	ctx->file_priv = ERR_PTR(-EBADF);
589 	i915_gem_context_set_closed(ctx); /* not user accessible */
590 	i915_gem_context_clear_bannable(ctx);
591 	i915_gem_context_set_force_single_submission(ctx);
592 	if (!USES_GUC_SUBMISSION(to_i915(dev)))
593 		ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
594 
595 	GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
596 out:
597 	mutex_unlock(&dev->struct_mutex);
598 	return ctx;
599 }
600 
601 static void
602 destroy_kernel_context(struct i915_gem_context **ctxp)
603 {
604 	struct i915_gem_context *ctx;
605 
606 	/* Keep the context ref so that we can free it immediately ourselves */
607 	ctx = i915_gem_context_get(fetch_and_zero(ctxp));
608 	GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
609 
610 	context_close(ctx);
611 	i915_gem_context_free(ctx);
612 }
613 
614 struct i915_gem_context *
615 i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio)
616 {
617 	struct i915_gem_context *ctx;
618 	int err;
619 
620 	ctx = i915_gem_create_context(i915, 0);
621 	if (IS_ERR(ctx))
622 		return ctx;
623 
624 	err = i915_gem_context_pin_hw_id(ctx);
625 	if (err) {
626 		destroy_kernel_context(&ctx);
627 		return ERR_PTR(err);
628 	}
629 
630 	i915_gem_context_clear_bannable(ctx);
631 	ctx->sched.priority = I915_USER_PRIORITY(prio);
632 	ctx->ring_size = PAGE_SIZE;
633 
634 	GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
635 
636 	return ctx;
637 }
638 
639 static void init_contexts(struct drm_i915_private *i915)
640 {
641 	mutex_init(&i915->contexts.mutex);
642 	INIT_LIST_HEAD(&i915->contexts.list);
643 
644 	/* Using the simple ida interface, the max is limited by sizeof(int) */
645 	BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
646 	BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > INT_MAX);
647 	ida_init(&i915->contexts.hw_ida);
648 	INIT_LIST_HEAD(&i915->contexts.hw_id_list);
649 
650 	INIT_WORK(&i915->contexts.free_work, contexts_free_worker);
651 	init_llist_head(&i915->contexts.free_list);
652 }
653 
654 int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
655 {
656 	struct i915_gem_context *ctx;
657 
658 	/* Reassure ourselves we are only called once */
659 	GEM_BUG_ON(dev_priv->kernel_context);
660 
661 	init_contexts(dev_priv);
662 
663 	/* lowest priority; idle task */
664 	ctx = i915_gem_context_create_kernel(dev_priv, I915_PRIORITY_MIN);
665 	if (IS_ERR(ctx)) {
666 		DRM_ERROR("Failed to create default global context\n");
667 		return PTR_ERR(ctx);
668 	}
669 	/*
670 	 * For easy recognisablity, we want the kernel context to be 0 and then
671 	 * all user contexts will have non-zero hw_id. Kernel contexts are
672 	 * permanently pinned, so that we never suffer a stall and can
673 	 * use them from any allocation context (e.g. for evicting other
674 	 * contexts and from inside the shrinker).
675 	 */
676 	GEM_BUG_ON(ctx->hw_id);
677 	GEM_BUG_ON(!atomic_read(&ctx->hw_id_pin_count));
678 	dev_priv->kernel_context = ctx;
679 
680 	DRM_DEBUG_DRIVER("%s context support initialized\n",
681 			 DRIVER_CAPS(dev_priv)->has_logical_contexts ?
682 			 "logical" : "fake");
683 	return 0;
684 }
685 
686 void i915_gem_contexts_fini(struct drm_i915_private *i915)
687 {
688 	lockdep_assert_held(&i915->drm.struct_mutex);
689 
690 	destroy_kernel_context(&i915->kernel_context);
691 
692 	/* Must free all deferred contexts (via flush_workqueue) first */
693 	GEM_BUG_ON(!list_empty(&i915->contexts.hw_id_list));
694 	ida_destroy(&i915->contexts.hw_ida);
695 }
696 
697 static int context_idr_cleanup(int id, void *p, void *data)
698 {
699 	context_close(p);
700 	return 0;
701 }
702 
703 static int vm_idr_cleanup(int id, void *p, void *data)
704 {
705 	i915_vm_put(p);
706 	return 0;
707 }
708 
709 static int gem_context_register(struct i915_gem_context *ctx,
710 				struct drm_i915_file_private *fpriv)
711 {
712 	int ret;
713 
714 	ctx->file_priv = fpriv;
715 	if (ctx->vm)
716 		ctx->vm->file = fpriv;
717 
718 	ctx->pid = get_task_pid(current, PIDTYPE_PID);
719 	ctx->name = kasprintf(GFP_KERNEL, "%s[%d]",
720 			      current->comm, pid_nr(ctx->pid));
721 	if (!ctx->name) {
722 		ret = -ENOMEM;
723 		goto err_pid;
724 	}
725 
726 	/* And finally expose ourselves to userspace via the idr */
727 	mutex_lock(&fpriv->context_idr_lock);
728 	ret = idr_alloc(&fpriv->context_idr, ctx, 0, 0, GFP_KERNEL);
729 	mutex_unlock(&fpriv->context_idr_lock);
730 	if (ret >= 0)
731 		goto out;
732 
733 	kfree(fetch_and_zero(&ctx->name));
734 err_pid:
735 	put_pid(fetch_and_zero(&ctx->pid));
736 out:
737 	return ret;
738 }
739 
740 int i915_gem_context_open(struct drm_i915_private *i915,
741 			  struct drm_file *file)
742 {
743 	struct drm_i915_file_private *file_priv = file->driver_priv;
744 	struct i915_gem_context *ctx;
745 	int err;
746 
747 	mutex_init(&file_priv->context_idr_lock);
748 	mutex_init(&file_priv->vm_idr_lock);
749 
750 	idr_init(&file_priv->context_idr);
751 	idr_init_base(&file_priv->vm_idr, 1);
752 
753 	mutex_lock(&i915->drm.struct_mutex);
754 	ctx = i915_gem_create_context(i915, 0);
755 	mutex_unlock(&i915->drm.struct_mutex);
756 	if (IS_ERR(ctx)) {
757 		err = PTR_ERR(ctx);
758 		goto err;
759 	}
760 
761 	err = gem_context_register(ctx, file_priv);
762 	if (err < 0)
763 		goto err_ctx;
764 
765 	GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
766 	GEM_BUG_ON(err > 0);
767 
768 	return 0;
769 
770 err_ctx:
771 	context_close(ctx);
772 err:
773 	idr_destroy(&file_priv->vm_idr);
774 	idr_destroy(&file_priv->context_idr);
775 	mutex_destroy(&file_priv->vm_idr_lock);
776 	mutex_destroy(&file_priv->context_idr_lock);
777 	return err;
778 }
779 
780 void i915_gem_context_close(struct drm_file *file)
781 {
782 	struct drm_i915_file_private *file_priv = file->driver_priv;
783 
784 	idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
785 	idr_destroy(&file_priv->context_idr);
786 	mutex_destroy(&file_priv->context_idr_lock);
787 
788 	idr_for_each(&file_priv->vm_idr, vm_idr_cleanup, NULL);
789 	idr_destroy(&file_priv->vm_idr);
790 	mutex_destroy(&file_priv->vm_idr_lock);
791 }
792 
793 int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
794 			     struct drm_file *file)
795 {
796 	struct drm_i915_private *i915 = to_i915(dev);
797 	struct drm_i915_gem_vm_control *args = data;
798 	struct drm_i915_file_private *file_priv = file->driver_priv;
799 	struct i915_ppgtt *ppgtt;
800 	int err;
801 
802 	if (!HAS_FULL_PPGTT(i915))
803 		return -ENODEV;
804 
805 	if (args->flags)
806 		return -EINVAL;
807 
808 	ppgtt = i915_ppgtt_create(i915);
809 	if (IS_ERR(ppgtt))
810 		return PTR_ERR(ppgtt);
811 
812 	ppgtt->vm.file = file_priv;
813 
814 	if (args->extensions) {
815 		err = i915_user_extensions(u64_to_user_ptr(args->extensions),
816 					   NULL, 0,
817 					   ppgtt);
818 		if (err)
819 			goto err_put;
820 	}
821 
822 	err = mutex_lock_interruptible(&file_priv->vm_idr_lock);
823 	if (err)
824 		goto err_put;
825 
826 	err = idr_alloc(&file_priv->vm_idr, &ppgtt->vm, 0, 0, GFP_KERNEL);
827 	if (err < 0)
828 		goto err_unlock;
829 
830 	GEM_BUG_ON(err == 0); /* reserved for invalid/unassigned ppgtt */
831 
832 	mutex_unlock(&file_priv->vm_idr_lock);
833 
834 	args->vm_id = err;
835 	return 0;
836 
837 err_unlock:
838 	mutex_unlock(&file_priv->vm_idr_lock);
839 err_put:
840 	i915_vm_put(&ppgtt->vm);
841 	return err;
842 }
843 
844 int i915_gem_vm_destroy_ioctl(struct drm_device *dev, void *data,
845 			      struct drm_file *file)
846 {
847 	struct drm_i915_file_private *file_priv = file->driver_priv;
848 	struct drm_i915_gem_vm_control *args = data;
849 	struct i915_address_space *vm;
850 	int err;
851 	u32 id;
852 
853 	if (args->flags)
854 		return -EINVAL;
855 
856 	if (args->extensions)
857 		return -EINVAL;
858 
859 	id = args->vm_id;
860 	if (!id)
861 		return -ENOENT;
862 
863 	err = mutex_lock_interruptible(&file_priv->vm_idr_lock);
864 	if (err)
865 		return err;
866 
867 	vm = idr_remove(&file_priv->vm_idr, id);
868 
869 	mutex_unlock(&file_priv->vm_idr_lock);
870 	if (!vm)
871 		return -ENOENT;
872 
873 	i915_vm_put(vm);
874 	return 0;
875 }
876 
877 struct context_barrier_task {
878 	struct i915_active base;
879 	void (*task)(void *data);
880 	void *data;
881 };
882 
883 static void cb_retire(struct i915_active *base)
884 {
885 	struct context_barrier_task *cb = container_of(base, typeof(*cb), base);
886 
887 	if (cb->task)
888 		cb->task(cb->data);
889 
890 	i915_active_fini(&cb->base);
891 	kfree(cb);
892 }
893 
894 I915_SELFTEST_DECLARE(static intel_engine_mask_t context_barrier_inject_fault);
895 static int context_barrier_task(struct i915_gem_context *ctx,
896 				intel_engine_mask_t engines,
897 				bool (*skip)(struct intel_context *ce, void *data),
898 				int (*emit)(struct i915_request *rq, void *data),
899 				void (*task)(void *data),
900 				void *data)
901 {
902 	struct drm_i915_private *i915 = ctx->i915;
903 	struct context_barrier_task *cb;
904 	struct i915_gem_engines_iter it;
905 	struct intel_context *ce;
906 	int err = 0;
907 
908 	lockdep_assert_held(&i915->drm.struct_mutex);
909 	GEM_BUG_ON(!task);
910 
911 	cb = kmalloc(sizeof(*cb), GFP_KERNEL);
912 	if (!cb)
913 		return -ENOMEM;
914 
915 	i915_active_init(i915, &cb->base, NULL, cb_retire);
916 	err = i915_active_acquire(&cb->base);
917 	if (err) {
918 		kfree(cb);
919 		return err;
920 	}
921 
922 	for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
923 		struct i915_request *rq;
924 
925 		if (I915_SELFTEST_ONLY(context_barrier_inject_fault &
926 				       ce->engine->mask)) {
927 			err = -ENXIO;
928 			break;
929 		}
930 
931 		if (!(ce->engine->mask & engines))
932 			continue;
933 
934 		if (skip && skip(ce, data))
935 			continue;
936 
937 		rq = intel_context_create_request(ce);
938 		if (IS_ERR(rq)) {
939 			err = PTR_ERR(rq);
940 			break;
941 		}
942 
943 		err = 0;
944 		if (emit)
945 			err = emit(rq, data);
946 		if (err == 0)
947 			err = i915_active_ref(&cb->base, rq->fence.context, rq);
948 
949 		i915_request_add(rq);
950 		if (err)
951 			break;
952 	}
953 	i915_gem_context_unlock_engines(ctx);
954 
955 	cb->task = err ? NULL : task; /* caller needs to unwind instead */
956 	cb->data = data;
957 
958 	i915_active_release(&cb->base);
959 
960 	return err;
961 }
962 
963 static int get_ppgtt(struct drm_i915_file_private *file_priv,
964 		     struct i915_gem_context *ctx,
965 		     struct drm_i915_gem_context_param *args)
966 {
967 	struct i915_address_space *vm;
968 	int ret;
969 
970 	if (!ctx->vm)
971 		return -ENODEV;
972 
973 	/* XXX rcu acquire? */
974 	ret = mutex_lock_interruptible(&ctx->i915->drm.struct_mutex);
975 	if (ret)
976 		return ret;
977 
978 	vm = i915_vm_get(ctx->vm);
979 	mutex_unlock(&ctx->i915->drm.struct_mutex);
980 
981 	ret = mutex_lock_interruptible(&file_priv->vm_idr_lock);
982 	if (ret)
983 		goto err_put;
984 
985 	ret = idr_alloc(&file_priv->vm_idr, vm, 0, 0, GFP_KERNEL);
986 	GEM_BUG_ON(!ret);
987 	if (ret < 0)
988 		goto err_unlock;
989 
990 	i915_vm_get(vm);
991 
992 	args->size = 0;
993 	args->value = ret;
994 
995 	ret = 0;
996 err_unlock:
997 	mutex_unlock(&file_priv->vm_idr_lock);
998 err_put:
999 	i915_vm_put(vm);
1000 	return ret;
1001 }
1002 
1003 static void set_ppgtt_barrier(void *data)
1004 {
1005 	struct i915_address_space *old = data;
1006 
1007 	if (INTEL_GEN(old->i915) < 8)
1008 		gen6_ppgtt_unpin_all(i915_vm_to_ppgtt(old));
1009 
1010 	i915_vm_put(old);
1011 }
1012 
1013 static int emit_ppgtt_update(struct i915_request *rq, void *data)
1014 {
1015 	struct i915_address_space *vm = rq->hw_context->vm;
1016 	struct intel_engine_cs *engine = rq->engine;
1017 	u32 base = engine->mmio_base;
1018 	u32 *cs;
1019 	int i;
1020 
1021 	if (i915_vm_is_4lvl(vm)) {
1022 		struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1023 		const dma_addr_t pd_daddr = px_dma(ppgtt->pd);
1024 
1025 		cs = intel_ring_begin(rq, 6);
1026 		if (IS_ERR(cs))
1027 			return PTR_ERR(cs);
1028 
1029 		*cs++ = MI_LOAD_REGISTER_IMM(2);
1030 
1031 		*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0));
1032 		*cs++ = upper_32_bits(pd_daddr);
1033 		*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0));
1034 		*cs++ = lower_32_bits(pd_daddr);
1035 
1036 		*cs++ = MI_NOOP;
1037 		intel_ring_advance(rq, cs);
1038 	} else if (HAS_LOGICAL_RING_CONTEXTS(engine->i915)) {
1039 		struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1040 
1041 		cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2);
1042 		if (IS_ERR(cs))
1043 			return PTR_ERR(cs);
1044 
1045 		*cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES);
1046 		for (i = GEN8_3LVL_PDPES; i--; ) {
1047 			const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1048 
1049 			*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));
1050 			*cs++ = upper_32_bits(pd_daddr);
1051 			*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));
1052 			*cs++ = lower_32_bits(pd_daddr);
1053 		}
1054 		*cs++ = MI_NOOP;
1055 		intel_ring_advance(rq, cs);
1056 	} else {
1057 		/* ppGTT is not part of the legacy context image */
1058 		gen6_ppgtt_pin(i915_vm_to_ppgtt(vm));
1059 	}
1060 
1061 	return 0;
1062 }
1063 
1064 static bool skip_ppgtt_update(struct intel_context *ce, void *data)
1065 {
1066 	if (HAS_LOGICAL_RING_CONTEXTS(ce->engine->i915))
1067 		return !ce->state;
1068 	else
1069 		return !atomic_read(&ce->pin_count);
1070 }
1071 
1072 static int set_ppgtt(struct drm_i915_file_private *file_priv,
1073 		     struct i915_gem_context *ctx,
1074 		     struct drm_i915_gem_context_param *args)
1075 {
1076 	struct i915_address_space *vm, *old;
1077 	int err;
1078 
1079 	if (args->size)
1080 		return -EINVAL;
1081 
1082 	if (!ctx->vm)
1083 		return -ENODEV;
1084 
1085 	if (upper_32_bits(args->value))
1086 		return -ENOENT;
1087 
1088 	err = mutex_lock_interruptible(&file_priv->vm_idr_lock);
1089 	if (err)
1090 		return err;
1091 
1092 	vm = idr_find(&file_priv->vm_idr, args->value);
1093 	if (vm)
1094 		i915_vm_get(vm);
1095 	mutex_unlock(&file_priv->vm_idr_lock);
1096 	if (!vm)
1097 		return -ENOENT;
1098 
1099 	err = mutex_lock_interruptible(&ctx->i915->drm.struct_mutex);
1100 	if (err)
1101 		goto out;
1102 
1103 	if (vm == ctx->vm)
1104 		goto unlock;
1105 
1106 	/* Teardown the existing obj:vma cache, it will have to be rebuilt. */
1107 	mutex_lock(&ctx->mutex);
1108 	lut_close(ctx);
1109 	mutex_unlock(&ctx->mutex);
1110 
1111 	old = __set_ppgtt(ctx, vm);
1112 
1113 	/*
1114 	 * We need to flush any requests using the current ppgtt before
1115 	 * we release it as the requests do not hold a reference themselves,
1116 	 * only indirectly through the context.
1117 	 */
1118 	err = context_barrier_task(ctx, ALL_ENGINES,
1119 				   skip_ppgtt_update,
1120 				   emit_ppgtt_update,
1121 				   set_ppgtt_barrier,
1122 				   old);
1123 	if (err) {
1124 		i915_vm_put(__set_ppgtt(ctx, old));
1125 		i915_vm_put(old);
1126 	}
1127 
1128 unlock:
1129 	mutex_unlock(&ctx->i915->drm.struct_mutex);
1130 
1131 out:
1132 	i915_vm_put(vm);
1133 	return err;
1134 }
1135 
1136 static int gen8_emit_rpcs_config(struct i915_request *rq,
1137 				 struct intel_context *ce,
1138 				 struct intel_sseu sseu)
1139 {
1140 	u64 offset;
1141 	u32 *cs;
1142 
1143 	cs = intel_ring_begin(rq, 4);
1144 	if (IS_ERR(cs))
1145 		return PTR_ERR(cs);
1146 
1147 	offset = i915_ggtt_offset(ce->state) +
1148 		 LRC_STATE_PN * PAGE_SIZE +
1149 		 (CTX_R_PWR_CLK_STATE + 1) * 4;
1150 
1151 	*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1152 	*cs++ = lower_32_bits(offset);
1153 	*cs++ = upper_32_bits(offset);
1154 	*cs++ = intel_sseu_make_rpcs(rq->i915, &sseu);
1155 
1156 	intel_ring_advance(rq, cs);
1157 
1158 	return 0;
1159 }
1160 
1161 static int
1162 gen8_modify_rpcs(struct intel_context *ce, struct intel_sseu sseu)
1163 {
1164 	struct i915_request *rq;
1165 	int ret;
1166 
1167 	lockdep_assert_held(&ce->pin_mutex);
1168 
1169 	/*
1170 	 * If the context is not idle, we have to submit an ordered request to
1171 	 * modify its context image via the kernel context (writing to our own
1172 	 * image, or into the registers directory, does not stick). Pristine
1173 	 * and idle contexts will be configured on pinning.
1174 	 */
1175 	if (!intel_context_is_pinned(ce))
1176 		return 0;
1177 
1178 	rq = i915_request_create(ce->engine->kernel_context);
1179 	if (IS_ERR(rq))
1180 		return PTR_ERR(rq);
1181 
1182 	/* Serialise with the remote context */
1183 	ret = intel_context_prepare_remote_request(ce, rq);
1184 	if (ret == 0)
1185 		ret = gen8_emit_rpcs_config(rq, ce, sseu);
1186 
1187 	i915_request_add(rq);
1188 	return ret;
1189 }
1190 
1191 static int
1192 __intel_context_reconfigure_sseu(struct intel_context *ce,
1193 				 struct intel_sseu sseu)
1194 {
1195 	int ret;
1196 
1197 	GEM_BUG_ON(INTEL_GEN(ce->gem_context->i915) < 8);
1198 
1199 	ret = intel_context_lock_pinned(ce);
1200 	if (ret)
1201 		return ret;
1202 
1203 	/* Nothing to do if unmodified. */
1204 	if (!memcmp(&ce->sseu, &sseu, sizeof(sseu)))
1205 		goto unlock;
1206 
1207 	ret = gen8_modify_rpcs(ce, sseu);
1208 	if (!ret)
1209 		ce->sseu = sseu;
1210 
1211 unlock:
1212 	intel_context_unlock_pinned(ce);
1213 	return ret;
1214 }
1215 
1216 static int
1217 intel_context_reconfigure_sseu(struct intel_context *ce, struct intel_sseu sseu)
1218 {
1219 	struct drm_i915_private *i915 = ce->gem_context->i915;
1220 	int ret;
1221 
1222 	ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1223 	if (ret)
1224 		return ret;
1225 
1226 	ret = __intel_context_reconfigure_sseu(ce, sseu);
1227 
1228 	mutex_unlock(&i915->drm.struct_mutex);
1229 
1230 	return ret;
1231 }
1232 
1233 static int
1234 user_to_context_sseu(struct drm_i915_private *i915,
1235 		     const struct drm_i915_gem_context_param_sseu *user,
1236 		     struct intel_sseu *context)
1237 {
1238 	const struct sseu_dev_info *device = &RUNTIME_INFO(i915)->sseu;
1239 
1240 	/* No zeros in any field. */
1241 	if (!user->slice_mask || !user->subslice_mask ||
1242 	    !user->min_eus_per_subslice || !user->max_eus_per_subslice)
1243 		return -EINVAL;
1244 
1245 	/* Max > min. */
1246 	if (user->max_eus_per_subslice < user->min_eus_per_subslice)
1247 		return -EINVAL;
1248 
1249 	/*
1250 	 * Some future proofing on the types since the uAPI is wider than the
1251 	 * current internal implementation.
1252 	 */
1253 	if (overflows_type(user->slice_mask, context->slice_mask) ||
1254 	    overflows_type(user->subslice_mask, context->subslice_mask) ||
1255 	    overflows_type(user->min_eus_per_subslice,
1256 			   context->min_eus_per_subslice) ||
1257 	    overflows_type(user->max_eus_per_subslice,
1258 			   context->max_eus_per_subslice))
1259 		return -EINVAL;
1260 
1261 	/* Check validity against hardware. */
1262 	if (user->slice_mask & ~device->slice_mask)
1263 		return -EINVAL;
1264 
1265 	if (user->subslice_mask & ~device->subslice_mask[0])
1266 		return -EINVAL;
1267 
1268 	if (user->max_eus_per_subslice > device->max_eus_per_subslice)
1269 		return -EINVAL;
1270 
1271 	context->slice_mask = user->slice_mask;
1272 	context->subslice_mask = user->subslice_mask;
1273 	context->min_eus_per_subslice = user->min_eus_per_subslice;
1274 	context->max_eus_per_subslice = user->max_eus_per_subslice;
1275 
1276 	/* Part specific restrictions. */
1277 	if (IS_GEN(i915, 11)) {
1278 		unsigned int hw_s = hweight8(device->slice_mask);
1279 		unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
1280 		unsigned int req_s = hweight8(context->slice_mask);
1281 		unsigned int req_ss = hweight8(context->subslice_mask);
1282 
1283 		/*
1284 		 * Only full subslice enablement is possible if more than one
1285 		 * slice is turned on.
1286 		 */
1287 		if (req_s > 1 && req_ss != hw_ss_per_s)
1288 			return -EINVAL;
1289 
1290 		/*
1291 		 * If more than four (SScount bitfield limit) subslices are
1292 		 * requested then the number has to be even.
1293 		 */
1294 		if (req_ss > 4 && (req_ss & 1))
1295 			return -EINVAL;
1296 
1297 		/*
1298 		 * If only one slice is enabled and subslice count is below the
1299 		 * device full enablement, it must be at most half of the all
1300 		 * available subslices.
1301 		 */
1302 		if (req_s == 1 && req_ss < hw_ss_per_s &&
1303 		    req_ss > (hw_ss_per_s / 2))
1304 			return -EINVAL;
1305 
1306 		/* ABI restriction - VME use case only. */
1307 
1308 		/* All slices or one slice only. */
1309 		if (req_s != 1 && req_s != hw_s)
1310 			return -EINVAL;
1311 
1312 		/*
1313 		 * Half subslices or full enablement only when one slice is
1314 		 * enabled.
1315 		 */
1316 		if (req_s == 1 &&
1317 		    (req_ss != hw_ss_per_s && req_ss != (hw_ss_per_s / 2)))
1318 			return -EINVAL;
1319 
1320 		/* No EU configuration changes. */
1321 		if ((user->min_eus_per_subslice !=
1322 		     device->max_eus_per_subslice) ||
1323 		    (user->max_eus_per_subslice !=
1324 		     device->max_eus_per_subslice))
1325 			return -EINVAL;
1326 	}
1327 
1328 	return 0;
1329 }
1330 
1331 static int set_sseu(struct i915_gem_context *ctx,
1332 		    struct drm_i915_gem_context_param *args)
1333 {
1334 	struct drm_i915_private *i915 = ctx->i915;
1335 	struct drm_i915_gem_context_param_sseu user_sseu;
1336 	struct intel_context *ce;
1337 	struct intel_sseu sseu;
1338 	unsigned long lookup;
1339 	int ret;
1340 
1341 	if (args->size < sizeof(user_sseu))
1342 		return -EINVAL;
1343 
1344 	if (!IS_GEN(i915, 11))
1345 		return -ENODEV;
1346 
1347 	if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
1348 			   sizeof(user_sseu)))
1349 		return -EFAULT;
1350 
1351 	if (user_sseu.rsvd)
1352 		return -EINVAL;
1353 
1354 	if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
1355 		return -EINVAL;
1356 
1357 	lookup = 0;
1358 	if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
1359 		lookup |= LOOKUP_USER_INDEX;
1360 
1361 	ce = lookup_user_engine(ctx, lookup, &user_sseu.engine);
1362 	if (IS_ERR(ce))
1363 		return PTR_ERR(ce);
1364 
1365 	/* Only render engine supports RPCS configuration. */
1366 	if (ce->engine->class != RENDER_CLASS) {
1367 		ret = -ENODEV;
1368 		goto out_ce;
1369 	}
1370 
1371 	ret = user_to_context_sseu(i915, &user_sseu, &sseu);
1372 	if (ret)
1373 		goto out_ce;
1374 
1375 	ret = intel_context_reconfigure_sseu(ce, sseu);
1376 	if (ret)
1377 		goto out_ce;
1378 
1379 	args->size = sizeof(user_sseu);
1380 
1381 out_ce:
1382 	intel_context_put(ce);
1383 	return ret;
1384 }
1385 
1386 struct set_engines {
1387 	struct i915_gem_context *ctx;
1388 	struct i915_gem_engines *engines;
1389 };
1390 
1391 static int
1392 set_engines__load_balance(struct i915_user_extension __user *base, void *data)
1393 {
1394 	struct i915_context_engines_load_balance __user *ext =
1395 		container_of_user(base, typeof(*ext), base);
1396 	const struct set_engines *set = data;
1397 	struct intel_engine_cs *stack[16];
1398 	struct intel_engine_cs **siblings;
1399 	struct intel_context *ce;
1400 	u16 num_siblings, idx;
1401 	unsigned int n;
1402 	int err;
1403 
1404 	if (!HAS_EXECLISTS(set->ctx->i915))
1405 		return -ENODEV;
1406 
1407 	if (USES_GUC_SUBMISSION(set->ctx->i915))
1408 		return -ENODEV; /* not implement yet */
1409 
1410 	if (get_user(idx, &ext->engine_index))
1411 		return -EFAULT;
1412 
1413 	if (idx >= set->engines->num_engines) {
1414 		DRM_DEBUG("Invalid placement value, %d >= %d\n",
1415 			  idx, set->engines->num_engines);
1416 		return -EINVAL;
1417 	}
1418 
1419 	idx = array_index_nospec(idx, set->engines->num_engines);
1420 	if (set->engines->engines[idx]) {
1421 		DRM_DEBUG("Invalid placement[%d], already occupied\n", idx);
1422 		return -EEXIST;
1423 	}
1424 
1425 	if (get_user(num_siblings, &ext->num_siblings))
1426 		return -EFAULT;
1427 
1428 	err = check_user_mbz(&ext->flags);
1429 	if (err)
1430 		return err;
1431 
1432 	err = check_user_mbz(&ext->mbz64);
1433 	if (err)
1434 		return err;
1435 
1436 	siblings = stack;
1437 	if (num_siblings > ARRAY_SIZE(stack)) {
1438 		siblings = kmalloc_array(num_siblings,
1439 					 sizeof(*siblings),
1440 					 GFP_KERNEL);
1441 		if (!siblings)
1442 			return -ENOMEM;
1443 	}
1444 
1445 	for (n = 0; n < num_siblings; n++) {
1446 		struct i915_engine_class_instance ci;
1447 
1448 		if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
1449 			err = -EFAULT;
1450 			goto out_siblings;
1451 		}
1452 
1453 		siblings[n] = intel_engine_lookup_user(set->ctx->i915,
1454 						       ci.engine_class,
1455 						       ci.engine_instance);
1456 		if (!siblings[n]) {
1457 			DRM_DEBUG("Invalid sibling[%d]: { class:%d, inst:%d }\n",
1458 				  n, ci.engine_class, ci.engine_instance);
1459 			err = -EINVAL;
1460 			goto out_siblings;
1461 		}
1462 	}
1463 
1464 	ce = intel_execlists_create_virtual(set->ctx, siblings, n);
1465 	if (IS_ERR(ce)) {
1466 		err = PTR_ERR(ce);
1467 		goto out_siblings;
1468 	}
1469 
1470 	if (cmpxchg(&set->engines->engines[idx], NULL, ce)) {
1471 		intel_context_put(ce);
1472 		err = -EEXIST;
1473 		goto out_siblings;
1474 	}
1475 
1476 out_siblings:
1477 	if (siblings != stack)
1478 		kfree(siblings);
1479 
1480 	return err;
1481 }
1482 
1483 static int
1484 set_engines__bond(struct i915_user_extension __user *base, void *data)
1485 {
1486 	struct i915_context_engines_bond __user *ext =
1487 		container_of_user(base, typeof(*ext), base);
1488 	const struct set_engines *set = data;
1489 	struct i915_engine_class_instance ci;
1490 	struct intel_engine_cs *virtual;
1491 	struct intel_engine_cs *master;
1492 	u16 idx, num_bonds;
1493 	int err, n;
1494 
1495 	if (get_user(idx, &ext->virtual_index))
1496 		return -EFAULT;
1497 
1498 	if (idx >= set->engines->num_engines) {
1499 		DRM_DEBUG("Invalid index for virtual engine: %d >= %d\n",
1500 			  idx, set->engines->num_engines);
1501 		return -EINVAL;
1502 	}
1503 
1504 	idx = array_index_nospec(idx, set->engines->num_engines);
1505 	if (!set->engines->engines[idx]) {
1506 		DRM_DEBUG("Invalid engine at %d\n", idx);
1507 		return -EINVAL;
1508 	}
1509 	virtual = set->engines->engines[idx]->engine;
1510 
1511 	err = check_user_mbz(&ext->flags);
1512 	if (err)
1513 		return err;
1514 
1515 	for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
1516 		err = check_user_mbz(&ext->mbz64[n]);
1517 		if (err)
1518 			return err;
1519 	}
1520 
1521 	if (copy_from_user(&ci, &ext->master, sizeof(ci)))
1522 		return -EFAULT;
1523 
1524 	master = intel_engine_lookup_user(set->ctx->i915,
1525 					  ci.engine_class, ci.engine_instance);
1526 	if (!master) {
1527 		DRM_DEBUG("Unrecognised master engine: { class:%u, instance:%u }\n",
1528 			  ci.engine_class, ci.engine_instance);
1529 		return -EINVAL;
1530 	}
1531 
1532 	if (get_user(num_bonds, &ext->num_bonds))
1533 		return -EFAULT;
1534 
1535 	for (n = 0; n < num_bonds; n++) {
1536 		struct intel_engine_cs *bond;
1537 
1538 		if (copy_from_user(&ci, &ext->engines[n], sizeof(ci)))
1539 			return -EFAULT;
1540 
1541 		bond = intel_engine_lookup_user(set->ctx->i915,
1542 						ci.engine_class,
1543 						ci.engine_instance);
1544 		if (!bond) {
1545 			DRM_DEBUG("Unrecognised engine[%d] for bonding: { class:%d, instance: %d }\n",
1546 				  n, ci.engine_class, ci.engine_instance);
1547 			return -EINVAL;
1548 		}
1549 
1550 		/*
1551 		 * A non-virtual engine has no siblings to choose between; and
1552 		 * a submit fence will always be directed to the one engine.
1553 		 */
1554 		if (intel_engine_is_virtual(virtual)) {
1555 			err = intel_virtual_engine_attach_bond(virtual,
1556 							       master,
1557 							       bond);
1558 			if (err)
1559 				return err;
1560 		}
1561 	}
1562 
1563 	return 0;
1564 }
1565 
1566 static const i915_user_extension_fn set_engines__extensions[] = {
1567 	[I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE] = set_engines__load_balance,
1568 	[I915_CONTEXT_ENGINES_EXT_BOND] = set_engines__bond,
1569 };
1570 
1571 static int
1572 set_engines(struct i915_gem_context *ctx,
1573 	    const struct drm_i915_gem_context_param *args)
1574 {
1575 	struct i915_context_param_engines __user *user =
1576 		u64_to_user_ptr(args->value);
1577 	struct set_engines set = { .ctx = ctx };
1578 	unsigned int num_engines, n;
1579 	u64 extensions;
1580 	int err;
1581 
1582 	if (!args->size) { /* switch back to legacy user_ring_map */
1583 		if (!i915_gem_context_user_engines(ctx))
1584 			return 0;
1585 
1586 		set.engines = default_engines(ctx);
1587 		if (IS_ERR(set.engines))
1588 			return PTR_ERR(set.engines);
1589 
1590 		goto replace;
1591 	}
1592 
1593 	BUILD_BUG_ON(!IS_ALIGNED(sizeof(*user), sizeof(*user->engines)));
1594 	if (args->size < sizeof(*user) ||
1595 	    !IS_ALIGNED(args->size, sizeof(*user->engines))) {
1596 		DRM_DEBUG("Invalid size for engine array: %d\n",
1597 			  args->size);
1598 		return -EINVAL;
1599 	}
1600 
1601 	/*
1602 	 * Note that I915_EXEC_RING_MASK limits execbuf to only using the
1603 	 * first 64 engines defined here.
1604 	 */
1605 	num_engines = (args->size - sizeof(*user)) / sizeof(*user->engines);
1606 
1607 	set.engines = kmalloc(struct_size(set.engines, engines, num_engines),
1608 			      GFP_KERNEL);
1609 	if (!set.engines)
1610 		return -ENOMEM;
1611 
1612 	init_rcu_head(&set.engines->rcu);
1613 	for (n = 0; n < num_engines; n++) {
1614 		struct i915_engine_class_instance ci;
1615 		struct intel_engine_cs *engine;
1616 
1617 		if (copy_from_user(&ci, &user->engines[n], sizeof(ci))) {
1618 			__free_engines(set.engines, n);
1619 			return -EFAULT;
1620 		}
1621 
1622 		if (ci.engine_class == (u16)I915_ENGINE_CLASS_INVALID &&
1623 		    ci.engine_instance == (u16)I915_ENGINE_CLASS_INVALID_NONE) {
1624 			set.engines->engines[n] = NULL;
1625 			continue;
1626 		}
1627 
1628 		engine = intel_engine_lookup_user(ctx->i915,
1629 						  ci.engine_class,
1630 						  ci.engine_instance);
1631 		if (!engine) {
1632 			DRM_DEBUG("Invalid engine[%d]: { class:%d, instance:%d }\n",
1633 				  n, ci.engine_class, ci.engine_instance);
1634 			__free_engines(set.engines, n);
1635 			return -ENOENT;
1636 		}
1637 
1638 		set.engines->engines[n] = intel_context_create(ctx, engine);
1639 		if (!set.engines->engines[n]) {
1640 			__free_engines(set.engines, n);
1641 			return -ENOMEM;
1642 		}
1643 	}
1644 	set.engines->num_engines = num_engines;
1645 
1646 	err = -EFAULT;
1647 	if (!get_user(extensions, &user->extensions))
1648 		err = i915_user_extensions(u64_to_user_ptr(extensions),
1649 					   set_engines__extensions,
1650 					   ARRAY_SIZE(set_engines__extensions),
1651 					   &set);
1652 	if (err) {
1653 		free_engines(set.engines);
1654 		return err;
1655 	}
1656 
1657 replace:
1658 	mutex_lock(&ctx->engines_mutex);
1659 	if (args->size)
1660 		i915_gem_context_set_user_engines(ctx);
1661 	else
1662 		i915_gem_context_clear_user_engines(ctx);
1663 	rcu_swap_protected(ctx->engines, set.engines, 1);
1664 	mutex_unlock(&ctx->engines_mutex);
1665 
1666 	call_rcu(&set.engines->rcu, free_engines_rcu);
1667 
1668 	return 0;
1669 }
1670 
1671 static struct i915_gem_engines *
1672 __copy_engines(struct i915_gem_engines *e)
1673 {
1674 	struct i915_gem_engines *copy;
1675 	unsigned int n;
1676 
1677 	copy = kmalloc(struct_size(e, engines, e->num_engines), GFP_KERNEL);
1678 	if (!copy)
1679 		return ERR_PTR(-ENOMEM);
1680 
1681 	init_rcu_head(&copy->rcu);
1682 	for (n = 0; n < e->num_engines; n++) {
1683 		if (e->engines[n])
1684 			copy->engines[n] = intel_context_get(e->engines[n]);
1685 		else
1686 			copy->engines[n] = NULL;
1687 	}
1688 	copy->num_engines = n;
1689 
1690 	return copy;
1691 }
1692 
1693 static int
1694 get_engines(struct i915_gem_context *ctx,
1695 	    struct drm_i915_gem_context_param *args)
1696 {
1697 	struct i915_context_param_engines __user *user;
1698 	struct i915_gem_engines *e;
1699 	size_t n, count, size;
1700 	int err = 0;
1701 
1702 	err = mutex_lock_interruptible(&ctx->engines_mutex);
1703 	if (err)
1704 		return err;
1705 
1706 	e = NULL;
1707 	if (i915_gem_context_user_engines(ctx))
1708 		e = __copy_engines(i915_gem_context_engines(ctx));
1709 	mutex_unlock(&ctx->engines_mutex);
1710 	if (IS_ERR_OR_NULL(e)) {
1711 		args->size = 0;
1712 		return PTR_ERR_OR_ZERO(e);
1713 	}
1714 
1715 	count = e->num_engines;
1716 
1717 	/* Be paranoid in case we have an impedance mismatch */
1718 	if (!check_struct_size(user, engines, count, &size)) {
1719 		err = -EINVAL;
1720 		goto err_free;
1721 	}
1722 	if (overflows_type(size, args->size)) {
1723 		err = -EINVAL;
1724 		goto err_free;
1725 	}
1726 
1727 	if (!args->size) {
1728 		args->size = size;
1729 		goto err_free;
1730 	}
1731 
1732 	if (args->size < size) {
1733 		err = -EINVAL;
1734 		goto err_free;
1735 	}
1736 
1737 	user = u64_to_user_ptr(args->value);
1738 	if (!access_ok(user, size)) {
1739 		err = -EFAULT;
1740 		goto err_free;
1741 	}
1742 
1743 	if (put_user(0, &user->extensions)) {
1744 		err = -EFAULT;
1745 		goto err_free;
1746 	}
1747 
1748 	for (n = 0; n < count; n++) {
1749 		struct i915_engine_class_instance ci = {
1750 			.engine_class = I915_ENGINE_CLASS_INVALID,
1751 			.engine_instance = I915_ENGINE_CLASS_INVALID_NONE,
1752 		};
1753 
1754 		if (e->engines[n]) {
1755 			ci.engine_class = e->engines[n]->engine->uabi_class;
1756 			ci.engine_instance = e->engines[n]->engine->instance;
1757 		}
1758 
1759 		if (copy_to_user(&user->engines[n], &ci, sizeof(ci))) {
1760 			err = -EFAULT;
1761 			goto err_free;
1762 		}
1763 	}
1764 
1765 	args->size = size;
1766 
1767 err_free:
1768 	free_engines(e);
1769 	return err;
1770 }
1771 
1772 static int ctx_setparam(struct drm_i915_file_private *fpriv,
1773 			struct i915_gem_context *ctx,
1774 			struct drm_i915_gem_context_param *args)
1775 {
1776 	int ret = 0;
1777 
1778 	switch (args->param) {
1779 	case I915_CONTEXT_PARAM_NO_ZEROMAP:
1780 		if (args->size)
1781 			ret = -EINVAL;
1782 		else if (args->value)
1783 			set_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags);
1784 		else
1785 			clear_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags);
1786 		break;
1787 
1788 	case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1789 		if (args->size)
1790 			ret = -EINVAL;
1791 		else if (args->value)
1792 			i915_gem_context_set_no_error_capture(ctx);
1793 		else
1794 			i915_gem_context_clear_no_error_capture(ctx);
1795 		break;
1796 
1797 	case I915_CONTEXT_PARAM_BANNABLE:
1798 		if (args->size)
1799 			ret = -EINVAL;
1800 		else if (!capable(CAP_SYS_ADMIN) && !args->value)
1801 			ret = -EPERM;
1802 		else if (args->value)
1803 			i915_gem_context_set_bannable(ctx);
1804 		else
1805 			i915_gem_context_clear_bannable(ctx);
1806 		break;
1807 
1808 	case I915_CONTEXT_PARAM_RECOVERABLE:
1809 		if (args->size)
1810 			ret = -EINVAL;
1811 		else if (args->value)
1812 			i915_gem_context_set_recoverable(ctx);
1813 		else
1814 			i915_gem_context_clear_recoverable(ctx);
1815 		break;
1816 
1817 	case I915_CONTEXT_PARAM_PRIORITY:
1818 		{
1819 			s64 priority = args->value;
1820 
1821 			if (args->size)
1822 				ret = -EINVAL;
1823 			else if (!(ctx->i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY))
1824 				ret = -ENODEV;
1825 			else if (priority > I915_CONTEXT_MAX_USER_PRIORITY ||
1826 				 priority < I915_CONTEXT_MIN_USER_PRIORITY)
1827 				ret = -EINVAL;
1828 			else if (priority > I915_CONTEXT_DEFAULT_PRIORITY &&
1829 				 !capable(CAP_SYS_NICE))
1830 				ret = -EPERM;
1831 			else
1832 				ctx->sched.priority =
1833 					I915_USER_PRIORITY(priority);
1834 		}
1835 		break;
1836 
1837 	case I915_CONTEXT_PARAM_SSEU:
1838 		ret = set_sseu(ctx, args);
1839 		break;
1840 
1841 	case I915_CONTEXT_PARAM_VM:
1842 		ret = set_ppgtt(fpriv, ctx, args);
1843 		break;
1844 
1845 	case I915_CONTEXT_PARAM_ENGINES:
1846 		ret = set_engines(ctx, args);
1847 		break;
1848 
1849 	case I915_CONTEXT_PARAM_BAN_PERIOD:
1850 	default:
1851 		ret = -EINVAL;
1852 		break;
1853 	}
1854 
1855 	return ret;
1856 }
1857 
1858 struct create_ext {
1859 	struct i915_gem_context *ctx;
1860 	struct drm_i915_file_private *fpriv;
1861 };
1862 
1863 static int create_setparam(struct i915_user_extension __user *ext, void *data)
1864 {
1865 	struct drm_i915_gem_context_create_ext_setparam local;
1866 	const struct create_ext *arg = data;
1867 
1868 	if (copy_from_user(&local, ext, sizeof(local)))
1869 		return -EFAULT;
1870 
1871 	if (local.param.ctx_id)
1872 		return -EINVAL;
1873 
1874 	return ctx_setparam(arg->fpriv, arg->ctx, &local.param);
1875 }
1876 
1877 static int clone_engines(struct i915_gem_context *dst,
1878 			 struct i915_gem_context *src)
1879 {
1880 	struct i915_gem_engines *e = i915_gem_context_lock_engines(src);
1881 	struct i915_gem_engines *clone;
1882 	bool user_engines;
1883 	unsigned long n;
1884 
1885 	clone = kmalloc(struct_size(e, engines, e->num_engines), GFP_KERNEL);
1886 	if (!clone)
1887 		goto err_unlock;
1888 
1889 	init_rcu_head(&clone->rcu);
1890 	for (n = 0; n < e->num_engines; n++) {
1891 		struct intel_engine_cs *engine;
1892 
1893 		if (!e->engines[n]) {
1894 			clone->engines[n] = NULL;
1895 			continue;
1896 		}
1897 		engine = e->engines[n]->engine;
1898 
1899 		/*
1900 		 * Virtual engines are singletons; they can only exist
1901 		 * inside a single context, because they embed their
1902 		 * HW context... As each virtual context implies a single
1903 		 * timeline (each engine can only dequeue a single request
1904 		 * at any time), it would be surprising for two contexts
1905 		 * to use the same engine. So let's create a copy of
1906 		 * the virtual engine instead.
1907 		 */
1908 		if (intel_engine_is_virtual(engine))
1909 			clone->engines[n] =
1910 				intel_execlists_clone_virtual(dst, engine);
1911 		else
1912 			clone->engines[n] = intel_context_create(dst, engine);
1913 		if (IS_ERR_OR_NULL(clone->engines[n])) {
1914 			__free_engines(clone, n);
1915 			goto err_unlock;
1916 		}
1917 	}
1918 	clone->num_engines = n;
1919 
1920 	user_engines = i915_gem_context_user_engines(src);
1921 	i915_gem_context_unlock_engines(src);
1922 
1923 	free_engines(dst->engines);
1924 	RCU_INIT_POINTER(dst->engines, clone);
1925 	if (user_engines)
1926 		i915_gem_context_set_user_engines(dst);
1927 	else
1928 		i915_gem_context_clear_user_engines(dst);
1929 	return 0;
1930 
1931 err_unlock:
1932 	i915_gem_context_unlock_engines(src);
1933 	return -ENOMEM;
1934 }
1935 
1936 static int clone_flags(struct i915_gem_context *dst,
1937 		       struct i915_gem_context *src)
1938 {
1939 	dst->user_flags = src->user_flags;
1940 	return 0;
1941 }
1942 
1943 static int clone_schedattr(struct i915_gem_context *dst,
1944 			   struct i915_gem_context *src)
1945 {
1946 	dst->sched = src->sched;
1947 	return 0;
1948 }
1949 
1950 static int clone_sseu(struct i915_gem_context *dst,
1951 		      struct i915_gem_context *src)
1952 {
1953 	struct i915_gem_engines *e = i915_gem_context_lock_engines(src);
1954 	struct i915_gem_engines *clone;
1955 	unsigned long n;
1956 	int err;
1957 
1958 	clone = dst->engines; /* no locking required; sole access */
1959 	if (e->num_engines != clone->num_engines) {
1960 		err = -EINVAL;
1961 		goto unlock;
1962 	}
1963 
1964 	for (n = 0; n < e->num_engines; n++) {
1965 		struct intel_context *ce = e->engines[n];
1966 
1967 		if (clone->engines[n]->engine->class != ce->engine->class) {
1968 			/* Must have compatible engine maps! */
1969 			err = -EINVAL;
1970 			goto unlock;
1971 		}
1972 
1973 		/* serialises with set_sseu */
1974 		err = intel_context_lock_pinned(ce);
1975 		if (err)
1976 			goto unlock;
1977 
1978 		clone->engines[n]->sseu = ce->sseu;
1979 		intel_context_unlock_pinned(ce);
1980 	}
1981 
1982 	err = 0;
1983 unlock:
1984 	i915_gem_context_unlock_engines(src);
1985 	return err;
1986 }
1987 
1988 static int clone_timeline(struct i915_gem_context *dst,
1989 			  struct i915_gem_context *src)
1990 {
1991 	if (src->timeline) {
1992 		GEM_BUG_ON(src->timeline == dst->timeline);
1993 
1994 		if (dst->timeline)
1995 			intel_timeline_put(dst->timeline);
1996 		dst->timeline = intel_timeline_get(src->timeline);
1997 	}
1998 
1999 	return 0;
2000 }
2001 
2002 static int clone_vm(struct i915_gem_context *dst,
2003 		    struct i915_gem_context *src)
2004 {
2005 	struct i915_address_space *vm;
2006 
2007 	rcu_read_lock();
2008 	do {
2009 		vm = READ_ONCE(src->vm);
2010 		if (!vm)
2011 			break;
2012 
2013 		if (!kref_get_unless_zero(&vm->ref))
2014 			continue;
2015 
2016 		/*
2017 		 * This ppgtt may have be reallocated between
2018 		 * the read and the kref, and reassigned to a third
2019 		 * context. In order to avoid inadvertent sharing
2020 		 * of this ppgtt with that third context (and not
2021 		 * src), we have to confirm that we have the same
2022 		 * ppgtt after passing through the strong memory
2023 		 * barrier implied by a successful
2024 		 * kref_get_unless_zero().
2025 		 *
2026 		 * Once we have acquired the current ppgtt of src,
2027 		 * we no longer care if it is released from src, as
2028 		 * it cannot be reallocated elsewhere.
2029 		 */
2030 
2031 		if (vm == READ_ONCE(src->vm))
2032 			break;
2033 
2034 		i915_vm_put(vm);
2035 	} while (1);
2036 	rcu_read_unlock();
2037 
2038 	if (vm) {
2039 		__assign_ppgtt(dst, vm);
2040 		i915_vm_put(vm);
2041 	}
2042 
2043 	return 0;
2044 }
2045 
2046 static int create_clone(struct i915_user_extension __user *ext, void *data)
2047 {
2048 	static int (* const fn[])(struct i915_gem_context *dst,
2049 				  struct i915_gem_context *src) = {
2050 #define MAP(x, y) [ilog2(I915_CONTEXT_CLONE_##x)] = y
2051 		MAP(ENGINES, clone_engines),
2052 		MAP(FLAGS, clone_flags),
2053 		MAP(SCHEDATTR, clone_schedattr),
2054 		MAP(SSEU, clone_sseu),
2055 		MAP(TIMELINE, clone_timeline),
2056 		MAP(VM, clone_vm),
2057 #undef MAP
2058 	};
2059 	struct drm_i915_gem_context_create_ext_clone local;
2060 	const struct create_ext *arg = data;
2061 	struct i915_gem_context *dst = arg->ctx;
2062 	struct i915_gem_context *src;
2063 	int err, bit;
2064 
2065 	if (copy_from_user(&local, ext, sizeof(local)))
2066 		return -EFAULT;
2067 
2068 	BUILD_BUG_ON(GENMASK(BITS_PER_TYPE(local.flags) - 1, ARRAY_SIZE(fn)) !=
2069 		     I915_CONTEXT_CLONE_UNKNOWN);
2070 
2071 	if (local.flags & I915_CONTEXT_CLONE_UNKNOWN)
2072 		return -EINVAL;
2073 
2074 	if (local.rsvd)
2075 		return -EINVAL;
2076 
2077 	rcu_read_lock();
2078 	src = __i915_gem_context_lookup_rcu(arg->fpriv, local.clone_id);
2079 	rcu_read_unlock();
2080 	if (!src)
2081 		return -ENOENT;
2082 
2083 	GEM_BUG_ON(src == dst);
2084 
2085 	for (bit = 0; bit < ARRAY_SIZE(fn); bit++) {
2086 		if (!(local.flags & BIT(bit)))
2087 			continue;
2088 
2089 		err = fn[bit](dst, src);
2090 		if (err)
2091 			return err;
2092 	}
2093 
2094 	return 0;
2095 }
2096 
2097 static const i915_user_extension_fn create_extensions[] = {
2098 	[I915_CONTEXT_CREATE_EXT_SETPARAM] = create_setparam,
2099 	[I915_CONTEXT_CREATE_EXT_CLONE] = create_clone,
2100 };
2101 
2102 static bool client_is_banned(struct drm_i915_file_private *file_priv)
2103 {
2104 	return atomic_read(&file_priv->ban_score) >= I915_CLIENT_SCORE_BANNED;
2105 }
2106 
2107 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2108 				  struct drm_file *file)
2109 {
2110 	struct drm_i915_private *i915 = to_i915(dev);
2111 	struct drm_i915_gem_context_create_ext *args = data;
2112 	struct create_ext ext_data;
2113 	int ret;
2114 
2115 	if (!DRIVER_CAPS(i915)->has_logical_contexts)
2116 		return -ENODEV;
2117 
2118 	if (args->flags & I915_CONTEXT_CREATE_FLAGS_UNKNOWN)
2119 		return -EINVAL;
2120 
2121 	ret = intel_gt_terminally_wedged(&i915->gt);
2122 	if (ret)
2123 		return ret;
2124 
2125 	ext_data.fpriv = file->driver_priv;
2126 	if (client_is_banned(ext_data.fpriv)) {
2127 		DRM_DEBUG("client %s[%d] banned from creating ctx\n",
2128 			  current->comm,
2129 			  pid_nr(get_task_pid(current, PIDTYPE_PID)));
2130 		return -EIO;
2131 	}
2132 
2133 	ret = i915_mutex_lock_interruptible(dev);
2134 	if (ret)
2135 		return ret;
2136 
2137 	ext_data.ctx = i915_gem_create_context(i915, args->flags);
2138 	mutex_unlock(&dev->struct_mutex);
2139 	if (IS_ERR(ext_data.ctx))
2140 		return PTR_ERR(ext_data.ctx);
2141 
2142 	if (args->flags & I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS) {
2143 		ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
2144 					   create_extensions,
2145 					   ARRAY_SIZE(create_extensions),
2146 					   &ext_data);
2147 		if (ret)
2148 			goto err_ctx;
2149 	}
2150 
2151 	ret = gem_context_register(ext_data.ctx, ext_data.fpriv);
2152 	if (ret < 0)
2153 		goto err_ctx;
2154 
2155 	args->ctx_id = ret;
2156 	DRM_DEBUG("HW context %d created\n", args->ctx_id);
2157 
2158 	return 0;
2159 
2160 err_ctx:
2161 	context_close(ext_data.ctx);
2162 	return ret;
2163 }
2164 
2165 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2166 				   struct drm_file *file)
2167 {
2168 	struct drm_i915_gem_context_destroy *args = data;
2169 	struct drm_i915_file_private *file_priv = file->driver_priv;
2170 	struct i915_gem_context *ctx;
2171 
2172 	if (args->pad != 0)
2173 		return -EINVAL;
2174 
2175 	if (!args->ctx_id)
2176 		return -ENOENT;
2177 
2178 	if (mutex_lock_interruptible(&file_priv->context_idr_lock))
2179 		return -EINTR;
2180 
2181 	ctx = idr_remove(&file_priv->context_idr, args->ctx_id);
2182 	mutex_unlock(&file_priv->context_idr_lock);
2183 	if (!ctx)
2184 		return -ENOENT;
2185 
2186 	context_close(ctx);
2187 	return 0;
2188 }
2189 
2190 static int get_sseu(struct i915_gem_context *ctx,
2191 		    struct drm_i915_gem_context_param *args)
2192 {
2193 	struct drm_i915_gem_context_param_sseu user_sseu;
2194 	struct intel_context *ce;
2195 	unsigned long lookup;
2196 	int err;
2197 
2198 	if (args->size == 0)
2199 		goto out;
2200 	else if (args->size < sizeof(user_sseu))
2201 		return -EINVAL;
2202 
2203 	if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
2204 			   sizeof(user_sseu)))
2205 		return -EFAULT;
2206 
2207 	if (user_sseu.rsvd)
2208 		return -EINVAL;
2209 
2210 	if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
2211 		return -EINVAL;
2212 
2213 	lookup = 0;
2214 	if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
2215 		lookup |= LOOKUP_USER_INDEX;
2216 
2217 	ce = lookup_user_engine(ctx, lookup, &user_sseu.engine);
2218 	if (IS_ERR(ce))
2219 		return PTR_ERR(ce);
2220 
2221 	err = intel_context_lock_pinned(ce); /* serialises with set_sseu */
2222 	if (err) {
2223 		intel_context_put(ce);
2224 		return err;
2225 	}
2226 
2227 	user_sseu.slice_mask = ce->sseu.slice_mask;
2228 	user_sseu.subslice_mask = ce->sseu.subslice_mask;
2229 	user_sseu.min_eus_per_subslice = ce->sseu.min_eus_per_subslice;
2230 	user_sseu.max_eus_per_subslice = ce->sseu.max_eus_per_subslice;
2231 
2232 	intel_context_unlock_pinned(ce);
2233 	intel_context_put(ce);
2234 
2235 	if (copy_to_user(u64_to_user_ptr(args->value), &user_sseu,
2236 			 sizeof(user_sseu)))
2237 		return -EFAULT;
2238 
2239 out:
2240 	args->size = sizeof(user_sseu);
2241 
2242 	return 0;
2243 }
2244 
2245 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
2246 				    struct drm_file *file)
2247 {
2248 	struct drm_i915_file_private *file_priv = file->driver_priv;
2249 	struct drm_i915_gem_context_param *args = data;
2250 	struct i915_gem_context *ctx;
2251 	int ret = 0;
2252 
2253 	ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
2254 	if (!ctx)
2255 		return -ENOENT;
2256 
2257 	switch (args->param) {
2258 	case I915_CONTEXT_PARAM_NO_ZEROMAP:
2259 		args->size = 0;
2260 		args->value = test_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags);
2261 		break;
2262 
2263 	case I915_CONTEXT_PARAM_GTT_SIZE:
2264 		args->size = 0;
2265 		if (ctx->vm)
2266 			args->value = ctx->vm->total;
2267 		else if (to_i915(dev)->ggtt.alias)
2268 			args->value = to_i915(dev)->ggtt.alias->vm.total;
2269 		else
2270 			args->value = to_i915(dev)->ggtt.vm.total;
2271 		break;
2272 
2273 	case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
2274 		args->size = 0;
2275 		args->value = i915_gem_context_no_error_capture(ctx);
2276 		break;
2277 
2278 	case I915_CONTEXT_PARAM_BANNABLE:
2279 		args->size = 0;
2280 		args->value = i915_gem_context_is_bannable(ctx);
2281 		break;
2282 
2283 	case I915_CONTEXT_PARAM_RECOVERABLE:
2284 		args->size = 0;
2285 		args->value = i915_gem_context_is_recoverable(ctx);
2286 		break;
2287 
2288 	case I915_CONTEXT_PARAM_PRIORITY:
2289 		args->size = 0;
2290 		args->value = ctx->sched.priority >> I915_USER_PRIORITY_SHIFT;
2291 		break;
2292 
2293 	case I915_CONTEXT_PARAM_SSEU:
2294 		ret = get_sseu(ctx, args);
2295 		break;
2296 
2297 	case I915_CONTEXT_PARAM_VM:
2298 		ret = get_ppgtt(file_priv, ctx, args);
2299 		break;
2300 
2301 	case I915_CONTEXT_PARAM_ENGINES:
2302 		ret = get_engines(ctx, args);
2303 		break;
2304 
2305 	case I915_CONTEXT_PARAM_BAN_PERIOD:
2306 	default:
2307 		ret = -EINVAL;
2308 		break;
2309 	}
2310 
2311 	i915_gem_context_put(ctx);
2312 	return ret;
2313 }
2314 
2315 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
2316 				    struct drm_file *file)
2317 {
2318 	struct drm_i915_file_private *file_priv = file->driver_priv;
2319 	struct drm_i915_gem_context_param *args = data;
2320 	struct i915_gem_context *ctx;
2321 	int ret;
2322 
2323 	ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
2324 	if (!ctx)
2325 		return -ENOENT;
2326 
2327 	ret = ctx_setparam(file_priv, ctx, args);
2328 
2329 	i915_gem_context_put(ctx);
2330 	return ret;
2331 }
2332 
2333 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
2334 				       void *data, struct drm_file *file)
2335 {
2336 	struct drm_i915_private *dev_priv = to_i915(dev);
2337 	struct drm_i915_reset_stats *args = data;
2338 	struct i915_gem_context *ctx;
2339 	int ret;
2340 
2341 	if (args->flags || args->pad)
2342 		return -EINVAL;
2343 
2344 	ret = -ENOENT;
2345 	rcu_read_lock();
2346 	ctx = __i915_gem_context_lookup_rcu(file->driver_priv, args->ctx_id);
2347 	if (!ctx)
2348 		goto out;
2349 
2350 	/*
2351 	 * We opt for unserialised reads here. This may result in tearing
2352 	 * in the extremely unlikely event of a GPU hang on this context
2353 	 * as we are querying them. If we need that extra layer of protection,
2354 	 * we should wrap the hangstats with a seqlock.
2355 	 */
2356 
2357 	if (capable(CAP_SYS_ADMIN))
2358 		args->reset_count = i915_reset_count(&dev_priv->gpu_error);
2359 	else
2360 		args->reset_count = 0;
2361 
2362 	args->batch_active = atomic_read(&ctx->guilty_count);
2363 	args->batch_pending = atomic_read(&ctx->active_count);
2364 
2365 	ret = 0;
2366 out:
2367 	rcu_read_unlock();
2368 	return ret;
2369 }
2370 
2371 int __i915_gem_context_pin_hw_id(struct i915_gem_context *ctx)
2372 {
2373 	struct drm_i915_private *i915 = ctx->i915;
2374 	int err = 0;
2375 
2376 	mutex_lock(&i915->contexts.mutex);
2377 
2378 	GEM_BUG_ON(i915_gem_context_is_closed(ctx));
2379 
2380 	if (list_empty(&ctx->hw_id_link)) {
2381 		GEM_BUG_ON(atomic_read(&ctx->hw_id_pin_count));
2382 
2383 		err = assign_hw_id(i915, &ctx->hw_id);
2384 		if (err)
2385 			goto out_unlock;
2386 
2387 		list_add_tail(&ctx->hw_id_link, &i915->contexts.hw_id_list);
2388 	}
2389 
2390 	GEM_BUG_ON(atomic_read(&ctx->hw_id_pin_count) == ~0u);
2391 	atomic_inc(&ctx->hw_id_pin_count);
2392 
2393 out_unlock:
2394 	mutex_unlock(&i915->contexts.mutex);
2395 	return err;
2396 }
2397 
2398 /* GEM context-engines iterator: for_each_gem_engine() */
2399 struct intel_context *
2400 i915_gem_engines_iter_next(struct i915_gem_engines_iter *it)
2401 {
2402 	const struct i915_gem_engines *e = it->engines;
2403 	struct intel_context *ctx;
2404 
2405 	do {
2406 		if (it->idx >= e->num_engines)
2407 			return NULL;
2408 
2409 		ctx = e->engines[it->idx++];
2410 	} while (!ctx);
2411 
2412 	return ctx;
2413 }
2414 
2415 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2416 #include "selftests/mock_context.c"
2417 #include "selftests/i915_gem_context.c"
2418 #endif
2419 
2420 static void i915_global_gem_context_shrink(void)
2421 {
2422 	kmem_cache_shrink(global.slab_luts);
2423 }
2424 
2425 static void i915_global_gem_context_exit(void)
2426 {
2427 	kmem_cache_destroy(global.slab_luts);
2428 }
2429 
2430 static struct i915_global_gem_context global = { {
2431 	.shrink = i915_global_gem_context_shrink,
2432 	.exit = i915_global_gem_context_exit,
2433 } };
2434 
2435 int __init i915_global_gem_context_init(void)
2436 {
2437 	global.slab_luts = KMEM_CACHE(i915_lut_handle, 0);
2438 	if (!global.slab_luts)
2439 		return -ENOMEM;
2440 
2441 	i915_global_register(&global.base);
2442 	return 0;
2443 }
2444