1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2011-2012 Intel Corporation 5 */ 6 7 /* 8 * This file implements HW context support. On gen5+ a HW context consists of an 9 * opaque GPU object which is referenced at times of context saves and restores. 10 * With RC6 enabled, the context is also referenced as the GPU enters and exists 11 * from RC6 (GPU has it's own internal power context, except on gen5). Though 12 * something like a context does exist for the media ring, the code only 13 * supports contexts for the render ring. 14 * 15 * In software, there is a distinction between contexts created by the user, 16 * and the default HW context. The default HW context is used by GPU clients 17 * that do not request setup of their own hardware context. The default 18 * context's state is never restored to help prevent programming errors. This 19 * would happen if a client ran and piggy-backed off another clients GPU state. 20 * The default context only exists to give the GPU some offset to load as the 21 * current to invoke a save of the context we actually care about. In fact, the 22 * code could likely be constructed, albeit in a more complicated fashion, to 23 * never use the default context, though that limits the driver's ability to 24 * swap out, and/or destroy other contexts. 25 * 26 * All other contexts are created as a request by the GPU client. These contexts 27 * store GPU state, and thus allow GPU clients to not re-emit state (and 28 * potentially query certain state) at any time. The kernel driver makes 29 * certain that the appropriate commands are inserted. 30 * 31 * The context life cycle is semi-complicated in that context BOs may live 32 * longer than the context itself because of the way the hardware, and object 33 * tracking works. Below is a very crude representation of the state machine 34 * describing the context life. 35 * refcount pincount active 36 * S0: initial state 0 0 0 37 * S1: context created 1 0 0 38 * S2: context is currently running 2 1 X 39 * S3: GPU referenced, but not current 2 0 1 40 * S4: context is current, but destroyed 1 1 0 41 * S5: like S3, but destroyed 1 0 1 42 * 43 * The most common (but not all) transitions: 44 * S0->S1: client creates a context 45 * S1->S2: client submits execbuf with context 46 * S2->S3: other clients submits execbuf with context 47 * S3->S1: context object was retired 48 * S3->S2: clients submits another execbuf 49 * S2->S4: context destroy called with current context 50 * S3->S5->S0: destroy path 51 * S4->S5->S0: destroy path on current context 52 * 53 * There are two confusing terms used above: 54 * The "current context" means the context which is currently running on the 55 * GPU. The GPU has loaded its state already and has stored away the gtt 56 * offset of the BO. The GPU is not actively referencing the data at this 57 * offset, but it will on the next context switch. The only way to avoid this 58 * is to do a GPU reset. 59 * 60 * An "active context' is one which was previously the "current context" and is 61 * on the active list waiting for the next context switch to occur. Until this 62 * happens, the object must remain at the same gtt offset. It is therefore 63 * possible to destroy a context, but it is still active. 64 * 65 */ 66 67 #include <linux/highmem.h> 68 #include <linux/log2.h> 69 #include <linux/nospec.h> 70 71 #include <drm/drm_cache.h> 72 #include <drm/drm_syncobj.h> 73 74 #include "gt/gen6_ppgtt.h" 75 #include "gt/intel_context.h" 76 #include "gt/intel_context_param.h" 77 #include "gt/intel_engine_heartbeat.h" 78 #include "gt/intel_engine_user.h" 79 #include "gt/intel_gpu_commands.h" 80 #include "gt/intel_ring.h" 81 82 #include "pxp/intel_pxp.h" 83 84 #include "i915_file_private.h" 85 #include "i915_gem_context.h" 86 #include "i915_trace.h" 87 #include "i915_user_extensions.h" 88 89 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 90 91 static struct kmem_cache *slab_luts; 92 93 struct i915_lut_handle *i915_lut_handle_alloc(void) 94 { 95 return kmem_cache_alloc(slab_luts, GFP_KERNEL); 96 } 97 98 void i915_lut_handle_free(struct i915_lut_handle *lut) 99 { 100 return kmem_cache_free(slab_luts, lut); 101 } 102 103 static void lut_close(struct i915_gem_context *ctx) 104 { 105 struct radix_tree_iter iter; 106 void __rcu **slot; 107 108 mutex_lock(&ctx->lut_mutex); 109 rcu_read_lock(); 110 radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) { 111 struct i915_vma *vma = rcu_dereference_raw(*slot); 112 struct drm_i915_gem_object *obj = vma->obj; 113 struct i915_lut_handle *lut; 114 115 if (!kref_get_unless_zero(&obj->base.refcount)) 116 continue; 117 118 spin_lock(&obj->lut_lock); 119 list_for_each_entry(lut, &obj->lut_list, obj_link) { 120 if (lut->ctx != ctx) 121 continue; 122 123 if (lut->handle != iter.index) 124 continue; 125 126 list_del(&lut->obj_link); 127 break; 128 } 129 spin_unlock(&obj->lut_lock); 130 131 if (&lut->obj_link != &obj->lut_list) { 132 i915_lut_handle_free(lut); 133 radix_tree_iter_delete(&ctx->handles_vma, &iter, slot); 134 i915_vma_close(vma); 135 i915_gem_object_put(obj); 136 } 137 138 i915_gem_object_put(obj); 139 } 140 rcu_read_unlock(); 141 mutex_unlock(&ctx->lut_mutex); 142 } 143 144 static struct intel_context * 145 lookup_user_engine(struct i915_gem_context *ctx, 146 unsigned long flags, 147 const struct i915_engine_class_instance *ci) 148 #define LOOKUP_USER_INDEX BIT(0) 149 { 150 int idx; 151 152 if (!!(flags & LOOKUP_USER_INDEX) != i915_gem_context_user_engines(ctx)) 153 return ERR_PTR(-EINVAL); 154 155 if (!i915_gem_context_user_engines(ctx)) { 156 struct intel_engine_cs *engine; 157 158 engine = intel_engine_lookup_user(ctx->i915, 159 ci->engine_class, 160 ci->engine_instance); 161 if (!engine) 162 return ERR_PTR(-EINVAL); 163 164 idx = engine->legacy_idx; 165 } else { 166 idx = ci->engine_instance; 167 } 168 169 return i915_gem_context_get_engine(ctx, idx); 170 } 171 172 static int validate_priority(struct drm_i915_private *i915, 173 const struct drm_i915_gem_context_param *args) 174 { 175 s64 priority = args->value; 176 177 if (args->size) 178 return -EINVAL; 179 180 if (!(i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY)) 181 return -ENODEV; 182 183 if (priority > I915_CONTEXT_MAX_USER_PRIORITY || 184 priority < I915_CONTEXT_MIN_USER_PRIORITY) 185 return -EINVAL; 186 187 if (priority > I915_CONTEXT_DEFAULT_PRIORITY && 188 !capable(CAP_SYS_NICE)) 189 return -EPERM; 190 191 return 0; 192 } 193 194 static void proto_context_close(struct drm_i915_private *i915, 195 struct i915_gem_proto_context *pc) 196 { 197 int i; 198 199 if (pc->pxp_wakeref) 200 intel_runtime_pm_put(&i915->runtime_pm, pc->pxp_wakeref); 201 if (pc->vm) 202 i915_vm_put(pc->vm); 203 if (pc->user_engines) { 204 for (i = 0; i < pc->num_user_engines; i++) 205 kfree(pc->user_engines[i].siblings); 206 kfree(pc->user_engines); 207 } 208 kfree(pc); 209 } 210 211 static int proto_context_set_persistence(struct drm_i915_private *i915, 212 struct i915_gem_proto_context *pc, 213 bool persist) 214 { 215 if (persist) { 216 /* 217 * Only contexts that are short-lived [that will expire or be 218 * reset] are allowed to survive past termination. We require 219 * hangcheck to ensure that the persistent requests are healthy. 220 */ 221 if (!i915->params.enable_hangcheck) 222 return -EINVAL; 223 224 pc->user_flags |= BIT(UCONTEXT_PERSISTENCE); 225 } else { 226 /* To cancel a context we use "preempt-to-idle" */ 227 if (!(i915->caps.scheduler & I915_SCHEDULER_CAP_PREEMPTION)) 228 return -ENODEV; 229 230 /* 231 * If the cancel fails, we then need to reset, cleanly! 232 * 233 * If the per-engine reset fails, all hope is lost! We resort 234 * to a full GPU reset in that unlikely case, but realistically 235 * if the engine could not reset, the full reset does not fare 236 * much better. The damage has been done. 237 * 238 * However, if we cannot reset an engine by itself, we cannot 239 * cleanup a hanging persistent context without causing 240 * colateral damage, and we should not pretend we can by 241 * exposing the interface. 242 */ 243 if (!intel_has_reset_engine(to_gt(i915))) 244 return -ENODEV; 245 246 pc->user_flags &= ~BIT(UCONTEXT_PERSISTENCE); 247 } 248 249 return 0; 250 } 251 252 static int proto_context_set_protected(struct drm_i915_private *i915, 253 struct i915_gem_proto_context *pc, 254 bool protected) 255 { 256 int ret = 0; 257 258 if (!protected) { 259 pc->uses_protected_content = false; 260 } else if (!intel_pxp_is_enabled(&to_gt(i915)->pxp)) { 261 ret = -ENODEV; 262 } else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) || 263 !(pc->user_flags & BIT(UCONTEXT_BANNABLE))) { 264 ret = -EPERM; 265 } else { 266 pc->uses_protected_content = true; 267 268 /* 269 * protected context usage requires the PXP session to be up, 270 * which in turn requires the device to be active. 271 */ 272 pc->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm); 273 274 if (!intel_pxp_is_active(&to_gt(i915)->pxp)) 275 ret = intel_pxp_start(&to_gt(i915)->pxp); 276 } 277 278 return ret; 279 } 280 281 static struct i915_gem_proto_context * 282 proto_context_create(struct drm_i915_private *i915, unsigned int flags) 283 { 284 struct i915_gem_proto_context *pc, *err; 285 286 pc = kzalloc(sizeof(*pc), GFP_KERNEL); 287 if (!pc) 288 return ERR_PTR(-ENOMEM); 289 290 pc->num_user_engines = -1; 291 pc->user_engines = NULL; 292 pc->user_flags = BIT(UCONTEXT_BANNABLE) | 293 BIT(UCONTEXT_RECOVERABLE); 294 if (i915->params.enable_hangcheck) 295 pc->user_flags |= BIT(UCONTEXT_PERSISTENCE); 296 pc->sched.priority = I915_PRIORITY_NORMAL; 297 298 if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) { 299 if (!HAS_EXECLISTS(i915)) { 300 err = ERR_PTR(-EINVAL); 301 goto proto_close; 302 } 303 pc->single_timeline = true; 304 } 305 306 return pc; 307 308 proto_close: 309 proto_context_close(i915, pc); 310 return err; 311 } 312 313 static int proto_context_register_locked(struct drm_i915_file_private *fpriv, 314 struct i915_gem_proto_context *pc, 315 u32 *id) 316 { 317 int ret; 318 void *old; 319 320 lockdep_assert_held(&fpriv->proto_context_lock); 321 322 ret = xa_alloc(&fpriv->context_xa, id, NULL, xa_limit_32b, GFP_KERNEL); 323 if (ret) 324 return ret; 325 326 old = xa_store(&fpriv->proto_context_xa, *id, pc, GFP_KERNEL); 327 if (xa_is_err(old)) { 328 xa_erase(&fpriv->context_xa, *id); 329 return xa_err(old); 330 } 331 WARN_ON(old); 332 333 return 0; 334 } 335 336 static int proto_context_register(struct drm_i915_file_private *fpriv, 337 struct i915_gem_proto_context *pc, 338 u32 *id) 339 { 340 int ret; 341 342 mutex_lock(&fpriv->proto_context_lock); 343 ret = proto_context_register_locked(fpriv, pc, id); 344 mutex_unlock(&fpriv->proto_context_lock); 345 346 return ret; 347 } 348 349 static struct i915_address_space * 350 i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id) 351 { 352 struct i915_address_space *vm; 353 354 xa_lock(&file_priv->vm_xa); 355 vm = xa_load(&file_priv->vm_xa, id); 356 if (vm) 357 kref_get(&vm->ref); 358 xa_unlock(&file_priv->vm_xa); 359 360 return vm; 361 } 362 363 static int set_proto_ctx_vm(struct drm_i915_file_private *fpriv, 364 struct i915_gem_proto_context *pc, 365 const struct drm_i915_gem_context_param *args) 366 { 367 struct drm_i915_private *i915 = fpriv->dev_priv; 368 struct i915_address_space *vm; 369 370 if (args->size) 371 return -EINVAL; 372 373 if (!HAS_FULL_PPGTT(i915)) 374 return -ENODEV; 375 376 if (upper_32_bits(args->value)) 377 return -ENOENT; 378 379 vm = i915_gem_vm_lookup(fpriv, args->value); 380 if (!vm) 381 return -ENOENT; 382 383 if (pc->vm) 384 i915_vm_put(pc->vm); 385 pc->vm = vm; 386 387 return 0; 388 } 389 390 struct set_proto_ctx_engines { 391 struct drm_i915_private *i915; 392 unsigned num_engines; 393 struct i915_gem_proto_engine *engines; 394 }; 395 396 static int 397 set_proto_ctx_engines_balance(struct i915_user_extension __user *base, 398 void *data) 399 { 400 struct i915_context_engines_load_balance __user *ext = 401 container_of_user(base, typeof(*ext), base); 402 const struct set_proto_ctx_engines *set = data; 403 struct drm_i915_private *i915 = set->i915; 404 struct intel_engine_cs **siblings; 405 u16 num_siblings, idx; 406 unsigned int n; 407 int err; 408 409 if (!HAS_EXECLISTS(i915)) 410 return -ENODEV; 411 412 if (get_user(idx, &ext->engine_index)) 413 return -EFAULT; 414 415 if (idx >= set->num_engines) { 416 drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n", 417 idx, set->num_engines); 418 return -EINVAL; 419 } 420 421 idx = array_index_nospec(idx, set->num_engines); 422 if (set->engines[idx].type != I915_GEM_ENGINE_TYPE_INVALID) { 423 drm_dbg(&i915->drm, 424 "Invalid placement[%d], already occupied\n", idx); 425 return -EEXIST; 426 } 427 428 if (get_user(num_siblings, &ext->num_siblings)) 429 return -EFAULT; 430 431 err = check_user_mbz(&ext->flags); 432 if (err) 433 return err; 434 435 err = check_user_mbz(&ext->mbz64); 436 if (err) 437 return err; 438 439 if (num_siblings == 0) 440 return 0; 441 442 siblings = kmalloc_array(num_siblings, sizeof(*siblings), GFP_KERNEL); 443 if (!siblings) 444 return -ENOMEM; 445 446 for (n = 0; n < num_siblings; n++) { 447 struct i915_engine_class_instance ci; 448 449 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) { 450 err = -EFAULT; 451 goto err_siblings; 452 } 453 454 siblings[n] = intel_engine_lookup_user(i915, 455 ci.engine_class, 456 ci.engine_instance); 457 if (!siblings[n]) { 458 drm_dbg(&i915->drm, 459 "Invalid sibling[%d]: { class:%d, inst:%d }\n", 460 n, ci.engine_class, ci.engine_instance); 461 err = -EINVAL; 462 goto err_siblings; 463 } 464 } 465 466 if (num_siblings == 1) { 467 set->engines[idx].type = I915_GEM_ENGINE_TYPE_PHYSICAL; 468 set->engines[idx].engine = siblings[0]; 469 kfree(siblings); 470 } else { 471 set->engines[idx].type = I915_GEM_ENGINE_TYPE_BALANCED; 472 set->engines[idx].num_siblings = num_siblings; 473 set->engines[idx].siblings = siblings; 474 } 475 476 return 0; 477 478 err_siblings: 479 kfree(siblings); 480 481 return err; 482 } 483 484 static int 485 set_proto_ctx_engines_bond(struct i915_user_extension __user *base, void *data) 486 { 487 struct i915_context_engines_bond __user *ext = 488 container_of_user(base, typeof(*ext), base); 489 const struct set_proto_ctx_engines *set = data; 490 struct drm_i915_private *i915 = set->i915; 491 struct i915_engine_class_instance ci; 492 struct intel_engine_cs *master; 493 u16 idx, num_bonds; 494 int err, n; 495 496 if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915) && 497 !IS_ROCKETLAKE(i915) && !IS_ALDERLAKE_S(i915)) { 498 drm_dbg(&i915->drm, 499 "Bonding not supported on this platform\n"); 500 return -ENODEV; 501 } 502 503 if (get_user(idx, &ext->virtual_index)) 504 return -EFAULT; 505 506 if (idx >= set->num_engines) { 507 drm_dbg(&i915->drm, 508 "Invalid index for virtual engine: %d >= %d\n", 509 idx, set->num_engines); 510 return -EINVAL; 511 } 512 513 idx = array_index_nospec(idx, set->num_engines); 514 if (set->engines[idx].type == I915_GEM_ENGINE_TYPE_INVALID) { 515 drm_dbg(&i915->drm, "Invalid engine at %d\n", idx); 516 return -EINVAL; 517 } 518 519 if (set->engines[idx].type != I915_GEM_ENGINE_TYPE_PHYSICAL) { 520 drm_dbg(&i915->drm, 521 "Bonding with virtual engines not allowed\n"); 522 return -EINVAL; 523 } 524 525 err = check_user_mbz(&ext->flags); 526 if (err) 527 return err; 528 529 for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) { 530 err = check_user_mbz(&ext->mbz64[n]); 531 if (err) 532 return err; 533 } 534 535 if (copy_from_user(&ci, &ext->master, sizeof(ci))) 536 return -EFAULT; 537 538 master = intel_engine_lookup_user(i915, 539 ci.engine_class, 540 ci.engine_instance); 541 if (!master) { 542 drm_dbg(&i915->drm, 543 "Unrecognised master engine: { class:%u, instance:%u }\n", 544 ci.engine_class, ci.engine_instance); 545 return -EINVAL; 546 } 547 548 if (intel_engine_uses_guc(master)) { 549 DRM_DEBUG("bonding extension not supported with GuC submission"); 550 return -ENODEV; 551 } 552 553 if (get_user(num_bonds, &ext->num_bonds)) 554 return -EFAULT; 555 556 for (n = 0; n < num_bonds; n++) { 557 struct intel_engine_cs *bond; 558 559 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) 560 return -EFAULT; 561 562 bond = intel_engine_lookup_user(i915, 563 ci.engine_class, 564 ci.engine_instance); 565 if (!bond) { 566 drm_dbg(&i915->drm, 567 "Unrecognised engine[%d] for bonding: { class:%d, instance: %d }\n", 568 n, ci.engine_class, ci.engine_instance); 569 return -EINVAL; 570 } 571 } 572 573 return 0; 574 } 575 576 static int 577 set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base, 578 void *data) 579 { 580 struct i915_context_engines_parallel_submit __user *ext = 581 container_of_user(base, typeof(*ext), base); 582 const struct set_proto_ctx_engines *set = data; 583 struct drm_i915_private *i915 = set->i915; 584 struct i915_engine_class_instance prev_engine; 585 u64 flags; 586 int err = 0, n, i, j; 587 u16 slot, width, num_siblings; 588 struct intel_engine_cs **siblings = NULL; 589 intel_engine_mask_t prev_mask; 590 591 if (get_user(slot, &ext->engine_index)) 592 return -EFAULT; 593 594 if (get_user(width, &ext->width)) 595 return -EFAULT; 596 597 if (get_user(num_siblings, &ext->num_siblings)) 598 return -EFAULT; 599 600 if (!intel_uc_uses_guc_submission(&to_gt(i915)->uc) && 601 num_siblings != 1) { 602 drm_dbg(&i915->drm, "Only 1 sibling (%d) supported in non-GuC mode\n", 603 num_siblings); 604 return -EINVAL; 605 } 606 607 if (slot >= set->num_engines) { 608 drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n", 609 slot, set->num_engines); 610 return -EINVAL; 611 } 612 613 if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) { 614 drm_dbg(&i915->drm, 615 "Invalid placement[%d], already occupied\n", slot); 616 return -EINVAL; 617 } 618 619 if (get_user(flags, &ext->flags)) 620 return -EFAULT; 621 622 if (flags) { 623 drm_dbg(&i915->drm, "Unknown flags 0x%02llx", flags); 624 return -EINVAL; 625 } 626 627 for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) { 628 err = check_user_mbz(&ext->mbz64[n]); 629 if (err) 630 return err; 631 } 632 633 if (width < 2) { 634 drm_dbg(&i915->drm, "Width (%d) < 2\n", width); 635 return -EINVAL; 636 } 637 638 if (num_siblings < 1) { 639 drm_dbg(&i915->drm, "Number siblings (%d) < 1\n", 640 num_siblings); 641 return -EINVAL; 642 } 643 644 siblings = kmalloc_array(num_siblings * width, 645 sizeof(*siblings), 646 GFP_KERNEL); 647 if (!siblings) 648 return -ENOMEM; 649 650 /* Create contexts / engines */ 651 for (i = 0; i < width; ++i) { 652 intel_engine_mask_t current_mask = 0; 653 654 for (j = 0; j < num_siblings; ++j) { 655 struct i915_engine_class_instance ci; 656 657 n = i * num_siblings + j; 658 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) { 659 err = -EFAULT; 660 goto out_err; 661 } 662 663 siblings[n] = 664 intel_engine_lookup_user(i915, ci.engine_class, 665 ci.engine_instance); 666 if (!siblings[n]) { 667 drm_dbg(&i915->drm, 668 "Invalid sibling[%d]: { class:%d, inst:%d }\n", 669 n, ci.engine_class, ci.engine_instance); 670 err = -EINVAL; 671 goto out_err; 672 } 673 674 /* 675 * We don't support breadcrumb handshake on these 676 * classes 677 */ 678 if (siblings[n]->class == RENDER_CLASS || 679 siblings[n]->class == COMPUTE_CLASS) { 680 err = -EINVAL; 681 goto out_err; 682 } 683 684 if (n) { 685 if (prev_engine.engine_class != 686 ci.engine_class) { 687 drm_dbg(&i915->drm, 688 "Mismatched class %d, %d\n", 689 prev_engine.engine_class, 690 ci.engine_class); 691 err = -EINVAL; 692 goto out_err; 693 } 694 } 695 696 prev_engine = ci; 697 current_mask |= siblings[n]->logical_mask; 698 } 699 700 if (i > 0) { 701 if (current_mask != prev_mask << 1) { 702 drm_dbg(&i915->drm, 703 "Non contiguous logical mask 0x%x, 0x%x\n", 704 prev_mask, current_mask); 705 err = -EINVAL; 706 goto out_err; 707 } 708 } 709 prev_mask = current_mask; 710 } 711 712 set->engines[slot].type = I915_GEM_ENGINE_TYPE_PARALLEL; 713 set->engines[slot].num_siblings = num_siblings; 714 set->engines[slot].width = width; 715 set->engines[slot].siblings = siblings; 716 717 return 0; 718 719 out_err: 720 kfree(siblings); 721 722 return err; 723 } 724 725 static const i915_user_extension_fn set_proto_ctx_engines_extensions[] = { 726 [I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE] = set_proto_ctx_engines_balance, 727 [I915_CONTEXT_ENGINES_EXT_BOND] = set_proto_ctx_engines_bond, 728 [I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT] = 729 set_proto_ctx_engines_parallel_submit, 730 }; 731 732 static int set_proto_ctx_engines(struct drm_i915_file_private *fpriv, 733 struct i915_gem_proto_context *pc, 734 const struct drm_i915_gem_context_param *args) 735 { 736 struct drm_i915_private *i915 = fpriv->dev_priv; 737 struct set_proto_ctx_engines set = { .i915 = i915 }; 738 struct i915_context_param_engines __user *user = 739 u64_to_user_ptr(args->value); 740 unsigned int n; 741 u64 extensions; 742 int err; 743 744 if (pc->num_user_engines >= 0) { 745 drm_dbg(&i915->drm, "Cannot set engines twice"); 746 return -EINVAL; 747 } 748 749 if (args->size < sizeof(*user) || 750 !IS_ALIGNED(args->size - sizeof(*user), sizeof(*user->engines))) { 751 drm_dbg(&i915->drm, "Invalid size for engine array: %d\n", 752 args->size); 753 return -EINVAL; 754 } 755 756 set.num_engines = (args->size - sizeof(*user)) / sizeof(*user->engines); 757 /* RING_MASK has no shift so we can use it directly here */ 758 if (set.num_engines > I915_EXEC_RING_MASK + 1) 759 return -EINVAL; 760 761 set.engines = kmalloc_array(set.num_engines, sizeof(*set.engines), GFP_KERNEL); 762 if (!set.engines) 763 return -ENOMEM; 764 765 for (n = 0; n < set.num_engines; n++) { 766 struct i915_engine_class_instance ci; 767 struct intel_engine_cs *engine; 768 769 if (copy_from_user(&ci, &user->engines[n], sizeof(ci))) { 770 kfree(set.engines); 771 return -EFAULT; 772 } 773 774 memset(&set.engines[n], 0, sizeof(set.engines[n])); 775 776 if (ci.engine_class == (u16)I915_ENGINE_CLASS_INVALID && 777 ci.engine_instance == (u16)I915_ENGINE_CLASS_INVALID_NONE) 778 continue; 779 780 engine = intel_engine_lookup_user(i915, 781 ci.engine_class, 782 ci.engine_instance); 783 if (!engine) { 784 drm_dbg(&i915->drm, 785 "Invalid engine[%d]: { class:%d, instance:%d }\n", 786 n, ci.engine_class, ci.engine_instance); 787 kfree(set.engines); 788 return -ENOENT; 789 } 790 791 set.engines[n].type = I915_GEM_ENGINE_TYPE_PHYSICAL; 792 set.engines[n].engine = engine; 793 } 794 795 err = -EFAULT; 796 if (!get_user(extensions, &user->extensions)) 797 err = i915_user_extensions(u64_to_user_ptr(extensions), 798 set_proto_ctx_engines_extensions, 799 ARRAY_SIZE(set_proto_ctx_engines_extensions), 800 &set); 801 if (err) { 802 kfree(set.engines); 803 return err; 804 } 805 806 pc->num_user_engines = set.num_engines; 807 pc->user_engines = set.engines; 808 809 return 0; 810 } 811 812 static int set_proto_ctx_sseu(struct drm_i915_file_private *fpriv, 813 struct i915_gem_proto_context *pc, 814 struct drm_i915_gem_context_param *args) 815 { 816 struct drm_i915_private *i915 = fpriv->dev_priv; 817 struct drm_i915_gem_context_param_sseu user_sseu; 818 struct intel_sseu *sseu; 819 int ret; 820 821 if (args->size < sizeof(user_sseu)) 822 return -EINVAL; 823 824 if (GRAPHICS_VER(i915) != 11) 825 return -ENODEV; 826 827 if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value), 828 sizeof(user_sseu))) 829 return -EFAULT; 830 831 if (user_sseu.rsvd) 832 return -EINVAL; 833 834 if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)) 835 return -EINVAL; 836 837 if (!!(user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX) != (pc->num_user_engines >= 0)) 838 return -EINVAL; 839 840 if (pc->num_user_engines >= 0) { 841 int idx = user_sseu.engine.engine_instance; 842 struct i915_gem_proto_engine *pe; 843 844 if (idx >= pc->num_user_engines) 845 return -EINVAL; 846 847 pe = &pc->user_engines[idx]; 848 849 /* Only render engine supports RPCS configuration. */ 850 if (pe->engine->class != RENDER_CLASS) 851 return -EINVAL; 852 853 sseu = &pe->sseu; 854 } else { 855 /* Only render engine supports RPCS configuration. */ 856 if (user_sseu.engine.engine_class != I915_ENGINE_CLASS_RENDER) 857 return -EINVAL; 858 859 /* There is only one render engine */ 860 if (user_sseu.engine.engine_instance != 0) 861 return -EINVAL; 862 863 sseu = &pc->legacy_rcs_sseu; 864 } 865 866 ret = i915_gem_user_to_context_sseu(to_gt(i915), &user_sseu, sseu); 867 if (ret) 868 return ret; 869 870 args->size = sizeof(user_sseu); 871 872 return 0; 873 } 874 875 static int set_proto_ctx_param(struct drm_i915_file_private *fpriv, 876 struct i915_gem_proto_context *pc, 877 struct drm_i915_gem_context_param *args) 878 { 879 int ret = 0; 880 881 switch (args->param) { 882 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: 883 if (args->size) 884 ret = -EINVAL; 885 else if (args->value) 886 pc->user_flags |= BIT(UCONTEXT_NO_ERROR_CAPTURE); 887 else 888 pc->user_flags &= ~BIT(UCONTEXT_NO_ERROR_CAPTURE); 889 break; 890 891 case I915_CONTEXT_PARAM_BANNABLE: 892 if (args->size) 893 ret = -EINVAL; 894 else if (!capable(CAP_SYS_ADMIN) && !args->value) 895 ret = -EPERM; 896 else if (args->value) 897 pc->user_flags |= BIT(UCONTEXT_BANNABLE); 898 else if (pc->uses_protected_content) 899 ret = -EPERM; 900 else 901 pc->user_flags &= ~BIT(UCONTEXT_BANNABLE); 902 break; 903 904 case I915_CONTEXT_PARAM_RECOVERABLE: 905 if (args->size) 906 ret = -EINVAL; 907 else if (!args->value) 908 pc->user_flags &= ~BIT(UCONTEXT_RECOVERABLE); 909 else if (pc->uses_protected_content) 910 ret = -EPERM; 911 else 912 pc->user_flags |= BIT(UCONTEXT_RECOVERABLE); 913 break; 914 915 case I915_CONTEXT_PARAM_PRIORITY: 916 ret = validate_priority(fpriv->dev_priv, args); 917 if (!ret) 918 pc->sched.priority = args->value; 919 break; 920 921 case I915_CONTEXT_PARAM_SSEU: 922 ret = set_proto_ctx_sseu(fpriv, pc, args); 923 break; 924 925 case I915_CONTEXT_PARAM_VM: 926 ret = set_proto_ctx_vm(fpriv, pc, args); 927 break; 928 929 case I915_CONTEXT_PARAM_ENGINES: 930 ret = set_proto_ctx_engines(fpriv, pc, args); 931 break; 932 933 case I915_CONTEXT_PARAM_PERSISTENCE: 934 if (args->size) 935 ret = -EINVAL; 936 else 937 ret = proto_context_set_persistence(fpriv->dev_priv, pc, 938 args->value); 939 break; 940 941 case I915_CONTEXT_PARAM_PROTECTED_CONTENT: 942 ret = proto_context_set_protected(fpriv->dev_priv, pc, 943 args->value); 944 break; 945 946 case I915_CONTEXT_PARAM_NO_ZEROMAP: 947 case I915_CONTEXT_PARAM_BAN_PERIOD: 948 case I915_CONTEXT_PARAM_RINGSIZE: 949 default: 950 ret = -EINVAL; 951 break; 952 } 953 954 return ret; 955 } 956 957 static int intel_context_set_gem(struct intel_context *ce, 958 struct i915_gem_context *ctx, 959 struct intel_sseu sseu) 960 { 961 int ret = 0; 962 963 GEM_BUG_ON(rcu_access_pointer(ce->gem_context)); 964 RCU_INIT_POINTER(ce->gem_context, ctx); 965 966 GEM_BUG_ON(intel_context_is_pinned(ce)); 967 ce->ring_size = SZ_16K; 968 969 i915_vm_put(ce->vm); 970 ce->vm = i915_gem_context_get_eb_vm(ctx); 971 972 if (ctx->sched.priority >= I915_PRIORITY_NORMAL && 973 intel_engine_has_timeslices(ce->engine) && 974 intel_engine_has_semaphores(ce->engine)) 975 __set_bit(CONTEXT_USE_SEMAPHORES, &ce->flags); 976 977 if (CONFIG_DRM_I915_REQUEST_TIMEOUT && 978 ctx->i915->params.request_timeout_ms) { 979 unsigned int timeout_ms = ctx->i915->params.request_timeout_ms; 980 981 intel_context_set_watchdog_us(ce, (u64)timeout_ms * 1000); 982 } 983 984 /* A valid SSEU has no zero fields */ 985 if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS)) 986 ret = intel_context_reconfigure_sseu(ce, sseu); 987 988 return ret; 989 } 990 991 static void __unpin_engines(struct i915_gem_engines *e, unsigned int count) 992 { 993 while (count--) { 994 struct intel_context *ce = e->engines[count], *child; 995 996 if (!ce || !test_bit(CONTEXT_PERMA_PIN, &ce->flags)) 997 continue; 998 999 for_each_child(ce, child) 1000 intel_context_unpin(child); 1001 intel_context_unpin(ce); 1002 } 1003 } 1004 1005 static void unpin_engines(struct i915_gem_engines *e) 1006 { 1007 __unpin_engines(e, e->num_engines); 1008 } 1009 1010 static void __free_engines(struct i915_gem_engines *e, unsigned int count) 1011 { 1012 while (count--) { 1013 if (!e->engines[count]) 1014 continue; 1015 1016 intel_context_put(e->engines[count]); 1017 } 1018 kfree(e); 1019 } 1020 1021 static void free_engines(struct i915_gem_engines *e) 1022 { 1023 __free_engines(e, e->num_engines); 1024 } 1025 1026 static void free_engines_rcu(struct rcu_head *rcu) 1027 { 1028 struct i915_gem_engines *engines = 1029 container_of(rcu, struct i915_gem_engines, rcu); 1030 1031 i915_sw_fence_fini(&engines->fence); 1032 free_engines(engines); 1033 } 1034 1035 static void accumulate_runtime(struct i915_drm_client *client, 1036 struct i915_gem_engines *engines) 1037 { 1038 struct i915_gem_engines_iter it; 1039 struct intel_context *ce; 1040 1041 if (!client) 1042 return; 1043 1044 /* Transfer accumulated runtime to the parent GEM context. */ 1045 for_each_gem_engine(ce, engines, it) { 1046 unsigned int class = ce->engine->uabi_class; 1047 1048 GEM_BUG_ON(class >= ARRAY_SIZE(client->past_runtime)); 1049 atomic64_add(intel_context_get_total_runtime_ns(ce), 1050 &client->past_runtime[class]); 1051 } 1052 } 1053 1054 static int 1055 engines_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) 1056 { 1057 struct i915_gem_engines *engines = 1058 container_of(fence, typeof(*engines), fence); 1059 struct i915_gem_context *ctx = engines->ctx; 1060 1061 switch (state) { 1062 case FENCE_COMPLETE: 1063 if (!list_empty(&engines->link)) { 1064 unsigned long flags; 1065 1066 spin_lock_irqsave(&ctx->stale.lock, flags); 1067 list_del(&engines->link); 1068 spin_unlock_irqrestore(&ctx->stale.lock, flags); 1069 } 1070 accumulate_runtime(ctx->client, engines); 1071 i915_gem_context_put(ctx); 1072 1073 break; 1074 1075 case FENCE_FREE: 1076 init_rcu_head(&engines->rcu); 1077 call_rcu(&engines->rcu, free_engines_rcu); 1078 break; 1079 } 1080 1081 return NOTIFY_DONE; 1082 } 1083 1084 static struct i915_gem_engines *alloc_engines(unsigned int count) 1085 { 1086 struct i915_gem_engines *e; 1087 1088 e = kzalloc(struct_size(e, engines, count), GFP_KERNEL); 1089 if (!e) 1090 return NULL; 1091 1092 i915_sw_fence_init(&e->fence, engines_notify); 1093 return e; 1094 } 1095 1096 static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx, 1097 struct intel_sseu rcs_sseu) 1098 { 1099 const struct intel_gt *gt = to_gt(ctx->i915); 1100 struct intel_engine_cs *engine; 1101 struct i915_gem_engines *e, *err; 1102 enum intel_engine_id id; 1103 1104 e = alloc_engines(I915_NUM_ENGINES); 1105 if (!e) 1106 return ERR_PTR(-ENOMEM); 1107 1108 for_each_engine(engine, gt, id) { 1109 struct intel_context *ce; 1110 struct intel_sseu sseu = {}; 1111 int ret; 1112 1113 if (engine->legacy_idx == INVALID_ENGINE) 1114 continue; 1115 1116 GEM_BUG_ON(engine->legacy_idx >= I915_NUM_ENGINES); 1117 GEM_BUG_ON(e->engines[engine->legacy_idx]); 1118 1119 ce = intel_context_create(engine); 1120 if (IS_ERR(ce)) { 1121 err = ERR_CAST(ce); 1122 goto free_engines; 1123 } 1124 1125 e->engines[engine->legacy_idx] = ce; 1126 e->num_engines = max(e->num_engines, engine->legacy_idx + 1); 1127 1128 if (engine->class == RENDER_CLASS) 1129 sseu = rcs_sseu; 1130 1131 ret = intel_context_set_gem(ce, ctx, sseu); 1132 if (ret) { 1133 err = ERR_PTR(ret); 1134 goto free_engines; 1135 } 1136 1137 } 1138 1139 return e; 1140 1141 free_engines: 1142 free_engines(e); 1143 return err; 1144 } 1145 1146 static int perma_pin_contexts(struct intel_context *ce) 1147 { 1148 struct intel_context *child; 1149 int i = 0, j = 0, ret; 1150 1151 GEM_BUG_ON(!intel_context_is_parent(ce)); 1152 1153 ret = intel_context_pin(ce); 1154 if (unlikely(ret)) 1155 return ret; 1156 1157 for_each_child(ce, child) { 1158 ret = intel_context_pin(child); 1159 if (unlikely(ret)) 1160 goto unwind; 1161 ++i; 1162 } 1163 1164 set_bit(CONTEXT_PERMA_PIN, &ce->flags); 1165 1166 return 0; 1167 1168 unwind: 1169 intel_context_unpin(ce); 1170 for_each_child(ce, child) { 1171 if (j++ < i) 1172 intel_context_unpin(child); 1173 else 1174 break; 1175 } 1176 1177 return ret; 1178 } 1179 1180 static struct i915_gem_engines *user_engines(struct i915_gem_context *ctx, 1181 unsigned int num_engines, 1182 struct i915_gem_proto_engine *pe) 1183 { 1184 struct i915_gem_engines *e, *err; 1185 unsigned int n; 1186 1187 e = alloc_engines(num_engines); 1188 if (!e) 1189 return ERR_PTR(-ENOMEM); 1190 e->num_engines = num_engines; 1191 1192 for (n = 0; n < num_engines; n++) { 1193 struct intel_context *ce, *child; 1194 int ret; 1195 1196 switch (pe[n].type) { 1197 case I915_GEM_ENGINE_TYPE_PHYSICAL: 1198 ce = intel_context_create(pe[n].engine); 1199 break; 1200 1201 case I915_GEM_ENGINE_TYPE_BALANCED: 1202 ce = intel_engine_create_virtual(pe[n].siblings, 1203 pe[n].num_siblings, 0); 1204 break; 1205 1206 case I915_GEM_ENGINE_TYPE_PARALLEL: 1207 ce = intel_engine_create_parallel(pe[n].siblings, 1208 pe[n].num_siblings, 1209 pe[n].width); 1210 break; 1211 1212 case I915_GEM_ENGINE_TYPE_INVALID: 1213 default: 1214 GEM_WARN_ON(pe[n].type != I915_GEM_ENGINE_TYPE_INVALID); 1215 continue; 1216 } 1217 1218 if (IS_ERR(ce)) { 1219 err = ERR_CAST(ce); 1220 goto free_engines; 1221 } 1222 1223 e->engines[n] = ce; 1224 1225 ret = intel_context_set_gem(ce, ctx, pe->sseu); 1226 if (ret) { 1227 err = ERR_PTR(ret); 1228 goto free_engines; 1229 } 1230 for_each_child(ce, child) { 1231 ret = intel_context_set_gem(child, ctx, pe->sseu); 1232 if (ret) { 1233 err = ERR_PTR(ret); 1234 goto free_engines; 1235 } 1236 } 1237 1238 /* 1239 * XXX: Must be done after calling intel_context_set_gem as that 1240 * function changes the ring size. The ring is allocated when 1241 * the context is pinned. If the ring size is changed after 1242 * allocation we have a mismatch of the ring size and will cause 1243 * the context to hang. Presumably with a bit of reordering we 1244 * could move the perma-pin step to the backend function 1245 * intel_engine_create_parallel. 1246 */ 1247 if (pe[n].type == I915_GEM_ENGINE_TYPE_PARALLEL) { 1248 ret = perma_pin_contexts(ce); 1249 if (ret) { 1250 err = ERR_PTR(ret); 1251 goto free_engines; 1252 } 1253 } 1254 } 1255 1256 return e; 1257 1258 free_engines: 1259 free_engines(e); 1260 return err; 1261 } 1262 1263 static void i915_gem_context_release_work(struct work_struct *work) 1264 { 1265 struct i915_gem_context *ctx = container_of(work, typeof(*ctx), 1266 release_work); 1267 struct i915_address_space *vm; 1268 1269 trace_i915_context_free(ctx); 1270 GEM_BUG_ON(!i915_gem_context_is_closed(ctx)); 1271 1272 if (ctx->syncobj) 1273 drm_syncobj_put(ctx->syncobj); 1274 1275 vm = ctx->vm; 1276 if (vm) 1277 i915_vm_put(vm); 1278 1279 if (ctx->pxp_wakeref) 1280 intel_runtime_pm_put(&ctx->i915->runtime_pm, ctx->pxp_wakeref); 1281 1282 if (ctx->client) 1283 i915_drm_client_put(ctx->client); 1284 1285 mutex_destroy(&ctx->engines_mutex); 1286 mutex_destroy(&ctx->lut_mutex); 1287 1288 put_pid(ctx->pid); 1289 mutex_destroy(&ctx->mutex); 1290 1291 kfree_rcu(ctx, rcu); 1292 } 1293 1294 void i915_gem_context_release(struct kref *ref) 1295 { 1296 struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref); 1297 1298 queue_work(ctx->i915->wq, &ctx->release_work); 1299 } 1300 1301 static inline struct i915_gem_engines * 1302 __context_engines_static(const struct i915_gem_context *ctx) 1303 { 1304 return rcu_dereference_protected(ctx->engines, true); 1305 } 1306 1307 static void __reset_context(struct i915_gem_context *ctx, 1308 struct intel_engine_cs *engine) 1309 { 1310 intel_gt_handle_error(engine->gt, engine->mask, 0, 1311 "context closure in %s", ctx->name); 1312 } 1313 1314 static bool __cancel_engine(struct intel_engine_cs *engine) 1315 { 1316 /* 1317 * Send a "high priority pulse" down the engine to cause the 1318 * current request to be momentarily preempted. (If it fails to 1319 * be preempted, it will be reset). As we have marked our context 1320 * as banned, any incomplete request, including any running, will 1321 * be skipped following the preemption. 1322 * 1323 * If there is no hangchecking (one of the reasons why we try to 1324 * cancel the context) and no forced preemption, there may be no 1325 * means by which we reset the GPU and evict the persistent hog. 1326 * Ergo if we are unable to inject a preemptive pulse that can 1327 * kill the banned context, we fallback to doing a local reset 1328 * instead. 1329 */ 1330 return intel_engine_pulse(engine) == 0; 1331 } 1332 1333 static struct intel_engine_cs *active_engine(struct intel_context *ce) 1334 { 1335 struct intel_engine_cs *engine = NULL; 1336 struct i915_request *rq; 1337 1338 if (intel_context_has_inflight(ce)) 1339 return intel_context_inflight(ce); 1340 1341 if (!ce->timeline) 1342 return NULL; 1343 1344 /* 1345 * rq->link is only SLAB_TYPESAFE_BY_RCU, we need to hold a reference 1346 * to the request to prevent it being transferred to a new timeline 1347 * (and onto a new timeline->requests list). 1348 */ 1349 rcu_read_lock(); 1350 list_for_each_entry_reverse(rq, &ce->timeline->requests, link) { 1351 bool found; 1352 1353 /* timeline is already completed upto this point? */ 1354 if (!i915_request_get_rcu(rq)) 1355 break; 1356 1357 /* Check with the backend if the request is inflight */ 1358 found = true; 1359 if (likely(rcu_access_pointer(rq->timeline) == ce->timeline)) 1360 found = i915_request_active_engine(rq, &engine); 1361 1362 i915_request_put(rq); 1363 if (found) 1364 break; 1365 } 1366 rcu_read_unlock(); 1367 1368 return engine; 1369 } 1370 1371 static void 1372 kill_engines(struct i915_gem_engines *engines, bool exit, bool persistent) 1373 { 1374 struct i915_gem_engines_iter it; 1375 struct intel_context *ce; 1376 1377 /* 1378 * Map the user's engine back to the actual engines; one virtual 1379 * engine will be mapped to multiple engines, and using ctx->engine[] 1380 * the same engine may be have multiple instances in the user's map. 1381 * However, we only care about pending requests, so only include 1382 * engines on which there are incomplete requests. 1383 */ 1384 for_each_gem_engine(ce, engines, it) { 1385 struct intel_engine_cs *engine; 1386 bool skip = false; 1387 1388 if (exit) 1389 skip = intel_context_set_exiting(ce); 1390 else if (!persistent) 1391 skip = intel_context_exit_nonpersistent(ce, NULL); 1392 1393 if (skip) 1394 continue; /* Already marked. */ 1395 1396 /* 1397 * Check the current active state of this context; if we 1398 * are currently executing on the GPU we need to evict 1399 * ourselves. On the other hand, if we haven't yet been 1400 * submitted to the GPU or if everything is complete, 1401 * we have nothing to do. 1402 */ 1403 engine = active_engine(ce); 1404 1405 /* First attempt to gracefully cancel the context */ 1406 if (engine && !__cancel_engine(engine) && (exit || !persistent)) 1407 /* 1408 * If we are unable to send a preemptive pulse to bump 1409 * the context from the GPU, we have to resort to a full 1410 * reset. We hope the collateral damage is worth it. 1411 */ 1412 __reset_context(engines->ctx, engine); 1413 } 1414 } 1415 1416 static void kill_context(struct i915_gem_context *ctx) 1417 { 1418 struct i915_gem_engines *pos, *next; 1419 1420 spin_lock_irq(&ctx->stale.lock); 1421 GEM_BUG_ON(!i915_gem_context_is_closed(ctx)); 1422 list_for_each_entry_safe(pos, next, &ctx->stale.engines, link) { 1423 if (!i915_sw_fence_await(&pos->fence)) { 1424 list_del_init(&pos->link); 1425 continue; 1426 } 1427 1428 spin_unlock_irq(&ctx->stale.lock); 1429 1430 kill_engines(pos, !ctx->i915->params.enable_hangcheck, 1431 i915_gem_context_is_persistent(ctx)); 1432 1433 spin_lock_irq(&ctx->stale.lock); 1434 GEM_BUG_ON(i915_sw_fence_signaled(&pos->fence)); 1435 list_safe_reset_next(pos, next, link); 1436 list_del_init(&pos->link); /* decouple from FENCE_COMPLETE */ 1437 1438 i915_sw_fence_complete(&pos->fence); 1439 } 1440 spin_unlock_irq(&ctx->stale.lock); 1441 } 1442 1443 static void engines_idle_release(struct i915_gem_context *ctx, 1444 struct i915_gem_engines *engines) 1445 { 1446 struct i915_gem_engines_iter it; 1447 struct intel_context *ce; 1448 1449 INIT_LIST_HEAD(&engines->link); 1450 1451 engines->ctx = i915_gem_context_get(ctx); 1452 1453 for_each_gem_engine(ce, engines, it) { 1454 int err; 1455 1456 /* serialises with execbuf */ 1457 set_bit(CONTEXT_CLOSED_BIT, &ce->flags); 1458 if (!intel_context_pin_if_active(ce)) 1459 continue; 1460 1461 /* Wait until context is finally scheduled out and retired */ 1462 err = i915_sw_fence_await_active(&engines->fence, 1463 &ce->active, 1464 I915_ACTIVE_AWAIT_BARRIER); 1465 intel_context_unpin(ce); 1466 if (err) 1467 goto kill; 1468 } 1469 1470 spin_lock_irq(&ctx->stale.lock); 1471 if (!i915_gem_context_is_closed(ctx)) 1472 list_add_tail(&engines->link, &ctx->stale.engines); 1473 spin_unlock_irq(&ctx->stale.lock); 1474 1475 kill: 1476 if (list_empty(&engines->link)) /* raced, already closed */ 1477 kill_engines(engines, true, 1478 i915_gem_context_is_persistent(ctx)); 1479 1480 i915_sw_fence_commit(&engines->fence); 1481 } 1482 1483 static void set_closed_name(struct i915_gem_context *ctx) 1484 { 1485 char *s; 1486 1487 /* Replace '[]' with '<>' to indicate closed in debug prints */ 1488 1489 s = strrchr(ctx->name, '['); 1490 if (!s) 1491 return; 1492 1493 *s = '<'; 1494 1495 s = strchr(s + 1, ']'); 1496 if (s) 1497 *s = '>'; 1498 } 1499 1500 static void context_close(struct i915_gem_context *ctx) 1501 { 1502 struct i915_drm_client *client; 1503 1504 /* Flush any concurrent set_engines() */ 1505 mutex_lock(&ctx->engines_mutex); 1506 unpin_engines(__context_engines_static(ctx)); 1507 engines_idle_release(ctx, rcu_replace_pointer(ctx->engines, NULL, 1)); 1508 i915_gem_context_set_closed(ctx); 1509 mutex_unlock(&ctx->engines_mutex); 1510 1511 mutex_lock(&ctx->mutex); 1512 1513 set_closed_name(ctx); 1514 1515 /* 1516 * The LUT uses the VMA as a backpointer to unref the object, 1517 * so we need to clear the LUT before we close all the VMA (inside 1518 * the ppgtt). 1519 */ 1520 lut_close(ctx); 1521 1522 ctx->file_priv = ERR_PTR(-EBADF); 1523 1524 spin_lock(&ctx->i915->gem.contexts.lock); 1525 list_del(&ctx->link); 1526 spin_unlock(&ctx->i915->gem.contexts.lock); 1527 1528 client = ctx->client; 1529 if (client) { 1530 spin_lock(&client->ctx_lock); 1531 list_del_rcu(&ctx->client_link); 1532 spin_unlock(&client->ctx_lock); 1533 } 1534 1535 mutex_unlock(&ctx->mutex); 1536 1537 /* 1538 * If the user has disabled hangchecking, we can not be sure that 1539 * the batches will ever complete after the context is closed, 1540 * keeping the context and all resources pinned forever. So in this 1541 * case we opt to forcibly kill off all remaining requests on 1542 * context close. 1543 */ 1544 kill_context(ctx); 1545 1546 i915_gem_context_put(ctx); 1547 } 1548 1549 static int __context_set_persistence(struct i915_gem_context *ctx, bool state) 1550 { 1551 if (i915_gem_context_is_persistent(ctx) == state) 1552 return 0; 1553 1554 if (state) { 1555 /* 1556 * Only contexts that are short-lived [that will expire or be 1557 * reset] are allowed to survive past termination. We require 1558 * hangcheck to ensure that the persistent requests are healthy. 1559 */ 1560 if (!ctx->i915->params.enable_hangcheck) 1561 return -EINVAL; 1562 1563 i915_gem_context_set_persistence(ctx); 1564 } else { 1565 /* To cancel a context we use "preempt-to-idle" */ 1566 if (!(ctx->i915->caps.scheduler & I915_SCHEDULER_CAP_PREEMPTION)) 1567 return -ENODEV; 1568 1569 /* 1570 * If the cancel fails, we then need to reset, cleanly! 1571 * 1572 * If the per-engine reset fails, all hope is lost! We resort 1573 * to a full GPU reset in that unlikely case, but realistically 1574 * if the engine could not reset, the full reset does not fare 1575 * much better. The damage has been done. 1576 * 1577 * However, if we cannot reset an engine by itself, we cannot 1578 * cleanup a hanging persistent context without causing 1579 * colateral damage, and we should not pretend we can by 1580 * exposing the interface. 1581 */ 1582 if (!intel_has_reset_engine(to_gt(ctx->i915))) 1583 return -ENODEV; 1584 1585 i915_gem_context_clear_persistence(ctx); 1586 } 1587 1588 return 0; 1589 } 1590 1591 static struct i915_gem_context * 1592 i915_gem_create_context(struct drm_i915_private *i915, 1593 const struct i915_gem_proto_context *pc) 1594 { 1595 struct i915_gem_context *ctx; 1596 struct i915_address_space *vm = NULL; 1597 struct i915_gem_engines *e; 1598 int err; 1599 int i; 1600 1601 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 1602 if (!ctx) 1603 return ERR_PTR(-ENOMEM); 1604 1605 kref_init(&ctx->ref); 1606 ctx->i915 = i915; 1607 ctx->sched = pc->sched; 1608 mutex_init(&ctx->mutex); 1609 INIT_LIST_HEAD(&ctx->link); 1610 INIT_WORK(&ctx->release_work, i915_gem_context_release_work); 1611 1612 spin_lock_init(&ctx->stale.lock); 1613 INIT_LIST_HEAD(&ctx->stale.engines); 1614 1615 if (pc->vm) { 1616 vm = i915_vm_get(pc->vm); 1617 } else if (HAS_FULL_PPGTT(i915)) { 1618 struct i915_ppgtt *ppgtt; 1619 1620 ppgtt = i915_ppgtt_create(to_gt(i915), 0); 1621 if (IS_ERR(ppgtt)) { 1622 drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n", 1623 PTR_ERR(ppgtt)); 1624 err = PTR_ERR(ppgtt); 1625 goto err_ctx; 1626 } 1627 vm = &ppgtt->vm; 1628 } 1629 if (vm) 1630 ctx->vm = vm; 1631 1632 mutex_init(&ctx->engines_mutex); 1633 if (pc->num_user_engines >= 0) { 1634 i915_gem_context_set_user_engines(ctx); 1635 e = user_engines(ctx, pc->num_user_engines, pc->user_engines); 1636 } else { 1637 i915_gem_context_clear_user_engines(ctx); 1638 e = default_engines(ctx, pc->legacy_rcs_sseu); 1639 } 1640 if (IS_ERR(e)) { 1641 err = PTR_ERR(e); 1642 goto err_vm; 1643 } 1644 RCU_INIT_POINTER(ctx->engines, e); 1645 1646 INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL); 1647 mutex_init(&ctx->lut_mutex); 1648 1649 /* NB: Mark all slices as needing a remap so that when the context first 1650 * loads it will restore whatever remap state already exists. If there 1651 * is no remap info, it will be a NOP. */ 1652 ctx->remap_slice = ALL_L3_SLICES(i915); 1653 1654 ctx->user_flags = pc->user_flags; 1655 1656 for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++) 1657 ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES; 1658 1659 if (pc->single_timeline) { 1660 err = drm_syncobj_create(&ctx->syncobj, 1661 DRM_SYNCOBJ_CREATE_SIGNALED, 1662 NULL); 1663 if (err) 1664 goto err_engines; 1665 } 1666 1667 if (pc->uses_protected_content) { 1668 ctx->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm); 1669 ctx->uses_protected_content = true; 1670 } 1671 1672 trace_i915_context_create(ctx); 1673 1674 return ctx; 1675 1676 err_engines: 1677 free_engines(e); 1678 err_vm: 1679 if (ctx->vm) 1680 i915_vm_put(ctx->vm); 1681 err_ctx: 1682 kfree(ctx); 1683 return ERR_PTR(err); 1684 } 1685 1686 static void init_contexts(struct i915_gem_contexts *gc) 1687 { 1688 spin_lock_init(&gc->lock); 1689 INIT_LIST_HEAD(&gc->list); 1690 } 1691 1692 void i915_gem_init__contexts(struct drm_i915_private *i915) 1693 { 1694 init_contexts(&i915->gem.contexts); 1695 } 1696 1697 static void gem_context_register(struct i915_gem_context *ctx, 1698 struct drm_i915_file_private *fpriv, 1699 u32 id) 1700 { 1701 struct drm_i915_private *i915 = ctx->i915; 1702 void *old; 1703 1704 ctx->file_priv = fpriv; 1705 1706 ctx->pid = get_task_pid(current, PIDTYPE_PID); 1707 ctx->client = i915_drm_client_get(fpriv->client); 1708 1709 snprintf(ctx->name, sizeof(ctx->name), "%s[%d]", 1710 current->comm, pid_nr(ctx->pid)); 1711 1712 /* And finally expose ourselves to userspace via the idr */ 1713 old = xa_store(&fpriv->context_xa, id, ctx, GFP_KERNEL); 1714 WARN_ON(old); 1715 1716 spin_lock(&ctx->client->ctx_lock); 1717 list_add_tail_rcu(&ctx->client_link, &ctx->client->ctx_list); 1718 spin_unlock(&ctx->client->ctx_lock); 1719 1720 spin_lock(&i915->gem.contexts.lock); 1721 list_add_tail(&ctx->link, &i915->gem.contexts.list); 1722 spin_unlock(&i915->gem.contexts.lock); 1723 } 1724 1725 int i915_gem_context_open(struct drm_i915_private *i915, 1726 struct drm_file *file) 1727 { 1728 struct drm_i915_file_private *file_priv = file->driver_priv; 1729 struct i915_gem_proto_context *pc; 1730 struct i915_gem_context *ctx; 1731 int err; 1732 1733 mutex_init(&file_priv->proto_context_lock); 1734 xa_init_flags(&file_priv->proto_context_xa, XA_FLAGS_ALLOC); 1735 1736 /* 0 reserved for the default context */ 1737 xa_init_flags(&file_priv->context_xa, XA_FLAGS_ALLOC1); 1738 1739 /* 0 reserved for invalid/unassigned ppgtt */ 1740 xa_init_flags(&file_priv->vm_xa, XA_FLAGS_ALLOC1); 1741 1742 pc = proto_context_create(i915, 0); 1743 if (IS_ERR(pc)) { 1744 err = PTR_ERR(pc); 1745 goto err; 1746 } 1747 1748 ctx = i915_gem_create_context(i915, pc); 1749 proto_context_close(i915, pc); 1750 if (IS_ERR(ctx)) { 1751 err = PTR_ERR(ctx); 1752 goto err; 1753 } 1754 1755 gem_context_register(ctx, file_priv, 0); 1756 1757 return 0; 1758 1759 err: 1760 xa_destroy(&file_priv->vm_xa); 1761 xa_destroy(&file_priv->context_xa); 1762 xa_destroy(&file_priv->proto_context_xa); 1763 mutex_destroy(&file_priv->proto_context_lock); 1764 return err; 1765 } 1766 1767 void i915_gem_context_close(struct drm_file *file) 1768 { 1769 struct drm_i915_file_private *file_priv = file->driver_priv; 1770 struct i915_gem_proto_context *pc; 1771 struct i915_address_space *vm; 1772 struct i915_gem_context *ctx; 1773 unsigned long idx; 1774 1775 xa_for_each(&file_priv->proto_context_xa, idx, pc) 1776 proto_context_close(file_priv->dev_priv, pc); 1777 xa_destroy(&file_priv->proto_context_xa); 1778 mutex_destroy(&file_priv->proto_context_lock); 1779 1780 xa_for_each(&file_priv->context_xa, idx, ctx) 1781 context_close(ctx); 1782 xa_destroy(&file_priv->context_xa); 1783 1784 xa_for_each(&file_priv->vm_xa, idx, vm) 1785 i915_vm_put(vm); 1786 xa_destroy(&file_priv->vm_xa); 1787 } 1788 1789 int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data, 1790 struct drm_file *file) 1791 { 1792 struct drm_i915_private *i915 = to_i915(dev); 1793 struct drm_i915_gem_vm_control *args = data; 1794 struct drm_i915_file_private *file_priv = file->driver_priv; 1795 struct i915_ppgtt *ppgtt; 1796 u32 id; 1797 int err; 1798 1799 if (!HAS_FULL_PPGTT(i915)) 1800 return -ENODEV; 1801 1802 if (args->flags) 1803 return -EINVAL; 1804 1805 ppgtt = i915_ppgtt_create(to_gt(i915), 0); 1806 if (IS_ERR(ppgtt)) 1807 return PTR_ERR(ppgtt); 1808 1809 if (args->extensions) { 1810 err = i915_user_extensions(u64_to_user_ptr(args->extensions), 1811 NULL, 0, 1812 ppgtt); 1813 if (err) 1814 goto err_put; 1815 } 1816 1817 err = xa_alloc(&file_priv->vm_xa, &id, &ppgtt->vm, 1818 xa_limit_32b, GFP_KERNEL); 1819 if (err) 1820 goto err_put; 1821 1822 GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */ 1823 args->vm_id = id; 1824 return 0; 1825 1826 err_put: 1827 i915_vm_put(&ppgtt->vm); 1828 return err; 1829 } 1830 1831 int i915_gem_vm_destroy_ioctl(struct drm_device *dev, void *data, 1832 struct drm_file *file) 1833 { 1834 struct drm_i915_file_private *file_priv = file->driver_priv; 1835 struct drm_i915_gem_vm_control *args = data; 1836 struct i915_address_space *vm; 1837 1838 if (args->flags) 1839 return -EINVAL; 1840 1841 if (args->extensions) 1842 return -EINVAL; 1843 1844 vm = xa_erase(&file_priv->vm_xa, args->vm_id); 1845 if (!vm) 1846 return -ENOENT; 1847 1848 i915_vm_put(vm); 1849 return 0; 1850 } 1851 1852 static int get_ppgtt(struct drm_i915_file_private *file_priv, 1853 struct i915_gem_context *ctx, 1854 struct drm_i915_gem_context_param *args) 1855 { 1856 struct i915_address_space *vm; 1857 int err; 1858 u32 id; 1859 1860 if (!i915_gem_context_has_full_ppgtt(ctx)) 1861 return -ENODEV; 1862 1863 vm = ctx->vm; 1864 GEM_BUG_ON(!vm); 1865 1866 err = xa_alloc(&file_priv->vm_xa, &id, vm, xa_limit_32b, GFP_KERNEL); 1867 if (err) 1868 return err; 1869 1870 i915_vm_get(vm); 1871 1872 GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */ 1873 args->value = id; 1874 args->size = 0; 1875 1876 return err; 1877 } 1878 1879 int 1880 i915_gem_user_to_context_sseu(struct intel_gt *gt, 1881 const struct drm_i915_gem_context_param_sseu *user, 1882 struct intel_sseu *context) 1883 { 1884 const struct sseu_dev_info *device = >->info.sseu; 1885 struct drm_i915_private *i915 = gt->i915; 1886 unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0); 1887 1888 /* No zeros in any field. */ 1889 if (!user->slice_mask || !user->subslice_mask || 1890 !user->min_eus_per_subslice || !user->max_eus_per_subslice) 1891 return -EINVAL; 1892 1893 /* Max > min. */ 1894 if (user->max_eus_per_subslice < user->min_eus_per_subslice) 1895 return -EINVAL; 1896 1897 /* 1898 * Some future proofing on the types since the uAPI is wider than the 1899 * current internal implementation. 1900 */ 1901 if (overflows_type(user->slice_mask, context->slice_mask) || 1902 overflows_type(user->subslice_mask, context->subslice_mask) || 1903 overflows_type(user->min_eus_per_subslice, 1904 context->min_eus_per_subslice) || 1905 overflows_type(user->max_eus_per_subslice, 1906 context->max_eus_per_subslice)) 1907 return -EINVAL; 1908 1909 /* Check validity against hardware. */ 1910 if (user->slice_mask & ~device->slice_mask) 1911 return -EINVAL; 1912 1913 if (user->subslice_mask & ~dev_subslice_mask) 1914 return -EINVAL; 1915 1916 if (user->max_eus_per_subslice > device->max_eus_per_subslice) 1917 return -EINVAL; 1918 1919 context->slice_mask = user->slice_mask; 1920 context->subslice_mask = user->subslice_mask; 1921 context->min_eus_per_subslice = user->min_eus_per_subslice; 1922 context->max_eus_per_subslice = user->max_eus_per_subslice; 1923 1924 /* Part specific restrictions. */ 1925 if (GRAPHICS_VER(i915) == 11) { 1926 unsigned int hw_s = hweight8(device->slice_mask); 1927 unsigned int hw_ss_per_s = hweight8(dev_subslice_mask); 1928 unsigned int req_s = hweight8(context->slice_mask); 1929 unsigned int req_ss = hweight8(context->subslice_mask); 1930 1931 /* 1932 * Only full subslice enablement is possible if more than one 1933 * slice is turned on. 1934 */ 1935 if (req_s > 1 && req_ss != hw_ss_per_s) 1936 return -EINVAL; 1937 1938 /* 1939 * If more than four (SScount bitfield limit) subslices are 1940 * requested then the number has to be even. 1941 */ 1942 if (req_ss > 4 && (req_ss & 1)) 1943 return -EINVAL; 1944 1945 /* 1946 * If only one slice is enabled and subslice count is below the 1947 * device full enablement, it must be at most half of the all 1948 * available subslices. 1949 */ 1950 if (req_s == 1 && req_ss < hw_ss_per_s && 1951 req_ss > (hw_ss_per_s / 2)) 1952 return -EINVAL; 1953 1954 /* ABI restriction - VME use case only. */ 1955 1956 /* All slices or one slice only. */ 1957 if (req_s != 1 && req_s != hw_s) 1958 return -EINVAL; 1959 1960 /* 1961 * Half subslices or full enablement only when one slice is 1962 * enabled. 1963 */ 1964 if (req_s == 1 && 1965 (req_ss != hw_ss_per_s && req_ss != (hw_ss_per_s / 2))) 1966 return -EINVAL; 1967 1968 /* No EU configuration changes. */ 1969 if ((user->min_eus_per_subslice != 1970 device->max_eus_per_subslice) || 1971 (user->max_eus_per_subslice != 1972 device->max_eus_per_subslice)) 1973 return -EINVAL; 1974 } 1975 1976 return 0; 1977 } 1978 1979 static int set_sseu(struct i915_gem_context *ctx, 1980 struct drm_i915_gem_context_param *args) 1981 { 1982 struct drm_i915_private *i915 = ctx->i915; 1983 struct drm_i915_gem_context_param_sseu user_sseu; 1984 struct intel_context *ce; 1985 struct intel_sseu sseu; 1986 unsigned long lookup; 1987 int ret; 1988 1989 if (args->size < sizeof(user_sseu)) 1990 return -EINVAL; 1991 1992 if (GRAPHICS_VER(i915) != 11) 1993 return -ENODEV; 1994 1995 if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value), 1996 sizeof(user_sseu))) 1997 return -EFAULT; 1998 1999 if (user_sseu.rsvd) 2000 return -EINVAL; 2001 2002 if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)) 2003 return -EINVAL; 2004 2005 lookup = 0; 2006 if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX) 2007 lookup |= LOOKUP_USER_INDEX; 2008 2009 ce = lookup_user_engine(ctx, lookup, &user_sseu.engine); 2010 if (IS_ERR(ce)) 2011 return PTR_ERR(ce); 2012 2013 /* Only render engine supports RPCS configuration. */ 2014 if (ce->engine->class != RENDER_CLASS) { 2015 ret = -ENODEV; 2016 goto out_ce; 2017 } 2018 2019 ret = i915_gem_user_to_context_sseu(ce->engine->gt, &user_sseu, &sseu); 2020 if (ret) 2021 goto out_ce; 2022 2023 ret = intel_context_reconfigure_sseu(ce, sseu); 2024 if (ret) 2025 goto out_ce; 2026 2027 args->size = sizeof(user_sseu); 2028 2029 out_ce: 2030 intel_context_put(ce); 2031 return ret; 2032 } 2033 2034 static int 2035 set_persistence(struct i915_gem_context *ctx, 2036 const struct drm_i915_gem_context_param *args) 2037 { 2038 if (args->size) 2039 return -EINVAL; 2040 2041 return __context_set_persistence(ctx, args->value); 2042 } 2043 2044 static int set_priority(struct i915_gem_context *ctx, 2045 const struct drm_i915_gem_context_param *args) 2046 { 2047 struct i915_gem_engines_iter it; 2048 struct intel_context *ce; 2049 int err; 2050 2051 err = validate_priority(ctx->i915, args); 2052 if (err) 2053 return err; 2054 2055 ctx->sched.priority = args->value; 2056 2057 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) { 2058 if (!intel_engine_has_timeslices(ce->engine)) 2059 continue; 2060 2061 if (ctx->sched.priority >= I915_PRIORITY_NORMAL && 2062 intel_engine_has_semaphores(ce->engine)) 2063 intel_context_set_use_semaphores(ce); 2064 else 2065 intel_context_clear_use_semaphores(ce); 2066 } 2067 i915_gem_context_unlock_engines(ctx); 2068 2069 return 0; 2070 } 2071 2072 static int get_protected(struct i915_gem_context *ctx, 2073 struct drm_i915_gem_context_param *args) 2074 { 2075 args->size = 0; 2076 args->value = i915_gem_context_uses_protected_content(ctx); 2077 2078 return 0; 2079 } 2080 2081 static int ctx_setparam(struct drm_i915_file_private *fpriv, 2082 struct i915_gem_context *ctx, 2083 struct drm_i915_gem_context_param *args) 2084 { 2085 int ret = 0; 2086 2087 switch (args->param) { 2088 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: 2089 if (args->size) 2090 ret = -EINVAL; 2091 else if (args->value) 2092 i915_gem_context_set_no_error_capture(ctx); 2093 else 2094 i915_gem_context_clear_no_error_capture(ctx); 2095 break; 2096 2097 case I915_CONTEXT_PARAM_BANNABLE: 2098 if (args->size) 2099 ret = -EINVAL; 2100 else if (!capable(CAP_SYS_ADMIN) && !args->value) 2101 ret = -EPERM; 2102 else if (args->value) 2103 i915_gem_context_set_bannable(ctx); 2104 else if (i915_gem_context_uses_protected_content(ctx)) 2105 ret = -EPERM; /* can't clear this for protected contexts */ 2106 else 2107 i915_gem_context_clear_bannable(ctx); 2108 break; 2109 2110 case I915_CONTEXT_PARAM_RECOVERABLE: 2111 if (args->size) 2112 ret = -EINVAL; 2113 else if (!args->value) 2114 i915_gem_context_clear_recoverable(ctx); 2115 else if (i915_gem_context_uses_protected_content(ctx)) 2116 ret = -EPERM; /* can't set this for protected contexts */ 2117 else 2118 i915_gem_context_set_recoverable(ctx); 2119 break; 2120 2121 case I915_CONTEXT_PARAM_PRIORITY: 2122 ret = set_priority(ctx, args); 2123 break; 2124 2125 case I915_CONTEXT_PARAM_SSEU: 2126 ret = set_sseu(ctx, args); 2127 break; 2128 2129 case I915_CONTEXT_PARAM_PERSISTENCE: 2130 ret = set_persistence(ctx, args); 2131 break; 2132 2133 case I915_CONTEXT_PARAM_PROTECTED_CONTENT: 2134 case I915_CONTEXT_PARAM_NO_ZEROMAP: 2135 case I915_CONTEXT_PARAM_BAN_PERIOD: 2136 case I915_CONTEXT_PARAM_RINGSIZE: 2137 case I915_CONTEXT_PARAM_VM: 2138 case I915_CONTEXT_PARAM_ENGINES: 2139 default: 2140 ret = -EINVAL; 2141 break; 2142 } 2143 2144 return ret; 2145 } 2146 2147 struct create_ext { 2148 struct i915_gem_proto_context *pc; 2149 struct drm_i915_file_private *fpriv; 2150 }; 2151 2152 static int create_setparam(struct i915_user_extension __user *ext, void *data) 2153 { 2154 struct drm_i915_gem_context_create_ext_setparam local; 2155 const struct create_ext *arg = data; 2156 2157 if (copy_from_user(&local, ext, sizeof(local))) 2158 return -EFAULT; 2159 2160 if (local.param.ctx_id) 2161 return -EINVAL; 2162 2163 return set_proto_ctx_param(arg->fpriv, arg->pc, &local.param); 2164 } 2165 2166 static int invalid_ext(struct i915_user_extension __user *ext, void *data) 2167 { 2168 return -EINVAL; 2169 } 2170 2171 static const i915_user_extension_fn create_extensions[] = { 2172 [I915_CONTEXT_CREATE_EXT_SETPARAM] = create_setparam, 2173 [I915_CONTEXT_CREATE_EXT_CLONE] = invalid_ext, 2174 }; 2175 2176 static bool client_is_banned(struct drm_i915_file_private *file_priv) 2177 { 2178 return atomic_read(&file_priv->ban_score) >= I915_CLIENT_SCORE_BANNED; 2179 } 2180 2181 static inline struct i915_gem_context * 2182 __context_lookup(struct drm_i915_file_private *file_priv, u32 id) 2183 { 2184 struct i915_gem_context *ctx; 2185 2186 rcu_read_lock(); 2187 ctx = xa_load(&file_priv->context_xa, id); 2188 if (ctx && !kref_get_unless_zero(&ctx->ref)) 2189 ctx = NULL; 2190 rcu_read_unlock(); 2191 2192 return ctx; 2193 } 2194 2195 static struct i915_gem_context * 2196 finalize_create_context_locked(struct drm_i915_file_private *file_priv, 2197 struct i915_gem_proto_context *pc, u32 id) 2198 { 2199 struct i915_gem_context *ctx; 2200 void *old; 2201 2202 lockdep_assert_held(&file_priv->proto_context_lock); 2203 2204 ctx = i915_gem_create_context(file_priv->dev_priv, pc); 2205 if (IS_ERR(ctx)) 2206 return ctx; 2207 2208 gem_context_register(ctx, file_priv, id); 2209 2210 old = xa_erase(&file_priv->proto_context_xa, id); 2211 GEM_BUG_ON(old != pc); 2212 proto_context_close(file_priv->dev_priv, pc); 2213 2214 /* One for the xarray and one for the caller */ 2215 return i915_gem_context_get(ctx); 2216 } 2217 2218 struct i915_gem_context * 2219 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) 2220 { 2221 struct i915_gem_proto_context *pc; 2222 struct i915_gem_context *ctx; 2223 2224 ctx = __context_lookup(file_priv, id); 2225 if (ctx) 2226 return ctx; 2227 2228 mutex_lock(&file_priv->proto_context_lock); 2229 /* Try one more time under the lock */ 2230 ctx = __context_lookup(file_priv, id); 2231 if (!ctx) { 2232 pc = xa_load(&file_priv->proto_context_xa, id); 2233 if (!pc) 2234 ctx = ERR_PTR(-ENOENT); 2235 else 2236 ctx = finalize_create_context_locked(file_priv, pc, id); 2237 } 2238 mutex_unlock(&file_priv->proto_context_lock); 2239 2240 return ctx; 2241 } 2242 2243 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 2244 struct drm_file *file) 2245 { 2246 struct drm_i915_private *i915 = to_i915(dev); 2247 struct drm_i915_gem_context_create_ext *args = data; 2248 struct create_ext ext_data; 2249 int ret; 2250 u32 id; 2251 2252 if (!DRIVER_CAPS(i915)->has_logical_contexts) 2253 return -ENODEV; 2254 2255 if (args->flags & I915_CONTEXT_CREATE_FLAGS_UNKNOWN) 2256 return -EINVAL; 2257 2258 ret = intel_gt_terminally_wedged(to_gt(i915)); 2259 if (ret) 2260 return ret; 2261 2262 ext_data.fpriv = file->driver_priv; 2263 if (client_is_banned(ext_data.fpriv)) { 2264 drm_dbg(&i915->drm, 2265 "client %s[%d] banned from creating ctx\n", 2266 current->comm, task_pid_nr(current)); 2267 return -EIO; 2268 } 2269 2270 ext_data.pc = proto_context_create(i915, args->flags); 2271 if (IS_ERR(ext_data.pc)) 2272 return PTR_ERR(ext_data.pc); 2273 2274 if (args->flags & I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS) { 2275 ret = i915_user_extensions(u64_to_user_ptr(args->extensions), 2276 create_extensions, 2277 ARRAY_SIZE(create_extensions), 2278 &ext_data); 2279 if (ret) 2280 goto err_pc; 2281 } 2282 2283 if (GRAPHICS_VER(i915) > 12) { 2284 struct i915_gem_context *ctx; 2285 2286 /* Get ourselves a context ID */ 2287 ret = xa_alloc(&ext_data.fpriv->context_xa, &id, NULL, 2288 xa_limit_32b, GFP_KERNEL); 2289 if (ret) 2290 goto err_pc; 2291 2292 ctx = i915_gem_create_context(i915, ext_data.pc); 2293 if (IS_ERR(ctx)) { 2294 ret = PTR_ERR(ctx); 2295 goto err_pc; 2296 } 2297 2298 proto_context_close(i915, ext_data.pc); 2299 gem_context_register(ctx, ext_data.fpriv, id); 2300 } else { 2301 ret = proto_context_register(ext_data.fpriv, ext_data.pc, &id); 2302 if (ret < 0) 2303 goto err_pc; 2304 } 2305 2306 args->ctx_id = id; 2307 drm_dbg(&i915->drm, "HW context %d created\n", args->ctx_id); 2308 2309 return 0; 2310 2311 err_pc: 2312 proto_context_close(i915, ext_data.pc); 2313 return ret; 2314 } 2315 2316 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 2317 struct drm_file *file) 2318 { 2319 struct drm_i915_gem_context_destroy *args = data; 2320 struct drm_i915_file_private *file_priv = file->driver_priv; 2321 struct i915_gem_proto_context *pc; 2322 struct i915_gem_context *ctx; 2323 2324 if (args->pad != 0) 2325 return -EINVAL; 2326 2327 if (!args->ctx_id) 2328 return -ENOENT; 2329 2330 /* We need to hold the proto-context lock here to prevent races 2331 * with finalize_create_context_locked(). 2332 */ 2333 mutex_lock(&file_priv->proto_context_lock); 2334 ctx = xa_erase(&file_priv->context_xa, args->ctx_id); 2335 pc = xa_erase(&file_priv->proto_context_xa, args->ctx_id); 2336 mutex_unlock(&file_priv->proto_context_lock); 2337 2338 if (!ctx && !pc) 2339 return -ENOENT; 2340 GEM_WARN_ON(ctx && pc); 2341 2342 if (pc) 2343 proto_context_close(file_priv->dev_priv, pc); 2344 2345 if (ctx) 2346 context_close(ctx); 2347 2348 return 0; 2349 } 2350 2351 static int get_sseu(struct i915_gem_context *ctx, 2352 struct drm_i915_gem_context_param *args) 2353 { 2354 struct drm_i915_gem_context_param_sseu user_sseu; 2355 struct intel_context *ce; 2356 unsigned long lookup; 2357 int err; 2358 2359 if (args->size == 0) 2360 goto out; 2361 else if (args->size < sizeof(user_sseu)) 2362 return -EINVAL; 2363 2364 if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value), 2365 sizeof(user_sseu))) 2366 return -EFAULT; 2367 2368 if (user_sseu.rsvd) 2369 return -EINVAL; 2370 2371 if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)) 2372 return -EINVAL; 2373 2374 lookup = 0; 2375 if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX) 2376 lookup |= LOOKUP_USER_INDEX; 2377 2378 ce = lookup_user_engine(ctx, lookup, &user_sseu.engine); 2379 if (IS_ERR(ce)) 2380 return PTR_ERR(ce); 2381 2382 err = intel_context_lock_pinned(ce); /* serialises with set_sseu */ 2383 if (err) { 2384 intel_context_put(ce); 2385 return err; 2386 } 2387 2388 user_sseu.slice_mask = ce->sseu.slice_mask; 2389 user_sseu.subslice_mask = ce->sseu.subslice_mask; 2390 user_sseu.min_eus_per_subslice = ce->sseu.min_eus_per_subslice; 2391 user_sseu.max_eus_per_subslice = ce->sseu.max_eus_per_subslice; 2392 2393 intel_context_unlock_pinned(ce); 2394 intel_context_put(ce); 2395 2396 if (copy_to_user(u64_to_user_ptr(args->value), &user_sseu, 2397 sizeof(user_sseu))) 2398 return -EFAULT; 2399 2400 out: 2401 args->size = sizeof(user_sseu); 2402 2403 return 0; 2404 } 2405 2406 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, 2407 struct drm_file *file) 2408 { 2409 struct drm_i915_file_private *file_priv = file->driver_priv; 2410 struct drm_i915_gem_context_param *args = data; 2411 struct i915_gem_context *ctx; 2412 struct i915_address_space *vm; 2413 int ret = 0; 2414 2415 ctx = i915_gem_context_lookup(file_priv, args->ctx_id); 2416 if (IS_ERR(ctx)) 2417 return PTR_ERR(ctx); 2418 2419 switch (args->param) { 2420 case I915_CONTEXT_PARAM_GTT_SIZE: 2421 args->size = 0; 2422 vm = i915_gem_context_get_eb_vm(ctx); 2423 args->value = vm->total; 2424 i915_vm_put(vm); 2425 2426 break; 2427 2428 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: 2429 args->size = 0; 2430 args->value = i915_gem_context_no_error_capture(ctx); 2431 break; 2432 2433 case I915_CONTEXT_PARAM_BANNABLE: 2434 args->size = 0; 2435 args->value = i915_gem_context_is_bannable(ctx); 2436 break; 2437 2438 case I915_CONTEXT_PARAM_RECOVERABLE: 2439 args->size = 0; 2440 args->value = i915_gem_context_is_recoverable(ctx); 2441 break; 2442 2443 case I915_CONTEXT_PARAM_PRIORITY: 2444 args->size = 0; 2445 args->value = ctx->sched.priority; 2446 break; 2447 2448 case I915_CONTEXT_PARAM_SSEU: 2449 ret = get_sseu(ctx, args); 2450 break; 2451 2452 case I915_CONTEXT_PARAM_VM: 2453 ret = get_ppgtt(file_priv, ctx, args); 2454 break; 2455 2456 case I915_CONTEXT_PARAM_PERSISTENCE: 2457 args->size = 0; 2458 args->value = i915_gem_context_is_persistent(ctx); 2459 break; 2460 2461 case I915_CONTEXT_PARAM_PROTECTED_CONTENT: 2462 ret = get_protected(ctx, args); 2463 break; 2464 2465 case I915_CONTEXT_PARAM_NO_ZEROMAP: 2466 case I915_CONTEXT_PARAM_BAN_PERIOD: 2467 case I915_CONTEXT_PARAM_ENGINES: 2468 case I915_CONTEXT_PARAM_RINGSIZE: 2469 default: 2470 ret = -EINVAL; 2471 break; 2472 } 2473 2474 i915_gem_context_put(ctx); 2475 return ret; 2476 } 2477 2478 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, 2479 struct drm_file *file) 2480 { 2481 struct drm_i915_file_private *file_priv = file->driver_priv; 2482 struct drm_i915_gem_context_param *args = data; 2483 struct i915_gem_proto_context *pc; 2484 struct i915_gem_context *ctx; 2485 int ret = 0; 2486 2487 mutex_lock(&file_priv->proto_context_lock); 2488 ctx = __context_lookup(file_priv, args->ctx_id); 2489 if (!ctx) { 2490 pc = xa_load(&file_priv->proto_context_xa, args->ctx_id); 2491 if (pc) { 2492 /* Contexts should be finalized inside 2493 * GEM_CONTEXT_CREATE starting with graphics 2494 * version 13. 2495 */ 2496 WARN_ON(GRAPHICS_VER(file_priv->dev_priv) > 12); 2497 ret = set_proto_ctx_param(file_priv, pc, args); 2498 } else { 2499 ret = -ENOENT; 2500 } 2501 } 2502 mutex_unlock(&file_priv->proto_context_lock); 2503 2504 if (ctx) { 2505 ret = ctx_setparam(file_priv, ctx, args); 2506 i915_gem_context_put(ctx); 2507 } 2508 2509 return ret; 2510 } 2511 2512 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, 2513 void *data, struct drm_file *file) 2514 { 2515 struct drm_i915_private *i915 = to_i915(dev); 2516 struct drm_i915_reset_stats *args = data; 2517 struct i915_gem_context *ctx; 2518 2519 if (args->flags || args->pad) 2520 return -EINVAL; 2521 2522 ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id); 2523 if (IS_ERR(ctx)) 2524 return PTR_ERR(ctx); 2525 2526 /* 2527 * We opt for unserialised reads here. This may result in tearing 2528 * in the extremely unlikely event of a GPU hang on this context 2529 * as we are querying them. If we need that extra layer of protection, 2530 * we should wrap the hangstats with a seqlock. 2531 */ 2532 2533 if (capable(CAP_SYS_ADMIN)) 2534 args->reset_count = i915_reset_count(&i915->gpu_error); 2535 else 2536 args->reset_count = 0; 2537 2538 args->batch_active = atomic_read(&ctx->guilty_count); 2539 args->batch_pending = atomic_read(&ctx->active_count); 2540 2541 i915_gem_context_put(ctx); 2542 return 0; 2543 } 2544 2545 /* GEM context-engines iterator: for_each_gem_engine() */ 2546 struct intel_context * 2547 i915_gem_engines_iter_next(struct i915_gem_engines_iter *it) 2548 { 2549 const struct i915_gem_engines *e = it->engines; 2550 struct intel_context *ctx; 2551 2552 if (unlikely(!e)) 2553 return NULL; 2554 2555 do { 2556 if (it->idx >= e->num_engines) 2557 return NULL; 2558 2559 ctx = e->engines[it->idx++]; 2560 } while (!ctx); 2561 2562 return ctx; 2563 } 2564 2565 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2566 #include "selftests/mock_context.c" 2567 #include "selftests/i915_gem_context.c" 2568 #endif 2569 2570 void i915_gem_context_module_exit(void) 2571 { 2572 kmem_cache_destroy(slab_luts); 2573 } 2574 2575 int __init i915_gem_context_module_init(void) 2576 { 2577 slab_luts = KMEM_CACHE(i915_lut_handle, 0); 2578 if (!slab_luts) 2579 return -ENOMEM; 2580 2581 return 0; 2582 } 2583