1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2011-2012 Intel Corporation 5 */ 6 7 /* 8 * This file implements HW context support. On gen5+ a HW context consists of an 9 * opaque GPU object which is referenced at times of context saves and restores. 10 * With RC6 enabled, the context is also referenced as the GPU enters and exists 11 * from RC6 (GPU has it's own internal power context, except on gen5). Though 12 * something like a context does exist for the media ring, the code only 13 * supports contexts for the render ring. 14 * 15 * In software, there is a distinction between contexts created by the user, 16 * and the default HW context. The default HW context is used by GPU clients 17 * that do not request setup of their own hardware context. The default 18 * context's state is never restored to help prevent programming errors. This 19 * would happen if a client ran and piggy-backed off another clients GPU state. 20 * The default context only exists to give the GPU some offset to load as the 21 * current to invoke a save of the context we actually care about. In fact, the 22 * code could likely be constructed, albeit in a more complicated fashion, to 23 * never use the default context, though that limits the driver's ability to 24 * swap out, and/or destroy other contexts. 25 * 26 * All other contexts are created as a request by the GPU client. These contexts 27 * store GPU state, and thus allow GPU clients to not re-emit state (and 28 * potentially query certain state) at any time. The kernel driver makes 29 * certain that the appropriate commands are inserted. 30 * 31 * The context life cycle is semi-complicated in that context BOs may live 32 * longer than the context itself because of the way the hardware, and object 33 * tracking works. Below is a very crude representation of the state machine 34 * describing the context life. 35 * refcount pincount active 36 * S0: initial state 0 0 0 37 * S1: context created 1 0 0 38 * S2: context is currently running 2 1 X 39 * S3: GPU referenced, but not current 2 0 1 40 * S4: context is current, but destroyed 1 1 0 41 * S5: like S3, but destroyed 1 0 1 42 * 43 * The most common (but not all) transitions: 44 * S0->S1: client creates a context 45 * S1->S2: client submits execbuf with context 46 * S2->S3: other clients submits execbuf with context 47 * S3->S1: context object was retired 48 * S3->S2: clients submits another execbuf 49 * S2->S4: context destroy called with current context 50 * S3->S5->S0: destroy path 51 * S4->S5->S0: destroy path on current context 52 * 53 * There are two confusing terms used above: 54 * The "current context" means the context which is currently running on the 55 * GPU. The GPU has loaded its state already and has stored away the gtt 56 * offset of the BO. The GPU is not actively referencing the data at this 57 * offset, but it will on the next context switch. The only way to avoid this 58 * is to do a GPU reset. 59 * 60 * An "active context' is one which was previously the "current context" and is 61 * on the active list waiting for the next context switch to occur. Until this 62 * happens, the object must remain at the same gtt offset. It is therefore 63 * possible to destroy a context, but it is still active. 64 * 65 */ 66 67 #include <linux/log2.h> 68 #include <linux/nospec.h> 69 70 #include <drm/i915_drm.h> 71 72 #include "gt/intel_lrc_reg.h" 73 #include "gt/intel_engine_user.h" 74 75 #include "i915_gem_context.h" 76 #include "i915_globals.h" 77 #include "i915_trace.h" 78 #include "i915_user_extensions.h" 79 80 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 81 82 static struct i915_global_gem_context { 83 struct i915_global base; 84 struct kmem_cache *slab_luts; 85 } global; 86 87 struct i915_lut_handle *i915_lut_handle_alloc(void) 88 { 89 return kmem_cache_alloc(global.slab_luts, GFP_KERNEL); 90 } 91 92 void i915_lut_handle_free(struct i915_lut_handle *lut) 93 { 94 return kmem_cache_free(global.slab_luts, lut); 95 } 96 97 static void lut_close(struct i915_gem_context *ctx) 98 { 99 struct radix_tree_iter iter; 100 void __rcu **slot; 101 102 lockdep_assert_held(&ctx->mutex); 103 104 rcu_read_lock(); 105 radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) { 106 struct i915_vma *vma = rcu_dereference_raw(*slot); 107 struct drm_i915_gem_object *obj = vma->obj; 108 struct i915_lut_handle *lut; 109 110 if (!kref_get_unless_zero(&obj->base.refcount)) 111 continue; 112 113 rcu_read_unlock(); 114 i915_gem_object_lock(obj); 115 list_for_each_entry(lut, &obj->lut_list, obj_link) { 116 if (lut->ctx != ctx) 117 continue; 118 119 if (lut->handle != iter.index) 120 continue; 121 122 list_del(&lut->obj_link); 123 break; 124 } 125 i915_gem_object_unlock(obj); 126 rcu_read_lock(); 127 128 if (&lut->obj_link != &obj->lut_list) { 129 i915_lut_handle_free(lut); 130 radix_tree_iter_delete(&ctx->handles_vma, &iter, slot); 131 if (atomic_dec_and_test(&vma->open_count) && 132 !i915_vma_is_ggtt(vma)) 133 i915_vma_close(vma); 134 i915_gem_object_put(obj); 135 } 136 137 i915_gem_object_put(obj); 138 } 139 rcu_read_unlock(); 140 } 141 142 static struct intel_context * 143 lookup_user_engine(struct i915_gem_context *ctx, 144 unsigned long flags, 145 const struct i915_engine_class_instance *ci) 146 #define LOOKUP_USER_INDEX BIT(0) 147 { 148 int idx; 149 150 if (!!(flags & LOOKUP_USER_INDEX) != i915_gem_context_user_engines(ctx)) 151 return ERR_PTR(-EINVAL); 152 153 if (!i915_gem_context_user_engines(ctx)) { 154 struct intel_engine_cs *engine; 155 156 engine = intel_engine_lookup_user(ctx->i915, 157 ci->engine_class, 158 ci->engine_instance); 159 if (!engine) 160 return ERR_PTR(-EINVAL); 161 162 idx = engine->legacy_idx; 163 } else { 164 idx = ci->engine_instance; 165 } 166 167 return i915_gem_context_get_engine(ctx, idx); 168 } 169 170 static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp) 171 { 172 unsigned int max; 173 174 lockdep_assert_held(&i915->contexts.mutex); 175 176 if (INTEL_GEN(i915) >= 12) 177 max = GEN12_MAX_CONTEXT_HW_ID; 178 else if (INTEL_GEN(i915) >= 11) 179 max = GEN11_MAX_CONTEXT_HW_ID; 180 else if (USES_GUC_SUBMISSION(i915)) 181 /* 182 * When using GuC in proxy submission, GuC consumes the 183 * highest bit in the context id to indicate proxy submission. 184 */ 185 max = MAX_GUC_CONTEXT_HW_ID; 186 else 187 max = MAX_CONTEXT_HW_ID; 188 189 return ida_simple_get(&i915->contexts.hw_ida, 0, max, gfp); 190 } 191 192 static int steal_hw_id(struct drm_i915_private *i915) 193 { 194 struct i915_gem_context *ctx, *cn; 195 LIST_HEAD(pinned); 196 int id = -ENOSPC; 197 198 lockdep_assert_held(&i915->contexts.mutex); 199 200 list_for_each_entry_safe(ctx, cn, 201 &i915->contexts.hw_id_list, hw_id_link) { 202 if (atomic_read(&ctx->hw_id_pin_count)) { 203 list_move_tail(&ctx->hw_id_link, &pinned); 204 continue; 205 } 206 207 GEM_BUG_ON(!ctx->hw_id); /* perma-pinned kernel context */ 208 list_del_init(&ctx->hw_id_link); 209 id = ctx->hw_id; 210 break; 211 } 212 213 /* 214 * Remember how far we got up on the last repossesion scan, so the 215 * list is kept in a "least recently scanned" order. 216 */ 217 list_splice_tail(&pinned, &i915->contexts.hw_id_list); 218 return id; 219 } 220 221 static int assign_hw_id(struct drm_i915_private *i915, unsigned int *out) 222 { 223 int ret; 224 225 lockdep_assert_held(&i915->contexts.mutex); 226 227 /* 228 * We prefer to steal/stall ourselves and our users over that of the 229 * entire system. That may be a little unfair to our users, and 230 * even hurt high priority clients. The choice is whether to oomkill 231 * something else, or steal a context id. 232 */ 233 ret = new_hw_id(i915, GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); 234 if (unlikely(ret < 0)) { 235 ret = steal_hw_id(i915); 236 if (ret < 0) /* once again for the correct errno code */ 237 ret = new_hw_id(i915, GFP_KERNEL); 238 if (ret < 0) 239 return ret; 240 } 241 242 *out = ret; 243 return 0; 244 } 245 246 static void release_hw_id(struct i915_gem_context *ctx) 247 { 248 struct drm_i915_private *i915 = ctx->i915; 249 250 if (list_empty(&ctx->hw_id_link)) 251 return; 252 253 mutex_lock(&i915->contexts.mutex); 254 if (!list_empty(&ctx->hw_id_link)) { 255 ida_simple_remove(&i915->contexts.hw_ida, ctx->hw_id); 256 list_del_init(&ctx->hw_id_link); 257 } 258 mutex_unlock(&i915->contexts.mutex); 259 } 260 261 static void __free_engines(struct i915_gem_engines *e, unsigned int count) 262 { 263 while (count--) { 264 if (!e->engines[count]) 265 continue; 266 267 intel_context_put(e->engines[count]); 268 } 269 kfree(e); 270 } 271 272 static void free_engines(struct i915_gem_engines *e) 273 { 274 __free_engines(e, e->num_engines); 275 } 276 277 static void free_engines_rcu(struct rcu_head *rcu) 278 { 279 free_engines(container_of(rcu, struct i915_gem_engines, rcu)); 280 } 281 282 static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx) 283 { 284 const struct intel_gt *gt = &ctx->i915->gt; 285 struct intel_engine_cs *engine; 286 struct i915_gem_engines *e; 287 enum intel_engine_id id; 288 289 e = kzalloc(struct_size(e, engines, I915_NUM_ENGINES), GFP_KERNEL); 290 if (!e) 291 return ERR_PTR(-ENOMEM); 292 293 init_rcu_head(&e->rcu); 294 for_each_engine(engine, gt, id) { 295 struct intel_context *ce; 296 297 ce = intel_context_create(ctx, engine); 298 if (IS_ERR(ce)) { 299 __free_engines(e, id); 300 return ERR_CAST(ce); 301 } 302 303 e->engines[id] = ce; 304 e->num_engines = id + 1; 305 } 306 307 return e; 308 } 309 310 static void i915_gem_context_free(struct i915_gem_context *ctx) 311 { 312 lockdep_assert_held(&ctx->i915->drm.struct_mutex); 313 GEM_BUG_ON(!i915_gem_context_is_closed(ctx)); 314 315 release_hw_id(ctx); 316 if (ctx->vm) 317 i915_vm_put(ctx->vm); 318 319 free_engines(rcu_access_pointer(ctx->engines)); 320 mutex_destroy(&ctx->engines_mutex); 321 322 if (ctx->timeline) 323 intel_timeline_put(ctx->timeline); 324 325 kfree(ctx->name); 326 put_pid(ctx->pid); 327 328 list_del(&ctx->link); 329 mutex_destroy(&ctx->mutex); 330 331 kfree_rcu(ctx, rcu); 332 } 333 334 static void contexts_free(struct drm_i915_private *i915) 335 { 336 struct llist_node *freed = llist_del_all(&i915->contexts.free_list); 337 struct i915_gem_context *ctx, *cn; 338 339 lockdep_assert_held(&i915->drm.struct_mutex); 340 341 llist_for_each_entry_safe(ctx, cn, freed, free_link) 342 i915_gem_context_free(ctx); 343 } 344 345 static void contexts_free_first(struct drm_i915_private *i915) 346 { 347 struct i915_gem_context *ctx; 348 struct llist_node *freed; 349 350 lockdep_assert_held(&i915->drm.struct_mutex); 351 352 freed = llist_del_first(&i915->contexts.free_list); 353 if (!freed) 354 return; 355 356 ctx = container_of(freed, typeof(*ctx), free_link); 357 i915_gem_context_free(ctx); 358 } 359 360 static void contexts_free_worker(struct work_struct *work) 361 { 362 struct drm_i915_private *i915 = 363 container_of(work, typeof(*i915), contexts.free_work); 364 365 mutex_lock(&i915->drm.struct_mutex); 366 contexts_free(i915); 367 mutex_unlock(&i915->drm.struct_mutex); 368 } 369 370 void i915_gem_context_release(struct kref *ref) 371 { 372 struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref); 373 struct drm_i915_private *i915 = ctx->i915; 374 375 trace_i915_context_free(ctx); 376 if (llist_add(&ctx->free_link, &i915->contexts.free_list)) 377 queue_work(i915->wq, &i915->contexts.free_work); 378 } 379 380 static void context_close(struct i915_gem_context *ctx) 381 { 382 mutex_lock(&ctx->mutex); 383 384 i915_gem_context_set_closed(ctx); 385 ctx->file_priv = ERR_PTR(-EBADF); 386 387 /* 388 * This context will never again be assinged to HW, so we can 389 * reuse its ID for the next context. 390 */ 391 release_hw_id(ctx); 392 393 /* 394 * The LUT uses the VMA as a backpointer to unref the object, 395 * so we need to clear the LUT before we close all the VMA (inside 396 * the ppgtt). 397 */ 398 lut_close(ctx); 399 400 mutex_unlock(&ctx->mutex); 401 i915_gem_context_put(ctx); 402 } 403 404 static struct i915_gem_context * 405 __create_context(struct drm_i915_private *i915) 406 { 407 struct i915_gem_context *ctx; 408 struct i915_gem_engines *e; 409 int err; 410 int i; 411 412 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 413 if (!ctx) 414 return ERR_PTR(-ENOMEM); 415 416 kref_init(&ctx->ref); 417 list_add_tail(&ctx->link, &i915->contexts.list); 418 ctx->i915 = i915; 419 ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL); 420 mutex_init(&ctx->mutex); 421 422 mutex_init(&ctx->engines_mutex); 423 e = default_engines(ctx); 424 if (IS_ERR(e)) { 425 err = PTR_ERR(e); 426 goto err_free; 427 } 428 RCU_INIT_POINTER(ctx->engines, e); 429 430 INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL); 431 INIT_LIST_HEAD(&ctx->hw_id_link); 432 433 /* NB: Mark all slices as needing a remap so that when the context first 434 * loads it will restore whatever remap state already exists. If there 435 * is no remap info, it will be a NOP. */ 436 ctx->remap_slice = ALL_L3_SLICES(i915); 437 438 i915_gem_context_set_bannable(ctx); 439 i915_gem_context_set_recoverable(ctx); 440 441 for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++) 442 ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES; 443 444 return ctx; 445 446 err_free: 447 kfree(ctx); 448 return ERR_PTR(err); 449 } 450 451 static void 452 context_apply_all(struct i915_gem_context *ctx, 453 void (*fn)(struct intel_context *ce, void *data), 454 void *data) 455 { 456 struct i915_gem_engines_iter it; 457 struct intel_context *ce; 458 459 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) 460 fn(ce, data); 461 i915_gem_context_unlock_engines(ctx); 462 } 463 464 static void __apply_ppgtt(struct intel_context *ce, void *vm) 465 { 466 i915_vm_put(ce->vm); 467 ce->vm = i915_vm_get(vm); 468 } 469 470 static struct i915_address_space * 471 __set_ppgtt(struct i915_gem_context *ctx, struct i915_address_space *vm) 472 { 473 struct i915_address_space *old = ctx->vm; 474 475 GEM_BUG_ON(old && i915_vm_is_4lvl(vm) != i915_vm_is_4lvl(old)); 476 477 ctx->vm = i915_vm_get(vm); 478 context_apply_all(ctx, __apply_ppgtt, vm); 479 480 return old; 481 } 482 483 static void __assign_ppgtt(struct i915_gem_context *ctx, 484 struct i915_address_space *vm) 485 { 486 if (vm == ctx->vm) 487 return; 488 489 vm = __set_ppgtt(ctx, vm); 490 if (vm) 491 i915_vm_put(vm); 492 } 493 494 static void __set_timeline(struct intel_timeline **dst, 495 struct intel_timeline *src) 496 { 497 struct intel_timeline *old = *dst; 498 499 *dst = src ? intel_timeline_get(src) : NULL; 500 501 if (old) 502 intel_timeline_put(old); 503 } 504 505 static void __apply_timeline(struct intel_context *ce, void *timeline) 506 { 507 __set_timeline(&ce->timeline, timeline); 508 } 509 510 static void __assign_timeline(struct i915_gem_context *ctx, 511 struct intel_timeline *timeline) 512 { 513 __set_timeline(&ctx->timeline, timeline); 514 context_apply_all(ctx, __apply_timeline, timeline); 515 } 516 517 static struct i915_gem_context * 518 i915_gem_create_context(struct drm_i915_private *dev_priv, unsigned int flags) 519 { 520 struct i915_gem_context *ctx; 521 522 lockdep_assert_held(&dev_priv->drm.struct_mutex); 523 524 if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE && 525 !HAS_EXECLISTS(dev_priv)) 526 return ERR_PTR(-EINVAL); 527 528 /* Reap the most stale context */ 529 contexts_free_first(dev_priv); 530 531 ctx = __create_context(dev_priv); 532 if (IS_ERR(ctx)) 533 return ctx; 534 535 if (HAS_FULL_PPGTT(dev_priv)) { 536 struct i915_ppgtt *ppgtt; 537 538 ppgtt = i915_ppgtt_create(dev_priv); 539 if (IS_ERR(ppgtt)) { 540 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", 541 PTR_ERR(ppgtt)); 542 context_close(ctx); 543 return ERR_CAST(ppgtt); 544 } 545 546 __assign_ppgtt(ctx, &ppgtt->vm); 547 i915_vm_put(&ppgtt->vm); 548 } 549 550 if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) { 551 struct intel_timeline *timeline; 552 553 timeline = intel_timeline_create(&dev_priv->gt, NULL); 554 if (IS_ERR(timeline)) { 555 context_close(ctx); 556 return ERR_CAST(timeline); 557 } 558 559 __assign_timeline(ctx, timeline); 560 intel_timeline_put(timeline); 561 } 562 563 trace_i915_context_create(ctx); 564 565 return ctx; 566 } 567 568 static void 569 destroy_kernel_context(struct i915_gem_context **ctxp) 570 { 571 struct i915_gem_context *ctx; 572 573 /* Keep the context ref so that we can free it immediately ourselves */ 574 ctx = i915_gem_context_get(fetch_and_zero(ctxp)); 575 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx)); 576 577 context_close(ctx); 578 i915_gem_context_free(ctx); 579 } 580 581 struct i915_gem_context * 582 i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio) 583 { 584 struct i915_gem_context *ctx; 585 int err; 586 587 ctx = i915_gem_create_context(i915, 0); 588 if (IS_ERR(ctx)) 589 return ctx; 590 591 err = i915_gem_context_pin_hw_id(ctx); 592 if (err) { 593 destroy_kernel_context(&ctx); 594 return ERR_PTR(err); 595 } 596 597 i915_gem_context_clear_bannable(ctx); 598 ctx->sched.priority = I915_USER_PRIORITY(prio); 599 600 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx)); 601 602 return ctx; 603 } 604 605 static void init_contexts(struct drm_i915_private *i915) 606 { 607 mutex_init(&i915->contexts.mutex); 608 INIT_LIST_HEAD(&i915->contexts.list); 609 610 /* Using the simple ida interface, the max is limited by sizeof(int) */ 611 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX); 612 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > INT_MAX); 613 ida_init(&i915->contexts.hw_ida); 614 INIT_LIST_HEAD(&i915->contexts.hw_id_list); 615 616 INIT_WORK(&i915->contexts.free_work, contexts_free_worker); 617 init_llist_head(&i915->contexts.free_list); 618 } 619 620 int i915_gem_contexts_init(struct drm_i915_private *dev_priv) 621 { 622 struct i915_gem_context *ctx; 623 624 /* Reassure ourselves we are only called once */ 625 GEM_BUG_ON(dev_priv->kernel_context); 626 627 init_contexts(dev_priv); 628 629 /* lowest priority; idle task */ 630 ctx = i915_gem_context_create_kernel(dev_priv, I915_PRIORITY_MIN); 631 if (IS_ERR(ctx)) { 632 DRM_ERROR("Failed to create default global context\n"); 633 return PTR_ERR(ctx); 634 } 635 /* 636 * For easy recognisablity, we want the kernel context to be 0 and then 637 * all user contexts will have non-zero hw_id. Kernel contexts are 638 * permanently pinned, so that we never suffer a stall and can 639 * use them from any allocation context (e.g. for evicting other 640 * contexts and from inside the shrinker). 641 */ 642 GEM_BUG_ON(ctx->hw_id); 643 GEM_BUG_ON(!atomic_read(&ctx->hw_id_pin_count)); 644 dev_priv->kernel_context = ctx; 645 646 DRM_DEBUG_DRIVER("%s context support initialized\n", 647 DRIVER_CAPS(dev_priv)->has_logical_contexts ? 648 "logical" : "fake"); 649 return 0; 650 } 651 652 void i915_gem_contexts_fini(struct drm_i915_private *i915) 653 { 654 lockdep_assert_held(&i915->drm.struct_mutex); 655 656 destroy_kernel_context(&i915->kernel_context); 657 658 /* Must free all deferred contexts (via flush_workqueue) first */ 659 GEM_BUG_ON(!list_empty(&i915->contexts.hw_id_list)); 660 ida_destroy(&i915->contexts.hw_ida); 661 } 662 663 static int context_idr_cleanup(int id, void *p, void *data) 664 { 665 context_close(p); 666 return 0; 667 } 668 669 static int vm_idr_cleanup(int id, void *p, void *data) 670 { 671 i915_vm_put(p); 672 return 0; 673 } 674 675 static int gem_context_register(struct i915_gem_context *ctx, 676 struct drm_i915_file_private *fpriv) 677 { 678 int ret; 679 680 ctx->file_priv = fpriv; 681 if (ctx->vm) 682 ctx->vm->file = fpriv; 683 684 ctx->pid = get_task_pid(current, PIDTYPE_PID); 685 ctx->name = kasprintf(GFP_KERNEL, "%s[%d]", 686 current->comm, pid_nr(ctx->pid)); 687 if (!ctx->name) { 688 ret = -ENOMEM; 689 goto err_pid; 690 } 691 692 /* And finally expose ourselves to userspace via the idr */ 693 mutex_lock(&fpriv->context_idr_lock); 694 ret = idr_alloc(&fpriv->context_idr, ctx, 0, 0, GFP_KERNEL); 695 mutex_unlock(&fpriv->context_idr_lock); 696 if (ret >= 0) 697 goto out; 698 699 kfree(fetch_and_zero(&ctx->name)); 700 err_pid: 701 put_pid(fetch_and_zero(&ctx->pid)); 702 out: 703 return ret; 704 } 705 706 int i915_gem_context_open(struct drm_i915_private *i915, 707 struct drm_file *file) 708 { 709 struct drm_i915_file_private *file_priv = file->driver_priv; 710 struct i915_gem_context *ctx; 711 int err; 712 713 mutex_init(&file_priv->context_idr_lock); 714 mutex_init(&file_priv->vm_idr_lock); 715 716 idr_init(&file_priv->context_idr); 717 idr_init_base(&file_priv->vm_idr, 1); 718 719 mutex_lock(&i915->drm.struct_mutex); 720 ctx = i915_gem_create_context(i915, 0); 721 mutex_unlock(&i915->drm.struct_mutex); 722 if (IS_ERR(ctx)) { 723 err = PTR_ERR(ctx); 724 goto err; 725 } 726 727 err = gem_context_register(ctx, file_priv); 728 if (err < 0) 729 goto err_ctx; 730 731 GEM_BUG_ON(i915_gem_context_is_kernel(ctx)); 732 GEM_BUG_ON(err > 0); 733 734 return 0; 735 736 err_ctx: 737 context_close(ctx); 738 err: 739 idr_destroy(&file_priv->vm_idr); 740 idr_destroy(&file_priv->context_idr); 741 mutex_destroy(&file_priv->vm_idr_lock); 742 mutex_destroy(&file_priv->context_idr_lock); 743 return err; 744 } 745 746 void i915_gem_context_close(struct drm_file *file) 747 { 748 struct drm_i915_file_private *file_priv = file->driver_priv; 749 750 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); 751 idr_destroy(&file_priv->context_idr); 752 mutex_destroy(&file_priv->context_idr_lock); 753 754 idr_for_each(&file_priv->vm_idr, vm_idr_cleanup, NULL); 755 idr_destroy(&file_priv->vm_idr); 756 mutex_destroy(&file_priv->vm_idr_lock); 757 } 758 759 int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data, 760 struct drm_file *file) 761 { 762 struct drm_i915_private *i915 = to_i915(dev); 763 struct drm_i915_gem_vm_control *args = data; 764 struct drm_i915_file_private *file_priv = file->driver_priv; 765 struct i915_ppgtt *ppgtt; 766 int err; 767 768 if (!HAS_FULL_PPGTT(i915)) 769 return -ENODEV; 770 771 if (args->flags) 772 return -EINVAL; 773 774 ppgtt = i915_ppgtt_create(i915); 775 if (IS_ERR(ppgtt)) 776 return PTR_ERR(ppgtt); 777 778 ppgtt->vm.file = file_priv; 779 780 if (args->extensions) { 781 err = i915_user_extensions(u64_to_user_ptr(args->extensions), 782 NULL, 0, 783 ppgtt); 784 if (err) 785 goto err_put; 786 } 787 788 err = mutex_lock_interruptible(&file_priv->vm_idr_lock); 789 if (err) 790 goto err_put; 791 792 err = idr_alloc(&file_priv->vm_idr, &ppgtt->vm, 0, 0, GFP_KERNEL); 793 if (err < 0) 794 goto err_unlock; 795 796 GEM_BUG_ON(err == 0); /* reserved for invalid/unassigned ppgtt */ 797 798 mutex_unlock(&file_priv->vm_idr_lock); 799 800 args->vm_id = err; 801 return 0; 802 803 err_unlock: 804 mutex_unlock(&file_priv->vm_idr_lock); 805 err_put: 806 i915_vm_put(&ppgtt->vm); 807 return err; 808 } 809 810 int i915_gem_vm_destroy_ioctl(struct drm_device *dev, void *data, 811 struct drm_file *file) 812 { 813 struct drm_i915_file_private *file_priv = file->driver_priv; 814 struct drm_i915_gem_vm_control *args = data; 815 struct i915_address_space *vm; 816 int err; 817 u32 id; 818 819 if (args->flags) 820 return -EINVAL; 821 822 if (args->extensions) 823 return -EINVAL; 824 825 id = args->vm_id; 826 if (!id) 827 return -ENOENT; 828 829 err = mutex_lock_interruptible(&file_priv->vm_idr_lock); 830 if (err) 831 return err; 832 833 vm = idr_remove(&file_priv->vm_idr, id); 834 835 mutex_unlock(&file_priv->vm_idr_lock); 836 if (!vm) 837 return -ENOENT; 838 839 i915_vm_put(vm); 840 return 0; 841 } 842 843 struct context_barrier_task { 844 struct i915_active base; 845 void (*task)(void *data); 846 void *data; 847 }; 848 849 static void cb_retire(struct i915_active *base) 850 { 851 struct context_barrier_task *cb = container_of(base, typeof(*cb), base); 852 853 if (cb->task) 854 cb->task(cb->data); 855 856 i915_active_fini(&cb->base); 857 kfree(cb); 858 } 859 860 I915_SELFTEST_DECLARE(static intel_engine_mask_t context_barrier_inject_fault); 861 static int context_barrier_task(struct i915_gem_context *ctx, 862 intel_engine_mask_t engines, 863 bool (*skip)(struct intel_context *ce, void *data), 864 int (*emit)(struct i915_request *rq, void *data), 865 void (*task)(void *data), 866 void *data) 867 { 868 struct drm_i915_private *i915 = ctx->i915; 869 struct context_barrier_task *cb; 870 struct i915_gem_engines_iter it; 871 struct intel_context *ce; 872 int err = 0; 873 874 lockdep_assert_held(&i915->drm.struct_mutex); 875 GEM_BUG_ON(!task); 876 877 cb = kmalloc(sizeof(*cb), GFP_KERNEL); 878 if (!cb) 879 return -ENOMEM; 880 881 i915_active_init(i915, &cb->base, NULL, cb_retire); 882 err = i915_active_acquire(&cb->base); 883 if (err) { 884 kfree(cb); 885 return err; 886 } 887 888 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) { 889 struct i915_request *rq; 890 891 if (I915_SELFTEST_ONLY(context_barrier_inject_fault & 892 ce->engine->mask)) { 893 err = -ENXIO; 894 break; 895 } 896 897 if (!(ce->engine->mask & engines)) 898 continue; 899 900 if (skip && skip(ce, data)) 901 continue; 902 903 rq = intel_context_create_request(ce); 904 if (IS_ERR(rq)) { 905 err = PTR_ERR(rq); 906 break; 907 } 908 909 err = 0; 910 if (emit) 911 err = emit(rq, data); 912 if (err == 0) 913 err = i915_active_ref(&cb->base, rq->timeline, rq); 914 915 i915_request_add(rq); 916 if (err) 917 break; 918 } 919 i915_gem_context_unlock_engines(ctx); 920 921 cb->task = err ? NULL : task; /* caller needs to unwind instead */ 922 cb->data = data; 923 924 i915_active_release(&cb->base); 925 926 return err; 927 } 928 929 static int get_ppgtt(struct drm_i915_file_private *file_priv, 930 struct i915_gem_context *ctx, 931 struct drm_i915_gem_context_param *args) 932 { 933 struct i915_address_space *vm; 934 int ret; 935 936 if (!ctx->vm) 937 return -ENODEV; 938 939 /* XXX rcu acquire? */ 940 ret = mutex_lock_interruptible(&ctx->i915->drm.struct_mutex); 941 if (ret) 942 return ret; 943 944 vm = i915_vm_get(ctx->vm); 945 mutex_unlock(&ctx->i915->drm.struct_mutex); 946 947 ret = mutex_lock_interruptible(&file_priv->vm_idr_lock); 948 if (ret) 949 goto err_put; 950 951 ret = idr_alloc(&file_priv->vm_idr, vm, 0, 0, GFP_KERNEL); 952 GEM_BUG_ON(!ret); 953 if (ret < 0) 954 goto err_unlock; 955 956 i915_vm_get(vm); 957 958 args->size = 0; 959 args->value = ret; 960 961 ret = 0; 962 err_unlock: 963 mutex_unlock(&file_priv->vm_idr_lock); 964 err_put: 965 i915_vm_put(vm); 966 return ret; 967 } 968 969 static void set_ppgtt_barrier(void *data) 970 { 971 struct i915_address_space *old = data; 972 973 if (INTEL_GEN(old->i915) < 8) 974 gen6_ppgtt_unpin_all(i915_vm_to_ppgtt(old)); 975 976 i915_vm_put(old); 977 } 978 979 static int emit_ppgtt_update(struct i915_request *rq, void *data) 980 { 981 struct i915_address_space *vm = rq->hw_context->vm; 982 struct intel_engine_cs *engine = rq->engine; 983 u32 base = engine->mmio_base; 984 u32 *cs; 985 int i; 986 987 if (i915_vm_is_4lvl(vm)) { 988 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); 989 const dma_addr_t pd_daddr = px_dma(ppgtt->pd); 990 991 cs = intel_ring_begin(rq, 6); 992 if (IS_ERR(cs)) 993 return PTR_ERR(cs); 994 995 *cs++ = MI_LOAD_REGISTER_IMM(2); 996 997 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0)); 998 *cs++ = upper_32_bits(pd_daddr); 999 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0)); 1000 *cs++ = lower_32_bits(pd_daddr); 1001 1002 *cs++ = MI_NOOP; 1003 intel_ring_advance(rq, cs); 1004 } else if (HAS_LOGICAL_RING_CONTEXTS(engine->i915)) { 1005 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); 1006 1007 cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2); 1008 if (IS_ERR(cs)) 1009 return PTR_ERR(cs); 1010 1011 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES); 1012 for (i = GEN8_3LVL_PDPES; i--; ) { 1013 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); 1014 1015 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i)); 1016 *cs++ = upper_32_bits(pd_daddr); 1017 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i)); 1018 *cs++ = lower_32_bits(pd_daddr); 1019 } 1020 *cs++ = MI_NOOP; 1021 intel_ring_advance(rq, cs); 1022 } else { 1023 /* ppGTT is not part of the legacy context image */ 1024 gen6_ppgtt_pin(i915_vm_to_ppgtt(vm)); 1025 } 1026 1027 return 0; 1028 } 1029 1030 static bool skip_ppgtt_update(struct intel_context *ce, void *data) 1031 { 1032 if (HAS_LOGICAL_RING_CONTEXTS(ce->engine->i915)) 1033 return !ce->state; 1034 else 1035 return !atomic_read(&ce->pin_count); 1036 } 1037 1038 static int set_ppgtt(struct drm_i915_file_private *file_priv, 1039 struct i915_gem_context *ctx, 1040 struct drm_i915_gem_context_param *args) 1041 { 1042 struct i915_address_space *vm, *old; 1043 int err; 1044 1045 if (args->size) 1046 return -EINVAL; 1047 1048 if (!ctx->vm) 1049 return -ENODEV; 1050 1051 if (upper_32_bits(args->value)) 1052 return -ENOENT; 1053 1054 err = mutex_lock_interruptible(&file_priv->vm_idr_lock); 1055 if (err) 1056 return err; 1057 1058 vm = idr_find(&file_priv->vm_idr, args->value); 1059 if (vm) 1060 i915_vm_get(vm); 1061 mutex_unlock(&file_priv->vm_idr_lock); 1062 if (!vm) 1063 return -ENOENT; 1064 1065 err = mutex_lock_interruptible(&ctx->i915->drm.struct_mutex); 1066 if (err) 1067 goto out; 1068 1069 if (vm == ctx->vm) 1070 goto unlock; 1071 1072 /* Teardown the existing obj:vma cache, it will have to be rebuilt. */ 1073 mutex_lock(&ctx->mutex); 1074 lut_close(ctx); 1075 mutex_unlock(&ctx->mutex); 1076 1077 old = __set_ppgtt(ctx, vm); 1078 1079 /* 1080 * We need to flush any requests using the current ppgtt before 1081 * we release it as the requests do not hold a reference themselves, 1082 * only indirectly through the context. 1083 */ 1084 err = context_barrier_task(ctx, ALL_ENGINES, 1085 skip_ppgtt_update, 1086 emit_ppgtt_update, 1087 set_ppgtt_barrier, 1088 old); 1089 if (err) { 1090 i915_vm_put(__set_ppgtt(ctx, old)); 1091 i915_vm_put(old); 1092 } 1093 1094 unlock: 1095 mutex_unlock(&ctx->i915->drm.struct_mutex); 1096 1097 out: 1098 i915_vm_put(vm); 1099 return err; 1100 } 1101 1102 static int gen8_emit_rpcs_config(struct i915_request *rq, 1103 struct intel_context *ce, 1104 struct intel_sseu sseu) 1105 { 1106 u64 offset; 1107 u32 *cs; 1108 1109 cs = intel_ring_begin(rq, 4); 1110 if (IS_ERR(cs)) 1111 return PTR_ERR(cs); 1112 1113 offset = i915_ggtt_offset(ce->state) + 1114 LRC_STATE_PN * PAGE_SIZE + 1115 (CTX_R_PWR_CLK_STATE + 1) * 4; 1116 1117 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; 1118 *cs++ = lower_32_bits(offset); 1119 *cs++ = upper_32_bits(offset); 1120 *cs++ = intel_sseu_make_rpcs(rq->i915, &sseu); 1121 1122 intel_ring_advance(rq, cs); 1123 1124 return 0; 1125 } 1126 1127 static int 1128 gen8_modify_rpcs(struct intel_context *ce, struct intel_sseu sseu) 1129 { 1130 struct i915_request *rq; 1131 int ret; 1132 1133 lockdep_assert_held(&ce->pin_mutex); 1134 1135 /* 1136 * If the context is not idle, we have to submit an ordered request to 1137 * modify its context image via the kernel context (writing to our own 1138 * image, or into the registers directory, does not stick). Pristine 1139 * and idle contexts will be configured on pinning. 1140 */ 1141 if (!intel_context_is_pinned(ce)) 1142 return 0; 1143 1144 rq = i915_request_create(ce->engine->kernel_context); 1145 if (IS_ERR(rq)) 1146 return PTR_ERR(rq); 1147 1148 /* Serialise with the remote context */ 1149 ret = intel_context_prepare_remote_request(ce, rq); 1150 if (ret == 0) 1151 ret = gen8_emit_rpcs_config(rq, ce, sseu); 1152 1153 i915_request_add(rq); 1154 return ret; 1155 } 1156 1157 static int 1158 __intel_context_reconfigure_sseu(struct intel_context *ce, 1159 struct intel_sseu sseu) 1160 { 1161 int ret; 1162 1163 GEM_BUG_ON(INTEL_GEN(ce->engine->i915) < 8); 1164 1165 ret = intel_context_lock_pinned(ce); 1166 if (ret) 1167 return ret; 1168 1169 /* Nothing to do if unmodified. */ 1170 if (!memcmp(&ce->sseu, &sseu, sizeof(sseu))) 1171 goto unlock; 1172 1173 ret = gen8_modify_rpcs(ce, sseu); 1174 if (!ret) 1175 ce->sseu = sseu; 1176 1177 unlock: 1178 intel_context_unlock_pinned(ce); 1179 return ret; 1180 } 1181 1182 static int 1183 intel_context_reconfigure_sseu(struct intel_context *ce, struct intel_sseu sseu) 1184 { 1185 struct drm_i915_private *i915 = ce->engine->i915; 1186 int ret; 1187 1188 ret = mutex_lock_interruptible(&i915->drm.struct_mutex); 1189 if (ret) 1190 return ret; 1191 1192 ret = __intel_context_reconfigure_sseu(ce, sseu); 1193 1194 mutex_unlock(&i915->drm.struct_mutex); 1195 1196 return ret; 1197 } 1198 1199 static int 1200 user_to_context_sseu(struct drm_i915_private *i915, 1201 const struct drm_i915_gem_context_param_sseu *user, 1202 struct intel_sseu *context) 1203 { 1204 const struct sseu_dev_info *device = &RUNTIME_INFO(i915)->sseu; 1205 1206 /* No zeros in any field. */ 1207 if (!user->slice_mask || !user->subslice_mask || 1208 !user->min_eus_per_subslice || !user->max_eus_per_subslice) 1209 return -EINVAL; 1210 1211 /* Max > min. */ 1212 if (user->max_eus_per_subslice < user->min_eus_per_subslice) 1213 return -EINVAL; 1214 1215 /* 1216 * Some future proofing on the types since the uAPI is wider than the 1217 * current internal implementation. 1218 */ 1219 if (overflows_type(user->slice_mask, context->slice_mask) || 1220 overflows_type(user->subslice_mask, context->subslice_mask) || 1221 overflows_type(user->min_eus_per_subslice, 1222 context->min_eus_per_subslice) || 1223 overflows_type(user->max_eus_per_subslice, 1224 context->max_eus_per_subslice)) 1225 return -EINVAL; 1226 1227 /* Check validity against hardware. */ 1228 if (user->slice_mask & ~device->slice_mask) 1229 return -EINVAL; 1230 1231 if (user->subslice_mask & ~device->subslice_mask[0]) 1232 return -EINVAL; 1233 1234 if (user->max_eus_per_subslice > device->max_eus_per_subslice) 1235 return -EINVAL; 1236 1237 context->slice_mask = user->slice_mask; 1238 context->subslice_mask = user->subslice_mask; 1239 context->min_eus_per_subslice = user->min_eus_per_subslice; 1240 context->max_eus_per_subslice = user->max_eus_per_subslice; 1241 1242 /* Part specific restrictions. */ 1243 if (IS_GEN(i915, 11)) { 1244 unsigned int hw_s = hweight8(device->slice_mask); 1245 unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]); 1246 unsigned int req_s = hweight8(context->slice_mask); 1247 unsigned int req_ss = hweight8(context->subslice_mask); 1248 1249 /* 1250 * Only full subslice enablement is possible if more than one 1251 * slice is turned on. 1252 */ 1253 if (req_s > 1 && req_ss != hw_ss_per_s) 1254 return -EINVAL; 1255 1256 /* 1257 * If more than four (SScount bitfield limit) subslices are 1258 * requested then the number has to be even. 1259 */ 1260 if (req_ss > 4 && (req_ss & 1)) 1261 return -EINVAL; 1262 1263 /* 1264 * If only one slice is enabled and subslice count is below the 1265 * device full enablement, it must be at most half of the all 1266 * available subslices. 1267 */ 1268 if (req_s == 1 && req_ss < hw_ss_per_s && 1269 req_ss > (hw_ss_per_s / 2)) 1270 return -EINVAL; 1271 1272 /* ABI restriction - VME use case only. */ 1273 1274 /* All slices or one slice only. */ 1275 if (req_s != 1 && req_s != hw_s) 1276 return -EINVAL; 1277 1278 /* 1279 * Half subslices or full enablement only when one slice is 1280 * enabled. 1281 */ 1282 if (req_s == 1 && 1283 (req_ss != hw_ss_per_s && req_ss != (hw_ss_per_s / 2))) 1284 return -EINVAL; 1285 1286 /* No EU configuration changes. */ 1287 if ((user->min_eus_per_subslice != 1288 device->max_eus_per_subslice) || 1289 (user->max_eus_per_subslice != 1290 device->max_eus_per_subslice)) 1291 return -EINVAL; 1292 } 1293 1294 return 0; 1295 } 1296 1297 static int set_sseu(struct i915_gem_context *ctx, 1298 struct drm_i915_gem_context_param *args) 1299 { 1300 struct drm_i915_private *i915 = ctx->i915; 1301 struct drm_i915_gem_context_param_sseu user_sseu; 1302 struct intel_context *ce; 1303 struct intel_sseu sseu; 1304 unsigned long lookup; 1305 int ret; 1306 1307 if (args->size < sizeof(user_sseu)) 1308 return -EINVAL; 1309 1310 if (!IS_GEN(i915, 11)) 1311 return -ENODEV; 1312 1313 if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value), 1314 sizeof(user_sseu))) 1315 return -EFAULT; 1316 1317 if (user_sseu.rsvd) 1318 return -EINVAL; 1319 1320 if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)) 1321 return -EINVAL; 1322 1323 lookup = 0; 1324 if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX) 1325 lookup |= LOOKUP_USER_INDEX; 1326 1327 ce = lookup_user_engine(ctx, lookup, &user_sseu.engine); 1328 if (IS_ERR(ce)) 1329 return PTR_ERR(ce); 1330 1331 /* Only render engine supports RPCS configuration. */ 1332 if (ce->engine->class != RENDER_CLASS) { 1333 ret = -ENODEV; 1334 goto out_ce; 1335 } 1336 1337 ret = user_to_context_sseu(i915, &user_sseu, &sseu); 1338 if (ret) 1339 goto out_ce; 1340 1341 ret = intel_context_reconfigure_sseu(ce, sseu); 1342 if (ret) 1343 goto out_ce; 1344 1345 args->size = sizeof(user_sseu); 1346 1347 out_ce: 1348 intel_context_put(ce); 1349 return ret; 1350 } 1351 1352 struct set_engines { 1353 struct i915_gem_context *ctx; 1354 struct i915_gem_engines *engines; 1355 }; 1356 1357 static int 1358 set_engines__load_balance(struct i915_user_extension __user *base, void *data) 1359 { 1360 struct i915_context_engines_load_balance __user *ext = 1361 container_of_user(base, typeof(*ext), base); 1362 const struct set_engines *set = data; 1363 struct intel_engine_cs *stack[16]; 1364 struct intel_engine_cs **siblings; 1365 struct intel_context *ce; 1366 u16 num_siblings, idx; 1367 unsigned int n; 1368 int err; 1369 1370 if (!HAS_EXECLISTS(set->ctx->i915)) 1371 return -ENODEV; 1372 1373 if (USES_GUC_SUBMISSION(set->ctx->i915)) 1374 return -ENODEV; /* not implement yet */ 1375 1376 if (get_user(idx, &ext->engine_index)) 1377 return -EFAULT; 1378 1379 if (idx >= set->engines->num_engines) { 1380 DRM_DEBUG("Invalid placement value, %d >= %d\n", 1381 idx, set->engines->num_engines); 1382 return -EINVAL; 1383 } 1384 1385 idx = array_index_nospec(idx, set->engines->num_engines); 1386 if (set->engines->engines[idx]) { 1387 DRM_DEBUG("Invalid placement[%d], already occupied\n", idx); 1388 return -EEXIST; 1389 } 1390 1391 if (get_user(num_siblings, &ext->num_siblings)) 1392 return -EFAULT; 1393 1394 err = check_user_mbz(&ext->flags); 1395 if (err) 1396 return err; 1397 1398 err = check_user_mbz(&ext->mbz64); 1399 if (err) 1400 return err; 1401 1402 siblings = stack; 1403 if (num_siblings > ARRAY_SIZE(stack)) { 1404 siblings = kmalloc_array(num_siblings, 1405 sizeof(*siblings), 1406 GFP_KERNEL); 1407 if (!siblings) 1408 return -ENOMEM; 1409 } 1410 1411 for (n = 0; n < num_siblings; n++) { 1412 struct i915_engine_class_instance ci; 1413 1414 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) { 1415 err = -EFAULT; 1416 goto out_siblings; 1417 } 1418 1419 siblings[n] = intel_engine_lookup_user(set->ctx->i915, 1420 ci.engine_class, 1421 ci.engine_instance); 1422 if (!siblings[n]) { 1423 DRM_DEBUG("Invalid sibling[%d]: { class:%d, inst:%d }\n", 1424 n, ci.engine_class, ci.engine_instance); 1425 err = -EINVAL; 1426 goto out_siblings; 1427 } 1428 } 1429 1430 ce = intel_execlists_create_virtual(set->ctx, siblings, n); 1431 if (IS_ERR(ce)) { 1432 err = PTR_ERR(ce); 1433 goto out_siblings; 1434 } 1435 1436 if (cmpxchg(&set->engines->engines[idx], NULL, ce)) { 1437 intel_context_put(ce); 1438 err = -EEXIST; 1439 goto out_siblings; 1440 } 1441 1442 out_siblings: 1443 if (siblings != stack) 1444 kfree(siblings); 1445 1446 return err; 1447 } 1448 1449 static int 1450 set_engines__bond(struct i915_user_extension __user *base, void *data) 1451 { 1452 struct i915_context_engines_bond __user *ext = 1453 container_of_user(base, typeof(*ext), base); 1454 const struct set_engines *set = data; 1455 struct i915_engine_class_instance ci; 1456 struct intel_engine_cs *virtual; 1457 struct intel_engine_cs *master; 1458 u16 idx, num_bonds; 1459 int err, n; 1460 1461 if (get_user(idx, &ext->virtual_index)) 1462 return -EFAULT; 1463 1464 if (idx >= set->engines->num_engines) { 1465 DRM_DEBUG("Invalid index for virtual engine: %d >= %d\n", 1466 idx, set->engines->num_engines); 1467 return -EINVAL; 1468 } 1469 1470 idx = array_index_nospec(idx, set->engines->num_engines); 1471 if (!set->engines->engines[idx]) { 1472 DRM_DEBUG("Invalid engine at %d\n", idx); 1473 return -EINVAL; 1474 } 1475 virtual = set->engines->engines[idx]->engine; 1476 1477 err = check_user_mbz(&ext->flags); 1478 if (err) 1479 return err; 1480 1481 for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) { 1482 err = check_user_mbz(&ext->mbz64[n]); 1483 if (err) 1484 return err; 1485 } 1486 1487 if (copy_from_user(&ci, &ext->master, sizeof(ci))) 1488 return -EFAULT; 1489 1490 master = intel_engine_lookup_user(set->ctx->i915, 1491 ci.engine_class, ci.engine_instance); 1492 if (!master) { 1493 DRM_DEBUG("Unrecognised master engine: { class:%u, instance:%u }\n", 1494 ci.engine_class, ci.engine_instance); 1495 return -EINVAL; 1496 } 1497 1498 if (get_user(num_bonds, &ext->num_bonds)) 1499 return -EFAULT; 1500 1501 for (n = 0; n < num_bonds; n++) { 1502 struct intel_engine_cs *bond; 1503 1504 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) 1505 return -EFAULT; 1506 1507 bond = intel_engine_lookup_user(set->ctx->i915, 1508 ci.engine_class, 1509 ci.engine_instance); 1510 if (!bond) { 1511 DRM_DEBUG("Unrecognised engine[%d] for bonding: { class:%d, instance: %d }\n", 1512 n, ci.engine_class, ci.engine_instance); 1513 return -EINVAL; 1514 } 1515 1516 /* 1517 * A non-virtual engine has no siblings to choose between; and 1518 * a submit fence will always be directed to the one engine. 1519 */ 1520 if (intel_engine_is_virtual(virtual)) { 1521 err = intel_virtual_engine_attach_bond(virtual, 1522 master, 1523 bond); 1524 if (err) 1525 return err; 1526 } 1527 } 1528 1529 return 0; 1530 } 1531 1532 static const i915_user_extension_fn set_engines__extensions[] = { 1533 [I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE] = set_engines__load_balance, 1534 [I915_CONTEXT_ENGINES_EXT_BOND] = set_engines__bond, 1535 }; 1536 1537 static int 1538 set_engines(struct i915_gem_context *ctx, 1539 const struct drm_i915_gem_context_param *args) 1540 { 1541 struct i915_context_param_engines __user *user = 1542 u64_to_user_ptr(args->value); 1543 struct set_engines set = { .ctx = ctx }; 1544 unsigned int num_engines, n; 1545 u64 extensions; 1546 int err; 1547 1548 if (!args->size) { /* switch back to legacy user_ring_map */ 1549 if (!i915_gem_context_user_engines(ctx)) 1550 return 0; 1551 1552 set.engines = default_engines(ctx); 1553 if (IS_ERR(set.engines)) 1554 return PTR_ERR(set.engines); 1555 1556 goto replace; 1557 } 1558 1559 BUILD_BUG_ON(!IS_ALIGNED(sizeof(*user), sizeof(*user->engines))); 1560 if (args->size < sizeof(*user) || 1561 !IS_ALIGNED(args->size, sizeof(*user->engines))) { 1562 DRM_DEBUG("Invalid size for engine array: %d\n", 1563 args->size); 1564 return -EINVAL; 1565 } 1566 1567 /* 1568 * Note that I915_EXEC_RING_MASK limits execbuf to only using the 1569 * first 64 engines defined here. 1570 */ 1571 num_engines = (args->size - sizeof(*user)) / sizeof(*user->engines); 1572 1573 set.engines = kmalloc(struct_size(set.engines, engines, num_engines), 1574 GFP_KERNEL); 1575 if (!set.engines) 1576 return -ENOMEM; 1577 1578 init_rcu_head(&set.engines->rcu); 1579 for (n = 0; n < num_engines; n++) { 1580 struct i915_engine_class_instance ci; 1581 struct intel_engine_cs *engine; 1582 struct intel_context *ce; 1583 1584 if (copy_from_user(&ci, &user->engines[n], sizeof(ci))) { 1585 __free_engines(set.engines, n); 1586 return -EFAULT; 1587 } 1588 1589 if (ci.engine_class == (u16)I915_ENGINE_CLASS_INVALID && 1590 ci.engine_instance == (u16)I915_ENGINE_CLASS_INVALID_NONE) { 1591 set.engines->engines[n] = NULL; 1592 continue; 1593 } 1594 1595 engine = intel_engine_lookup_user(ctx->i915, 1596 ci.engine_class, 1597 ci.engine_instance); 1598 if (!engine) { 1599 DRM_DEBUG("Invalid engine[%d]: { class:%d, instance:%d }\n", 1600 n, ci.engine_class, ci.engine_instance); 1601 __free_engines(set.engines, n); 1602 return -ENOENT; 1603 } 1604 1605 ce = intel_context_create(ctx, engine); 1606 if (IS_ERR(ce)) { 1607 __free_engines(set.engines, n); 1608 return PTR_ERR(ce); 1609 } 1610 1611 set.engines->engines[n] = ce; 1612 } 1613 set.engines->num_engines = num_engines; 1614 1615 err = -EFAULT; 1616 if (!get_user(extensions, &user->extensions)) 1617 err = i915_user_extensions(u64_to_user_ptr(extensions), 1618 set_engines__extensions, 1619 ARRAY_SIZE(set_engines__extensions), 1620 &set); 1621 if (err) { 1622 free_engines(set.engines); 1623 return err; 1624 } 1625 1626 replace: 1627 mutex_lock(&ctx->engines_mutex); 1628 if (args->size) 1629 i915_gem_context_set_user_engines(ctx); 1630 else 1631 i915_gem_context_clear_user_engines(ctx); 1632 rcu_swap_protected(ctx->engines, set.engines, 1); 1633 mutex_unlock(&ctx->engines_mutex); 1634 1635 call_rcu(&set.engines->rcu, free_engines_rcu); 1636 1637 return 0; 1638 } 1639 1640 static struct i915_gem_engines * 1641 __copy_engines(struct i915_gem_engines *e) 1642 { 1643 struct i915_gem_engines *copy; 1644 unsigned int n; 1645 1646 copy = kmalloc(struct_size(e, engines, e->num_engines), GFP_KERNEL); 1647 if (!copy) 1648 return ERR_PTR(-ENOMEM); 1649 1650 init_rcu_head(©->rcu); 1651 for (n = 0; n < e->num_engines; n++) { 1652 if (e->engines[n]) 1653 copy->engines[n] = intel_context_get(e->engines[n]); 1654 else 1655 copy->engines[n] = NULL; 1656 } 1657 copy->num_engines = n; 1658 1659 return copy; 1660 } 1661 1662 static int 1663 get_engines(struct i915_gem_context *ctx, 1664 struct drm_i915_gem_context_param *args) 1665 { 1666 struct i915_context_param_engines __user *user; 1667 struct i915_gem_engines *e; 1668 size_t n, count, size; 1669 int err = 0; 1670 1671 err = mutex_lock_interruptible(&ctx->engines_mutex); 1672 if (err) 1673 return err; 1674 1675 e = NULL; 1676 if (i915_gem_context_user_engines(ctx)) 1677 e = __copy_engines(i915_gem_context_engines(ctx)); 1678 mutex_unlock(&ctx->engines_mutex); 1679 if (IS_ERR_OR_NULL(e)) { 1680 args->size = 0; 1681 return PTR_ERR_OR_ZERO(e); 1682 } 1683 1684 count = e->num_engines; 1685 1686 /* Be paranoid in case we have an impedance mismatch */ 1687 if (!check_struct_size(user, engines, count, &size)) { 1688 err = -EINVAL; 1689 goto err_free; 1690 } 1691 if (overflows_type(size, args->size)) { 1692 err = -EINVAL; 1693 goto err_free; 1694 } 1695 1696 if (!args->size) { 1697 args->size = size; 1698 goto err_free; 1699 } 1700 1701 if (args->size < size) { 1702 err = -EINVAL; 1703 goto err_free; 1704 } 1705 1706 user = u64_to_user_ptr(args->value); 1707 if (!access_ok(user, size)) { 1708 err = -EFAULT; 1709 goto err_free; 1710 } 1711 1712 if (put_user(0, &user->extensions)) { 1713 err = -EFAULT; 1714 goto err_free; 1715 } 1716 1717 for (n = 0; n < count; n++) { 1718 struct i915_engine_class_instance ci = { 1719 .engine_class = I915_ENGINE_CLASS_INVALID, 1720 .engine_instance = I915_ENGINE_CLASS_INVALID_NONE, 1721 }; 1722 1723 if (e->engines[n]) { 1724 ci.engine_class = e->engines[n]->engine->uabi_class; 1725 ci.engine_instance = e->engines[n]->engine->uabi_instance; 1726 } 1727 1728 if (copy_to_user(&user->engines[n], &ci, sizeof(ci))) { 1729 err = -EFAULT; 1730 goto err_free; 1731 } 1732 } 1733 1734 args->size = size; 1735 1736 err_free: 1737 free_engines(e); 1738 return err; 1739 } 1740 1741 static int ctx_setparam(struct drm_i915_file_private *fpriv, 1742 struct i915_gem_context *ctx, 1743 struct drm_i915_gem_context_param *args) 1744 { 1745 int ret = 0; 1746 1747 switch (args->param) { 1748 case I915_CONTEXT_PARAM_NO_ZEROMAP: 1749 if (args->size) 1750 ret = -EINVAL; 1751 else if (args->value) 1752 set_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags); 1753 else 1754 clear_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags); 1755 break; 1756 1757 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: 1758 if (args->size) 1759 ret = -EINVAL; 1760 else if (args->value) 1761 i915_gem_context_set_no_error_capture(ctx); 1762 else 1763 i915_gem_context_clear_no_error_capture(ctx); 1764 break; 1765 1766 case I915_CONTEXT_PARAM_BANNABLE: 1767 if (args->size) 1768 ret = -EINVAL; 1769 else if (!capable(CAP_SYS_ADMIN) && !args->value) 1770 ret = -EPERM; 1771 else if (args->value) 1772 i915_gem_context_set_bannable(ctx); 1773 else 1774 i915_gem_context_clear_bannable(ctx); 1775 break; 1776 1777 case I915_CONTEXT_PARAM_RECOVERABLE: 1778 if (args->size) 1779 ret = -EINVAL; 1780 else if (args->value) 1781 i915_gem_context_set_recoverable(ctx); 1782 else 1783 i915_gem_context_clear_recoverable(ctx); 1784 break; 1785 1786 case I915_CONTEXT_PARAM_PRIORITY: 1787 { 1788 s64 priority = args->value; 1789 1790 if (args->size) 1791 ret = -EINVAL; 1792 else if (!(ctx->i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY)) 1793 ret = -ENODEV; 1794 else if (priority > I915_CONTEXT_MAX_USER_PRIORITY || 1795 priority < I915_CONTEXT_MIN_USER_PRIORITY) 1796 ret = -EINVAL; 1797 else if (priority > I915_CONTEXT_DEFAULT_PRIORITY && 1798 !capable(CAP_SYS_NICE)) 1799 ret = -EPERM; 1800 else 1801 ctx->sched.priority = 1802 I915_USER_PRIORITY(priority); 1803 } 1804 break; 1805 1806 case I915_CONTEXT_PARAM_SSEU: 1807 ret = set_sseu(ctx, args); 1808 break; 1809 1810 case I915_CONTEXT_PARAM_VM: 1811 ret = set_ppgtt(fpriv, ctx, args); 1812 break; 1813 1814 case I915_CONTEXT_PARAM_ENGINES: 1815 ret = set_engines(ctx, args); 1816 break; 1817 1818 case I915_CONTEXT_PARAM_BAN_PERIOD: 1819 default: 1820 ret = -EINVAL; 1821 break; 1822 } 1823 1824 return ret; 1825 } 1826 1827 struct create_ext { 1828 struct i915_gem_context *ctx; 1829 struct drm_i915_file_private *fpriv; 1830 }; 1831 1832 static int create_setparam(struct i915_user_extension __user *ext, void *data) 1833 { 1834 struct drm_i915_gem_context_create_ext_setparam local; 1835 const struct create_ext *arg = data; 1836 1837 if (copy_from_user(&local, ext, sizeof(local))) 1838 return -EFAULT; 1839 1840 if (local.param.ctx_id) 1841 return -EINVAL; 1842 1843 return ctx_setparam(arg->fpriv, arg->ctx, &local.param); 1844 } 1845 1846 static int clone_engines(struct i915_gem_context *dst, 1847 struct i915_gem_context *src) 1848 { 1849 struct i915_gem_engines *e = i915_gem_context_lock_engines(src); 1850 struct i915_gem_engines *clone; 1851 bool user_engines; 1852 unsigned long n; 1853 1854 clone = kmalloc(struct_size(e, engines, e->num_engines), GFP_KERNEL); 1855 if (!clone) 1856 goto err_unlock; 1857 1858 init_rcu_head(&clone->rcu); 1859 for (n = 0; n < e->num_engines; n++) { 1860 struct intel_engine_cs *engine; 1861 1862 if (!e->engines[n]) { 1863 clone->engines[n] = NULL; 1864 continue; 1865 } 1866 engine = e->engines[n]->engine; 1867 1868 /* 1869 * Virtual engines are singletons; they can only exist 1870 * inside a single context, because they embed their 1871 * HW context... As each virtual context implies a single 1872 * timeline (each engine can only dequeue a single request 1873 * at any time), it would be surprising for two contexts 1874 * to use the same engine. So let's create a copy of 1875 * the virtual engine instead. 1876 */ 1877 if (intel_engine_is_virtual(engine)) 1878 clone->engines[n] = 1879 intel_execlists_clone_virtual(dst, engine); 1880 else 1881 clone->engines[n] = intel_context_create(dst, engine); 1882 if (IS_ERR_OR_NULL(clone->engines[n])) { 1883 __free_engines(clone, n); 1884 goto err_unlock; 1885 } 1886 } 1887 clone->num_engines = n; 1888 1889 user_engines = i915_gem_context_user_engines(src); 1890 i915_gem_context_unlock_engines(src); 1891 1892 free_engines(dst->engines); 1893 RCU_INIT_POINTER(dst->engines, clone); 1894 if (user_engines) 1895 i915_gem_context_set_user_engines(dst); 1896 else 1897 i915_gem_context_clear_user_engines(dst); 1898 return 0; 1899 1900 err_unlock: 1901 i915_gem_context_unlock_engines(src); 1902 return -ENOMEM; 1903 } 1904 1905 static int clone_flags(struct i915_gem_context *dst, 1906 struct i915_gem_context *src) 1907 { 1908 dst->user_flags = src->user_flags; 1909 return 0; 1910 } 1911 1912 static int clone_schedattr(struct i915_gem_context *dst, 1913 struct i915_gem_context *src) 1914 { 1915 dst->sched = src->sched; 1916 return 0; 1917 } 1918 1919 static int clone_sseu(struct i915_gem_context *dst, 1920 struct i915_gem_context *src) 1921 { 1922 struct i915_gem_engines *e = i915_gem_context_lock_engines(src); 1923 struct i915_gem_engines *clone; 1924 unsigned long n; 1925 int err; 1926 1927 clone = dst->engines; /* no locking required; sole access */ 1928 if (e->num_engines != clone->num_engines) { 1929 err = -EINVAL; 1930 goto unlock; 1931 } 1932 1933 for (n = 0; n < e->num_engines; n++) { 1934 struct intel_context *ce = e->engines[n]; 1935 1936 if (clone->engines[n]->engine->class != ce->engine->class) { 1937 /* Must have compatible engine maps! */ 1938 err = -EINVAL; 1939 goto unlock; 1940 } 1941 1942 /* serialises with set_sseu */ 1943 err = intel_context_lock_pinned(ce); 1944 if (err) 1945 goto unlock; 1946 1947 clone->engines[n]->sseu = ce->sseu; 1948 intel_context_unlock_pinned(ce); 1949 } 1950 1951 err = 0; 1952 unlock: 1953 i915_gem_context_unlock_engines(src); 1954 return err; 1955 } 1956 1957 static int clone_timeline(struct i915_gem_context *dst, 1958 struct i915_gem_context *src) 1959 { 1960 if (src->timeline) 1961 __assign_timeline(dst, src->timeline); 1962 1963 return 0; 1964 } 1965 1966 static int clone_vm(struct i915_gem_context *dst, 1967 struct i915_gem_context *src) 1968 { 1969 struct i915_address_space *vm; 1970 1971 rcu_read_lock(); 1972 do { 1973 vm = READ_ONCE(src->vm); 1974 if (!vm) 1975 break; 1976 1977 if (!kref_get_unless_zero(&vm->ref)) 1978 continue; 1979 1980 /* 1981 * This ppgtt may have be reallocated between 1982 * the read and the kref, and reassigned to a third 1983 * context. In order to avoid inadvertent sharing 1984 * of this ppgtt with that third context (and not 1985 * src), we have to confirm that we have the same 1986 * ppgtt after passing through the strong memory 1987 * barrier implied by a successful 1988 * kref_get_unless_zero(). 1989 * 1990 * Once we have acquired the current ppgtt of src, 1991 * we no longer care if it is released from src, as 1992 * it cannot be reallocated elsewhere. 1993 */ 1994 1995 if (vm == READ_ONCE(src->vm)) 1996 break; 1997 1998 i915_vm_put(vm); 1999 } while (1); 2000 rcu_read_unlock(); 2001 2002 if (vm) { 2003 __assign_ppgtt(dst, vm); 2004 i915_vm_put(vm); 2005 } 2006 2007 return 0; 2008 } 2009 2010 static int create_clone(struct i915_user_extension __user *ext, void *data) 2011 { 2012 static int (* const fn[])(struct i915_gem_context *dst, 2013 struct i915_gem_context *src) = { 2014 #define MAP(x, y) [ilog2(I915_CONTEXT_CLONE_##x)] = y 2015 MAP(ENGINES, clone_engines), 2016 MAP(FLAGS, clone_flags), 2017 MAP(SCHEDATTR, clone_schedattr), 2018 MAP(SSEU, clone_sseu), 2019 MAP(TIMELINE, clone_timeline), 2020 MAP(VM, clone_vm), 2021 #undef MAP 2022 }; 2023 struct drm_i915_gem_context_create_ext_clone local; 2024 const struct create_ext *arg = data; 2025 struct i915_gem_context *dst = arg->ctx; 2026 struct i915_gem_context *src; 2027 int err, bit; 2028 2029 if (copy_from_user(&local, ext, sizeof(local))) 2030 return -EFAULT; 2031 2032 BUILD_BUG_ON(GENMASK(BITS_PER_TYPE(local.flags) - 1, ARRAY_SIZE(fn)) != 2033 I915_CONTEXT_CLONE_UNKNOWN); 2034 2035 if (local.flags & I915_CONTEXT_CLONE_UNKNOWN) 2036 return -EINVAL; 2037 2038 if (local.rsvd) 2039 return -EINVAL; 2040 2041 rcu_read_lock(); 2042 src = __i915_gem_context_lookup_rcu(arg->fpriv, local.clone_id); 2043 rcu_read_unlock(); 2044 if (!src) 2045 return -ENOENT; 2046 2047 GEM_BUG_ON(src == dst); 2048 2049 for (bit = 0; bit < ARRAY_SIZE(fn); bit++) { 2050 if (!(local.flags & BIT(bit))) 2051 continue; 2052 2053 err = fn[bit](dst, src); 2054 if (err) 2055 return err; 2056 } 2057 2058 return 0; 2059 } 2060 2061 static const i915_user_extension_fn create_extensions[] = { 2062 [I915_CONTEXT_CREATE_EXT_SETPARAM] = create_setparam, 2063 [I915_CONTEXT_CREATE_EXT_CLONE] = create_clone, 2064 }; 2065 2066 static bool client_is_banned(struct drm_i915_file_private *file_priv) 2067 { 2068 return atomic_read(&file_priv->ban_score) >= I915_CLIENT_SCORE_BANNED; 2069 } 2070 2071 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 2072 struct drm_file *file) 2073 { 2074 struct drm_i915_private *i915 = to_i915(dev); 2075 struct drm_i915_gem_context_create_ext *args = data; 2076 struct create_ext ext_data; 2077 int ret; 2078 2079 if (!DRIVER_CAPS(i915)->has_logical_contexts) 2080 return -ENODEV; 2081 2082 if (args->flags & I915_CONTEXT_CREATE_FLAGS_UNKNOWN) 2083 return -EINVAL; 2084 2085 ret = intel_gt_terminally_wedged(&i915->gt); 2086 if (ret) 2087 return ret; 2088 2089 ext_data.fpriv = file->driver_priv; 2090 if (client_is_banned(ext_data.fpriv)) { 2091 DRM_DEBUG("client %s[%d] banned from creating ctx\n", 2092 current->comm, 2093 pid_nr(get_task_pid(current, PIDTYPE_PID))); 2094 return -EIO; 2095 } 2096 2097 ret = i915_mutex_lock_interruptible(dev); 2098 if (ret) 2099 return ret; 2100 2101 ext_data.ctx = i915_gem_create_context(i915, args->flags); 2102 mutex_unlock(&dev->struct_mutex); 2103 if (IS_ERR(ext_data.ctx)) 2104 return PTR_ERR(ext_data.ctx); 2105 2106 if (args->flags & I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS) { 2107 ret = i915_user_extensions(u64_to_user_ptr(args->extensions), 2108 create_extensions, 2109 ARRAY_SIZE(create_extensions), 2110 &ext_data); 2111 if (ret) 2112 goto err_ctx; 2113 } 2114 2115 ret = gem_context_register(ext_data.ctx, ext_data.fpriv); 2116 if (ret < 0) 2117 goto err_ctx; 2118 2119 args->ctx_id = ret; 2120 DRM_DEBUG("HW context %d created\n", args->ctx_id); 2121 2122 return 0; 2123 2124 err_ctx: 2125 context_close(ext_data.ctx); 2126 return ret; 2127 } 2128 2129 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 2130 struct drm_file *file) 2131 { 2132 struct drm_i915_gem_context_destroy *args = data; 2133 struct drm_i915_file_private *file_priv = file->driver_priv; 2134 struct i915_gem_context *ctx; 2135 2136 if (args->pad != 0) 2137 return -EINVAL; 2138 2139 if (!args->ctx_id) 2140 return -ENOENT; 2141 2142 if (mutex_lock_interruptible(&file_priv->context_idr_lock)) 2143 return -EINTR; 2144 2145 ctx = idr_remove(&file_priv->context_idr, args->ctx_id); 2146 mutex_unlock(&file_priv->context_idr_lock); 2147 if (!ctx) 2148 return -ENOENT; 2149 2150 context_close(ctx); 2151 return 0; 2152 } 2153 2154 static int get_sseu(struct i915_gem_context *ctx, 2155 struct drm_i915_gem_context_param *args) 2156 { 2157 struct drm_i915_gem_context_param_sseu user_sseu; 2158 struct intel_context *ce; 2159 unsigned long lookup; 2160 int err; 2161 2162 if (args->size == 0) 2163 goto out; 2164 else if (args->size < sizeof(user_sseu)) 2165 return -EINVAL; 2166 2167 if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value), 2168 sizeof(user_sseu))) 2169 return -EFAULT; 2170 2171 if (user_sseu.rsvd) 2172 return -EINVAL; 2173 2174 if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)) 2175 return -EINVAL; 2176 2177 lookup = 0; 2178 if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX) 2179 lookup |= LOOKUP_USER_INDEX; 2180 2181 ce = lookup_user_engine(ctx, lookup, &user_sseu.engine); 2182 if (IS_ERR(ce)) 2183 return PTR_ERR(ce); 2184 2185 err = intel_context_lock_pinned(ce); /* serialises with set_sseu */ 2186 if (err) { 2187 intel_context_put(ce); 2188 return err; 2189 } 2190 2191 user_sseu.slice_mask = ce->sseu.slice_mask; 2192 user_sseu.subslice_mask = ce->sseu.subslice_mask; 2193 user_sseu.min_eus_per_subslice = ce->sseu.min_eus_per_subslice; 2194 user_sseu.max_eus_per_subslice = ce->sseu.max_eus_per_subslice; 2195 2196 intel_context_unlock_pinned(ce); 2197 intel_context_put(ce); 2198 2199 if (copy_to_user(u64_to_user_ptr(args->value), &user_sseu, 2200 sizeof(user_sseu))) 2201 return -EFAULT; 2202 2203 out: 2204 args->size = sizeof(user_sseu); 2205 2206 return 0; 2207 } 2208 2209 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, 2210 struct drm_file *file) 2211 { 2212 struct drm_i915_file_private *file_priv = file->driver_priv; 2213 struct drm_i915_gem_context_param *args = data; 2214 struct i915_gem_context *ctx; 2215 int ret = 0; 2216 2217 ctx = i915_gem_context_lookup(file_priv, args->ctx_id); 2218 if (!ctx) 2219 return -ENOENT; 2220 2221 switch (args->param) { 2222 case I915_CONTEXT_PARAM_NO_ZEROMAP: 2223 args->size = 0; 2224 args->value = test_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags); 2225 break; 2226 2227 case I915_CONTEXT_PARAM_GTT_SIZE: 2228 args->size = 0; 2229 if (ctx->vm) 2230 args->value = ctx->vm->total; 2231 else if (to_i915(dev)->ggtt.alias) 2232 args->value = to_i915(dev)->ggtt.alias->vm.total; 2233 else 2234 args->value = to_i915(dev)->ggtt.vm.total; 2235 break; 2236 2237 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: 2238 args->size = 0; 2239 args->value = i915_gem_context_no_error_capture(ctx); 2240 break; 2241 2242 case I915_CONTEXT_PARAM_BANNABLE: 2243 args->size = 0; 2244 args->value = i915_gem_context_is_bannable(ctx); 2245 break; 2246 2247 case I915_CONTEXT_PARAM_RECOVERABLE: 2248 args->size = 0; 2249 args->value = i915_gem_context_is_recoverable(ctx); 2250 break; 2251 2252 case I915_CONTEXT_PARAM_PRIORITY: 2253 args->size = 0; 2254 args->value = ctx->sched.priority >> I915_USER_PRIORITY_SHIFT; 2255 break; 2256 2257 case I915_CONTEXT_PARAM_SSEU: 2258 ret = get_sseu(ctx, args); 2259 break; 2260 2261 case I915_CONTEXT_PARAM_VM: 2262 ret = get_ppgtt(file_priv, ctx, args); 2263 break; 2264 2265 case I915_CONTEXT_PARAM_ENGINES: 2266 ret = get_engines(ctx, args); 2267 break; 2268 2269 case I915_CONTEXT_PARAM_BAN_PERIOD: 2270 default: 2271 ret = -EINVAL; 2272 break; 2273 } 2274 2275 i915_gem_context_put(ctx); 2276 return ret; 2277 } 2278 2279 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, 2280 struct drm_file *file) 2281 { 2282 struct drm_i915_file_private *file_priv = file->driver_priv; 2283 struct drm_i915_gem_context_param *args = data; 2284 struct i915_gem_context *ctx; 2285 int ret; 2286 2287 ctx = i915_gem_context_lookup(file_priv, args->ctx_id); 2288 if (!ctx) 2289 return -ENOENT; 2290 2291 ret = ctx_setparam(file_priv, ctx, args); 2292 2293 i915_gem_context_put(ctx); 2294 return ret; 2295 } 2296 2297 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, 2298 void *data, struct drm_file *file) 2299 { 2300 struct drm_i915_private *dev_priv = to_i915(dev); 2301 struct drm_i915_reset_stats *args = data; 2302 struct i915_gem_context *ctx; 2303 int ret; 2304 2305 if (args->flags || args->pad) 2306 return -EINVAL; 2307 2308 ret = -ENOENT; 2309 rcu_read_lock(); 2310 ctx = __i915_gem_context_lookup_rcu(file->driver_priv, args->ctx_id); 2311 if (!ctx) 2312 goto out; 2313 2314 /* 2315 * We opt for unserialised reads here. This may result in tearing 2316 * in the extremely unlikely event of a GPU hang on this context 2317 * as we are querying them. If we need that extra layer of protection, 2318 * we should wrap the hangstats with a seqlock. 2319 */ 2320 2321 if (capable(CAP_SYS_ADMIN)) 2322 args->reset_count = i915_reset_count(&dev_priv->gpu_error); 2323 else 2324 args->reset_count = 0; 2325 2326 args->batch_active = atomic_read(&ctx->guilty_count); 2327 args->batch_pending = atomic_read(&ctx->active_count); 2328 2329 ret = 0; 2330 out: 2331 rcu_read_unlock(); 2332 return ret; 2333 } 2334 2335 int __i915_gem_context_pin_hw_id(struct i915_gem_context *ctx) 2336 { 2337 struct drm_i915_private *i915 = ctx->i915; 2338 int err = 0; 2339 2340 mutex_lock(&i915->contexts.mutex); 2341 2342 GEM_BUG_ON(i915_gem_context_is_closed(ctx)); 2343 2344 if (list_empty(&ctx->hw_id_link)) { 2345 GEM_BUG_ON(atomic_read(&ctx->hw_id_pin_count)); 2346 2347 err = assign_hw_id(i915, &ctx->hw_id); 2348 if (err) 2349 goto out_unlock; 2350 2351 list_add_tail(&ctx->hw_id_link, &i915->contexts.hw_id_list); 2352 } 2353 2354 GEM_BUG_ON(atomic_read(&ctx->hw_id_pin_count) == ~0u); 2355 atomic_inc(&ctx->hw_id_pin_count); 2356 2357 out_unlock: 2358 mutex_unlock(&i915->contexts.mutex); 2359 return err; 2360 } 2361 2362 /* GEM context-engines iterator: for_each_gem_engine() */ 2363 struct intel_context * 2364 i915_gem_engines_iter_next(struct i915_gem_engines_iter *it) 2365 { 2366 const struct i915_gem_engines *e = it->engines; 2367 struct intel_context *ctx; 2368 2369 do { 2370 if (it->idx >= e->num_engines) 2371 return NULL; 2372 2373 ctx = e->engines[it->idx++]; 2374 } while (!ctx); 2375 2376 return ctx; 2377 } 2378 2379 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2380 #include "selftests/mock_context.c" 2381 #include "selftests/i915_gem_context.c" 2382 #endif 2383 2384 static void i915_global_gem_context_shrink(void) 2385 { 2386 kmem_cache_shrink(global.slab_luts); 2387 } 2388 2389 static void i915_global_gem_context_exit(void) 2390 { 2391 kmem_cache_destroy(global.slab_luts); 2392 } 2393 2394 static struct i915_global_gem_context global = { { 2395 .shrink = i915_global_gem_context_shrink, 2396 .exit = i915_global_gem_context_exit, 2397 } }; 2398 2399 int __init i915_global_gem_context_init(void) 2400 { 2401 global.slab_luts = KMEM_CACHE(i915_lut_handle, 0); 2402 if (!global.slab_luts) 2403 return -ENOMEM; 2404 2405 i915_global_register(&global.base); 2406 return 0; 2407 } 2408