1 /*
2  * SPDX-License-Identifier: MIT
3  *
4  * Copyright © 2011-2012 Intel Corporation
5  */
6 
7 /*
8  * This file implements HW context support. On gen5+ a HW context consists of an
9  * opaque GPU object which is referenced at times of context saves and restores.
10  * With RC6 enabled, the context is also referenced as the GPU enters and exists
11  * from RC6 (GPU has it's own internal power context, except on gen5). Though
12  * something like a context does exist for the media ring, the code only
13  * supports contexts for the render ring.
14  *
15  * In software, there is a distinction between contexts created by the user,
16  * and the default HW context. The default HW context is used by GPU clients
17  * that do not request setup of their own hardware context. The default
18  * context's state is never restored to help prevent programming errors. This
19  * would happen if a client ran and piggy-backed off another clients GPU state.
20  * The default context only exists to give the GPU some offset to load as the
21  * current to invoke a save of the context we actually care about. In fact, the
22  * code could likely be constructed, albeit in a more complicated fashion, to
23  * never use the default context, though that limits the driver's ability to
24  * swap out, and/or destroy other contexts.
25  *
26  * All other contexts are created as a request by the GPU client. These contexts
27  * store GPU state, and thus allow GPU clients to not re-emit state (and
28  * potentially query certain state) at any time. The kernel driver makes
29  * certain that the appropriate commands are inserted.
30  *
31  * The context life cycle is semi-complicated in that context BOs may live
32  * longer than the context itself because of the way the hardware, and object
33  * tracking works. Below is a very crude representation of the state machine
34  * describing the context life.
35  *                                         refcount     pincount     active
36  * S0: initial state                          0            0           0
37  * S1: context created                        1            0           0
38  * S2: context is currently running           2            1           X
39  * S3: GPU referenced, but not current        2            0           1
40  * S4: context is current, but destroyed      1            1           0
41  * S5: like S3, but destroyed                 1            0           1
42  *
43  * The most common (but not all) transitions:
44  * S0->S1: client creates a context
45  * S1->S2: client submits execbuf with context
46  * S2->S3: other clients submits execbuf with context
47  * S3->S1: context object was retired
48  * S3->S2: clients submits another execbuf
49  * S2->S4: context destroy called with current context
50  * S3->S5->S0: destroy path
51  * S4->S5->S0: destroy path on current context
52  *
53  * There are two confusing terms used above:
54  *  The "current context" means the context which is currently running on the
55  *  GPU. The GPU has loaded its state already and has stored away the gtt
56  *  offset of the BO. The GPU is not actively referencing the data at this
57  *  offset, but it will on the next context switch. The only way to avoid this
58  *  is to do a GPU reset.
59  *
60  *  An "active context' is one which was previously the "current context" and is
61  *  on the active list waiting for the next context switch to occur. Until this
62  *  happens, the object must remain at the same gtt offset. It is therefore
63  *  possible to destroy a context, but it is still active.
64  *
65  */
66 
67 #include <linux/highmem.h>
68 #include <linux/log2.h>
69 #include <linux/nospec.h>
70 
71 #include <drm/drm_cache.h>
72 #include <drm/drm_syncobj.h>
73 
74 #include "gt/gen6_ppgtt.h"
75 #include "gt/intel_context.h"
76 #include "gt/intel_context_param.h"
77 #include "gt/intel_engine_heartbeat.h"
78 #include "gt/intel_engine_user.h"
79 #include "gt/intel_gpu_commands.h"
80 #include "gt/intel_ring.h"
81 
82 #include "pxp/intel_pxp.h"
83 
84 #include "i915_file_private.h"
85 #include "i915_gem_context.h"
86 #include "i915_trace.h"
87 #include "i915_user_extensions.h"
88 
89 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
90 
91 static struct kmem_cache *slab_luts;
92 
93 struct i915_lut_handle *i915_lut_handle_alloc(void)
94 {
95 	return kmem_cache_alloc(slab_luts, GFP_KERNEL);
96 }
97 
98 void i915_lut_handle_free(struct i915_lut_handle *lut)
99 {
100 	return kmem_cache_free(slab_luts, lut);
101 }
102 
103 static void lut_close(struct i915_gem_context *ctx)
104 {
105 	struct radix_tree_iter iter;
106 	void __rcu **slot;
107 
108 	mutex_lock(&ctx->lut_mutex);
109 	rcu_read_lock();
110 	radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) {
111 		struct i915_vma *vma = rcu_dereference_raw(*slot);
112 		struct drm_i915_gem_object *obj = vma->obj;
113 		struct i915_lut_handle *lut;
114 
115 		if (!kref_get_unless_zero(&obj->base.refcount))
116 			continue;
117 
118 		spin_lock(&obj->lut_lock);
119 		list_for_each_entry(lut, &obj->lut_list, obj_link) {
120 			if (lut->ctx != ctx)
121 				continue;
122 
123 			if (lut->handle != iter.index)
124 				continue;
125 
126 			list_del(&lut->obj_link);
127 			break;
128 		}
129 		spin_unlock(&obj->lut_lock);
130 
131 		if (&lut->obj_link != &obj->lut_list) {
132 			i915_lut_handle_free(lut);
133 			radix_tree_iter_delete(&ctx->handles_vma, &iter, slot);
134 			i915_vma_close(vma);
135 			i915_gem_object_put(obj);
136 		}
137 
138 		i915_gem_object_put(obj);
139 	}
140 	rcu_read_unlock();
141 	mutex_unlock(&ctx->lut_mutex);
142 }
143 
144 static struct intel_context *
145 lookup_user_engine(struct i915_gem_context *ctx,
146 		   unsigned long flags,
147 		   const struct i915_engine_class_instance *ci)
148 #define LOOKUP_USER_INDEX BIT(0)
149 {
150 	int idx;
151 
152 	if (!!(flags & LOOKUP_USER_INDEX) != i915_gem_context_user_engines(ctx))
153 		return ERR_PTR(-EINVAL);
154 
155 	if (!i915_gem_context_user_engines(ctx)) {
156 		struct intel_engine_cs *engine;
157 
158 		engine = intel_engine_lookup_user(ctx->i915,
159 						  ci->engine_class,
160 						  ci->engine_instance);
161 		if (!engine)
162 			return ERR_PTR(-EINVAL);
163 
164 		idx = engine->legacy_idx;
165 	} else {
166 		idx = ci->engine_instance;
167 	}
168 
169 	return i915_gem_context_get_engine(ctx, idx);
170 }
171 
172 static int validate_priority(struct drm_i915_private *i915,
173 			     const struct drm_i915_gem_context_param *args)
174 {
175 	s64 priority = args->value;
176 
177 	if (args->size)
178 		return -EINVAL;
179 
180 	if (!(i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY))
181 		return -ENODEV;
182 
183 	if (priority > I915_CONTEXT_MAX_USER_PRIORITY ||
184 	    priority < I915_CONTEXT_MIN_USER_PRIORITY)
185 		return -EINVAL;
186 
187 	if (priority > I915_CONTEXT_DEFAULT_PRIORITY &&
188 	    !capable(CAP_SYS_NICE))
189 		return -EPERM;
190 
191 	return 0;
192 }
193 
194 static void proto_context_close(struct drm_i915_private *i915,
195 				struct i915_gem_proto_context *pc)
196 {
197 	int i;
198 
199 	if (pc->pxp_wakeref)
200 		intel_runtime_pm_put(&i915->runtime_pm, pc->pxp_wakeref);
201 	if (pc->vm)
202 		i915_vm_put(pc->vm);
203 	if (pc->user_engines) {
204 		for (i = 0; i < pc->num_user_engines; i++)
205 			kfree(pc->user_engines[i].siblings);
206 		kfree(pc->user_engines);
207 	}
208 	kfree(pc);
209 }
210 
211 static int proto_context_set_persistence(struct drm_i915_private *i915,
212 					 struct i915_gem_proto_context *pc,
213 					 bool persist)
214 {
215 	if (persist) {
216 		/*
217 		 * Only contexts that are short-lived [that will expire or be
218 		 * reset] are allowed to survive past termination. We require
219 		 * hangcheck to ensure that the persistent requests are healthy.
220 		 */
221 		if (!i915->params.enable_hangcheck)
222 			return -EINVAL;
223 
224 		pc->user_flags |= BIT(UCONTEXT_PERSISTENCE);
225 	} else {
226 		/* To cancel a context we use "preempt-to-idle" */
227 		if (!(i915->caps.scheduler & I915_SCHEDULER_CAP_PREEMPTION))
228 			return -ENODEV;
229 
230 		/*
231 		 * If the cancel fails, we then need to reset, cleanly!
232 		 *
233 		 * If the per-engine reset fails, all hope is lost! We resort
234 		 * to a full GPU reset in that unlikely case, but realistically
235 		 * if the engine could not reset, the full reset does not fare
236 		 * much better. The damage has been done.
237 		 *
238 		 * However, if we cannot reset an engine by itself, we cannot
239 		 * cleanup a hanging persistent context without causing
240 		 * colateral damage, and we should not pretend we can by
241 		 * exposing the interface.
242 		 */
243 		if (!intel_has_reset_engine(to_gt(i915)))
244 			return -ENODEV;
245 
246 		pc->user_flags &= ~BIT(UCONTEXT_PERSISTENCE);
247 	}
248 
249 	return 0;
250 }
251 
252 static int proto_context_set_protected(struct drm_i915_private *i915,
253 				       struct i915_gem_proto_context *pc,
254 				       bool protected)
255 {
256 	int ret = 0;
257 
258 	if (!protected) {
259 		pc->uses_protected_content = false;
260 	} else if (!intel_pxp_is_enabled(i915->pxp)) {
261 		ret = -ENODEV;
262 	} else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) ||
263 		   !(pc->user_flags & BIT(UCONTEXT_BANNABLE))) {
264 		ret = -EPERM;
265 	} else {
266 		pc->uses_protected_content = true;
267 
268 		/*
269 		 * protected context usage requires the PXP session to be up,
270 		 * which in turn requires the device to be active.
271 		 */
272 		pc->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm);
273 
274 		if (!intel_pxp_is_active(i915->pxp))
275 			ret = intel_pxp_start(i915->pxp);
276 	}
277 
278 	return ret;
279 }
280 
281 static struct i915_gem_proto_context *
282 proto_context_create(struct drm_i915_private *i915, unsigned int flags)
283 {
284 	struct i915_gem_proto_context *pc, *err;
285 
286 	pc = kzalloc(sizeof(*pc), GFP_KERNEL);
287 	if (!pc)
288 		return ERR_PTR(-ENOMEM);
289 
290 	pc->num_user_engines = -1;
291 	pc->user_engines = NULL;
292 	pc->user_flags = BIT(UCONTEXT_BANNABLE) |
293 			 BIT(UCONTEXT_RECOVERABLE);
294 	if (i915->params.enable_hangcheck)
295 		pc->user_flags |= BIT(UCONTEXT_PERSISTENCE);
296 	pc->sched.priority = I915_PRIORITY_NORMAL;
297 
298 	if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) {
299 		if (!HAS_EXECLISTS(i915)) {
300 			err = ERR_PTR(-EINVAL);
301 			goto proto_close;
302 		}
303 		pc->single_timeline = true;
304 	}
305 
306 	return pc;
307 
308 proto_close:
309 	proto_context_close(i915, pc);
310 	return err;
311 }
312 
313 static int proto_context_register_locked(struct drm_i915_file_private *fpriv,
314 					 struct i915_gem_proto_context *pc,
315 					 u32 *id)
316 {
317 	int ret;
318 	void *old;
319 
320 	lockdep_assert_held(&fpriv->proto_context_lock);
321 
322 	ret = xa_alloc(&fpriv->context_xa, id, NULL, xa_limit_32b, GFP_KERNEL);
323 	if (ret)
324 		return ret;
325 
326 	old = xa_store(&fpriv->proto_context_xa, *id, pc, GFP_KERNEL);
327 	if (xa_is_err(old)) {
328 		xa_erase(&fpriv->context_xa, *id);
329 		return xa_err(old);
330 	}
331 	WARN_ON(old);
332 
333 	return 0;
334 }
335 
336 static int proto_context_register(struct drm_i915_file_private *fpriv,
337 				  struct i915_gem_proto_context *pc,
338 				  u32 *id)
339 {
340 	int ret;
341 
342 	mutex_lock(&fpriv->proto_context_lock);
343 	ret = proto_context_register_locked(fpriv, pc, id);
344 	mutex_unlock(&fpriv->proto_context_lock);
345 
346 	return ret;
347 }
348 
349 static struct i915_address_space *
350 i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id)
351 {
352 	struct i915_address_space *vm;
353 
354 	xa_lock(&file_priv->vm_xa);
355 	vm = xa_load(&file_priv->vm_xa, id);
356 	if (vm)
357 		kref_get(&vm->ref);
358 	xa_unlock(&file_priv->vm_xa);
359 
360 	return vm;
361 }
362 
363 static int set_proto_ctx_vm(struct drm_i915_file_private *fpriv,
364 			    struct i915_gem_proto_context *pc,
365 			    const struct drm_i915_gem_context_param *args)
366 {
367 	struct drm_i915_private *i915 = fpriv->i915;
368 	struct i915_address_space *vm;
369 
370 	if (args->size)
371 		return -EINVAL;
372 
373 	if (!HAS_FULL_PPGTT(i915))
374 		return -ENODEV;
375 
376 	if (upper_32_bits(args->value))
377 		return -ENOENT;
378 
379 	vm = i915_gem_vm_lookup(fpriv, args->value);
380 	if (!vm)
381 		return -ENOENT;
382 
383 	if (pc->vm)
384 		i915_vm_put(pc->vm);
385 	pc->vm = vm;
386 
387 	return 0;
388 }
389 
390 struct set_proto_ctx_engines {
391 	struct drm_i915_private *i915;
392 	unsigned num_engines;
393 	struct i915_gem_proto_engine *engines;
394 };
395 
396 static int
397 set_proto_ctx_engines_balance(struct i915_user_extension __user *base,
398 			      void *data)
399 {
400 	struct i915_context_engines_load_balance __user *ext =
401 		container_of_user(base, typeof(*ext), base);
402 	const struct set_proto_ctx_engines *set = data;
403 	struct drm_i915_private *i915 = set->i915;
404 	struct intel_engine_cs **siblings;
405 	u16 num_siblings, idx;
406 	unsigned int n;
407 	int err;
408 
409 	if (!HAS_EXECLISTS(i915))
410 		return -ENODEV;
411 
412 	if (get_user(idx, &ext->engine_index))
413 		return -EFAULT;
414 
415 	if (idx >= set->num_engines) {
416 		drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
417 			idx, set->num_engines);
418 		return -EINVAL;
419 	}
420 
421 	idx = array_index_nospec(idx, set->num_engines);
422 	if (set->engines[idx].type != I915_GEM_ENGINE_TYPE_INVALID) {
423 		drm_dbg(&i915->drm,
424 			"Invalid placement[%d], already occupied\n", idx);
425 		return -EEXIST;
426 	}
427 
428 	if (get_user(num_siblings, &ext->num_siblings))
429 		return -EFAULT;
430 
431 	err = check_user_mbz(&ext->flags);
432 	if (err)
433 		return err;
434 
435 	err = check_user_mbz(&ext->mbz64);
436 	if (err)
437 		return err;
438 
439 	if (num_siblings == 0)
440 		return 0;
441 
442 	siblings = kmalloc_array(num_siblings, sizeof(*siblings), GFP_KERNEL);
443 	if (!siblings)
444 		return -ENOMEM;
445 
446 	for (n = 0; n < num_siblings; n++) {
447 		struct i915_engine_class_instance ci;
448 
449 		if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
450 			err = -EFAULT;
451 			goto err_siblings;
452 		}
453 
454 		siblings[n] = intel_engine_lookup_user(i915,
455 						       ci.engine_class,
456 						       ci.engine_instance);
457 		if (!siblings[n]) {
458 			drm_dbg(&i915->drm,
459 				"Invalid sibling[%d]: { class:%d, inst:%d }\n",
460 				n, ci.engine_class, ci.engine_instance);
461 			err = -EINVAL;
462 			goto err_siblings;
463 		}
464 	}
465 
466 	if (num_siblings == 1) {
467 		set->engines[idx].type = I915_GEM_ENGINE_TYPE_PHYSICAL;
468 		set->engines[idx].engine = siblings[0];
469 		kfree(siblings);
470 	} else {
471 		set->engines[idx].type = I915_GEM_ENGINE_TYPE_BALANCED;
472 		set->engines[idx].num_siblings = num_siblings;
473 		set->engines[idx].siblings = siblings;
474 	}
475 
476 	return 0;
477 
478 err_siblings:
479 	kfree(siblings);
480 
481 	return err;
482 }
483 
484 static int
485 set_proto_ctx_engines_bond(struct i915_user_extension __user *base, void *data)
486 {
487 	struct i915_context_engines_bond __user *ext =
488 		container_of_user(base, typeof(*ext), base);
489 	const struct set_proto_ctx_engines *set = data;
490 	struct drm_i915_private *i915 = set->i915;
491 	struct i915_engine_class_instance ci;
492 	struct intel_engine_cs *master;
493 	u16 idx, num_bonds;
494 	int err, n;
495 
496 	if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915) &&
497 	    !IS_ROCKETLAKE(i915) && !IS_ALDERLAKE_S(i915)) {
498 		drm_dbg(&i915->drm,
499 			"Bonding not supported on this platform\n");
500 		return -ENODEV;
501 	}
502 
503 	if (get_user(idx, &ext->virtual_index))
504 		return -EFAULT;
505 
506 	if (idx >= set->num_engines) {
507 		drm_dbg(&i915->drm,
508 			"Invalid index for virtual engine: %d >= %d\n",
509 			idx, set->num_engines);
510 		return -EINVAL;
511 	}
512 
513 	idx = array_index_nospec(idx, set->num_engines);
514 	if (set->engines[idx].type == I915_GEM_ENGINE_TYPE_INVALID) {
515 		drm_dbg(&i915->drm, "Invalid engine at %d\n", idx);
516 		return -EINVAL;
517 	}
518 
519 	if (set->engines[idx].type != I915_GEM_ENGINE_TYPE_PHYSICAL) {
520 		drm_dbg(&i915->drm,
521 			"Bonding with virtual engines not allowed\n");
522 		return -EINVAL;
523 	}
524 
525 	err = check_user_mbz(&ext->flags);
526 	if (err)
527 		return err;
528 
529 	for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
530 		err = check_user_mbz(&ext->mbz64[n]);
531 		if (err)
532 			return err;
533 	}
534 
535 	if (copy_from_user(&ci, &ext->master, sizeof(ci)))
536 		return -EFAULT;
537 
538 	master = intel_engine_lookup_user(i915,
539 					  ci.engine_class,
540 					  ci.engine_instance);
541 	if (!master) {
542 		drm_dbg(&i915->drm,
543 			"Unrecognised master engine: { class:%u, instance:%u }\n",
544 			ci.engine_class, ci.engine_instance);
545 		return -EINVAL;
546 	}
547 
548 	if (intel_engine_uses_guc(master)) {
549 		drm_dbg(&i915->drm, "bonding extension not supported with GuC submission");
550 		return -ENODEV;
551 	}
552 
553 	if (get_user(num_bonds, &ext->num_bonds))
554 		return -EFAULT;
555 
556 	for (n = 0; n < num_bonds; n++) {
557 		struct intel_engine_cs *bond;
558 
559 		if (copy_from_user(&ci, &ext->engines[n], sizeof(ci)))
560 			return -EFAULT;
561 
562 		bond = intel_engine_lookup_user(i915,
563 						ci.engine_class,
564 						ci.engine_instance);
565 		if (!bond) {
566 			drm_dbg(&i915->drm,
567 				"Unrecognised engine[%d] for bonding: { class:%d, instance: %d }\n",
568 				n, ci.engine_class, ci.engine_instance);
569 			return -EINVAL;
570 		}
571 	}
572 
573 	return 0;
574 }
575 
576 static int
577 set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
578 				      void *data)
579 {
580 	struct i915_context_engines_parallel_submit __user *ext =
581 		container_of_user(base, typeof(*ext), base);
582 	const struct set_proto_ctx_engines *set = data;
583 	struct drm_i915_private *i915 = set->i915;
584 	struct i915_engine_class_instance prev_engine;
585 	u64 flags;
586 	int err = 0, n, i, j;
587 	u16 slot, width, num_siblings;
588 	struct intel_engine_cs **siblings = NULL;
589 	intel_engine_mask_t prev_mask;
590 
591 	if (get_user(slot, &ext->engine_index))
592 		return -EFAULT;
593 
594 	if (get_user(width, &ext->width))
595 		return -EFAULT;
596 
597 	if (get_user(num_siblings, &ext->num_siblings))
598 		return -EFAULT;
599 
600 	if (!intel_uc_uses_guc_submission(&to_gt(i915)->uc) &&
601 	    num_siblings != 1) {
602 		drm_dbg(&i915->drm, "Only 1 sibling (%d) supported in non-GuC mode\n",
603 			num_siblings);
604 		return -EINVAL;
605 	}
606 
607 	if (slot >= set->num_engines) {
608 		drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
609 			slot, set->num_engines);
610 		return -EINVAL;
611 	}
612 
613 	if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) {
614 		drm_dbg(&i915->drm,
615 			"Invalid placement[%d], already occupied\n", slot);
616 		return -EINVAL;
617 	}
618 
619 	if (get_user(flags, &ext->flags))
620 		return -EFAULT;
621 
622 	if (flags) {
623 		drm_dbg(&i915->drm, "Unknown flags 0x%02llx", flags);
624 		return -EINVAL;
625 	}
626 
627 	for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
628 		err = check_user_mbz(&ext->mbz64[n]);
629 		if (err)
630 			return err;
631 	}
632 
633 	if (width < 2) {
634 		drm_dbg(&i915->drm, "Width (%d) < 2\n", width);
635 		return -EINVAL;
636 	}
637 
638 	if (num_siblings < 1) {
639 		drm_dbg(&i915->drm, "Number siblings (%d) < 1\n",
640 			num_siblings);
641 		return -EINVAL;
642 	}
643 
644 	siblings = kmalloc_array(num_siblings * width,
645 				 sizeof(*siblings),
646 				 GFP_KERNEL);
647 	if (!siblings)
648 		return -ENOMEM;
649 
650 	/* Create contexts / engines */
651 	for (i = 0; i < width; ++i) {
652 		intel_engine_mask_t current_mask = 0;
653 
654 		for (j = 0; j < num_siblings; ++j) {
655 			struct i915_engine_class_instance ci;
656 
657 			n = i * num_siblings + j;
658 			if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
659 				err = -EFAULT;
660 				goto out_err;
661 			}
662 
663 			siblings[n] =
664 				intel_engine_lookup_user(i915, ci.engine_class,
665 							 ci.engine_instance);
666 			if (!siblings[n]) {
667 				drm_dbg(&i915->drm,
668 					"Invalid sibling[%d]: { class:%d, inst:%d }\n",
669 					n, ci.engine_class, ci.engine_instance);
670 				err = -EINVAL;
671 				goto out_err;
672 			}
673 
674 			/*
675 			 * We don't support breadcrumb handshake on these
676 			 * classes
677 			 */
678 			if (siblings[n]->class == RENDER_CLASS ||
679 			    siblings[n]->class == COMPUTE_CLASS) {
680 				err = -EINVAL;
681 				goto out_err;
682 			}
683 
684 			if (n) {
685 				if (prev_engine.engine_class !=
686 				    ci.engine_class) {
687 					drm_dbg(&i915->drm,
688 						"Mismatched class %d, %d\n",
689 						prev_engine.engine_class,
690 						ci.engine_class);
691 					err = -EINVAL;
692 					goto out_err;
693 				}
694 			}
695 
696 			prev_engine = ci;
697 			current_mask |= siblings[n]->logical_mask;
698 		}
699 
700 		if (i > 0) {
701 			if (current_mask != prev_mask << 1) {
702 				drm_dbg(&i915->drm,
703 					"Non contiguous logical mask 0x%x, 0x%x\n",
704 					prev_mask, current_mask);
705 				err = -EINVAL;
706 				goto out_err;
707 			}
708 		}
709 		prev_mask = current_mask;
710 	}
711 
712 	set->engines[slot].type = I915_GEM_ENGINE_TYPE_PARALLEL;
713 	set->engines[slot].num_siblings = num_siblings;
714 	set->engines[slot].width = width;
715 	set->engines[slot].siblings = siblings;
716 
717 	return 0;
718 
719 out_err:
720 	kfree(siblings);
721 
722 	return err;
723 }
724 
725 static const i915_user_extension_fn set_proto_ctx_engines_extensions[] = {
726 	[I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE] = set_proto_ctx_engines_balance,
727 	[I915_CONTEXT_ENGINES_EXT_BOND] = set_proto_ctx_engines_bond,
728 	[I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT] =
729 		set_proto_ctx_engines_parallel_submit,
730 };
731 
732 static int set_proto_ctx_engines(struct drm_i915_file_private *fpriv,
733 			         struct i915_gem_proto_context *pc,
734 			         const struct drm_i915_gem_context_param *args)
735 {
736 	struct drm_i915_private *i915 = fpriv->i915;
737 	struct set_proto_ctx_engines set = { .i915 = i915 };
738 	struct i915_context_param_engines __user *user =
739 		u64_to_user_ptr(args->value);
740 	unsigned int n;
741 	u64 extensions;
742 	int err;
743 
744 	if (pc->num_user_engines >= 0) {
745 		drm_dbg(&i915->drm, "Cannot set engines twice");
746 		return -EINVAL;
747 	}
748 
749 	if (args->size < sizeof(*user) ||
750 	    !IS_ALIGNED(args->size - sizeof(*user), sizeof(*user->engines))) {
751 		drm_dbg(&i915->drm, "Invalid size for engine array: %d\n",
752 			args->size);
753 		return -EINVAL;
754 	}
755 
756 	set.num_engines = (args->size - sizeof(*user)) / sizeof(*user->engines);
757 	/* RING_MASK has no shift so we can use it directly here */
758 	if (set.num_engines > I915_EXEC_RING_MASK + 1)
759 		return -EINVAL;
760 
761 	set.engines = kmalloc_array(set.num_engines, sizeof(*set.engines), GFP_KERNEL);
762 	if (!set.engines)
763 		return -ENOMEM;
764 
765 	for (n = 0; n < set.num_engines; n++) {
766 		struct i915_engine_class_instance ci;
767 		struct intel_engine_cs *engine;
768 
769 		if (copy_from_user(&ci, &user->engines[n], sizeof(ci))) {
770 			kfree(set.engines);
771 			return -EFAULT;
772 		}
773 
774 		memset(&set.engines[n], 0, sizeof(set.engines[n]));
775 
776 		if (ci.engine_class == (u16)I915_ENGINE_CLASS_INVALID &&
777 		    ci.engine_instance == (u16)I915_ENGINE_CLASS_INVALID_NONE)
778 			continue;
779 
780 		engine = intel_engine_lookup_user(i915,
781 						  ci.engine_class,
782 						  ci.engine_instance);
783 		if (!engine) {
784 			drm_dbg(&i915->drm,
785 				"Invalid engine[%d]: { class:%d, instance:%d }\n",
786 				n, ci.engine_class, ci.engine_instance);
787 			kfree(set.engines);
788 			return -ENOENT;
789 		}
790 
791 		set.engines[n].type = I915_GEM_ENGINE_TYPE_PHYSICAL;
792 		set.engines[n].engine = engine;
793 	}
794 
795 	err = -EFAULT;
796 	if (!get_user(extensions, &user->extensions))
797 		err = i915_user_extensions(u64_to_user_ptr(extensions),
798 					   set_proto_ctx_engines_extensions,
799 					   ARRAY_SIZE(set_proto_ctx_engines_extensions),
800 					   &set);
801 	if (err) {
802 		kfree(set.engines);
803 		return err;
804 	}
805 
806 	pc->num_user_engines = set.num_engines;
807 	pc->user_engines = set.engines;
808 
809 	return 0;
810 }
811 
812 static int set_proto_ctx_sseu(struct drm_i915_file_private *fpriv,
813 			      struct i915_gem_proto_context *pc,
814 			      struct drm_i915_gem_context_param *args)
815 {
816 	struct drm_i915_private *i915 = fpriv->i915;
817 	struct drm_i915_gem_context_param_sseu user_sseu;
818 	struct intel_sseu *sseu;
819 	int ret;
820 
821 	if (args->size < sizeof(user_sseu))
822 		return -EINVAL;
823 
824 	if (GRAPHICS_VER(i915) != 11)
825 		return -ENODEV;
826 
827 	if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
828 			   sizeof(user_sseu)))
829 		return -EFAULT;
830 
831 	if (user_sseu.rsvd)
832 		return -EINVAL;
833 
834 	if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
835 		return -EINVAL;
836 
837 	if (!!(user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX) != (pc->num_user_engines >= 0))
838 		return -EINVAL;
839 
840 	if (pc->num_user_engines >= 0) {
841 		int idx = user_sseu.engine.engine_instance;
842 		struct i915_gem_proto_engine *pe;
843 
844 		if (idx >= pc->num_user_engines)
845 			return -EINVAL;
846 
847 		idx = array_index_nospec(idx, pc->num_user_engines);
848 		pe = &pc->user_engines[idx];
849 
850 		/* Only render engine supports RPCS configuration. */
851 		if (pe->engine->class != RENDER_CLASS)
852 			return -EINVAL;
853 
854 		sseu = &pe->sseu;
855 	} else {
856 		/* Only render engine supports RPCS configuration. */
857 		if (user_sseu.engine.engine_class != I915_ENGINE_CLASS_RENDER)
858 			return -EINVAL;
859 
860 		/* There is only one render engine */
861 		if (user_sseu.engine.engine_instance != 0)
862 			return -EINVAL;
863 
864 		sseu = &pc->legacy_rcs_sseu;
865 	}
866 
867 	ret = i915_gem_user_to_context_sseu(to_gt(i915), &user_sseu, sseu);
868 	if (ret)
869 		return ret;
870 
871 	args->size = sizeof(user_sseu);
872 
873 	return 0;
874 }
875 
876 static int set_proto_ctx_param(struct drm_i915_file_private *fpriv,
877 			       struct i915_gem_proto_context *pc,
878 			       struct drm_i915_gem_context_param *args)
879 {
880 	int ret = 0;
881 
882 	switch (args->param) {
883 	case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
884 		if (args->size)
885 			ret = -EINVAL;
886 		else if (args->value)
887 			pc->user_flags |= BIT(UCONTEXT_NO_ERROR_CAPTURE);
888 		else
889 			pc->user_flags &= ~BIT(UCONTEXT_NO_ERROR_CAPTURE);
890 		break;
891 
892 	case I915_CONTEXT_PARAM_BANNABLE:
893 		if (args->size)
894 			ret = -EINVAL;
895 		else if (!capable(CAP_SYS_ADMIN) && !args->value)
896 			ret = -EPERM;
897 		else if (args->value)
898 			pc->user_flags |= BIT(UCONTEXT_BANNABLE);
899 		else if (pc->uses_protected_content)
900 			ret = -EPERM;
901 		else
902 			pc->user_flags &= ~BIT(UCONTEXT_BANNABLE);
903 		break;
904 
905 	case I915_CONTEXT_PARAM_RECOVERABLE:
906 		if (args->size)
907 			ret = -EINVAL;
908 		else if (!args->value)
909 			pc->user_flags &= ~BIT(UCONTEXT_RECOVERABLE);
910 		else if (pc->uses_protected_content)
911 			ret = -EPERM;
912 		else
913 			pc->user_flags |= BIT(UCONTEXT_RECOVERABLE);
914 		break;
915 
916 	case I915_CONTEXT_PARAM_PRIORITY:
917 		ret = validate_priority(fpriv->i915, args);
918 		if (!ret)
919 			pc->sched.priority = args->value;
920 		break;
921 
922 	case I915_CONTEXT_PARAM_SSEU:
923 		ret = set_proto_ctx_sseu(fpriv, pc, args);
924 		break;
925 
926 	case I915_CONTEXT_PARAM_VM:
927 		ret = set_proto_ctx_vm(fpriv, pc, args);
928 		break;
929 
930 	case I915_CONTEXT_PARAM_ENGINES:
931 		ret = set_proto_ctx_engines(fpriv, pc, args);
932 		break;
933 
934 	case I915_CONTEXT_PARAM_PERSISTENCE:
935 		if (args->size)
936 			ret = -EINVAL;
937 		else
938 			ret = proto_context_set_persistence(fpriv->i915, pc,
939 							    args->value);
940 		break;
941 
942 	case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
943 		ret = proto_context_set_protected(fpriv->i915, pc,
944 						  args->value);
945 		break;
946 
947 	case I915_CONTEXT_PARAM_NO_ZEROMAP:
948 	case I915_CONTEXT_PARAM_BAN_PERIOD:
949 	case I915_CONTEXT_PARAM_RINGSIZE:
950 	default:
951 		ret = -EINVAL;
952 		break;
953 	}
954 
955 	return ret;
956 }
957 
958 static int intel_context_set_gem(struct intel_context *ce,
959 				 struct i915_gem_context *ctx,
960 				 struct intel_sseu sseu)
961 {
962 	int ret = 0;
963 
964 	GEM_BUG_ON(rcu_access_pointer(ce->gem_context));
965 	RCU_INIT_POINTER(ce->gem_context, ctx);
966 
967 	GEM_BUG_ON(intel_context_is_pinned(ce));
968 
969 	if (ce->engine->class == COMPUTE_CLASS)
970 		ce->ring_size = SZ_512K;
971 	else
972 		ce->ring_size = SZ_16K;
973 
974 	i915_vm_put(ce->vm);
975 	ce->vm = i915_gem_context_get_eb_vm(ctx);
976 
977 	if (ctx->sched.priority >= I915_PRIORITY_NORMAL &&
978 	    intel_engine_has_timeslices(ce->engine) &&
979 	    intel_engine_has_semaphores(ce->engine))
980 		__set_bit(CONTEXT_USE_SEMAPHORES, &ce->flags);
981 
982 	if (CONFIG_DRM_I915_REQUEST_TIMEOUT &&
983 	    ctx->i915->params.request_timeout_ms) {
984 		unsigned int timeout_ms = ctx->i915->params.request_timeout_ms;
985 
986 		intel_context_set_watchdog_us(ce, (u64)timeout_ms * 1000);
987 	}
988 
989 	/* A valid SSEU has no zero fields */
990 	if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS))
991 		ret = intel_context_reconfigure_sseu(ce, sseu);
992 
993 	return ret;
994 }
995 
996 static void __unpin_engines(struct i915_gem_engines *e, unsigned int count)
997 {
998 	while (count--) {
999 		struct intel_context *ce = e->engines[count], *child;
1000 
1001 		if (!ce || !test_bit(CONTEXT_PERMA_PIN, &ce->flags))
1002 			continue;
1003 
1004 		for_each_child(ce, child)
1005 			intel_context_unpin(child);
1006 		intel_context_unpin(ce);
1007 	}
1008 }
1009 
1010 static void unpin_engines(struct i915_gem_engines *e)
1011 {
1012 	__unpin_engines(e, e->num_engines);
1013 }
1014 
1015 static void __free_engines(struct i915_gem_engines *e, unsigned int count)
1016 {
1017 	while (count--) {
1018 		if (!e->engines[count])
1019 			continue;
1020 
1021 		intel_context_put(e->engines[count]);
1022 	}
1023 	kfree(e);
1024 }
1025 
1026 static void free_engines(struct i915_gem_engines *e)
1027 {
1028 	__free_engines(e, e->num_engines);
1029 }
1030 
1031 static void free_engines_rcu(struct rcu_head *rcu)
1032 {
1033 	struct i915_gem_engines *engines =
1034 		container_of(rcu, struct i915_gem_engines, rcu);
1035 
1036 	i915_sw_fence_fini(&engines->fence);
1037 	free_engines(engines);
1038 }
1039 
1040 static void accumulate_runtime(struct i915_drm_client *client,
1041 			       struct i915_gem_engines *engines)
1042 {
1043 	struct i915_gem_engines_iter it;
1044 	struct intel_context *ce;
1045 
1046 	if (!client)
1047 		return;
1048 
1049 	/* Transfer accumulated runtime to the parent GEM context. */
1050 	for_each_gem_engine(ce, engines, it) {
1051 		unsigned int class = ce->engine->uabi_class;
1052 
1053 		GEM_BUG_ON(class >= ARRAY_SIZE(client->past_runtime));
1054 		atomic64_add(intel_context_get_total_runtime_ns(ce),
1055 			     &client->past_runtime[class]);
1056 	}
1057 }
1058 
1059 static int
1060 engines_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
1061 {
1062 	struct i915_gem_engines *engines =
1063 		container_of(fence, typeof(*engines), fence);
1064 	struct i915_gem_context *ctx = engines->ctx;
1065 
1066 	switch (state) {
1067 	case FENCE_COMPLETE:
1068 		if (!list_empty(&engines->link)) {
1069 			unsigned long flags;
1070 
1071 			spin_lock_irqsave(&ctx->stale.lock, flags);
1072 			list_del(&engines->link);
1073 			spin_unlock_irqrestore(&ctx->stale.lock, flags);
1074 		}
1075 		accumulate_runtime(ctx->client, engines);
1076 		i915_gem_context_put(ctx);
1077 
1078 		break;
1079 
1080 	case FENCE_FREE:
1081 		init_rcu_head(&engines->rcu);
1082 		call_rcu(&engines->rcu, free_engines_rcu);
1083 		break;
1084 	}
1085 
1086 	return NOTIFY_DONE;
1087 }
1088 
1089 static struct i915_gem_engines *alloc_engines(unsigned int count)
1090 {
1091 	struct i915_gem_engines *e;
1092 
1093 	e = kzalloc(struct_size(e, engines, count), GFP_KERNEL);
1094 	if (!e)
1095 		return NULL;
1096 
1097 	i915_sw_fence_init(&e->fence, engines_notify);
1098 	return e;
1099 }
1100 
1101 static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx,
1102 						struct intel_sseu rcs_sseu)
1103 {
1104 	const unsigned int max = I915_NUM_ENGINES;
1105 	struct intel_engine_cs *engine;
1106 	struct i915_gem_engines *e, *err;
1107 
1108 	e = alloc_engines(max);
1109 	if (!e)
1110 		return ERR_PTR(-ENOMEM);
1111 
1112 	for_each_uabi_engine(engine, ctx->i915) {
1113 		struct intel_context *ce;
1114 		struct intel_sseu sseu = {};
1115 		int ret;
1116 
1117 		if (engine->legacy_idx == INVALID_ENGINE)
1118 			continue;
1119 
1120 		GEM_BUG_ON(engine->legacy_idx >= max);
1121 		GEM_BUG_ON(e->engines[engine->legacy_idx]);
1122 
1123 		ce = intel_context_create(engine);
1124 		if (IS_ERR(ce)) {
1125 			err = ERR_CAST(ce);
1126 			goto free_engines;
1127 		}
1128 
1129 		e->engines[engine->legacy_idx] = ce;
1130 		e->num_engines = max(e->num_engines, engine->legacy_idx + 1);
1131 
1132 		if (engine->class == RENDER_CLASS)
1133 			sseu = rcs_sseu;
1134 
1135 		ret = intel_context_set_gem(ce, ctx, sseu);
1136 		if (ret) {
1137 			err = ERR_PTR(ret);
1138 			goto free_engines;
1139 		}
1140 
1141 	}
1142 
1143 	return e;
1144 
1145 free_engines:
1146 	free_engines(e);
1147 	return err;
1148 }
1149 
1150 static int perma_pin_contexts(struct intel_context *ce)
1151 {
1152 	struct intel_context *child;
1153 	int i = 0, j = 0, ret;
1154 
1155 	GEM_BUG_ON(!intel_context_is_parent(ce));
1156 
1157 	ret = intel_context_pin(ce);
1158 	if (unlikely(ret))
1159 		return ret;
1160 
1161 	for_each_child(ce, child) {
1162 		ret = intel_context_pin(child);
1163 		if (unlikely(ret))
1164 			goto unwind;
1165 		++i;
1166 	}
1167 
1168 	set_bit(CONTEXT_PERMA_PIN, &ce->flags);
1169 
1170 	return 0;
1171 
1172 unwind:
1173 	intel_context_unpin(ce);
1174 	for_each_child(ce, child) {
1175 		if (j++ < i)
1176 			intel_context_unpin(child);
1177 		else
1178 			break;
1179 	}
1180 
1181 	return ret;
1182 }
1183 
1184 static struct i915_gem_engines *user_engines(struct i915_gem_context *ctx,
1185 					     unsigned int num_engines,
1186 					     struct i915_gem_proto_engine *pe)
1187 {
1188 	struct i915_gem_engines *e, *err;
1189 	unsigned int n;
1190 
1191 	e = alloc_engines(num_engines);
1192 	if (!e)
1193 		return ERR_PTR(-ENOMEM);
1194 	e->num_engines = num_engines;
1195 
1196 	for (n = 0; n < num_engines; n++) {
1197 		struct intel_context *ce, *child;
1198 		int ret;
1199 
1200 		switch (pe[n].type) {
1201 		case I915_GEM_ENGINE_TYPE_PHYSICAL:
1202 			ce = intel_context_create(pe[n].engine);
1203 			break;
1204 
1205 		case I915_GEM_ENGINE_TYPE_BALANCED:
1206 			ce = intel_engine_create_virtual(pe[n].siblings,
1207 							 pe[n].num_siblings, 0);
1208 			break;
1209 
1210 		case I915_GEM_ENGINE_TYPE_PARALLEL:
1211 			ce = intel_engine_create_parallel(pe[n].siblings,
1212 							  pe[n].num_siblings,
1213 							  pe[n].width);
1214 			break;
1215 
1216 		case I915_GEM_ENGINE_TYPE_INVALID:
1217 		default:
1218 			GEM_WARN_ON(pe[n].type != I915_GEM_ENGINE_TYPE_INVALID);
1219 			continue;
1220 		}
1221 
1222 		if (IS_ERR(ce)) {
1223 			err = ERR_CAST(ce);
1224 			goto free_engines;
1225 		}
1226 
1227 		e->engines[n] = ce;
1228 
1229 		ret = intel_context_set_gem(ce, ctx, pe->sseu);
1230 		if (ret) {
1231 			err = ERR_PTR(ret);
1232 			goto free_engines;
1233 		}
1234 		for_each_child(ce, child) {
1235 			ret = intel_context_set_gem(child, ctx, pe->sseu);
1236 			if (ret) {
1237 				err = ERR_PTR(ret);
1238 				goto free_engines;
1239 			}
1240 		}
1241 
1242 		/*
1243 		 * XXX: Must be done after calling intel_context_set_gem as that
1244 		 * function changes the ring size. The ring is allocated when
1245 		 * the context is pinned. If the ring size is changed after
1246 		 * allocation we have a mismatch of the ring size and will cause
1247 		 * the context to hang. Presumably with a bit of reordering we
1248 		 * could move the perma-pin step to the backend function
1249 		 * intel_engine_create_parallel.
1250 		 */
1251 		if (pe[n].type == I915_GEM_ENGINE_TYPE_PARALLEL) {
1252 			ret = perma_pin_contexts(ce);
1253 			if (ret) {
1254 				err = ERR_PTR(ret);
1255 				goto free_engines;
1256 			}
1257 		}
1258 	}
1259 
1260 	return e;
1261 
1262 free_engines:
1263 	free_engines(e);
1264 	return err;
1265 }
1266 
1267 static void i915_gem_context_release_work(struct work_struct *work)
1268 {
1269 	struct i915_gem_context *ctx = container_of(work, typeof(*ctx),
1270 						    release_work);
1271 	struct i915_address_space *vm;
1272 
1273 	trace_i915_context_free(ctx);
1274 	GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
1275 
1276 	spin_lock(&ctx->i915->gem.contexts.lock);
1277 	list_del(&ctx->link);
1278 	spin_unlock(&ctx->i915->gem.contexts.lock);
1279 
1280 	if (ctx->syncobj)
1281 		drm_syncobj_put(ctx->syncobj);
1282 
1283 	vm = ctx->vm;
1284 	if (vm)
1285 		i915_vm_put(vm);
1286 
1287 	if (ctx->pxp_wakeref)
1288 		intel_runtime_pm_put(&ctx->i915->runtime_pm, ctx->pxp_wakeref);
1289 
1290 	if (ctx->client)
1291 		i915_drm_client_put(ctx->client);
1292 
1293 	mutex_destroy(&ctx->engines_mutex);
1294 	mutex_destroy(&ctx->lut_mutex);
1295 
1296 	put_pid(ctx->pid);
1297 	mutex_destroy(&ctx->mutex);
1298 
1299 	kfree_rcu(ctx, rcu);
1300 }
1301 
1302 void i915_gem_context_release(struct kref *ref)
1303 {
1304 	struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
1305 
1306 	queue_work(ctx->i915->wq, &ctx->release_work);
1307 }
1308 
1309 static inline struct i915_gem_engines *
1310 __context_engines_static(const struct i915_gem_context *ctx)
1311 {
1312 	return rcu_dereference_protected(ctx->engines, true);
1313 }
1314 
1315 static void __reset_context(struct i915_gem_context *ctx,
1316 			    struct intel_engine_cs *engine)
1317 {
1318 	intel_gt_handle_error(engine->gt, engine->mask, 0,
1319 			      "context closure in %s", ctx->name);
1320 }
1321 
1322 static bool __cancel_engine(struct intel_engine_cs *engine)
1323 {
1324 	/*
1325 	 * Send a "high priority pulse" down the engine to cause the
1326 	 * current request to be momentarily preempted. (If it fails to
1327 	 * be preempted, it will be reset). As we have marked our context
1328 	 * as banned, any incomplete request, including any running, will
1329 	 * be skipped following the preemption.
1330 	 *
1331 	 * If there is no hangchecking (one of the reasons why we try to
1332 	 * cancel the context) and no forced preemption, there may be no
1333 	 * means by which we reset the GPU and evict the persistent hog.
1334 	 * Ergo if we are unable to inject a preemptive pulse that can
1335 	 * kill the banned context, we fallback to doing a local reset
1336 	 * instead.
1337 	 */
1338 	return intel_engine_pulse(engine) == 0;
1339 }
1340 
1341 static struct intel_engine_cs *active_engine(struct intel_context *ce)
1342 {
1343 	struct intel_engine_cs *engine = NULL;
1344 	struct i915_request *rq;
1345 
1346 	if (intel_context_has_inflight(ce))
1347 		return intel_context_inflight(ce);
1348 
1349 	if (!ce->timeline)
1350 		return NULL;
1351 
1352 	/*
1353 	 * rq->link is only SLAB_TYPESAFE_BY_RCU, we need to hold a reference
1354 	 * to the request to prevent it being transferred to a new timeline
1355 	 * (and onto a new timeline->requests list).
1356 	 */
1357 	rcu_read_lock();
1358 	list_for_each_entry_reverse(rq, &ce->timeline->requests, link) {
1359 		bool found;
1360 
1361 		/* timeline is already completed upto this point? */
1362 		if (!i915_request_get_rcu(rq))
1363 			break;
1364 
1365 		/* Check with the backend if the request is inflight */
1366 		found = true;
1367 		if (likely(rcu_access_pointer(rq->timeline) == ce->timeline))
1368 			found = i915_request_active_engine(rq, &engine);
1369 
1370 		i915_request_put(rq);
1371 		if (found)
1372 			break;
1373 	}
1374 	rcu_read_unlock();
1375 
1376 	return engine;
1377 }
1378 
1379 static void
1380 kill_engines(struct i915_gem_engines *engines, bool exit, bool persistent)
1381 {
1382 	struct i915_gem_engines_iter it;
1383 	struct intel_context *ce;
1384 
1385 	/*
1386 	 * Map the user's engine back to the actual engines; one virtual
1387 	 * engine will be mapped to multiple engines, and using ctx->engine[]
1388 	 * the same engine may be have multiple instances in the user's map.
1389 	 * However, we only care about pending requests, so only include
1390 	 * engines on which there are incomplete requests.
1391 	 */
1392 	for_each_gem_engine(ce, engines, it) {
1393 		struct intel_engine_cs *engine;
1394 
1395 		if ((exit || !persistent) && intel_context_revoke(ce))
1396 			continue; /* Already marked. */
1397 
1398 		/*
1399 		 * Check the current active state of this context; if we
1400 		 * are currently executing on the GPU we need to evict
1401 		 * ourselves. On the other hand, if we haven't yet been
1402 		 * submitted to the GPU or if everything is complete,
1403 		 * we have nothing to do.
1404 		 */
1405 		engine = active_engine(ce);
1406 
1407 		/* First attempt to gracefully cancel the context */
1408 		if (engine && !__cancel_engine(engine) && (exit || !persistent))
1409 			/*
1410 			 * If we are unable to send a preemptive pulse to bump
1411 			 * the context from the GPU, we have to resort to a full
1412 			 * reset. We hope the collateral damage is worth it.
1413 			 */
1414 			__reset_context(engines->ctx, engine);
1415 	}
1416 }
1417 
1418 static void kill_context(struct i915_gem_context *ctx)
1419 {
1420 	struct i915_gem_engines *pos, *next;
1421 
1422 	spin_lock_irq(&ctx->stale.lock);
1423 	GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
1424 	list_for_each_entry_safe(pos, next, &ctx->stale.engines, link) {
1425 		if (!i915_sw_fence_await(&pos->fence)) {
1426 			list_del_init(&pos->link);
1427 			continue;
1428 		}
1429 
1430 		spin_unlock_irq(&ctx->stale.lock);
1431 
1432 		kill_engines(pos, !ctx->i915->params.enable_hangcheck,
1433 			     i915_gem_context_is_persistent(ctx));
1434 
1435 		spin_lock_irq(&ctx->stale.lock);
1436 		GEM_BUG_ON(i915_sw_fence_signaled(&pos->fence));
1437 		list_safe_reset_next(pos, next, link);
1438 		list_del_init(&pos->link); /* decouple from FENCE_COMPLETE */
1439 
1440 		i915_sw_fence_complete(&pos->fence);
1441 	}
1442 	spin_unlock_irq(&ctx->stale.lock);
1443 }
1444 
1445 static void engines_idle_release(struct i915_gem_context *ctx,
1446 				 struct i915_gem_engines *engines)
1447 {
1448 	struct i915_gem_engines_iter it;
1449 	struct intel_context *ce;
1450 
1451 	INIT_LIST_HEAD(&engines->link);
1452 
1453 	engines->ctx = i915_gem_context_get(ctx);
1454 
1455 	for_each_gem_engine(ce, engines, it) {
1456 		int err;
1457 
1458 		/* serialises with execbuf */
1459 		intel_context_close(ce);
1460 		if (!intel_context_pin_if_active(ce))
1461 			continue;
1462 
1463 		/* Wait until context is finally scheduled out and retired */
1464 		err = i915_sw_fence_await_active(&engines->fence,
1465 						 &ce->active,
1466 						 I915_ACTIVE_AWAIT_BARRIER);
1467 		intel_context_unpin(ce);
1468 		if (err)
1469 			goto kill;
1470 	}
1471 
1472 	spin_lock_irq(&ctx->stale.lock);
1473 	if (!i915_gem_context_is_closed(ctx))
1474 		list_add_tail(&engines->link, &ctx->stale.engines);
1475 	spin_unlock_irq(&ctx->stale.lock);
1476 
1477 kill:
1478 	if (list_empty(&engines->link)) /* raced, already closed */
1479 		kill_engines(engines, true,
1480 			     i915_gem_context_is_persistent(ctx));
1481 
1482 	i915_sw_fence_commit(&engines->fence);
1483 }
1484 
1485 static void set_closed_name(struct i915_gem_context *ctx)
1486 {
1487 	char *s;
1488 
1489 	/* Replace '[]' with '<>' to indicate closed in debug prints */
1490 
1491 	s = strrchr(ctx->name, '[');
1492 	if (!s)
1493 		return;
1494 
1495 	*s = '<';
1496 
1497 	s = strchr(s + 1, ']');
1498 	if (s)
1499 		*s = '>';
1500 }
1501 
1502 static void context_close(struct i915_gem_context *ctx)
1503 {
1504 	struct i915_drm_client *client;
1505 
1506 	/* Flush any concurrent set_engines() */
1507 	mutex_lock(&ctx->engines_mutex);
1508 	unpin_engines(__context_engines_static(ctx));
1509 	engines_idle_release(ctx, rcu_replace_pointer(ctx->engines, NULL, 1));
1510 	i915_gem_context_set_closed(ctx);
1511 	mutex_unlock(&ctx->engines_mutex);
1512 
1513 	mutex_lock(&ctx->mutex);
1514 
1515 	set_closed_name(ctx);
1516 
1517 	/*
1518 	 * The LUT uses the VMA as a backpointer to unref the object,
1519 	 * so we need to clear the LUT before we close all the VMA (inside
1520 	 * the ppgtt).
1521 	 */
1522 	lut_close(ctx);
1523 
1524 	ctx->file_priv = ERR_PTR(-EBADF);
1525 
1526 	client = ctx->client;
1527 	if (client) {
1528 		spin_lock(&client->ctx_lock);
1529 		list_del_rcu(&ctx->client_link);
1530 		spin_unlock(&client->ctx_lock);
1531 	}
1532 
1533 	mutex_unlock(&ctx->mutex);
1534 
1535 	/*
1536 	 * If the user has disabled hangchecking, we can not be sure that
1537 	 * the batches will ever complete after the context is closed,
1538 	 * keeping the context and all resources pinned forever. So in this
1539 	 * case we opt to forcibly kill off all remaining requests on
1540 	 * context close.
1541 	 */
1542 	kill_context(ctx);
1543 
1544 	i915_gem_context_put(ctx);
1545 }
1546 
1547 static int __context_set_persistence(struct i915_gem_context *ctx, bool state)
1548 {
1549 	if (i915_gem_context_is_persistent(ctx) == state)
1550 		return 0;
1551 
1552 	if (state) {
1553 		/*
1554 		 * Only contexts that are short-lived [that will expire or be
1555 		 * reset] are allowed to survive past termination. We require
1556 		 * hangcheck to ensure that the persistent requests are healthy.
1557 		 */
1558 		if (!ctx->i915->params.enable_hangcheck)
1559 			return -EINVAL;
1560 
1561 		i915_gem_context_set_persistence(ctx);
1562 	} else {
1563 		/* To cancel a context we use "preempt-to-idle" */
1564 		if (!(ctx->i915->caps.scheduler & I915_SCHEDULER_CAP_PREEMPTION))
1565 			return -ENODEV;
1566 
1567 		/*
1568 		 * If the cancel fails, we then need to reset, cleanly!
1569 		 *
1570 		 * If the per-engine reset fails, all hope is lost! We resort
1571 		 * to a full GPU reset in that unlikely case, but realistically
1572 		 * if the engine could not reset, the full reset does not fare
1573 		 * much better. The damage has been done.
1574 		 *
1575 		 * However, if we cannot reset an engine by itself, we cannot
1576 		 * cleanup a hanging persistent context without causing
1577 		 * colateral damage, and we should not pretend we can by
1578 		 * exposing the interface.
1579 		 */
1580 		if (!intel_has_reset_engine(to_gt(ctx->i915)))
1581 			return -ENODEV;
1582 
1583 		i915_gem_context_clear_persistence(ctx);
1584 	}
1585 
1586 	return 0;
1587 }
1588 
1589 static struct i915_gem_context *
1590 i915_gem_create_context(struct drm_i915_private *i915,
1591 			const struct i915_gem_proto_context *pc)
1592 {
1593 	struct i915_gem_context *ctx;
1594 	struct i915_address_space *vm = NULL;
1595 	struct i915_gem_engines *e;
1596 	int err;
1597 	int i;
1598 
1599 	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
1600 	if (!ctx)
1601 		return ERR_PTR(-ENOMEM);
1602 
1603 	kref_init(&ctx->ref);
1604 	ctx->i915 = i915;
1605 	ctx->sched = pc->sched;
1606 	mutex_init(&ctx->mutex);
1607 	INIT_LIST_HEAD(&ctx->link);
1608 	INIT_WORK(&ctx->release_work, i915_gem_context_release_work);
1609 
1610 	spin_lock_init(&ctx->stale.lock);
1611 	INIT_LIST_HEAD(&ctx->stale.engines);
1612 
1613 	if (pc->vm) {
1614 		vm = i915_vm_get(pc->vm);
1615 	} else if (HAS_FULL_PPGTT(i915)) {
1616 		struct i915_ppgtt *ppgtt;
1617 
1618 		ppgtt = i915_ppgtt_create(to_gt(i915), 0);
1619 		if (IS_ERR(ppgtt)) {
1620 			drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
1621 				PTR_ERR(ppgtt));
1622 			err = PTR_ERR(ppgtt);
1623 			goto err_ctx;
1624 		}
1625 		vm = &ppgtt->vm;
1626 	}
1627 	if (vm)
1628 		ctx->vm = vm;
1629 
1630 	mutex_init(&ctx->engines_mutex);
1631 	if (pc->num_user_engines >= 0) {
1632 		i915_gem_context_set_user_engines(ctx);
1633 		e = user_engines(ctx, pc->num_user_engines, pc->user_engines);
1634 	} else {
1635 		i915_gem_context_clear_user_engines(ctx);
1636 		e = default_engines(ctx, pc->legacy_rcs_sseu);
1637 	}
1638 	if (IS_ERR(e)) {
1639 		err = PTR_ERR(e);
1640 		goto err_vm;
1641 	}
1642 	RCU_INIT_POINTER(ctx->engines, e);
1643 
1644 	INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL);
1645 	mutex_init(&ctx->lut_mutex);
1646 
1647 	/* NB: Mark all slices as needing a remap so that when the context first
1648 	 * loads it will restore whatever remap state already exists. If there
1649 	 * is no remap info, it will be a NOP. */
1650 	ctx->remap_slice = ALL_L3_SLICES(i915);
1651 
1652 	ctx->user_flags = pc->user_flags;
1653 
1654 	for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
1655 		ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
1656 
1657 	if (pc->single_timeline) {
1658 		err = drm_syncobj_create(&ctx->syncobj,
1659 					 DRM_SYNCOBJ_CREATE_SIGNALED,
1660 					 NULL);
1661 		if (err)
1662 			goto err_engines;
1663 	}
1664 
1665 	if (pc->uses_protected_content) {
1666 		ctx->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1667 		ctx->uses_protected_content = true;
1668 	}
1669 
1670 	trace_i915_context_create(ctx);
1671 
1672 	return ctx;
1673 
1674 err_engines:
1675 	free_engines(e);
1676 err_vm:
1677 	if (ctx->vm)
1678 		i915_vm_put(ctx->vm);
1679 err_ctx:
1680 	kfree(ctx);
1681 	return ERR_PTR(err);
1682 }
1683 
1684 static void init_contexts(struct i915_gem_contexts *gc)
1685 {
1686 	spin_lock_init(&gc->lock);
1687 	INIT_LIST_HEAD(&gc->list);
1688 }
1689 
1690 void i915_gem_init__contexts(struct drm_i915_private *i915)
1691 {
1692 	init_contexts(&i915->gem.contexts);
1693 }
1694 
1695 /*
1696  * Note that this implicitly consumes the ctx reference, by placing
1697  * the ctx in the context_xa.
1698  */
1699 static void gem_context_register(struct i915_gem_context *ctx,
1700 				 struct drm_i915_file_private *fpriv,
1701 				 u32 id)
1702 {
1703 	struct drm_i915_private *i915 = ctx->i915;
1704 	void *old;
1705 
1706 	ctx->file_priv = fpriv;
1707 
1708 	ctx->pid = get_task_pid(current, PIDTYPE_PID);
1709 	ctx->client = i915_drm_client_get(fpriv->client);
1710 
1711 	snprintf(ctx->name, sizeof(ctx->name), "%s[%d]",
1712 		 current->comm, pid_nr(ctx->pid));
1713 
1714 	spin_lock(&ctx->client->ctx_lock);
1715 	list_add_tail_rcu(&ctx->client_link, &ctx->client->ctx_list);
1716 	spin_unlock(&ctx->client->ctx_lock);
1717 
1718 	spin_lock(&i915->gem.contexts.lock);
1719 	list_add_tail(&ctx->link, &i915->gem.contexts.list);
1720 	spin_unlock(&i915->gem.contexts.lock);
1721 
1722 	/* And finally expose ourselves to userspace via the idr */
1723 	old = xa_store(&fpriv->context_xa, id, ctx, GFP_KERNEL);
1724 	WARN_ON(old);
1725 }
1726 
1727 int i915_gem_context_open(struct drm_i915_private *i915,
1728 			  struct drm_file *file)
1729 {
1730 	struct drm_i915_file_private *file_priv = file->driver_priv;
1731 	struct i915_gem_proto_context *pc;
1732 	struct i915_gem_context *ctx;
1733 	int err;
1734 
1735 	mutex_init(&file_priv->proto_context_lock);
1736 	xa_init_flags(&file_priv->proto_context_xa, XA_FLAGS_ALLOC);
1737 
1738 	/* 0 reserved for the default context */
1739 	xa_init_flags(&file_priv->context_xa, XA_FLAGS_ALLOC1);
1740 
1741 	/* 0 reserved for invalid/unassigned ppgtt */
1742 	xa_init_flags(&file_priv->vm_xa, XA_FLAGS_ALLOC1);
1743 
1744 	pc = proto_context_create(i915, 0);
1745 	if (IS_ERR(pc)) {
1746 		err = PTR_ERR(pc);
1747 		goto err;
1748 	}
1749 
1750 	ctx = i915_gem_create_context(i915, pc);
1751 	proto_context_close(i915, pc);
1752 	if (IS_ERR(ctx)) {
1753 		err = PTR_ERR(ctx);
1754 		goto err;
1755 	}
1756 
1757 	gem_context_register(ctx, file_priv, 0);
1758 
1759 	return 0;
1760 
1761 err:
1762 	xa_destroy(&file_priv->vm_xa);
1763 	xa_destroy(&file_priv->context_xa);
1764 	xa_destroy(&file_priv->proto_context_xa);
1765 	mutex_destroy(&file_priv->proto_context_lock);
1766 	return err;
1767 }
1768 
1769 void i915_gem_context_close(struct drm_file *file)
1770 {
1771 	struct drm_i915_file_private *file_priv = file->driver_priv;
1772 	struct i915_gem_proto_context *pc;
1773 	struct i915_address_space *vm;
1774 	struct i915_gem_context *ctx;
1775 	unsigned long idx;
1776 
1777 	xa_for_each(&file_priv->proto_context_xa, idx, pc)
1778 		proto_context_close(file_priv->i915, pc);
1779 	xa_destroy(&file_priv->proto_context_xa);
1780 	mutex_destroy(&file_priv->proto_context_lock);
1781 
1782 	xa_for_each(&file_priv->context_xa, idx, ctx)
1783 		context_close(ctx);
1784 	xa_destroy(&file_priv->context_xa);
1785 
1786 	xa_for_each(&file_priv->vm_xa, idx, vm)
1787 		i915_vm_put(vm);
1788 	xa_destroy(&file_priv->vm_xa);
1789 }
1790 
1791 int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
1792 			     struct drm_file *file)
1793 {
1794 	struct drm_i915_private *i915 = to_i915(dev);
1795 	struct drm_i915_gem_vm_control *args = data;
1796 	struct drm_i915_file_private *file_priv = file->driver_priv;
1797 	struct i915_ppgtt *ppgtt;
1798 	u32 id;
1799 	int err;
1800 
1801 	if (!HAS_FULL_PPGTT(i915))
1802 		return -ENODEV;
1803 
1804 	if (args->flags)
1805 		return -EINVAL;
1806 
1807 	ppgtt = i915_ppgtt_create(to_gt(i915), 0);
1808 	if (IS_ERR(ppgtt))
1809 		return PTR_ERR(ppgtt);
1810 
1811 	if (args->extensions) {
1812 		err = i915_user_extensions(u64_to_user_ptr(args->extensions),
1813 					   NULL, 0,
1814 					   ppgtt);
1815 		if (err)
1816 			goto err_put;
1817 	}
1818 
1819 	err = xa_alloc(&file_priv->vm_xa, &id, &ppgtt->vm,
1820 		       xa_limit_32b, GFP_KERNEL);
1821 	if (err)
1822 		goto err_put;
1823 
1824 	GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */
1825 	args->vm_id = id;
1826 	return 0;
1827 
1828 err_put:
1829 	i915_vm_put(&ppgtt->vm);
1830 	return err;
1831 }
1832 
1833 int i915_gem_vm_destroy_ioctl(struct drm_device *dev, void *data,
1834 			      struct drm_file *file)
1835 {
1836 	struct drm_i915_file_private *file_priv = file->driver_priv;
1837 	struct drm_i915_gem_vm_control *args = data;
1838 	struct i915_address_space *vm;
1839 
1840 	if (args->flags)
1841 		return -EINVAL;
1842 
1843 	if (args->extensions)
1844 		return -EINVAL;
1845 
1846 	vm = xa_erase(&file_priv->vm_xa, args->vm_id);
1847 	if (!vm)
1848 		return -ENOENT;
1849 
1850 	i915_vm_put(vm);
1851 	return 0;
1852 }
1853 
1854 static int get_ppgtt(struct drm_i915_file_private *file_priv,
1855 		     struct i915_gem_context *ctx,
1856 		     struct drm_i915_gem_context_param *args)
1857 {
1858 	struct i915_address_space *vm;
1859 	int err;
1860 	u32 id;
1861 
1862 	if (!i915_gem_context_has_full_ppgtt(ctx))
1863 		return -ENODEV;
1864 
1865 	vm = ctx->vm;
1866 	GEM_BUG_ON(!vm);
1867 
1868 	/*
1869 	 * Get a reference for the allocated handle.  Once the handle is
1870 	 * visible in the vm_xa table, userspace could try to close it
1871 	 * from under our feet, so we need to hold the extra reference
1872 	 * first.
1873 	 */
1874 	i915_vm_get(vm);
1875 
1876 	err = xa_alloc(&file_priv->vm_xa, &id, vm, xa_limit_32b, GFP_KERNEL);
1877 	if (err) {
1878 		i915_vm_put(vm);
1879 		return err;
1880 	}
1881 
1882 	GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */
1883 	args->value = id;
1884 	args->size = 0;
1885 
1886 	return err;
1887 }
1888 
1889 int
1890 i915_gem_user_to_context_sseu(struct intel_gt *gt,
1891 			      const struct drm_i915_gem_context_param_sseu *user,
1892 			      struct intel_sseu *context)
1893 {
1894 	const struct sseu_dev_info *device = &gt->info.sseu;
1895 	struct drm_i915_private *i915 = gt->i915;
1896 	unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
1897 
1898 	/* No zeros in any field. */
1899 	if (!user->slice_mask || !user->subslice_mask ||
1900 	    !user->min_eus_per_subslice || !user->max_eus_per_subslice)
1901 		return -EINVAL;
1902 
1903 	/* Max > min. */
1904 	if (user->max_eus_per_subslice < user->min_eus_per_subslice)
1905 		return -EINVAL;
1906 
1907 	/*
1908 	 * Some future proofing on the types since the uAPI is wider than the
1909 	 * current internal implementation.
1910 	 */
1911 	if (overflows_type(user->slice_mask, context->slice_mask) ||
1912 	    overflows_type(user->subslice_mask, context->subslice_mask) ||
1913 	    overflows_type(user->min_eus_per_subslice,
1914 			   context->min_eus_per_subslice) ||
1915 	    overflows_type(user->max_eus_per_subslice,
1916 			   context->max_eus_per_subslice))
1917 		return -EINVAL;
1918 
1919 	/* Check validity against hardware. */
1920 	if (user->slice_mask & ~device->slice_mask)
1921 		return -EINVAL;
1922 
1923 	if (user->subslice_mask & ~dev_subslice_mask)
1924 		return -EINVAL;
1925 
1926 	if (user->max_eus_per_subslice > device->max_eus_per_subslice)
1927 		return -EINVAL;
1928 
1929 	context->slice_mask = user->slice_mask;
1930 	context->subslice_mask = user->subslice_mask;
1931 	context->min_eus_per_subslice = user->min_eus_per_subslice;
1932 	context->max_eus_per_subslice = user->max_eus_per_subslice;
1933 
1934 	/* Part specific restrictions. */
1935 	if (GRAPHICS_VER(i915) == 11) {
1936 		unsigned int hw_s = hweight8(device->slice_mask);
1937 		unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
1938 		unsigned int req_s = hweight8(context->slice_mask);
1939 		unsigned int req_ss = hweight8(context->subslice_mask);
1940 
1941 		/*
1942 		 * Only full subslice enablement is possible if more than one
1943 		 * slice is turned on.
1944 		 */
1945 		if (req_s > 1 && req_ss != hw_ss_per_s)
1946 			return -EINVAL;
1947 
1948 		/*
1949 		 * If more than four (SScount bitfield limit) subslices are
1950 		 * requested then the number has to be even.
1951 		 */
1952 		if (req_ss > 4 && (req_ss & 1))
1953 			return -EINVAL;
1954 
1955 		/*
1956 		 * If only one slice is enabled and subslice count is below the
1957 		 * device full enablement, it must be at most half of the all
1958 		 * available subslices.
1959 		 */
1960 		if (req_s == 1 && req_ss < hw_ss_per_s &&
1961 		    req_ss > (hw_ss_per_s / 2))
1962 			return -EINVAL;
1963 
1964 		/* ABI restriction - VME use case only. */
1965 
1966 		/* All slices or one slice only. */
1967 		if (req_s != 1 && req_s != hw_s)
1968 			return -EINVAL;
1969 
1970 		/*
1971 		 * Half subslices or full enablement only when one slice is
1972 		 * enabled.
1973 		 */
1974 		if (req_s == 1 &&
1975 		    (req_ss != hw_ss_per_s && req_ss != (hw_ss_per_s / 2)))
1976 			return -EINVAL;
1977 
1978 		/* No EU configuration changes. */
1979 		if ((user->min_eus_per_subslice !=
1980 		     device->max_eus_per_subslice) ||
1981 		    (user->max_eus_per_subslice !=
1982 		     device->max_eus_per_subslice))
1983 			return -EINVAL;
1984 	}
1985 
1986 	return 0;
1987 }
1988 
1989 static int set_sseu(struct i915_gem_context *ctx,
1990 		    struct drm_i915_gem_context_param *args)
1991 {
1992 	struct drm_i915_private *i915 = ctx->i915;
1993 	struct drm_i915_gem_context_param_sseu user_sseu;
1994 	struct intel_context *ce;
1995 	struct intel_sseu sseu;
1996 	unsigned long lookup;
1997 	int ret;
1998 
1999 	if (args->size < sizeof(user_sseu))
2000 		return -EINVAL;
2001 
2002 	if (GRAPHICS_VER(i915) != 11)
2003 		return -ENODEV;
2004 
2005 	if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
2006 			   sizeof(user_sseu)))
2007 		return -EFAULT;
2008 
2009 	if (user_sseu.rsvd)
2010 		return -EINVAL;
2011 
2012 	if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
2013 		return -EINVAL;
2014 
2015 	lookup = 0;
2016 	if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
2017 		lookup |= LOOKUP_USER_INDEX;
2018 
2019 	ce = lookup_user_engine(ctx, lookup, &user_sseu.engine);
2020 	if (IS_ERR(ce))
2021 		return PTR_ERR(ce);
2022 
2023 	/* Only render engine supports RPCS configuration. */
2024 	if (ce->engine->class != RENDER_CLASS) {
2025 		ret = -ENODEV;
2026 		goto out_ce;
2027 	}
2028 
2029 	ret = i915_gem_user_to_context_sseu(ce->engine->gt, &user_sseu, &sseu);
2030 	if (ret)
2031 		goto out_ce;
2032 
2033 	ret = intel_context_reconfigure_sseu(ce, sseu);
2034 	if (ret)
2035 		goto out_ce;
2036 
2037 	args->size = sizeof(user_sseu);
2038 
2039 out_ce:
2040 	intel_context_put(ce);
2041 	return ret;
2042 }
2043 
2044 static int
2045 set_persistence(struct i915_gem_context *ctx,
2046 		const struct drm_i915_gem_context_param *args)
2047 {
2048 	if (args->size)
2049 		return -EINVAL;
2050 
2051 	return __context_set_persistence(ctx, args->value);
2052 }
2053 
2054 static int set_priority(struct i915_gem_context *ctx,
2055 			const struct drm_i915_gem_context_param *args)
2056 {
2057 	struct i915_gem_engines_iter it;
2058 	struct intel_context *ce;
2059 	int err;
2060 
2061 	err = validate_priority(ctx->i915, args);
2062 	if (err)
2063 		return err;
2064 
2065 	ctx->sched.priority = args->value;
2066 
2067 	for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
2068 		if (!intel_engine_has_timeslices(ce->engine))
2069 			continue;
2070 
2071 		if (ctx->sched.priority >= I915_PRIORITY_NORMAL &&
2072 		    intel_engine_has_semaphores(ce->engine))
2073 			intel_context_set_use_semaphores(ce);
2074 		else
2075 			intel_context_clear_use_semaphores(ce);
2076 	}
2077 	i915_gem_context_unlock_engines(ctx);
2078 
2079 	return 0;
2080 }
2081 
2082 static int get_protected(struct i915_gem_context *ctx,
2083 			 struct drm_i915_gem_context_param *args)
2084 {
2085 	args->size = 0;
2086 	args->value = i915_gem_context_uses_protected_content(ctx);
2087 
2088 	return 0;
2089 }
2090 
2091 static int ctx_setparam(struct drm_i915_file_private *fpriv,
2092 			struct i915_gem_context *ctx,
2093 			struct drm_i915_gem_context_param *args)
2094 {
2095 	int ret = 0;
2096 
2097 	switch (args->param) {
2098 	case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
2099 		if (args->size)
2100 			ret = -EINVAL;
2101 		else if (args->value)
2102 			i915_gem_context_set_no_error_capture(ctx);
2103 		else
2104 			i915_gem_context_clear_no_error_capture(ctx);
2105 		break;
2106 
2107 	case I915_CONTEXT_PARAM_BANNABLE:
2108 		if (args->size)
2109 			ret = -EINVAL;
2110 		else if (!capable(CAP_SYS_ADMIN) && !args->value)
2111 			ret = -EPERM;
2112 		else if (args->value)
2113 			i915_gem_context_set_bannable(ctx);
2114 		else if (i915_gem_context_uses_protected_content(ctx))
2115 			ret = -EPERM; /* can't clear this for protected contexts */
2116 		else
2117 			i915_gem_context_clear_bannable(ctx);
2118 		break;
2119 
2120 	case I915_CONTEXT_PARAM_RECOVERABLE:
2121 		if (args->size)
2122 			ret = -EINVAL;
2123 		else if (!args->value)
2124 			i915_gem_context_clear_recoverable(ctx);
2125 		else if (i915_gem_context_uses_protected_content(ctx))
2126 			ret = -EPERM; /* can't set this for protected contexts */
2127 		else
2128 			i915_gem_context_set_recoverable(ctx);
2129 		break;
2130 
2131 	case I915_CONTEXT_PARAM_PRIORITY:
2132 		ret = set_priority(ctx, args);
2133 		break;
2134 
2135 	case I915_CONTEXT_PARAM_SSEU:
2136 		ret = set_sseu(ctx, args);
2137 		break;
2138 
2139 	case I915_CONTEXT_PARAM_PERSISTENCE:
2140 		ret = set_persistence(ctx, args);
2141 		break;
2142 
2143 	case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
2144 	case I915_CONTEXT_PARAM_NO_ZEROMAP:
2145 	case I915_CONTEXT_PARAM_BAN_PERIOD:
2146 	case I915_CONTEXT_PARAM_RINGSIZE:
2147 	case I915_CONTEXT_PARAM_VM:
2148 	case I915_CONTEXT_PARAM_ENGINES:
2149 	default:
2150 		ret = -EINVAL;
2151 		break;
2152 	}
2153 
2154 	return ret;
2155 }
2156 
2157 struct create_ext {
2158 	struct i915_gem_proto_context *pc;
2159 	struct drm_i915_file_private *fpriv;
2160 };
2161 
2162 static int create_setparam(struct i915_user_extension __user *ext, void *data)
2163 {
2164 	struct drm_i915_gem_context_create_ext_setparam local;
2165 	const struct create_ext *arg = data;
2166 
2167 	if (copy_from_user(&local, ext, sizeof(local)))
2168 		return -EFAULT;
2169 
2170 	if (local.param.ctx_id)
2171 		return -EINVAL;
2172 
2173 	return set_proto_ctx_param(arg->fpriv, arg->pc, &local.param);
2174 }
2175 
2176 static int invalid_ext(struct i915_user_extension __user *ext, void *data)
2177 {
2178 	return -EINVAL;
2179 }
2180 
2181 static const i915_user_extension_fn create_extensions[] = {
2182 	[I915_CONTEXT_CREATE_EXT_SETPARAM] = create_setparam,
2183 	[I915_CONTEXT_CREATE_EXT_CLONE] = invalid_ext,
2184 };
2185 
2186 static bool client_is_banned(struct drm_i915_file_private *file_priv)
2187 {
2188 	return atomic_read(&file_priv->ban_score) >= I915_CLIENT_SCORE_BANNED;
2189 }
2190 
2191 static inline struct i915_gem_context *
2192 __context_lookup(struct drm_i915_file_private *file_priv, u32 id)
2193 {
2194 	struct i915_gem_context *ctx;
2195 
2196 	rcu_read_lock();
2197 	ctx = xa_load(&file_priv->context_xa, id);
2198 	if (ctx && !kref_get_unless_zero(&ctx->ref))
2199 		ctx = NULL;
2200 	rcu_read_unlock();
2201 
2202 	return ctx;
2203 }
2204 
2205 static struct i915_gem_context *
2206 finalize_create_context_locked(struct drm_i915_file_private *file_priv,
2207 			       struct i915_gem_proto_context *pc, u32 id)
2208 {
2209 	struct i915_gem_context *ctx;
2210 	void *old;
2211 
2212 	lockdep_assert_held(&file_priv->proto_context_lock);
2213 
2214 	ctx = i915_gem_create_context(file_priv->i915, pc);
2215 	if (IS_ERR(ctx))
2216 		return ctx;
2217 
2218 	/*
2219 	 * One for the xarray and one for the caller.  We need to grab
2220 	 * the reference *prior* to making the ctx visble to userspace
2221 	 * in gem_context_register(), as at any point after that
2222 	 * userspace can try to race us with another thread destroying
2223 	 * the context under our feet.
2224 	 */
2225 	i915_gem_context_get(ctx);
2226 
2227 	gem_context_register(ctx, file_priv, id);
2228 
2229 	old = xa_erase(&file_priv->proto_context_xa, id);
2230 	GEM_BUG_ON(old != pc);
2231 	proto_context_close(file_priv->i915, pc);
2232 
2233 	return ctx;
2234 }
2235 
2236 struct i915_gem_context *
2237 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
2238 {
2239 	struct i915_gem_proto_context *pc;
2240 	struct i915_gem_context *ctx;
2241 
2242 	ctx = __context_lookup(file_priv, id);
2243 	if (ctx)
2244 		return ctx;
2245 
2246 	mutex_lock(&file_priv->proto_context_lock);
2247 	/* Try one more time under the lock */
2248 	ctx = __context_lookup(file_priv, id);
2249 	if (!ctx) {
2250 		pc = xa_load(&file_priv->proto_context_xa, id);
2251 		if (!pc)
2252 			ctx = ERR_PTR(-ENOENT);
2253 		else
2254 			ctx = finalize_create_context_locked(file_priv, pc, id);
2255 	}
2256 	mutex_unlock(&file_priv->proto_context_lock);
2257 
2258 	return ctx;
2259 }
2260 
2261 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2262 				  struct drm_file *file)
2263 {
2264 	struct drm_i915_private *i915 = to_i915(dev);
2265 	struct drm_i915_gem_context_create_ext *args = data;
2266 	struct create_ext ext_data;
2267 	int ret;
2268 	u32 id;
2269 
2270 	if (!DRIVER_CAPS(i915)->has_logical_contexts)
2271 		return -ENODEV;
2272 
2273 	if (args->flags & I915_CONTEXT_CREATE_FLAGS_UNKNOWN)
2274 		return -EINVAL;
2275 
2276 	ret = intel_gt_terminally_wedged(to_gt(i915));
2277 	if (ret)
2278 		return ret;
2279 
2280 	ext_data.fpriv = file->driver_priv;
2281 	if (client_is_banned(ext_data.fpriv)) {
2282 		drm_dbg(&i915->drm,
2283 			"client %s[%d] banned from creating ctx\n",
2284 			current->comm, task_pid_nr(current));
2285 		return -EIO;
2286 	}
2287 
2288 	ext_data.pc = proto_context_create(i915, args->flags);
2289 	if (IS_ERR(ext_data.pc))
2290 		return PTR_ERR(ext_data.pc);
2291 
2292 	if (args->flags & I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS) {
2293 		ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
2294 					   create_extensions,
2295 					   ARRAY_SIZE(create_extensions),
2296 					   &ext_data);
2297 		if (ret)
2298 			goto err_pc;
2299 	}
2300 
2301 	if (GRAPHICS_VER(i915) > 12) {
2302 		struct i915_gem_context *ctx;
2303 
2304 		/* Get ourselves a context ID */
2305 		ret = xa_alloc(&ext_data.fpriv->context_xa, &id, NULL,
2306 			       xa_limit_32b, GFP_KERNEL);
2307 		if (ret)
2308 			goto err_pc;
2309 
2310 		ctx = i915_gem_create_context(i915, ext_data.pc);
2311 		if (IS_ERR(ctx)) {
2312 			ret = PTR_ERR(ctx);
2313 			goto err_pc;
2314 		}
2315 
2316 		proto_context_close(i915, ext_data.pc);
2317 		gem_context_register(ctx, ext_data.fpriv, id);
2318 	} else {
2319 		ret = proto_context_register(ext_data.fpriv, ext_data.pc, &id);
2320 		if (ret < 0)
2321 			goto err_pc;
2322 	}
2323 
2324 	args->ctx_id = id;
2325 
2326 	return 0;
2327 
2328 err_pc:
2329 	proto_context_close(i915, ext_data.pc);
2330 	return ret;
2331 }
2332 
2333 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2334 				   struct drm_file *file)
2335 {
2336 	struct drm_i915_gem_context_destroy *args = data;
2337 	struct drm_i915_file_private *file_priv = file->driver_priv;
2338 	struct i915_gem_proto_context *pc;
2339 	struct i915_gem_context *ctx;
2340 
2341 	if (args->pad != 0)
2342 		return -EINVAL;
2343 
2344 	if (!args->ctx_id)
2345 		return -ENOENT;
2346 
2347 	/* We need to hold the proto-context lock here to prevent races
2348 	 * with finalize_create_context_locked().
2349 	 */
2350 	mutex_lock(&file_priv->proto_context_lock);
2351 	ctx = xa_erase(&file_priv->context_xa, args->ctx_id);
2352 	pc = xa_erase(&file_priv->proto_context_xa, args->ctx_id);
2353 	mutex_unlock(&file_priv->proto_context_lock);
2354 
2355 	if (!ctx && !pc)
2356 		return -ENOENT;
2357 	GEM_WARN_ON(ctx && pc);
2358 
2359 	if (pc)
2360 		proto_context_close(file_priv->i915, pc);
2361 
2362 	if (ctx)
2363 		context_close(ctx);
2364 
2365 	return 0;
2366 }
2367 
2368 static int get_sseu(struct i915_gem_context *ctx,
2369 		    struct drm_i915_gem_context_param *args)
2370 {
2371 	struct drm_i915_gem_context_param_sseu user_sseu;
2372 	struct intel_context *ce;
2373 	unsigned long lookup;
2374 	int err;
2375 
2376 	if (args->size == 0)
2377 		goto out;
2378 	else if (args->size < sizeof(user_sseu))
2379 		return -EINVAL;
2380 
2381 	if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
2382 			   sizeof(user_sseu)))
2383 		return -EFAULT;
2384 
2385 	if (user_sseu.rsvd)
2386 		return -EINVAL;
2387 
2388 	if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
2389 		return -EINVAL;
2390 
2391 	lookup = 0;
2392 	if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
2393 		lookup |= LOOKUP_USER_INDEX;
2394 
2395 	ce = lookup_user_engine(ctx, lookup, &user_sseu.engine);
2396 	if (IS_ERR(ce))
2397 		return PTR_ERR(ce);
2398 
2399 	err = intel_context_lock_pinned(ce); /* serialises with set_sseu */
2400 	if (err) {
2401 		intel_context_put(ce);
2402 		return err;
2403 	}
2404 
2405 	user_sseu.slice_mask = ce->sseu.slice_mask;
2406 	user_sseu.subslice_mask = ce->sseu.subslice_mask;
2407 	user_sseu.min_eus_per_subslice = ce->sseu.min_eus_per_subslice;
2408 	user_sseu.max_eus_per_subslice = ce->sseu.max_eus_per_subslice;
2409 
2410 	intel_context_unlock_pinned(ce);
2411 	intel_context_put(ce);
2412 
2413 	if (copy_to_user(u64_to_user_ptr(args->value), &user_sseu,
2414 			 sizeof(user_sseu)))
2415 		return -EFAULT;
2416 
2417 out:
2418 	args->size = sizeof(user_sseu);
2419 
2420 	return 0;
2421 }
2422 
2423 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
2424 				    struct drm_file *file)
2425 {
2426 	struct drm_i915_file_private *file_priv = file->driver_priv;
2427 	struct drm_i915_gem_context_param *args = data;
2428 	struct i915_gem_context *ctx;
2429 	struct i915_address_space *vm;
2430 	int ret = 0;
2431 
2432 	ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
2433 	if (IS_ERR(ctx))
2434 		return PTR_ERR(ctx);
2435 
2436 	switch (args->param) {
2437 	case I915_CONTEXT_PARAM_GTT_SIZE:
2438 		args->size = 0;
2439 		vm = i915_gem_context_get_eb_vm(ctx);
2440 		args->value = vm->total;
2441 		i915_vm_put(vm);
2442 
2443 		break;
2444 
2445 	case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
2446 		args->size = 0;
2447 		args->value = i915_gem_context_no_error_capture(ctx);
2448 		break;
2449 
2450 	case I915_CONTEXT_PARAM_BANNABLE:
2451 		args->size = 0;
2452 		args->value = i915_gem_context_is_bannable(ctx);
2453 		break;
2454 
2455 	case I915_CONTEXT_PARAM_RECOVERABLE:
2456 		args->size = 0;
2457 		args->value = i915_gem_context_is_recoverable(ctx);
2458 		break;
2459 
2460 	case I915_CONTEXT_PARAM_PRIORITY:
2461 		args->size = 0;
2462 		args->value = ctx->sched.priority;
2463 		break;
2464 
2465 	case I915_CONTEXT_PARAM_SSEU:
2466 		ret = get_sseu(ctx, args);
2467 		break;
2468 
2469 	case I915_CONTEXT_PARAM_VM:
2470 		ret = get_ppgtt(file_priv, ctx, args);
2471 		break;
2472 
2473 	case I915_CONTEXT_PARAM_PERSISTENCE:
2474 		args->size = 0;
2475 		args->value = i915_gem_context_is_persistent(ctx);
2476 		break;
2477 
2478 	case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
2479 		ret = get_protected(ctx, args);
2480 		break;
2481 
2482 	case I915_CONTEXT_PARAM_NO_ZEROMAP:
2483 	case I915_CONTEXT_PARAM_BAN_PERIOD:
2484 	case I915_CONTEXT_PARAM_ENGINES:
2485 	case I915_CONTEXT_PARAM_RINGSIZE:
2486 	default:
2487 		ret = -EINVAL;
2488 		break;
2489 	}
2490 
2491 	i915_gem_context_put(ctx);
2492 	return ret;
2493 }
2494 
2495 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
2496 				    struct drm_file *file)
2497 {
2498 	struct drm_i915_file_private *file_priv = file->driver_priv;
2499 	struct drm_i915_gem_context_param *args = data;
2500 	struct i915_gem_proto_context *pc;
2501 	struct i915_gem_context *ctx;
2502 	int ret = 0;
2503 
2504 	mutex_lock(&file_priv->proto_context_lock);
2505 	ctx = __context_lookup(file_priv, args->ctx_id);
2506 	if (!ctx) {
2507 		pc = xa_load(&file_priv->proto_context_xa, args->ctx_id);
2508 		if (pc) {
2509 			/* Contexts should be finalized inside
2510 			 * GEM_CONTEXT_CREATE starting with graphics
2511 			 * version 13.
2512 			 */
2513 			WARN_ON(GRAPHICS_VER(file_priv->i915) > 12);
2514 			ret = set_proto_ctx_param(file_priv, pc, args);
2515 		} else {
2516 			ret = -ENOENT;
2517 		}
2518 	}
2519 	mutex_unlock(&file_priv->proto_context_lock);
2520 
2521 	if (ctx) {
2522 		ret = ctx_setparam(file_priv, ctx, args);
2523 		i915_gem_context_put(ctx);
2524 	}
2525 
2526 	return ret;
2527 }
2528 
2529 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
2530 				       void *data, struct drm_file *file)
2531 {
2532 	struct drm_i915_private *i915 = to_i915(dev);
2533 	struct drm_i915_reset_stats *args = data;
2534 	struct i915_gem_context *ctx;
2535 
2536 	if (args->flags || args->pad)
2537 		return -EINVAL;
2538 
2539 	ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id);
2540 	if (IS_ERR(ctx))
2541 		return PTR_ERR(ctx);
2542 
2543 	/*
2544 	 * We opt for unserialised reads here. This may result in tearing
2545 	 * in the extremely unlikely event of a GPU hang on this context
2546 	 * as we are querying them. If we need that extra layer of protection,
2547 	 * we should wrap the hangstats with a seqlock.
2548 	 */
2549 
2550 	if (capable(CAP_SYS_ADMIN))
2551 		args->reset_count = i915_reset_count(&i915->gpu_error);
2552 	else
2553 		args->reset_count = 0;
2554 
2555 	args->batch_active = atomic_read(&ctx->guilty_count);
2556 	args->batch_pending = atomic_read(&ctx->active_count);
2557 
2558 	i915_gem_context_put(ctx);
2559 	return 0;
2560 }
2561 
2562 /* GEM context-engines iterator: for_each_gem_engine() */
2563 struct intel_context *
2564 i915_gem_engines_iter_next(struct i915_gem_engines_iter *it)
2565 {
2566 	const struct i915_gem_engines *e = it->engines;
2567 	struct intel_context *ctx;
2568 
2569 	if (unlikely(!e))
2570 		return NULL;
2571 
2572 	do {
2573 		if (it->idx >= e->num_engines)
2574 			return NULL;
2575 
2576 		ctx = e->engines[it->idx++];
2577 	} while (!ctx);
2578 
2579 	return ctx;
2580 }
2581 
2582 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2583 #include "selftests/mock_context.c"
2584 #include "selftests/i915_gem_context.c"
2585 #endif
2586 
2587 void i915_gem_context_module_exit(void)
2588 {
2589 	kmem_cache_destroy(slab_luts);
2590 }
2591 
2592 int __init i915_gem_context_module_init(void)
2593 {
2594 	slab_luts = KMEM_CACHE(i915_lut_handle, 0);
2595 	if (!slab_luts)
2596 		return -ENOMEM;
2597 
2598 	return 0;
2599 }
2600