1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __VLV_DSI_REGS_H__ 7 #define __VLV_DSI_REGS_H__ 8 9 #include "i915_reg_defs.h" 10 11 #define VLV_MIPI_BASE VLV_DISPLAY_BASE 12 #define BXT_MIPI_BASE 0x60000 13 14 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ 15 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) 16 17 /* BXT MIPI mode configure */ 18 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 19 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 20 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ 21 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) 22 23 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC 24 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC 25 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ 26 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) 27 28 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 29 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 30 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ 31 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) 32 33 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) 34 #define STAP_SELECT (1 << 0) 35 36 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) 37 #define HS_IO_CTRL_SELECT (1 << 0) 38 39 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 40 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 41 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) 42 43 /* BXT port control */ 44 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 45 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0 46 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) 47 48 #define DPI_ENABLE (1 << 31) /* A + C */ 49 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 50 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 51 #define DUAL_LINK_MODE_SHIFT 26 52 #define DUAL_LINK_MODE_MASK (1 << 26) 53 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 54 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 55 #define DITHERING_ENABLE (1 << 25) /* A + C */ 56 #define FLOPPED_HSTX (1 << 23) 57 #define DE_INVERT (1 << 19) /* XXX */ 58 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 59 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 60 #define AFE_LATCHOUT (1 << 17) 61 #define LP_OUTPUT_HOLD (1 << 16) 62 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 63 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 64 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 65 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 66 #define CSB_SHIFT 9 67 #define CSB_MASK (3 << 9) 68 #define CSB_20MHZ (0 << 9) 69 #define CSB_10MHZ (1 << 9) 70 #define CSB_40MHZ (2 << 9) 71 #define BANDGAP_MASK (1 << 8) 72 #define BANDGAP_PNW_CIRCUIT (0 << 8) 73 #define BANDGAP_LNC_CIRCUIT (1 << 8) 74 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 75 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 76 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ 77 #define TEARING_EFFECT_SHIFT 2 /* A + C */ 78 #define TEARING_EFFECT_MASK (3 << 2) 79 #define TEARING_EFFECT_OFF (0 << 2) 80 #define TEARING_EFFECT_DSI (1 << 2) 81 #define TEARING_EFFECT_GPIO (2 << 2) 82 #define LANE_CONFIGURATION_SHIFT 0 83 #define LANE_CONFIGURATION_MASK (3 << 0) 84 #define LANE_CONFIGURATION_4LANE (0 << 0) 85 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 86 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 87 88 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 89 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 90 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) 91 #define TEARING_EFFECT_DELAY_SHIFT 0 92 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 93 94 /* XXX: all bits reserved */ 95 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 96 97 /* MIPI DSI Controller and D-PHY registers */ 98 99 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) 100 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) 101 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) 102 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 103 #define ULPS_STATE_MASK (3 << 1) 104 #define ULPS_STATE_ENTER (2 << 1) 105 #define ULPS_STATE_EXIT (1 << 1) 106 #define ULPS_STATE_NORMAL_OPERATION (0 << 1) 107 #define DEVICE_READY (1 << 0) 108 109 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) 110 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) 111 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) 112 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) 113 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) 114 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) 115 #define TEARING_EFFECT (1 << 31) 116 #define SPL_PKT_SENT_INTERRUPT (1 << 30) 117 #define GEN_READ_DATA_AVAIL (1 << 29) 118 #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 119 #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 120 #define RX_PROT_VIOLATION (1 << 26) 121 #define RX_INVALID_TX_LENGTH (1 << 25) 122 #define ACK_WITH_NO_ERROR (1 << 24) 123 #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 124 #define LP_RX_TIMEOUT (1 << 22) 125 #define HS_TX_TIMEOUT (1 << 21) 126 #define DPI_FIFO_UNDERRUN (1 << 20) 127 #define LOW_CONTENTION (1 << 19) 128 #define HIGH_CONTENTION (1 << 18) 129 #define TXDSI_VC_ID_INVALID (1 << 17) 130 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 131 #define TXCHECKSUM_ERROR (1 << 15) 132 #define TXECC_MULTIBIT_ERROR (1 << 14) 133 #define TXECC_SINGLE_BIT_ERROR (1 << 13) 134 #define TXFALSE_CONTROL_ERROR (1 << 12) 135 #define RXDSI_VC_ID_INVALID (1 << 11) 136 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 137 #define RXCHECKSUM_ERROR (1 << 9) 138 #define RXECC_MULTIBIT_ERROR (1 << 8) 139 #define RXECC_SINGLE_BIT_ERROR (1 << 7) 140 #define RXFALSE_CONTROL_ERROR (1 << 6) 141 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 142 #define RX_LP_TX_SYNC_ERROR (1 << 4) 143 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 144 #define RXEOT_SYNC_ERROR (1 << 2) 145 #define RXSOT_SYNC_ERROR (1 << 1) 146 #define RXSOT_ERROR (1 << 0) 147 148 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) 149 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) 150 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) 151 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 152 #define CMD_MODE_NOT_SUPPORTED (0 << 13) 153 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 154 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 155 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 156 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 157 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 158 #define VID_MODE_FORMAT_MASK (0xf << 7) 159 #define VID_MODE_NOT_SUPPORTED (0 << 7) 160 #define VID_MODE_FORMAT_RGB565 (1 << 7) 161 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7) 162 #define VID_MODE_FORMAT_RGB666 (3 << 7) 163 #define VID_MODE_FORMAT_RGB888 (4 << 7) 164 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 165 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 166 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 167 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 168 #define DATA_LANES_PRG_REG_SHIFT 0 169 #define DATA_LANES_PRG_REG_MASK (7 << 0) 170 171 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) 172 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) 173 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) 174 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 175 176 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) 177 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) 178 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) 179 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 180 181 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) 182 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) 183 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) 184 #define TURN_AROUND_TIMEOUT_MASK 0x3f 185 186 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) 187 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) 188 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) 189 #define DEVICE_RESET_TIMER_MASK 0xffff 190 191 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) 192 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) 193 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) 194 #define VERTICAL_ADDRESS_SHIFT 16 195 #define VERTICAL_ADDRESS_MASK (0xffff << 16) 196 #define HORIZONTAL_ADDRESS_SHIFT 0 197 #define HORIZONTAL_ADDRESS_MASK 0xffff 198 199 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) 200 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) 201 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) 202 #define DBI_FIFO_EMPTY_HALF (0 << 0) 203 #define DBI_FIFO_EMPTY_QUARTER (1 << 0) 204 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 205 206 /* regs below are bits 15:0 */ 207 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) 208 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) 209 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) 210 211 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) 212 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) 213 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) 214 215 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) 216 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) 217 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) 218 219 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) 220 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) 221 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) 222 223 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) 224 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) 225 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) 226 227 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) 228 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) 229 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) 230 231 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) 232 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) 233 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) 234 235 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) 236 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) 237 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) 238 239 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) 240 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) 241 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) 242 #define DPI_LP_MODE (1 << 6) 243 #define BACKLIGHT_OFF (1 << 5) 244 #define BACKLIGHT_ON (1 << 4) 245 #define COLOR_MODE_OFF (1 << 3) 246 #define COLOR_MODE_ON (1 << 2) 247 #define TURN_ON (1 << 1) 248 #define SHUTDOWN (1 << 0) 249 250 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) 251 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) 252 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) 253 #define COMMAND_BYTE_SHIFT 0 254 #define COMMAND_BYTE_MASK (0x3f << 0) 255 256 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) 257 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) 258 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) 259 #define MASTER_INIT_TIMER_SHIFT 0 260 #define MASTER_INIT_TIMER_MASK (0xffff << 0) 261 262 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) 263 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) 264 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ 265 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) 266 #define MAX_RETURN_PKT_SIZE_SHIFT 0 267 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 268 269 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) 270 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) 271 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) 272 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 273 #define DISABLE_VIDEO_BTA (1 << 3) 274 #define IP_TG_CONFIG (1 << 2) 275 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 276 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 277 #define VIDEO_MODE_BURST (3 << 0) 278 279 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) 280 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) 281 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) 282 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) 283 #define BXT_DPHY_DEFEATURE_EN (1 << 8) 284 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 285 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 286 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 287 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 288 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 289 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 290 #define CLOCKSTOP (1 << 1) 291 #define EOT_DISABLE (1 << 0) 292 293 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) 294 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) 295 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) 296 #define LP_BYTECLK_SHIFT 0 297 #define LP_BYTECLK_MASK (0xffff << 0) 298 299 #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4) 300 #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4) 301 #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) 302 303 #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098) 304 #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898) 305 #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) 306 307 /* bits 31:0 */ 308 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) 309 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) 310 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) 311 312 /* bits 31:0 */ 313 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) 314 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) 315 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) 316 317 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) 318 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) 319 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) 320 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) 321 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) 322 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) 323 #define LONG_PACKET_WORD_COUNT_SHIFT 8 324 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 325 #define SHORT_PACKET_PARAM_SHIFT 8 326 #define SHORT_PACKET_PARAM_MASK (0xffff << 8) 327 #define VIRTUAL_CHANNEL_SHIFT 6 328 #define VIRTUAL_CHANNEL_MASK (3 << 6) 329 #define DATA_TYPE_SHIFT 0 330 #define DATA_TYPE_MASK (0x3f << 0) 331 /* data type values, see include/video/mipi_display.h */ 332 333 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) 334 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) 335 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) 336 #define DPI_FIFO_EMPTY (1 << 28) 337 #define DBI_FIFO_EMPTY (1 << 27) 338 #define LP_CTRL_FIFO_EMPTY (1 << 26) 339 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 340 #define LP_CTRL_FIFO_FULL (1 << 24) 341 #define HS_CTRL_FIFO_EMPTY (1 << 18) 342 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 343 #define HS_CTRL_FIFO_FULL (1 << 16) 344 #define LP_DATA_FIFO_EMPTY (1 << 10) 345 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 346 #define LP_DATA_FIFO_FULL (1 << 8) 347 #define HS_DATA_FIFO_EMPTY (1 << 2) 348 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 349 #define HS_DATA_FIFO_FULL (1 << 0) 350 351 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) 352 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) 353 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) 354 #define DBI_HS_LP_MODE_MASK (1 << 0) 355 #define DBI_LP_MODE (1 << 0) 356 #define DBI_HS_MODE (0 << 0) 357 358 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) 359 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) 360 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) 361 #define EXIT_ZERO_COUNT_SHIFT 24 362 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) 363 #define TRAIL_COUNT_SHIFT 16 364 #define TRAIL_COUNT_MASK (0x1f << 16) 365 #define CLK_ZERO_COUNT_SHIFT 8 366 #define CLK_ZERO_COUNT_MASK (0xff << 8) 367 #define PREPARE_COUNT_SHIFT 0 368 #define PREPARE_COUNT_MASK (0x3f << 0) 369 370 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) 371 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) 372 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) 373 374 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088) 375 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888) 376 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) 377 #define LP_HS_SSW_CNT_SHIFT 16 378 #define LP_HS_SSW_CNT_MASK (0xffff << 16) 379 #define HS_LP_PWR_SW_CNT_SHIFT 0 380 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 381 382 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) 383 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) 384 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) 385 #define STOP_STATE_STALL_COUNTER_SHIFT 0 386 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 387 388 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) 389 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) 390 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) 391 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) 392 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) 393 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) 394 #define RX_CONTENTION_DETECTED (1 << 0) 395 396 /* XXX: only pipe A ?!? */ 397 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) 398 #define DBI_TYPEC_ENABLE (1 << 31) 399 #define DBI_TYPEC_WIP (1 << 30) 400 #define DBI_TYPEC_OPTION_SHIFT 28 401 #define DBI_TYPEC_OPTION_MASK (3 << 28) 402 #define DBI_TYPEC_FREQ_SHIFT 24 403 #define DBI_TYPEC_FREQ_MASK (0xf << 24) 404 #define DBI_TYPEC_OVERRIDE (1 << 8) 405 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 406 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 407 408 /* MIPI adapter registers */ 409 410 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) 411 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) 412 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) 413 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 414 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 415 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 416 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 417 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 418 #define READ_REQUEST_PRIORITY_SHIFT 3 419 #define READ_REQUEST_PRIORITY_MASK (3 << 3) 420 #define READ_REQUEST_PRIORITY_LOW (0 << 3) 421 #define READ_REQUEST_PRIORITY_HIGH (3 << 3) 422 #define RGB_FLIP_TO_BGR (1 << 2) 423 424 #define BXT_PIPE_SELECT_SHIFT 7 425 #define BXT_PIPE_SELECT_MASK (7 << 7) 426 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7) 427 #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */ 428 #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */ 429 #define GLK_MIPIIO_RESET_RELEASED (1 << 28) 430 #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */ 431 #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */ 432 #define GLK_LP_WAKE (1 << 22) 433 #define GLK_LP11_LOW_PWR_MODE (1 << 21) 434 #define GLK_LP00_LOW_PWR_MODE (1 << 20) 435 #define GLK_FIREWALL_ENABLE (1 << 16) 436 #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) 437 #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10 438 #define BXT_DSC_ENABLE (1 << 3) 439 #define BXT_RGB_FLIP (1 << 2) 440 #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ 441 #define GLK_MIPIIO_ENABLE (1 << 0) 442 443 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) 444 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) 445 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) 446 #define DATA_MEM_ADDRESS_SHIFT 5 447 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 448 #define DATA_VALID (1 << 0) 449 450 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) 451 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) 452 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) 453 #define DATA_LENGTH_SHIFT 0 454 #define DATA_LENGTH_MASK (0xfffff << 0) 455 456 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) 457 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) 458 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) 459 #define COMMAND_MEM_ADDRESS_SHIFT 5 460 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 461 #define AUTO_PWG_ENABLE (1 << 2) 462 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 463 #define COMMAND_VALID (1 << 0) 464 465 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) 466 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) 467 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) 468 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 469 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 470 471 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) 472 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) 473 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ 474 475 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) 476 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) 477 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) 478 #define READ_DATA_VALID(n) (1 << (n)) 479 480 #endif /* __VLV_DSI_REGS_H__ */ 481