1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Shobhit Kumar <shobhit.kumar@intel.com> 25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> 26 */ 27 28 #include <linux/kernel.h> 29 30 #include "i915_drv.h" 31 #include "intel_de.h" 32 #include "intel_display_types.h" 33 #include "intel_dsi.h" 34 #include "vlv_dsi_pll.h" 35 #include "vlv_sideband.h" 36 37 static const u16 lfsr_converts[] = { 38 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ 39 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ 40 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ 41 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ 42 }; 43 44 /* Get DSI clock from pixel clock */ 45 static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt, 46 int lane_count) 47 { 48 u32 dsi_clk_khz; 49 u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt); 50 51 /* DSI data rate = pixel clock * bits per pixel / lane count 52 pixel clock is converted from KHz to Hz */ 53 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); 54 55 return dsi_clk_khz; 56 } 57 58 static int dsi_calc_mnp(struct drm_i915_private *dev_priv, 59 struct intel_crtc_state *config, 60 int target_dsi_clk) 61 { 62 unsigned int m_min, m_max, p_min = 2, p_max = 6; 63 unsigned int m, n, p; 64 unsigned int calc_m, calc_p; 65 int delta, ref_clk; 66 67 /* target_dsi_clk is expected in kHz */ 68 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { 69 drm_err(&dev_priv->drm, "DSI CLK Out of Range\n"); 70 return -ECHRNG; 71 } 72 73 if (IS_CHERRYVIEW(dev_priv)) { 74 ref_clk = 100000; 75 n = 4; 76 m_min = 70; 77 m_max = 96; 78 } else { 79 ref_clk = 25000; 80 n = 1; 81 m_min = 62; 82 m_max = 92; 83 } 84 85 calc_p = p_min; 86 calc_m = m_min; 87 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n)); 88 89 for (m = m_min; m <= m_max && delta; m++) { 90 for (p = p_min; p <= p_max && delta; p++) { 91 /* 92 * Find the optimal m and p divisors with minimal delta 93 * +/- the required clock 94 */ 95 int calc_dsi_clk = (m * ref_clk) / (p * n); 96 int d = abs(target_dsi_clk - calc_dsi_clk); 97 if (d < delta) { 98 delta = d; 99 calc_m = m; 100 calc_p = p; 101 } 102 } 103 } 104 105 /* register has log2(N1), this works fine for powers of two */ 106 config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); 107 config->dsi_pll.div = 108 (ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT | 109 (u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT; 110 111 return 0; 112 } 113 114 /* 115 * XXX: The muxing and gating is hard coded for now. Need to add support for 116 * sharing PLLs with two DSI outputs. 117 */ 118 int vlv_dsi_pll_compute(struct intel_encoder *encoder, 119 struct intel_crtc_state *config) 120 { 121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 122 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 123 int ret; 124 u32 dsi_clk; 125 126 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, 127 intel_dsi->lane_count); 128 129 ret = dsi_calc_mnp(dev_priv, config, dsi_clk); 130 if (ret) { 131 drm_dbg_kms(&dev_priv->drm, "dsi_calc_mnp failed\n"); 132 return ret; 133 } 134 135 if (intel_dsi->ports & (1 << PORT_A)) 136 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; 137 138 if (intel_dsi->ports & (1 << PORT_C)) 139 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; 140 141 config->dsi_pll.ctrl |= DSI_PLL_VCO_EN; 142 143 drm_dbg_kms(&dev_priv->drm, "dsi pll div %08x, ctrl %08x\n", 144 config->dsi_pll.div, config->dsi_pll.ctrl); 145 146 return 0; 147 } 148 149 void vlv_dsi_pll_enable(struct intel_encoder *encoder, 150 const struct intel_crtc_state *config) 151 { 152 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 153 154 drm_dbg_kms(&dev_priv->drm, "\n"); 155 156 vlv_cck_get(dev_priv); 157 158 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); 159 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div); 160 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 161 config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN); 162 163 /* wait at least 0.5 us after ungating before enabling VCO, 164 * allow hrtimer subsystem optimization by relaxing timing 165 */ 166 usleep_range(10, 50); 167 168 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl); 169 170 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & 171 DSI_PLL_LOCK, 20)) { 172 173 vlv_cck_put(dev_priv); 174 drm_err(&dev_priv->drm, "DSI PLL lock failed\n"); 175 return; 176 } 177 vlv_cck_put(dev_priv); 178 179 drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n"); 180 } 181 182 void vlv_dsi_pll_disable(struct intel_encoder *encoder) 183 { 184 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 185 u32 tmp; 186 187 drm_dbg_kms(&dev_priv->drm, "\n"); 188 189 vlv_cck_get(dev_priv); 190 191 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 192 tmp &= ~DSI_PLL_VCO_EN; 193 tmp |= DSI_PLL_LDO_GATE; 194 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); 195 196 vlv_cck_put(dev_priv); 197 } 198 199 bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv) 200 { 201 bool enabled; 202 u32 val; 203 u32 mask; 204 205 mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED; 206 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); 207 enabled = (val & mask) == mask; 208 209 if (!enabled) 210 return false; 211 212 /* 213 * Dividers must be programmed with valid values. As per BSEPC, for 214 * GEMINLAKE only PORT A divider values are checked while for BXT 215 * both divider values are validated. Check this here for 216 * paranoia, since BIOS is known to misconfigure PLLs in this way at 217 * times, and since accessing DSI registers with invalid dividers 218 * causes a system hang. 219 */ 220 val = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); 221 if (IS_GEMINILAKE(dev_priv)) { 222 if (!(val & BXT_DSIA_16X_MASK)) { 223 drm_dbg(&dev_priv->drm, 224 "Invalid PLL divider (%08x)\n", val); 225 enabled = false; 226 } 227 } else { 228 if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) { 229 drm_dbg(&dev_priv->drm, 230 "Invalid PLL divider (%08x)\n", val); 231 enabled = false; 232 } 233 } 234 235 return enabled; 236 } 237 238 void bxt_dsi_pll_disable(struct intel_encoder *encoder) 239 { 240 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 241 u32 val; 242 243 drm_dbg_kms(&dev_priv->drm, "\n"); 244 245 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); 246 val &= ~BXT_DSI_PLL_DO_ENABLE; 247 intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val); 248 249 /* 250 * PLL lock should deassert within 200us. 251 * Wait up to 1ms before timing out. 252 */ 253 if (intel_de_wait_for_clear(dev_priv, BXT_DSI_PLL_ENABLE, 254 BXT_DSI_PLL_LOCKED, 1)) 255 drm_err(&dev_priv->drm, 256 "Timeout waiting for PLL lock deassertion\n"); 257 } 258 259 u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, 260 struct intel_crtc_state *config) 261 { 262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 263 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 264 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 265 u32 dsi_clock, pclk; 266 u32 pll_ctl, pll_div; 267 u32 m = 0, p = 0, n; 268 int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000; 269 int i; 270 271 drm_dbg_kms(&dev_priv->drm, "\n"); 272 273 vlv_cck_get(dev_priv); 274 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 275 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); 276 vlv_cck_put(dev_priv); 277 278 config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK; 279 config->dsi_pll.div = pll_div; 280 281 /* mask out other bits and extract the P1 divisor */ 282 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; 283 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); 284 285 /* N1 divisor */ 286 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; 287 n = 1 << n; /* register has log2(N1) */ 288 289 /* mask out the other bits and extract the M1 divisor */ 290 pll_div &= DSI_PLL_M1_DIV_MASK; 291 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; 292 293 while (pll_ctl) { 294 pll_ctl = pll_ctl >> 1; 295 p++; 296 } 297 p--; 298 299 if (!p) { 300 drm_err(&dev_priv->drm, "wrong P1 divisor\n"); 301 return 0; 302 } 303 304 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { 305 if (lfsr_converts[i] == pll_div) 306 break; 307 } 308 309 if (i == ARRAY_SIZE(lfsr_converts)) { 310 drm_err(&dev_priv->drm, "wrong m_seed programmed\n"); 311 return 0; 312 } 313 314 m = i + 62; 315 316 dsi_clock = (m * refclk) / (p * n); 317 318 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); 319 320 return pclk; 321 } 322 323 u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, 324 struct intel_crtc_state *config) 325 { 326 u32 pclk; 327 u32 dsi_clk; 328 u32 dsi_ratio; 329 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 330 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 331 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 332 333 config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); 334 335 dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; 336 337 dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; 338 339 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); 340 341 drm_dbg(&dev_priv->drm, "Calculated pclk=%u\n", pclk); 342 return pclk; 343 } 344 345 void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) 346 { 347 u32 temp; 348 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 349 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 350 351 temp = intel_de_read(dev_priv, MIPI_CTRL(port)); 352 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 353 intel_de_write(dev_priv, MIPI_CTRL(port), 354 temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT); 355 } 356 357 static void glk_dsi_program_esc_clock(struct drm_device *dev, 358 const struct intel_crtc_state *config) 359 { 360 struct drm_i915_private *dev_priv = to_i915(dev); 361 u32 dsi_rate = 0; 362 u32 pll_ratio = 0; 363 u32 ddr_clk = 0; 364 u32 div1_value = 0; 365 u32 div2_value = 0; 366 u32 txesc1_div = 0; 367 u32 txesc2_div = 0; 368 369 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; 370 371 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; 372 373 ddr_clk = dsi_rate / 2; 374 375 /* Variable divider value */ 376 div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000); 377 378 /* Calculate TXESC1 divider */ 379 if (div1_value <= 10) 380 txesc1_div = div1_value; 381 else if ((div1_value > 10) && (div1_value <= 20)) 382 txesc1_div = DIV_ROUND_UP(div1_value, 2); 383 else if ((div1_value > 20) && (div1_value <= 30)) 384 txesc1_div = DIV_ROUND_UP(div1_value, 4); 385 else if ((div1_value > 30) && (div1_value <= 40)) 386 txesc1_div = DIV_ROUND_UP(div1_value, 6); 387 else if ((div1_value > 40) && (div1_value <= 50)) 388 txesc1_div = DIV_ROUND_UP(div1_value, 8); 389 else 390 txesc1_div = 10; 391 392 /* Calculate TXESC2 divider */ 393 div2_value = DIV_ROUND_UP(div1_value, txesc1_div); 394 395 if (div2_value < 10) 396 txesc2_div = div2_value; 397 else 398 txesc2_div = 10; 399 400 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, 401 (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK); 402 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, 403 (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK); 404 } 405 406 /* Program BXT Mipi clocks and dividers */ 407 static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port, 408 const struct intel_crtc_state *config) 409 { 410 struct drm_i915_private *dev_priv = to_i915(dev); 411 u32 tmp; 412 u32 dsi_rate = 0; 413 u32 pll_ratio = 0; 414 u32 rx_div; 415 u32 tx_div; 416 u32 rx_div_upper; 417 u32 rx_div_lower; 418 u32 mipi_8by3_divider; 419 420 /* Clear old configurations */ 421 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); 422 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); 423 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); 424 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); 425 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); 426 427 /* Get the current DSI rate(actual) */ 428 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; 429 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; 430 431 /* 432 * tx clock should be <= 20MHz and the div value must be 433 * subtracted by 1 as per bspec 434 */ 435 tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1; 436 /* 437 * rx clock should be <= 150MHz and the div value must be 438 * subtracted by 1 as per bspec 439 */ 440 rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1; 441 442 /* 443 * rx divider value needs to be updated in the 444 * two differnt bit fields in the register hence splitting the 445 * rx divider value accordingly 446 */ 447 rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2; 448 rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2; 449 450 mipi_8by3_divider = 0x2; 451 452 tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider); 453 tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div); 454 tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower); 455 tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper); 456 457 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); 458 } 459 460 int bxt_dsi_pll_compute(struct intel_encoder *encoder, 461 struct intel_crtc_state *config) 462 { 463 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 464 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 465 u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max; 466 u32 dsi_clk; 467 468 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, 469 intel_dsi->lane_count); 470 471 /* 472 * From clock diagram, to get PLL ratio divider, divide double of DSI 473 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to 474 * round 'up' the result 475 */ 476 dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ); 477 478 if (IS_BROXTON(dev_priv)) { 479 dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN; 480 dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX; 481 } else { 482 dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN; 483 dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX; 484 } 485 486 if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) { 487 drm_err(&dev_priv->drm, 488 "Can't get a suitable ratio from DSI PLL ratios\n"); 489 return -ECHRNG; 490 } else 491 drm_dbg_kms(&dev_priv->drm, "DSI PLL calculation is Done!!\n"); 492 493 /* 494 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x 495 * Spec says both have to be programmed, even if one is not getting 496 * used. Configure MIPI_CLOCK_CTL dividers in modeset 497 */ 498 config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2; 499 500 /* As per recommendation from hardware team, 501 * Prog PVD ratio =1 if dsi ratio <= 50 502 */ 503 if (IS_BROXTON(dev_priv) && dsi_ratio <= 50) 504 config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1; 505 506 return 0; 507 } 508 509 void bxt_dsi_pll_enable(struct intel_encoder *encoder, 510 const struct intel_crtc_state *config) 511 { 512 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 513 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 514 enum port port; 515 u32 val; 516 517 drm_dbg_kms(&dev_priv->drm, "\n"); 518 519 /* Configure PLL vales */ 520 intel_de_write(dev_priv, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); 521 intel_de_posting_read(dev_priv, BXT_DSI_PLL_CTL); 522 523 /* Program TX, RX, Dphy clocks */ 524 if (IS_BROXTON(dev_priv)) { 525 for_each_dsi_port(port, intel_dsi->ports) 526 bxt_dsi_program_clocks(encoder->base.dev, port, config); 527 } else { 528 glk_dsi_program_esc_clock(encoder->base.dev, config); 529 } 530 531 /* Enable DSI PLL */ 532 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); 533 val |= BXT_DSI_PLL_DO_ENABLE; 534 intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val); 535 536 /* Timeout and fail if PLL not locked */ 537 if (intel_de_wait_for_set(dev_priv, BXT_DSI_PLL_ENABLE, 538 BXT_DSI_PLL_LOCKED, 1)) { 539 drm_err(&dev_priv->drm, 540 "Timed out waiting for DSI PLL to lock\n"); 541 return; 542 } 543 544 drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n"); 545 } 546 547 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) 548 { 549 u32 tmp; 550 struct drm_device *dev = encoder->base.dev; 551 struct drm_i915_private *dev_priv = to_i915(dev); 552 553 /* Clear old configurations */ 554 if (IS_BROXTON(dev_priv)) { 555 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); 556 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); 557 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); 558 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); 559 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); 560 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); 561 } else { 562 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV1); 563 tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK; 564 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, tmp); 565 566 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV2); 567 tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK; 568 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, tmp); 569 } 570 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); 571 } 572 573 static void assert_dsi_pll(struct drm_i915_private *i915, bool state) 574 { 575 bool cur_state; 576 577 vlv_cck_get(i915); 578 cur_state = vlv_cck_read(i915, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN; 579 vlv_cck_put(i915); 580 581 I915_STATE_WARN(cur_state != state, 582 "DSI PLL state assertion failure (expected %s, current %s)\n", 583 onoff(state), onoff(cur_state)); 584 } 585 586 void assert_dsi_pll_enabled(struct drm_i915_private *i915) 587 { 588 assert_dsi_pll(i915, true); 589 } 590 591 void assert_dsi_pll_disabled(struct drm_i915_private *i915) 592 { 593 assert_dsi_pll(i915, false); 594 } 595