1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Jani Nikula <jani.nikula@intel.com> 24 */ 25 26 #include <linux/slab.h> 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_crtc.h> 30 #include <drm/drm_edid.h> 31 #include <drm/drm_mipi_dsi.h> 32 33 #include "i915_drv.h" 34 #include "i915_reg.h" 35 #include "intel_atomic.h" 36 #include "intel_backlight.h" 37 #include "intel_connector.h" 38 #include "intel_crtc.h" 39 #include "intel_de.h" 40 #include "intel_display_types.h" 41 #include "intel_dsi.h" 42 #include "intel_dsi_vbt.h" 43 #include "intel_fifo_underrun.h" 44 #include "intel_panel.h" 45 #include "skl_scaler.h" 46 #include "vlv_dsi.h" 47 #include "vlv_dsi_pll.h" 48 #include "vlv_dsi_regs.h" 49 #include "vlv_sideband.h" 50 51 /* return pixels in terms of txbyteclkhs */ 52 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, 53 u16 burst_mode_ratio) 54 { 55 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, 56 8 * 100), lane_count); 57 } 58 59 /* return pixels equvalent to txbyteclkhs */ 60 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, 61 u16 burst_mode_ratio) 62 { 63 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), 64 (bpp * burst_mode_ratio)); 65 } 66 67 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 68 { 69 /* It just so happens the VBT matches register contents. */ 70 switch (fmt) { 71 case VID_MODE_FORMAT_RGB888: 72 return MIPI_DSI_FMT_RGB888; 73 case VID_MODE_FORMAT_RGB666: 74 return MIPI_DSI_FMT_RGB666; 75 case VID_MODE_FORMAT_RGB666_PACKED: 76 return MIPI_DSI_FMT_RGB666_PACKED; 77 case VID_MODE_FORMAT_RGB565: 78 return MIPI_DSI_FMT_RGB565; 79 default: 80 MISSING_CASE(fmt); 81 return MIPI_DSI_FMT_RGB666; 82 } 83 } 84 85 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) 86 { 87 struct drm_encoder *encoder = &intel_dsi->base.base; 88 struct drm_device *dev = encoder->dev; 89 struct drm_i915_private *dev_priv = to_i915(dev); 90 u32 mask; 91 92 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | 93 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; 94 95 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), 96 mask, 100)) 97 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); 98 } 99 100 static void write_data(struct drm_i915_private *dev_priv, 101 i915_reg_t reg, 102 const u8 *data, u32 len) 103 { 104 u32 i, j; 105 106 for (i = 0; i < len; i += 4) { 107 u32 val = 0; 108 109 for (j = 0; j < min_t(u32, len - i, 4); j++) 110 val |= *data++ << 8 * j; 111 112 intel_de_write(dev_priv, reg, val); 113 } 114 } 115 116 static void read_data(struct drm_i915_private *dev_priv, 117 i915_reg_t reg, 118 u8 *data, u32 len) 119 { 120 u32 i, j; 121 122 for (i = 0; i < len; i += 4) { 123 u32 val = intel_de_read(dev_priv, reg); 124 125 for (j = 0; j < min_t(u32, len - i, 4); j++) 126 *data++ = val >> 8 * j; 127 } 128 } 129 130 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, 131 const struct mipi_dsi_msg *msg) 132 { 133 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 134 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; 135 struct drm_i915_private *dev_priv = to_i915(dev); 136 enum port port = intel_dsi_host->port; 137 struct mipi_dsi_packet packet; 138 ssize_t ret; 139 const u8 *header, *data; 140 i915_reg_t data_reg, ctrl_reg; 141 u32 data_mask, ctrl_mask; 142 143 ret = mipi_dsi_create_packet(&packet, msg); 144 if (ret < 0) 145 return ret; 146 147 header = packet.header; 148 data = packet.payload; 149 150 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 151 data_reg = MIPI_LP_GEN_DATA(port); 152 data_mask = LP_DATA_FIFO_FULL; 153 ctrl_reg = MIPI_LP_GEN_CTRL(port); 154 ctrl_mask = LP_CTRL_FIFO_FULL; 155 } else { 156 data_reg = MIPI_HS_GEN_DATA(port); 157 data_mask = HS_DATA_FIFO_FULL; 158 ctrl_reg = MIPI_HS_GEN_CTRL(port); 159 ctrl_mask = HS_CTRL_FIFO_FULL; 160 } 161 162 /* note: this is never true for reads */ 163 if (packet.payload_length) { 164 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 165 data_mask, 50)) 166 drm_err(&dev_priv->drm, 167 "Timeout waiting for HS/LP DATA FIFO !full\n"); 168 169 write_data(dev_priv, data_reg, packet.payload, 170 packet.payload_length); 171 } 172 173 if (msg->rx_len) { 174 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 175 GEN_READ_DATA_AVAIL); 176 } 177 178 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 179 ctrl_mask, 50)) { 180 drm_err(&dev_priv->drm, 181 "Timeout waiting for HS/LP CTRL FIFO !full\n"); 182 } 183 184 intel_de_write(dev_priv, ctrl_reg, 185 header[2] << 16 | header[1] << 8 | header[0]); 186 187 /* ->rx_len is set only for reads */ 188 if (msg->rx_len) { 189 data_mask = GEN_READ_DATA_AVAIL; 190 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), 191 data_mask, 50)) 192 drm_err(&dev_priv->drm, 193 "Timeout waiting for read data.\n"); 194 195 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); 196 } 197 198 /* XXX: fix for reads and writes */ 199 return 4 + packet.payload_length; 200 } 201 202 static int intel_dsi_host_attach(struct mipi_dsi_host *host, 203 struct mipi_dsi_device *dsi) 204 { 205 return 0; 206 } 207 208 static int intel_dsi_host_detach(struct mipi_dsi_host *host, 209 struct mipi_dsi_device *dsi) 210 { 211 return 0; 212 } 213 214 static const struct mipi_dsi_host_ops intel_dsi_host_ops = { 215 .attach = intel_dsi_host_attach, 216 .detach = intel_dsi_host_detach, 217 .transfer = intel_dsi_host_transfer, 218 }; 219 220 /* 221 * send a video mode command 222 * 223 * XXX: commands with data in MIPI_DPI_DATA? 224 */ 225 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, 226 enum port port) 227 { 228 struct drm_encoder *encoder = &intel_dsi->base.base; 229 struct drm_device *dev = encoder->dev; 230 struct drm_i915_private *dev_priv = to_i915(dev); 231 u32 mask; 232 233 /* XXX: pipe, hs */ 234 if (hs) 235 cmd &= ~DPI_LP_MODE; 236 else 237 cmd |= DPI_LP_MODE; 238 239 /* clear bit */ 240 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); 241 242 /* XXX: old code skips write if control unchanged */ 243 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) 244 drm_dbg_kms(&dev_priv->drm, 245 "Same special packet %02x twice in a row.\n", cmd); 246 247 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); 248 249 mask = SPL_PKT_SENT_INTERRUPT; 250 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) 251 drm_err(&dev_priv->drm, 252 "Video mode command 0x%08x send failed.\n", cmd); 253 254 return 0; 255 } 256 257 static void band_gap_reset(struct drm_i915_private *dev_priv) 258 { 259 vlv_flisdsi_get(dev_priv); 260 261 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); 262 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); 263 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); 264 udelay(150); 265 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); 266 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); 267 268 vlv_flisdsi_put(dev_priv); 269 } 270 271 static int intel_dsi_compute_config(struct intel_encoder *encoder, 272 struct intel_crtc_state *pipe_config, 273 struct drm_connector_state *conn_state) 274 { 275 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 276 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 277 base); 278 struct intel_connector *intel_connector = intel_dsi->attached_connector; 279 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 280 int ret; 281 282 drm_dbg_kms(&dev_priv->drm, "\n"); 283 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 284 285 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 286 if (ret) 287 return ret; 288 289 ret = intel_panel_fitting(pipe_config, conn_state); 290 if (ret) 291 return ret; 292 293 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 294 return -EINVAL; 295 296 /* DSI uses short packets for sync events, so clear mode flags for DSI */ 297 adjusted_mode->flags = 0; 298 299 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 300 pipe_config->pipe_bpp = 24; 301 else 302 pipe_config->pipe_bpp = 18; 303 304 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 305 /* Enable Frame time stamp based scanline reporting */ 306 pipe_config->mode_flags |= 307 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 308 309 /* Dual link goes to DSI transcoder A. */ 310 if (intel_dsi->ports == BIT(PORT_C)) 311 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; 312 else 313 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; 314 315 ret = bxt_dsi_pll_compute(encoder, pipe_config); 316 if (ret) 317 return -EINVAL; 318 } else { 319 ret = vlv_dsi_pll_compute(encoder, pipe_config); 320 if (ret) 321 return -EINVAL; 322 } 323 324 pipe_config->clock_set = true; 325 326 return 0; 327 } 328 329 static bool glk_dsi_enable_io(struct intel_encoder *encoder) 330 { 331 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 332 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 333 enum port port; 334 bool cold_boot = false; 335 336 /* Set the MIPI mode 337 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. 338 * Power ON MIPI IO first and then write into IO reset and LP wake bits 339 */ 340 for_each_dsi_port(port, intel_dsi->ports) 341 intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE); 342 343 /* Put the IO into reset */ 344 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); 345 346 /* Program LP Wake */ 347 for_each_dsi_port(port, intel_dsi->ports) { 348 u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 349 intel_de_rmw(dev_priv, MIPI_CTRL(port), 350 GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0); 351 } 352 353 /* Wait for Pwr ACK */ 354 for_each_dsi_port(port, intel_dsi->ports) { 355 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 356 GLK_MIPIIO_PORT_POWERED, 20)) 357 drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); 358 } 359 360 /* Check for cold boot scenario */ 361 for_each_dsi_port(port, intel_dsi->ports) { 362 cold_boot |= 363 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); 364 } 365 366 return cold_boot; 367 } 368 369 static void glk_dsi_device_ready(struct intel_encoder *encoder) 370 { 371 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 372 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 373 enum port port; 374 375 /* Wait for MIPI PHY status bit to set */ 376 for_each_dsi_port(port, intel_dsi->ports) { 377 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 378 GLK_PHY_STATUS_PORT_READY, 20)) 379 drm_err(&dev_priv->drm, "PHY is not ON\n"); 380 } 381 382 /* Get IO out of reset */ 383 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); 384 385 /* Get IO out of Low power state*/ 386 for_each_dsi_port(port, intel_dsi->ports) { 387 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { 388 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 389 ULPS_STATE_MASK, DEVICE_READY); 390 usleep_range(10, 15); 391 } else { 392 /* Enter ULPS */ 393 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 394 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); 395 396 /* Wait for ULPS active */ 397 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 398 GLK_ULPS_NOT_ACTIVE, 20)) 399 drm_err(&dev_priv->drm, "ULPS not active\n"); 400 401 /* Exit ULPS */ 402 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 403 ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY); 404 405 /* Enter Normal Mode */ 406 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 407 ULPS_STATE_MASK, 408 ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); 409 410 intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0); 411 } 412 } 413 414 /* Wait for Stop state */ 415 for_each_dsi_port(port, intel_dsi->ports) { 416 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 417 GLK_DATA_LANE_STOP_STATE, 20)) 418 drm_err(&dev_priv->drm, 419 "Date lane not in STOP state\n"); 420 } 421 422 /* Wait for AFE LATCH */ 423 for_each_dsi_port(port, intel_dsi->ports) { 424 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), 425 AFE_LATCHOUT, 20)) 426 drm_err(&dev_priv->drm, 427 "D-PHY not entering LP-11 state\n"); 428 } 429 } 430 431 static void bxt_dsi_device_ready(struct intel_encoder *encoder) 432 { 433 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 434 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 435 enum port port; 436 u32 val; 437 438 drm_dbg_kms(&dev_priv->drm, "\n"); 439 440 /* Enable MIPI PHY transparent latch */ 441 for_each_dsi_port(port, intel_dsi->ports) { 442 intel_de_rmw(dev_priv, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); 443 usleep_range(2000, 2500); 444 } 445 446 /* Clear ULPS and set device ready */ 447 for_each_dsi_port(port, intel_dsi->ports) { 448 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 449 val &= ~ULPS_STATE_MASK; 450 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 451 usleep_range(2000, 2500); 452 val |= DEVICE_READY; 453 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 454 } 455 } 456 457 static void vlv_dsi_device_ready(struct intel_encoder *encoder) 458 { 459 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 460 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 461 enum port port; 462 463 drm_dbg_kms(&dev_priv->drm, "\n"); 464 465 vlv_flisdsi_get(dev_priv); 466 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms 467 * needed everytime after power gate */ 468 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); 469 vlv_flisdsi_put(dev_priv); 470 471 /* bandgap reset is needed after everytime we do power gate */ 472 band_gap_reset(dev_priv); 473 474 for_each_dsi_port(port, intel_dsi->ports) { 475 476 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 477 ULPS_STATE_ENTER); 478 usleep_range(2500, 3000); 479 480 /* Enable MIPI PHY transparent latch 481 * Common bit for both MIPI Port A & MIPI Port C 482 * No similar bit in MIPI Port C reg 483 */ 484 intel_de_rmw(dev_priv, MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); 485 usleep_range(1000, 1500); 486 487 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 488 ULPS_STATE_EXIT); 489 usleep_range(2500, 3000); 490 491 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 492 DEVICE_READY); 493 usleep_range(2500, 3000); 494 } 495 } 496 497 static void intel_dsi_device_ready(struct intel_encoder *encoder) 498 { 499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 500 501 if (IS_GEMINILAKE(dev_priv)) 502 glk_dsi_device_ready(encoder); 503 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 504 bxt_dsi_device_ready(encoder); 505 else 506 vlv_dsi_device_ready(encoder); 507 } 508 509 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) 510 { 511 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 512 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 513 enum port port; 514 515 /* Enter ULPS */ 516 for_each_dsi_port(port, intel_dsi->ports) 517 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 518 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); 519 520 /* Wait for MIPI PHY status bit to unset */ 521 for_each_dsi_port(port, intel_dsi->ports) { 522 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 523 GLK_PHY_STATUS_PORT_READY, 20)) 524 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); 525 } 526 527 /* Wait for Pwr ACK bit to unset */ 528 for_each_dsi_port(port, intel_dsi->ports) { 529 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 530 GLK_MIPIIO_PORT_POWERED, 20)) 531 drm_err(&dev_priv->drm, 532 "MIPI IO Port is not powergated\n"); 533 } 534 } 535 536 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) 537 { 538 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 539 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 540 enum port port; 541 542 /* Put the IO into reset */ 543 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); 544 545 /* Wait for MIPI PHY status bit to unset */ 546 for_each_dsi_port(port, intel_dsi->ports) { 547 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 548 GLK_PHY_STATUS_PORT_READY, 20)) 549 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); 550 } 551 552 /* Clear MIPI mode */ 553 for_each_dsi_port(port, intel_dsi->ports) 554 intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_ENABLE, 0); 555 } 556 557 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) 558 { 559 glk_dsi_enter_low_power_mode(encoder); 560 glk_dsi_disable_mipi_io(encoder); 561 } 562 563 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) 564 { 565 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 566 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 567 enum port port; 568 569 drm_dbg_kms(&dev_priv->drm, "\n"); 570 for_each_dsi_port(port, intel_dsi->ports) { 571 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ 572 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? 573 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); 574 575 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 576 DEVICE_READY | ULPS_STATE_ENTER); 577 usleep_range(2000, 2500); 578 579 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 580 DEVICE_READY | ULPS_STATE_EXIT); 581 usleep_range(2000, 2500); 582 583 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 584 DEVICE_READY | ULPS_STATE_ENTER); 585 usleep_range(2000, 2500); 586 587 /* 588 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI 589 * Port A only. MIPI Port C has no similar bit for checking. 590 */ 591 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) && 592 intel_de_wait_for_clear(dev_priv, port_ctrl, 593 AFE_LATCHOUT, 30)) 594 drm_err(&dev_priv->drm, "DSI LP not going Low\n"); 595 596 /* Disable MIPI PHY transparent latch */ 597 intel_de_rmw(dev_priv, port_ctrl, LP_OUTPUT_HOLD, 0); 598 usleep_range(1000, 1500); 599 600 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); 601 usleep_range(2000, 2500); 602 } 603 } 604 605 static void intel_dsi_port_enable(struct intel_encoder *encoder, 606 const struct intel_crtc_state *crtc_state) 607 { 608 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 609 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 610 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 611 enum port port; 612 613 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 614 u32 temp = intel_dsi->pixel_overlap; 615 616 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 617 for_each_dsi_port(port, intel_dsi->ports) 618 intel_de_rmw(dev_priv, MIPI_CTRL(port), 619 BXT_PIXEL_OVERLAP_CNT_MASK, 620 temp << BXT_PIXEL_OVERLAP_CNT_SHIFT); 621 } else { 622 intel_de_rmw(dev_priv, VLV_CHICKEN_3, 623 PIXEL_OVERLAP_CNT_MASK, 624 temp << PIXEL_OVERLAP_CNT_SHIFT); 625 } 626 } 627 628 for_each_dsi_port(port, intel_dsi->ports) { 629 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? 630 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 631 u32 temp; 632 633 temp = intel_de_read(dev_priv, port_ctrl); 634 635 temp &= ~LANE_CONFIGURATION_MASK; 636 temp &= ~DUAL_LINK_MODE_MASK; 637 638 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { 639 temp |= (intel_dsi->dual_link - 1) 640 << DUAL_LINK_MODE_SHIFT; 641 if (IS_BROXTON(dev_priv)) 642 temp |= LANE_CONFIGURATION_DUAL_LINK_A; 643 else 644 temp |= crtc->pipe ? 645 LANE_CONFIGURATION_DUAL_LINK_B : 646 LANE_CONFIGURATION_DUAL_LINK_A; 647 } 648 649 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) 650 temp |= DITHERING_ENABLE; 651 652 /* assert ip_tg_enable signal */ 653 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); 654 intel_de_posting_read(dev_priv, port_ctrl); 655 } 656 } 657 658 static void intel_dsi_port_disable(struct intel_encoder *encoder) 659 { 660 struct drm_device *dev = encoder->base.dev; 661 struct drm_i915_private *dev_priv = to_i915(dev); 662 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 663 enum port port; 664 665 for_each_dsi_port(port, intel_dsi->ports) { 666 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? 667 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 668 669 /* de-assert ip_tg_enable signal */ 670 intel_de_rmw(dev_priv, port_ctrl, DPI_ENABLE, 0); 671 intel_de_posting_read(dev_priv, port_ctrl); 672 } 673 } 674 675 static void intel_dsi_wait_panel_power_cycle(struct intel_dsi *intel_dsi) 676 { 677 ktime_t panel_power_on_time; 678 s64 panel_power_off_duration; 679 680 panel_power_on_time = ktime_get_boottime(); 681 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, 682 intel_dsi->panel_power_off_time); 683 684 if (panel_power_off_duration < (s64)intel_dsi->panel_pwr_cycle_delay) 685 msleep(intel_dsi->panel_pwr_cycle_delay - panel_power_off_duration); 686 } 687 688 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 689 const struct intel_crtc_state *pipe_config); 690 static void intel_dsi_unprepare(struct intel_encoder *encoder); 691 692 /* 693 * Panel enable/disable sequences from the VBT spec. 694 * 695 * Note the spec has AssertReset / DeassertReset swapped from their 696 * usual naming. We use the normal names to avoid confusion (so below 697 * they are swapped compared to the spec). 698 * 699 * Steps starting with MIPI refer to VBT sequences, note that for v2 700 * VBTs several steps which have a VBT in v2 are expected to be handled 701 * directly by the driver, by directly driving gpios for example. 702 * 703 * v2 video mode seq v3 video mode seq command mode seq 704 * - power on - MIPIPanelPowerOn - power on 705 * - wait t1+t2 - wait t1+t2 706 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin 707 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 708 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds 709 * - MIPITearOn 710 * - MIPIDisplayOn 711 * - turn on DPI - turn on DPI - set pipe to dsr mode 712 * - MIPIDisplayOn - MIPIDisplayOn 713 * - wait t5 - wait t5 714 * - backlight on - MIPIBacklightOn - backlight on 715 * ... ... ... issue mem cmds ... 716 * - backlight off - MIPIBacklightOff - backlight off 717 * - wait t6 - wait t6 718 * - MIPIDisplayOff 719 * - turn off DPI - turn off DPI - disable pipe dsr mode 720 * - MIPITearOff 721 * - MIPIDisplayOff - MIPIDisplayOff 722 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 723 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin 724 * - wait t3 - wait t3 725 * - power off - MIPIPanelPowerOff - power off 726 * - wait t4 - wait t4 727 */ 728 729 /* 730 * DSI port enable has to be done before pipe and plane enable, so we do it in 731 * the pre_enable hook instead of the enable hook. 732 */ 733 static void intel_dsi_pre_enable(struct intel_atomic_state *state, 734 struct intel_encoder *encoder, 735 const struct intel_crtc_state *pipe_config, 736 const struct drm_connector_state *conn_state) 737 { 738 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 739 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 740 struct intel_connector *connector = to_intel_connector(conn_state->connector); 741 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 742 enum pipe pipe = crtc->pipe; 743 enum port port; 744 bool glk_cold_boot = false; 745 746 drm_dbg_kms(&dev_priv->drm, "\n"); 747 748 intel_dsi_wait_panel_power_cycle(intel_dsi); 749 750 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 751 752 /* 753 * The BIOS may leave the PLL in a wonky state where it doesn't 754 * lock. It needs to be fully powered down to fix it. 755 */ 756 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 757 bxt_dsi_pll_disable(encoder); 758 bxt_dsi_pll_enable(encoder, pipe_config); 759 } else { 760 vlv_dsi_pll_disable(encoder); 761 vlv_dsi_pll_enable(encoder, pipe_config); 762 } 763 764 if (IS_BROXTON(dev_priv)) { 765 /* Add MIPI IO reset programming for modeset */ 766 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL); 767 768 /* Power up DSI regulator */ 769 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 770 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); 771 } 772 773 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 774 /* Disable DPOunit clock gating, can stall pipe */ 775 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), 776 0, DPOUNIT_CLOCK_GATE_DISABLE); 777 } 778 779 if (!IS_GEMINILAKE(dev_priv)) 780 intel_dsi_prepare(encoder, pipe_config); 781 782 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 783 784 /* 785 * Give the panel time to power-on and then deassert its reset. 786 * Depending on the VBT MIPI sequences version the deassert-seq 787 * may contain the necessary delay, intel_dsi_msleep() will skip 788 * the delay in that case. If there is no deassert-seq, then an 789 * unconditional msleep is used to give the panel time to power-on. 790 */ 791 if (connector->panel.vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) { 792 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 793 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 794 } else { 795 msleep(intel_dsi->panel_on_delay); 796 } 797 798 if (IS_GEMINILAKE(dev_priv)) { 799 glk_cold_boot = glk_dsi_enable_io(encoder); 800 801 /* Prepare port in cold boot(s3/s4) scenario */ 802 if (glk_cold_boot) 803 intel_dsi_prepare(encoder, pipe_config); 804 } 805 806 /* Put device in ready state (LP-11) */ 807 intel_dsi_device_ready(encoder); 808 809 /* Prepare port in normal boot scenario */ 810 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) 811 intel_dsi_prepare(encoder, pipe_config); 812 813 /* Send initialization commands in LP mode */ 814 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 815 816 /* 817 * Enable port in pre-enable phase itself because as per hw team 818 * recommendation, port should be enabled before plane & pipe 819 */ 820 if (is_cmd_mode(intel_dsi)) { 821 for_each_dsi_port(port, intel_dsi->ports) 822 intel_de_write(dev_priv, 823 MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); 824 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); 825 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 826 } else { 827 msleep(20); /* XXX */ 828 for_each_dsi_port(port, intel_dsi->ports) 829 dpi_send_cmd(intel_dsi, TURN_ON, false, port); 830 intel_dsi_msleep(intel_dsi, 100); 831 832 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 833 834 intel_dsi_port_enable(encoder, pipe_config); 835 } 836 837 intel_backlight_enable(pipe_config, conn_state); 838 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 839 } 840 841 static void bxt_dsi_enable(struct intel_atomic_state *state, 842 struct intel_encoder *encoder, 843 const struct intel_crtc_state *crtc_state, 844 const struct drm_connector_state *conn_state) 845 { 846 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 847 848 intel_crtc_vblank_on(crtc_state); 849 } 850 851 /* 852 * DSI port disable has to be done after pipe and plane disable, so we do it in 853 * the post_disable hook. 854 */ 855 static void intel_dsi_disable(struct intel_atomic_state *state, 856 struct intel_encoder *encoder, 857 const struct intel_crtc_state *old_crtc_state, 858 const struct drm_connector_state *old_conn_state) 859 { 860 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 861 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 862 enum port port; 863 864 drm_dbg_kms(&i915->drm, "\n"); 865 866 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 867 intel_backlight_disable(old_conn_state); 868 869 /* 870 * According to the spec we should send SHUTDOWN before 871 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing 872 * has shown that the v3 sequence works for v2 VBTs too 873 */ 874 if (is_vid_mode(intel_dsi)) { 875 /* Send Shutdown command to the panel in LP mode */ 876 for_each_dsi_port(port, intel_dsi->ports) 877 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); 878 msleep(10); 879 } 880 } 881 882 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 883 { 884 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 885 886 if (IS_GEMINILAKE(dev_priv)) 887 glk_dsi_clear_device_ready(encoder); 888 else 889 vlv_dsi_clear_device_ready(encoder); 890 } 891 892 static void intel_dsi_post_disable(struct intel_atomic_state *state, 893 struct intel_encoder *encoder, 894 const struct intel_crtc_state *old_crtc_state, 895 const struct drm_connector_state *old_conn_state) 896 { 897 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 898 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 899 enum port port; 900 901 drm_dbg_kms(&dev_priv->drm, "\n"); 902 903 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 904 intel_crtc_vblank_off(old_crtc_state); 905 906 skl_scaler_disable(old_crtc_state); 907 } 908 909 if (is_vid_mode(intel_dsi)) { 910 for_each_dsi_port(port, intel_dsi->ports) 911 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 912 913 intel_dsi_port_disable(encoder); 914 usleep_range(2000, 5000); 915 } 916 917 intel_dsi_unprepare(encoder); 918 919 /* 920 * if disable packets are sent before sending shutdown packet then in 921 * some next enable sequence send turn on packet error is observed 922 */ 923 if (is_cmd_mode(intel_dsi)) 924 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF); 925 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 926 927 /* Transition to LP-00 */ 928 intel_dsi_clear_device_ready(encoder); 929 930 if (IS_BROXTON(dev_priv)) { 931 /* Power down DSI regulator to save power */ 932 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 933 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 934 HS_IO_CTRL_SELECT); 935 936 /* Add MIPI IO reset programming for modeset */ 937 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0); 938 } 939 940 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 941 bxt_dsi_pll_disable(encoder); 942 } else { 943 vlv_dsi_pll_disable(encoder); 944 945 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), 946 DPOUNIT_CLOCK_GATE_DISABLE, 0); 947 } 948 949 /* Assert reset */ 950 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 951 952 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); 953 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 954 955 intel_dsi->panel_power_off_time = ktime_get_boottime(); 956 } 957 958 static void intel_dsi_shutdown(struct intel_encoder *encoder) 959 { 960 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 961 962 intel_dsi_wait_panel_power_cycle(intel_dsi); 963 } 964 965 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 966 enum pipe *pipe) 967 { 968 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 969 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 970 intel_wakeref_t wakeref; 971 enum port port; 972 bool active = false; 973 974 drm_dbg_kms(&dev_priv->drm, "\n"); 975 976 wakeref = intel_display_power_get_if_enabled(dev_priv, 977 encoder->power_domain); 978 if (!wakeref) 979 return false; 980 981 /* 982 * On Broxton the PLL needs to be enabled with a valid divider 983 * configuration, otherwise accessing DSI registers will hang the 984 * machine. See BSpec North Display Engine registers/MIPI[BXT]. 985 */ 986 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 987 !bxt_dsi_pll_is_enabled(dev_priv)) 988 goto out_put_power; 989 990 /* XXX: this only works for one DSI output */ 991 for_each_dsi_port(port, intel_dsi->ports) { 992 i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? 993 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 994 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE; 995 996 /* 997 * Due to some hardware limitations on VLV/CHV, the DPI enable 998 * bit in port C control register does not get set. As a 999 * workaround, check pipe B conf instead. 1000 */ 1001 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1002 port == PORT_C) 1003 enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; 1004 1005 /* Try command mode if video mode not enabled */ 1006 if (!enabled) { 1007 u32 tmp = intel_de_read(dev_priv, 1008 MIPI_DSI_FUNC_PRG(port)); 1009 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; 1010 } 1011 1012 if (!enabled) 1013 continue; 1014 1015 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) 1016 continue; 1017 1018 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1019 u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1020 tmp &= BXT_PIPE_SELECT_MASK; 1021 tmp >>= BXT_PIPE_SELECT_SHIFT; 1022 1023 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) 1024 continue; 1025 1026 *pipe = tmp; 1027 } else { 1028 *pipe = port == PORT_A ? PIPE_A : PIPE_B; 1029 } 1030 1031 active = true; 1032 break; 1033 } 1034 1035 out_put_power: 1036 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1037 1038 return active; 1039 } 1040 1041 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, 1042 struct intel_crtc_state *pipe_config) 1043 { 1044 struct drm_device *dev = encoder->base.dev; 1045 struct drm_i915_private *dev_priv = to_i915(dev); 1046 struct drm_display_mode *adjusted_mode = 1047 &pipe_config->hw.adjusted_mode; 1048 struct drm_display_mode *adjusted_mode_sw; 1049 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1050 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1051 unsigned int lane_count = intel_dsi->lane_count; 1052 unsigned int bpp, fmt; 1053 enum port port; 1054 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1055 u16 hfp_sw, hsync_sw, hbp_sw; 1056 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, 1057 crtc_hblank_start_sw, crtc_hblank_end_sw; 1058 1059 /* FIXME: hw readout should not depend on SW state */ 1060 adjusted_mode_sw = &crtc->config->hw.adjusted_mode; 1061 1062 /* 1063 * Atleast one port is active as encoder->get_config called only if 1064 * encoder->get_hw_state() returns true. 1065 */ 1066 for_each_dsi_port(port, intel_dsi->ports) { 1067 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) 1068 break; 1069 } 1070 1071 fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; 1072 bpp = mipi_dsi_pixel_format_to_bpp( 1073 pixel_format_from_register_bits(fmt)); 1074 1075 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); 1076 1077 /* Enable Frame time stamo based scanline reporting */ 1078 pipe_config->mode_flags |= 1079 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 1080 1081 /* In terms of pixels */ 1082 adjusted_mode->crtc_hdisplay = 1083 intel_de_read(dev_priv, 1084 BXT_MIPI_TRANS_HACTIVE(port)); 1085 adjusted_mode->crtc_vdisplay = 1086 intel_de_read(dev_priv, 1087 BXT_MIPI_TRANS_VACTIVE(port)); 1088 adjusted_mode->crtc_vtotal = 1089 intel_de_read(dev_priv, 1090 BXT_MIPI_TRANS_VTOTAL(port)); 1091 1092 hactive = adjusted_mode->crtc_hdisplay; 1093 hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); 1094 1095 /* 1096 * Meaningful for video mode non-burst sync pulse mode only, 1097 * can be zero for non-burst sync events and burst modes 1098 */ 1099 hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); 1100 hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); 1101 1102 /* harizontal values are in terms of high speed byte clock */ 1103 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, 1104 intel_dsi->burst_mode_ratio); 1105 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, 1106 intel_dsi->burst_mode_ratio); 1107 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, 1108 intel_dsi->burst_mode_ratio); 1109 1110 if (intel_dsi->dual_link) { 1111 hfp *= 2; 1112 hsync *= 2; 1113 hbp *= 2; 1114 } 1115 1116 /* vertical values are in terms of lines */ 1117 vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); 1118 vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); 1119 vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port)); 1120 1121 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; 1122 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; 1123 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; 1124 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1125 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1126 1127 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; 1128 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; 1129 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1130 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1131 1132 /* 1133 * In BXT DSI there is no regs programmed with few horizontal timings 1134 * in Pixels but txbyteclkhs.. So retrieval process adds some 1135 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. 1136 * Actually here for the given adjusted_mode, we are calculating the 1137 * value programmed to the port and then back to the horizontal timing 1138 * param in pixels. This is the expected value, including roundup errors 1139 * And if that is same as retrieved value from port, then 1140 * (HW state) adjusted_mode's horizontal timings are corrected to 1141 * match with SW state to nullify the errors. 1142 */ 1143 /* Calculating the value programmed to the Port register */ 1144 hfp_sw = adjusted_mode_sw->crtc_hsync_start - 1145 adjusted_mode_sw->crtc_hdisplay; 1146 hsync_sw = adjusted_mode_sw->crtc_hsync_end - 1147 adjusted_mode_sw->crtc_hsync_start; 1148 hbp_sw = adjusted_mode_sw->crtc_htotal - 1149 adjusted_mode_sw->crtc_hsync_end; 1150 1151 if (intel_dsi->dual_link) { 1152 hfp_sw /= 2; 1153 hsync_sw /= 2; 1154 hbp_sw /= 2; 1155 } 1156 1157 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, 1158 intel_dsi->burst_mode_ratio); 1159 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, 1160 intel_dsi->burst_mode_ratio); 1161 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, 1162 intel_dsi->burst_mode_ratio); 1163 1164 /* Reverse calculating the adjusted mode parameters from port reg vals*/ 1165 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, 1166 intel_dsi->burst_mode_ratio); 1167 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, 1168 intel_dsi->burst_mode_ratio); 1169 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, 1170 intel_dsi->burst_mode_ratio); 1171 1172 if (intel_dsi->dual_link) { 1173 hfp_sw *= 2; 1174 hsync_sw *= 2; 1175 hbp_sw *= 2; 1176 } 1177 1178 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + 1179 hsync_sw + hbp_sw; 1180 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; 1181 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; 1182 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; 1183 crtc_hblank_end_sw = crtc_htotal_sw; 1184 1185 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) 1186 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; 1187 1188 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) 1189 adjusted_mode->crtc_hsync_start = 1190 adjusted_mode_sw->crtc_hsync_start; 1191 1192 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) 1193 adjusted_mode->crtc_hsync_end = 1194 adjusted_mode_sw->crtc_hsync_end; 1195 1196 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) 1197 adjusted_mode->crtc_hblank_start = 1198 adjusted_mode_sw->crtc_hblank_start; 1199 1200 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) 1201 adjusted_mode->crtc_hblank_end = 1202 adjusted_mode_sw->crtc_hblank_end; 1203 } 1204 1205 static void intel_dsi_get_config(struct intel_encoder *encoder, 1206 struct intel_crtc_state *pipe_config) 1207 { 1208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1209 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1210 u32 pclk; 1211 1212 drm_dbg_kms(&dev_priv->drm, "\n"); 1213 1214 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1215 1216 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1217 bxt_dsi_get_pipe_config(encoder, pipe_config); 1218 pclk = bxt_dsi_get_pclk(encoder, pipe_config); 1219 } else { 1220 pclk = vlv_dsi_get_pclk(encoder, pipe_config); 1221 } 1222 1223 pipe_config->port_clock = pclk; 1224 1225 /* FIXME definitely not right for burst/cmd mode/pixel overlap */ 1226 pipe_config->hw.adjusted_mode.crtc_clock = pclk; 1227 if (intel_dsi->dual_link) 1228 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1229 } 1230 1231 /* return txclkesc cycles in terms of divider and duration in us */ 1232 static u16 txclkesc(u32 divider, unsigned int us) 1233 { 1234 switch (divider) { 1235 case ESCAPE_CLOCK_DIVIDER_1: 1236 default: 1237 return 20 * us; 1238 case ESCAPE_CLOCK_DIVIDER_2: 1239 return 10 * us; 1240 case ESCAPE_CLOCK_DIVIDER_4: 1241 return 5 * us; 1242 } 1243 } 1244 1245 static void set_dsi_timings(struct drm_encoder *encoder, 1246 const struct drm_display_mode *adjusted_mode) 1247 { 1248 struct drm_device *dev = encoder->dev; 1249 struct drm_i915_private *dev_priv = to_i915(dev); 1250 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1251 enum port port; 1252 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1253 unsigned int lane_count = intel_dsi->lane_count; 1254 1255 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1256 1257 hactive = adjusted_mode->crtc_hdisplay; 1258 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; 1259 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1260 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; 1261 1262 if (intel_dsi->dual_link) { 1263 hactive /= 2; 1264 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1265 hactive += intel_dsi->pixel_overlap; 1266 hfp /= 2; 1267 hsync /= 2; 1268 hbp /= 2; 1269 } 1270 1271 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; 1272 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; 1273 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; 1274 1275 /* horizontal values are in terms of high speed byte clock */ 1276 hactive = txbyteclkhs(hactive, bpp, lane_count, 1277 intel_dsi->burst_mode_ratio); 1278 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1279 hsync = txbyteclkhs(hsync, bpp, lane_count, 1280 intel_dsi->burst_mode_ratio); 1281 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1282 1283 for_each_dsi_port(port, intel_dsi->ports) { 1284 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1285 /* 1286 * Program hdisplay and vdisplay on MIPI transcoder. 1287 * This is different from calculated hactive and 1288 * vactive, as they are calculated per channel basis, 1289 * whereas these values should be based on resolution. 1290 */ 1291 intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), 1292 adjusted_mode->crtc_hdisplay); 1293 intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), 1294 adjusted_mode->crtc_vdisplay); 1295 intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), 1296 adjusted_mode->crtc_vtotal); 1297 } 1298 1299 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), 1300 hactive); 1301 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); 1302 1303 /* meaningful for video mode non-burst sync pulse mode only, 1304 * can be zero for non-burst sync events and burst modes */ 1305 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), 1306 hsync); 1307 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); 1308 1309 /* vertical values are in terms of lines */ 1310 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); 1311 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), 1312 vsync); 1313 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); 1314 } 1315 } 1316 1317 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) 1318 { 1319 switch (fmt) { 1320 case MIPI_DSI_FMT_RGB888: 1321 return VID_MODE_FORMAT_RGB888; 1322 case MIPI_DSI_FMT_RGB666: 1323 return VID_MODE_FORMAT_RGB666; 1324 case MIPI_DSI_FMT_RGB666_PACKED: 1325 return VID_MODE_FORMAT_RGB666_PACKED; 1326 case MIPI_DSI_FMT_RGB565: 1327 return VID_MODE_FORMAT_RGB565; 1328 default: 1329 MISSING_CASE(fmt); 1330 return VID_MODE_FORMAT_RGB666; 1331 } 1332 } 1333 1334 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 1335 const struct intel_crtc_state *pipe_config) 1336 { 1337 struct drm_encoder *encoder = &intel_encoder->base; 1338 struct drm_device *dev = encoder->dev; 1339 struct drm_i915_private *dev_priv = to_i915(dev); 1340 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1341 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1342 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1343 enum port port; 1344 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1345 u32 val, tmp; 1346 u16 mode_hdisplay; 1347 1348 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe)); 1349 1350 mode_hdisplay = adjusted_mode->crtc_hdisplay; 1351 1352 if (intel_dsi->dual_link) { 1353 mode_hdisplay /= 2; 1354 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1355 mode_hdisplay += intel_dsi->pixel_overlap; 1356 } 1357 1358 for_each_dsi_port(port, intel_dsi->ports) { 1359 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1360 /* 1361 * escape clock divider, 20MHz, shared for A and C. 1362 * device ready must be off when doing this! txclkesc? 1363 */ 1364 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 1365 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 1366 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), 1367 tmp | ESCAPE_CLOCK_DIVIDER_1); 1368 1369 /* read request priority is per pipe */ 1370 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1371 tmp &= ~READ_REQUEST_PRIORITY_MASK; 1372 intel_de_write(dev_priv, MIPI_CTRL(port), 1373 tmp | READ_REQUEST_PRIORITY_HIGH); 1374 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1375 enum pipe pipe = crtc->pipe; 1376 1377 intel_de_rmw(dev_priv, MIPI_CTRL(port), 1378 BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe)); 1379 } 1380 1381 /* XXX: why here, why like this? handling in irq handler?! */ 1382 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); 1383 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); 1384 1385 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), 1386 intel_dsi->dphy_reg); 1387 1388 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), 1389 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); 1390 } 1391 1392 set_dsi_timings(encoder, adjusted_mode); 1393 1394 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; 1395 if (is_cmd_mode(intel_dsi)) { 1396 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; 1397 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ 1398 } else { 1399 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; 1400 val |= pixel_format_to_reg(intel_dsi->pixel_format); 1401 } 1402 1403 tmp = 0; 1404 if (intel_dsi->eotp_pkt == 0) 1405 tmp |= EOT_DISABLE; 1406 if (intel_dsi->clock_stop) 1407 tmp |= CLOCKSTOP; 1408 1409 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1410 tmp |= BXT_DPHY_DEFEATURE_EN; 1411 if (!is_cmd_mode(intel_dsi)) 1412 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; 1413 } 1414 1415 for_each_dsi_port(port, intel_dsi->ports) { 1416 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); 1417 1418 /* timeouts for recovery. one frame IIUC. if counter expires, 1419 * EOT and stop state. */ 1420 1421 /* 1422 * In burst mode, value greater than one DPI line Time in byte 1423 * clock (txbyteclkhs) To timeout this timer 1+ of the above 1424 * said value is recommended. 1425 * 1426 * In non-burst mode, Value greater than one DPI frame time in 1427 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1428 * said value is recommended. 1429 * 1430 * In DBI only mode, value greater than one DBI frame time in 1431 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1432 * said value is recommended. 1433 */ 1434 1435 if (is_vid_mode(intel_dsi) && 1436 intel_dsi->video_mode == BURST_MODE) { 1437 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), 1438 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1439 } else { 1440 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), 1441 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1442 } 1443 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), 1444 intel_dsi->lp_rx_timeout); 1445 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), 1446 intel_dsi->turn_arnd_val); 1447 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), 1448 intel_dsi->rst_timer_val); 1449 1450 /* dphy stuff */ 1451 1452 /* in terms of low power clock */ 1453 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), 1454 txclkesc(intel_dsi->escape_clk_div, 100)); 1455 1456 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1457 !intel_dsi->dual_link) { 1458 /* 1459 * BXT spec says write MIPI_INIT_COUNT for 1460 * both the ports, even if only one is 1461 * getting used. So write the other port 1462 * if not in dual link mode. 1463 */ 1464 intel_de_write(dev_priv, 1465 MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A), 1466 intel_dsi->init_count); 1467 } 1468 1469 /* recovery disables */ 1470 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); 1471 1472 /* in terms of low power clock */ 1473 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), 1474 intel_dsi->init_count); 1475 1476 /* in terms of txbyteclkhs. actual high to low switch + 1477 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. 1478 * 1479 * XXX: write MIPI_STOP_STATE_STALL? 1480 */ 1481 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), 1482 intel_dsi->hs_to_lp_count); 1483 1484 /* XXX: low power clock equivalence in terms of byte clock. 1485 * the number of byte clocks occupied in one low power clock. 1486 * based on txbyteclkhs and txclkesc. 1487 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL 1488 * ) / 105.??? 1489 */ 1490 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), 1491 intel_dsi->lp_byte_clk); 1492 1493 if (IS_GEMINILAKE(dev_priv)) { 1494 intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), 1495 intel_dsi->lp_byte_clk); 1496 /* Shadow of DPHY reg */ 1497 intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), 1498 intel_dsi->dphy_reg); 1499 } 1500 1501 /* the bw essential for transmitting 16 long packets containing 1502 * 252 bytes meant for dcs write memory command is programmed in 1503 * this register in terms of byte clocks. based on dsi transfer 1504 * rate and the number of lanes configured the time taken to 1505 * transmit 16 long packets in a dsi stream varies. */ 1506 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), 1507 intel_dsi->bw_timer); 1508 1509 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), 1510 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); 1511 1512 if (is_vid_mode(intel_dsi)) { 1513 u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG; 1514 1515 /* 1516 * Some panels might have resolution which is not a 1517 * multiple of 64 like 1366 x 768. Enable RANDOM 1518 * resolution support for such panels by default. 1519 */ 1520 fmt |= RANDOM_DPI_DISPLAY_RESOLUTION; 1521 1522 switch (intel_dsi->video_mode) { 1523 default: 1524 MISSING_CASE(intel_dsi->video_mode); 1525 fallthrough; 1526 case NON_BURST_SYNC_EVENTS: 1527 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS; 1528 break; 1529 case NON_BURST_SYNC_PULSE: 1530 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE; 1531 break; 1532 case BURST_MODE: 1533 fmt |= VIDEO_MODE_BURST; 1534 break; 1535 } 1536 1537 intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt); 1538 } 1539 } 1540 } 1541 1542 static void intel_dsi_unprepare(struct intel_encoder *encoder) 1543 { 1544 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1545 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1546 enum port port; 1547 1548 if (IS_GEMINILAKE(dev_priv)) 1549 return; 1550 1551 for_each_dsi_port(port, intel_dsi->ports) { 1552 /* Panel commands can be sent when clock is in LP11 */ 1553 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); 1554 1555 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1556 bxt_dsi_reset_clocks(encoder, port); 1557 else 1558 vlv_dsi_reset_clocks(encoder, port); 1559 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); 1560 1561 intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(port), VID_MODE_FORMAT_MASK, 0); 1562 1563 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); 1564 } 1565 } 1566 1567 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) 1568 { 1569 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1570 1571 intel_dsi_vbt_gpio_cleanup(intel_dsi); 1572 intel_encoder_destroy(encoder); 1573 } 1574 1575 static const struct drm_encoder_funcs intel_dsi_funcs = { 1576 .destroy = intel_dsi_encoder_destroy, 1577 }; 1578 1579 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 1580 .get_modes = intel_dsi_get_modes, 1581 .mode_valid = intel_dsi_mode_valid, 1582 .atomic_check = intel_digital_connector_atomic_check, 1583 }; 1584 1585 static const struct drm_connector_funcs intel_dsi_connector_funcs = { 1586 .detect = intel_panel_detect, 1587 .late_register = intel_connector_register, 1588 .early_unregister = intel_connector_unregister, 1589 .destroy = intel_connector_destroy, 1590 .fill_modes = drm_helper_probe_single_connector_modes, 1591 .atomic_get_property = intel_digital_connector_atomic_get_property, 1592 .atomic_set_property = intel_digital_connector_atomic_set_property, 1593 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1594 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1595 }; 1596 1597 static void vlv_dsi_add_properties(struct intel_connector *connector) 1598 { 1599 const struct drm_display_mode *fixed_mode = 1600 intel_panel_preferred_fixed_mode(connector); 1601 1602 intel_attach_scaling_mode_property(&connector->base); 1603 1604 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1605 intel_dsi_get_panel_orientation(connector), 1606 fixed_mode->hdisplay, 1607 fixed_mode->vdisplay); 1608 } 1609 1610 #define NS_KHZ_RATIO 1000000 1611 1612 #define PREPARE_CNT_MAX 0x3F 1613 #define EXIT_ZERO_CNT_MAX 0x3F 1614 #define CLK_ZERO_CNT_MAX 0xFF 1615 #define TRAIL_CNT_MAX 0x1F 1616 1617 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) 1618 { 1619 struct drm_device *dev = intel_dsi->base.base.dev; 1620 struct drm_i915_private *dev_priv = to_i915(dev); 1621 struct intel_connector *connector = intel_dsi->attached_connector; 1622 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1623 u32 tlpx_ns, extra_byte_count, tlpx_ui; 1624 u32 ui_num, ui_den; 1625 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1626 u32 ths_prepare_ns, tclk_trail_ns; 1627 u32 tclk_prepare_clkzero, ths_prepare_hszero; 1628 u32 lp_to_hs_switch, hs_to_lp_switch; 1629 u32 mul; 1630 1631 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1632 1633 switch (intel_dsi->lane_count) { 1634 case 1: 1635 case 2: 1636 extra_byte_count = 2; 1637 break; 1638 case 3: 1639 extra_byte_count = 4; 1640 break; 1641 case 4: 1642 default: 1643 extra_byte_count = 3; 1644 break; 1645 } 1646 1647 /* in Kbps */ 1648 ui_num = NS_KHZ_RATIO; 1649 ui_den = intel_dsi_bitrate(intel_dsi); 1650 1651 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; 1652 ths_prepare_hszero = mipi_config->ths_prepare_hszero; 1653 1654 /* 1655 * B060 1656 * LP byte clock = TLPX/ (8UI) 1657 */ 1658 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); 1659 1660 /* DDR clock period = 2 * UI 1661 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ) 1662 * UI(nsec) = 10^6 / bitrate 1663 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate 1664 * DDR clock count = ns_value / DDR clock period 1665 * 1666 * For GEMINILAKE dphy_param_reg will be programmed in terms of 1667 * HS byte clock count for other platform in HS ddr clock count 1668 */ 1669 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; 1670 ths_prepare_ns = max(mipi_config->ths_prepare, 1671 mipi_config->tclk_prepare); 1672 1673 /* prepare count */ 1674 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul); 1675 1676 if (prepare_cnt > PREPARE_CNT_MAX) { 1677 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", 1678 prepare_cnt); 1679 prepare_cnt = PREPARE_CNT_MAX; 1680 } 1681 1682 /* exit zero count */ 1683 exit_zero_cnt = DIV_ROUND_UP( 1684 (ths_prepare_hszero - ths_prepare_ns) * ui_den, 1685 ui_num * mul 1686 ); 1687 1688 /* 1689 * Exit zero is unified val ths_zero and ths_exit 1690 * minimum value for ths_exit = 110ns 1691 * min (exit_zero_cnt * 2) = 110/UI 1692 * exit_zero_cnt = 55/UI 1693 */ 1694 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num) 1695 exit_zero_cnt += 1; 1696 1697 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) { 1698 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", 1699 exit_zero_cnt); 1700 exit_zero_cnt = EXIT_ZERO_CNT_MAX; 1701 } 1702 1703 /* clk zero count */ 1704 clk_zero_cnt = DIV_ROUND_UP( 1705 (tclk_prepare_clkzero - ths_prepare_ns) 1706 * ui_den, ui_num * mul); 1707 1708 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) { 1709 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", 1710 clk_zero_cnt); 1711 clk_zero_cnt = CLK_ZERO_CNT_MAX; 1712 } 1713 1714 /* trail count */ 1715 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1716 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul); 1717 1718 if (trail_cnt > TRAIL_CNT_MAX) { 1719 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", 1720 trail_cnt); 1721 trail_cnt = TRAIL_CNT_MAX; 1722 } 1723 1724 /* B080 */ 1725 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | 1726 clk_zero_cnt << 8 | prepare_cnt; 1727 1728 /* 1729 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT * 1730 * mul + 10UI + Extra Byte Count 1731 * 1732 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count 1733 * Extra Byte Count is calculated according to number of lanes. 1734 * High Low Switch Count is the Max of LP to HS and 1735 * HS to LP switch count 1736 * 1737 */ 1738 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); 1739 1740 /* B044 */ 1741 /* FIXME: 1742 * The comment above does not match with the code */ 1743 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul + 1744 exit_zero_cnt * mul + 10, 8); 1745 1746 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); 1747 1748 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); 1749 intel_dsi->hs_to_lp_count += extra_byte_count; 1750 1751 /* B088 */ 1752 /* LP -> HS for clock lanes 1753 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + 1754 * extra byte count 1755 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * 1756 * 2(in UI) + extra byte count 1757 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / 1758 * 8 + extra byte count 1759 */ 1760 intel_dsi->clk_lp_to_hs_count = 1761 DIV_ROUND_UP( 1762 4 * tlpx_ui + prepare_cnt * 2 + 1763 clk_zero_cnt * 2, 1764 8); 1765 1766 intel_dsi->clk_lp_to_hs_count += extra_byte_count; 1767 1768 /* HS->LP for Clock Lanes 1769 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + 1770 * Extra byte count 1771 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count 1772 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + 1773 * Extra byte count 1774 */ 1775 intel_dsi->clk_hs_to_lp_count = 1776 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, 1777 8); 1778 intel_dsi->clk_hs_to_lp_count += extra_byte_count; 1779 1780 intel_dsi_log_params(intel_dsi); 1781 } 1782 1783 void vlv_dsi_init(struct drm_i915_private *dev_priv) 1784 { 1785 struct intel_dsi *intel_dsi; 1786 struct intel_encoder *intel_encoder; 1787 struct drm_encoder *encoder; 1788 struct intel_connector *intel_connector; 1789 struct drm_connector *connector; 1790 struct drm_display_mode *current_mode; 1791 enum port port; 1792 enum pipe pipe; 1793 1794 drm_dbg_kms(&dev_priv->drm, "\n"); 1795 1796 /* There is no detection method for MIPI so rely on VBT */ 1797 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1798 return; 1799 1800 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1801 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE; 1802 else 1803 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE; 1804 1805 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1806 if (!intel_dsi) 1807 return; 1808 1809 intel_connector = intel_connector_alloc(); 1810 if (!intel_connector) { 1811 kfree(intel_dsi); 1812 return; 1813 } 1814 1815 intel_encoder = &intel_dsi->base; 1816 encoder = &intel_encoder->base; 1817 intel_dsi->attached_connector = intel_connector; 1818 1819 connector = &intel_connector->base; 1820 1821 drm_encoder_init(&dev_priv->drm, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, 1822 "DSI %c", port_name(port)); 1823 1824 intel_encoder->compute_config = intel_dsi_compute_config; 1825 intel_encoder->pre_enable = intel_dsi_pre_enable; 1826 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1827 intel_encoder->enable = bxt_dsi_enable; 1828 intel_encoder->disable = intel_dsi_disable; 1829 intel_encoder->post_disable = intel_dsi_post_disable; 1830 intel_encoder->get_hw_state = intel_dsi_get_hw_state; 1831 intel_encoder->get_config = intel_dsi_get_config; 1832 intel_encoder->update_pipe = intel_backlight_update; 1833 intel_encoder->shutdown = intel_dsi_shutdown; 1834 1835 intel_connector->get_hw_state = intel_connector_get_hw_state; 1836 1837 intel_encoder->port = port; 1838 intel_encoder->type = INTEL_OUTPUT_DSI; 1839 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1840 intel_encoder->cloneable = 0; 1841 1842 /* 1843 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI 1844 * port C. BXT isn't limited like this. 1845 */ 1846 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1847 intel_encoder->pipe_mask = ~0; 1848 else if (port == PORT_A) 1849 intel_encoder->pipe_mask = BIT(PIPE_A); 1850 else 1851 intel_encoder->pipe_mask = BIT(PIPE_B); 1852 1853 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1854 1855 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL, NULL); 1856 1857 if (intel_connector->panel.vbt.dsi.config->dual_link) 1858 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); 1859 else 1860 intel_dsi->ports = BIT(port); 1861 1862 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 1863 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 1864 1865 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 1866 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 1867 1868 /* Create a DSI host (and a device) for each port. */ 1869 for_each_dsi_port(port, intel_dsi->ports) { 1870 struct intel_dsi_host *host; 1871 1872 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops, 1873 port); 1874 if (!host) 1875 goto err; 1876 1877 intel_dsi->dsi_hosts[port] = host; 1878 } 1879 1880 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1881 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 1882 goto err; 1883 } 1884 1885 /* Use clock read-back from current hw-state for fastboot */ 1886 current_mode = intel_encoder_current_mode(intel_encoder); 1887 if (current_mode) { 1888 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", 1889 intel_dsi->pclk, current_mode->clock); 1890 if (intel_fuzzy_clock_check(intel_dsi->pclk, 1891 current_mode->clock)) { 1892 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); 1893 intel_dsi->pclk = current_mode->clock; 1894 } 1895 1896 kfree(current_mode); 1897 } 1898 1899 vlv_dphy_param_init(intel_dsi); 1900 1901 intel_dsi_vbt_gpio_init(intel_dsi, 1902 intel_dsi_get_hw_state(intel_encoder, &pipe)); 1903 1904 drm_connector_init(&dev_priv->drm, connector, &intel_dsi_connector_funcs, 1905 DRM_MODE_CONNECTOR_DSI); 1906 1907 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); 1908 1909 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ 1910 1911 intel_connector_attach_encoder(intel_connector, intel_encoder); 1912 1913 mutex_lock(&dev_priv->drm.mode_config.mutex); 1914 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 1915 mutex_unlock(&dev_priv->drm.mode_config.mutex); 1916 1917 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 1918 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); 1919 goto err_cleanup_connector; 1920 } 1921 1922 intel_panel_init(intel_connector, NULL); 1923 1924 intel_backlight_setup(intel_connector, INVALID_PIPE); 1925 1926 vlv_dsi_add_properties(intel_connector); 1927 1928 return; 1929 1930 err_cleanup_connector: 1931 drm_connector_cleanup(&intel_connector->base); 1932 err: 1933 drm_encoder_cleanup(&intel_encoder->base); 1934 kfree(intel_dsi); 1935 kfree(intel_connector); 1936 } 1937