1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Jani Nikula <jani.nikula@intel.com> 24 */ 25 26 #include <linux/slab.h> 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_crtc.h> 30 #include <drm/drm_edid.h> 31 #include <drm/drm_mipi_dsi.h> 32 33 #include "i915_drv.h" 34 #include "i915_reg.h" 35 #include "intel_atomic.h" 36 #include "intel_backlight.h" 37 #include "intel_connector.h" 38 #include "intel_crtc.h" 39 #include "intel_de.h" 40 #include "intel_display_types.h" 41 #include "intel_dsi.h" 42 #include "intel_dsi_vbt.h" 43 #include "intel_fifo_underrun.h" 44 #include "intel_panel.h" 45 #include "skl_scaler.h" 46 #include "vlv_dsi.h" 47 #include "vlv_dsi_pll.h" 48 #include "vlv_dsi_regs.h" 49 #include "vlv_sideband.h" 50 51 /* return pixels in terms of txbyteclkhs */ 52 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, 53 u16 burst_mode_ratio) 54 { 55 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, 56 8 * 100), lane_count); 57 } 58 59 /* return pixels equvalent to txbyteclkhs */ 60 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, 61 u16 burst_mode_ratio) 62 { 63 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), 64 (bpp * burst_mode_ratio)); 65 } 66 67 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 68 { 69 /* It just so happens the VBT matches register contents. */ 70 switch (fmt) { 71 case VID_MODE_FORMAT_RGB888: 72 return MIPI_DSI_FMT_RGB888; 73 case VID_MODE_FORMAT_RGB666: 74 return MIPI_DSI_FMT_RGB666; 75 case VID_MODE_FORMAT_RGB666_PACKED: 76 return MIPI_DSI_FMT_RGB666_PACKED; 77 case VID_MODE_FORMAT_RGB565: 78 return MIPI_DSI_FMT_RGB565; 79 default: 80 MISSING_CASE(fmt); 81 return MIPI_DSI_FMT_RGB666; 82 } 83 } 84 85 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) 86 { 87 struct drm_encoder *encoder = &intel_dsi->base.base; 88 struct drm_device *dev = encoder->dev; 89 struct drm_i915_private *dev_priv = to_i915(dev); 90 u32 mask; 91 92 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | 93 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; 94 95 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), 96 mask, 100)) 97 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); 98 } 99 100 static void write_data(struct drm_i915_private *dev_priv, 101 i915_reg_t reg, 102 const u8 *data, u32 len) 103 { 104 u32 i, j; 105 106 for (i = 0; i < len; i += 4) { 107 u32 val = 0; 108 109 for (j = 0; j < min_t(u32, len - i, 4); j++) 110 val |= *data++ << 8 * j; 111 112 intel_de_write(dev_priv, reg, val); 113 } 114 } 115 116 static void read_data(struct drm_i915_private *dev_priv, 117 i915_reg_t reg, 118 u8 *data, u32 len) 119 { 120 u32 i, j; 121 122 for (i = 0; i < len; i += 4) { 123 u32 val = intel_de_read(dev_priv, reg); 124 125 for (j = 0; j < min_t(u32, len - i, 4); j++) 126 *data++ = val >> 8 * j; 127 } 128 } 129 130 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, 131 const struct mipi_dsi_msg *msg) 132 { 133 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 134 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; 135 struct drm_i915_private *dev_priv = to_i915(dev); 136 enum port port = intel_dsi_host->port; 137 struct mipi_dsi_packet packet; 138 ssize_t ret; 139 const u8 *header, *data; 140 i915_reg_t data_reg, ctrl_reg; 141 u32 data_mask, ctrl_mask; 142 143 ret = mipi_dsi_create_packet(&packet, msg); 144 if (ret < 0) 145 return ret; 146 147 header = packet.header; 148 data = packet.payload; 149 150 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 151 data_reg = MIPI_LP_GEN_DATA(port); 152 data_mask = LP_DATA_FIFO_FULL; 153 ctrl_reg = MIPI_LP_GEN_CTRL(port); 154 ctrl_mask = LP_CTRL_FIFO_FULL; 155 } else { 156 data_reg = MIPI_HS_GEN_DATA(port); 157 data_mask = HS_DATA_FIFO_FULL; 158 ctrl_reg = MIPI_HS_GEN_CTRL(port); 159 ctrl_mask = HS_CTRL_FIFO_FULL; 160 } 161 162 /* note: this is never true for reads */ 163 if (packet.payload_length) { 164 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 165 data_mask, 50)) 166 drm_err(&dev_priv->drm, 167 "Timeout waiting for HS/LP DATA FIFO !full\n"); 168 169 write_data(dev_priv, data_reg, packet.payload, 170 packet.payload_length); 171 } 172 173 if (msg->rx_len) { 174 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 175 GEN_READ_DATA_AVAIL); 176 } 177 178 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 179 ctrl_mask, 50)) { 180 drm_err(&dev_priv->drm, 181 "Timeout waiting for HS/LP CTRL FIFO !full\n"); 182 } 183 184 intel_de_write(dev_priv, ctrl_reg, 185 header[2] << 16 | header[1] << 8 | header[0]); 186 187 /* ->rx_len is set only for reads */ 188 if (msg->rx_len) { 189 data_mask = GEN_READ_DATA_AVAIL; 190 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), 191 data_mask, 50)) 192 drm_err(&dev_priv->drm, 193 "Timeout waiting for read data.\n"); 194 195 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); 196 } 197 198 /* XXX: fix for reads and writes */ 199 return 4 + packet.payload_length; 200 } 201 202 static int intel_dsi_host_attach(struct mipi_dsi_host *host, 203 struct mipi_dsi_device *dsi) 204 { 205 return 0; 206 } 207 208 static int intel_dsi_host_detach(struct mipi_dsi_host *host, 209 struct mipi_dsi_device *dsi) 210 { 211 return 0; 212 } 213 214 static const struct mipi_dsi_host_ops intel_dsi_host_ops = { 215 .attach = intel_dsi_host_attach, 216 .detach = intel_dsi_host_detach, 217 .transfer = intel_dsi_host_transfer, 218 }; 219 220 /* 221 * send a video mode command 222 * 223 * XXX: commands with data in MIPI_DPI_DATA? 224 */ 225 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, 226 enum port port) 227 { 228 struct drm_encoder *encoder = &intel_dsi->base.base; 229 struct drm_device *dev = encoder->dev; 230 struct drm_i915_private *dev_priv = to_i915(dev); 231 u32 mask; 232 233 /* XXX: pipe, hs */ 234 if (hs) 235 cmd &= ~DPI_LP_MODE; 236 else 237 cmd |= DPI_LP_MODE; 238 239 /* clear bit */ 240 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); 241 242 /* XXX: old code skips write if control unchanged */ 243 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) 244 drm_dbg_kms(&dev_priv->drm, 245 "Same special packet %02x twice in a row.\n", cmd); 246 247 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); 248 249 mask = SPL_PKT_SENT_INTERRUPT; 250 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) 251 drm_err(&dev_priv->drm, 252 "Video mode command 0x%08x send failed.\n", cmd); 253 254 return 0; 255 } 256 257 static void band_gap_reset(struct drm_i915_private *dev_priv) 258 { 259 vlv_flisdsi_get(dev_priv); 260 261 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); 262 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); 263 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); 264 udelay(150); 265 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); 266 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); 267 268 vlv_flisdsi_put(dev_priv); 269 } 270 271 static int intel_dsi_compute_config(struct intel_encoder *encoder, 272 struct intel_crtc_state *pipe_config, 273 struct drm_connector_state *conn_state) 274 { 275 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 276 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 277 base); 278 struct intel_connector *intel_connector = intel_dsi->attached_connector; 279 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 280 int ret; 281 282 drm_dbg_kms(&dev_priv->drm, "\n"); 283 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 284 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 285 286 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 287 if (ret) 288 return ret; 289 290 ret = intel_panel_fitting(pipe_config, conn_state); 291 if (ret) 292 return ret; 293 294 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 295 return -EINVAL; 296 297 /* DSI uses short packets for sync events, so clear mode flags for DSI */ 298 adjusted_mode->flags = 0; 299 300 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 301 pipe_config->pipe_bpp = 24; 302 else 303 pipe_config->pipe_bpp = 18; 304 305 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 306 /* Enable Frame time stamp based scanline reporting */ 307 pipe_config->mode_flags |= 308 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 309 310 /* Dual link goes to DSI transcoder A. */ 311 if (intel_dsi->ports == BIT(PORT_C)) 312 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; 313 else 314 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; 315 316 ret = bxt_dsi_pll_compute(encoder, pipe_config); 317 if (ret) 318 return -EINVAL; 319 } else { 320 ret = vlv_dsi_pll_compute(encoder, pipe_config); 321 if (ret) 322 return -EINVAL; 323 } 324 325 pipe_config->clock_set = true; 326 327 return 0; 328 } 329 330 static bool glk_dsi_enable_io(struct intel_encoder *encoder) 331 { 332 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 333 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 334 enum port port; 335 bool cold_boot = false; 336 337 /* Set the MIPI mode 338 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. 339 * Power ON MIPI IO first and then write into IO reset and LP wake bits 340 */ 341 for_each_dsi_port(port, intel_dsi->ports) 342 intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE); 343 344 /* Put the IO into reset */ 345 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); 346 347 /* Program LP Wake */ 348 for_each_dsi_port(port, intel_dsi->ports) { 349 u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 350 intel_de_rmw(dev_priv, MIPI_CTRL(port), 351 GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0); 352 } 353 354 /* Wait for Pwr ACK */ 355 for_each_dsi_port(port, intel_dsi->ports) { 356 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 357 GLK_MIPIIO_PORT_POWERED, 20)) 358 drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); 359 } 360 361 /* Check for cold boot scenario */ 362 for_each_dsi_port(port, intel_dsi->ports) { 363 cold_boot |= 364 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); 365 } 366 367 return cold_boot; 368 } 369 370 static void glk_dsi_device_ready(struct intel_encoder *encoder) 371 { 372 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 373 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 374 enum port port; 375 376 /* Wait for MIPI PHY status bit to set */ 377 for_each_dsi_port(port, intel_dsi->ports) { 378 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 379 GLK_PHY_STATUS_PORT_READY, 20)) 380 drm_err(&dev_priv->drm, "PHY is not ON\n"); 381 } 382 383 /* Get IO out of reset */ 384 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); 385 386 /* Get IO out of Low power state*/ 387 for_each_dsi_port(port, intel_dsi->ports) { 388 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { 389 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 390 ULPS_STATE_MASK, DEVICE_READY); 391 usleep_range(10, 15); 392 } else { 393 /* Enter ULPS */ 394 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 395 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); 396 397 /* Wait for ULPS active */ 398 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 399 GLK_ULPS_NOT_ACTIVE, 20)) 400 drm_err(&dev_priv->drm, "ULPS not active\n"); 401 402 /* Exit ULPS */ 403 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 404 ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY); 405 406 /* Enter Normal Mode */ 407 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 408 ULPS_STATE_MASK, 409 ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); 410 411 intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0); 412 } 413 } 414 415 /* Wait for Stop state */ 416 for_each_dsi_port(port, intel_dsi->ports) { 417 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 418 GLK_DATA_LANE_STOP_STATE, 20)) 419 drm_err(&dev_priv->drm, 420 "Date lane not in STOP state\n"); 421 } 422 423 /* Wait for AFE LATCH */ 424 for_each_dsi_port(port, intel_dsi->ports) { 425 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), 426 AFE_LATCHOUT, 20)) 427 drm_err(&dev_priv->drm, 428 "D-PHY not entering LP-11 state\n"); 429 } 430 } 431 432 static void bxt_dsi_device_ready(struct intel_encoder *encoder) 433 { 434 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 435 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 436 enum port port; 437 u32 val; 438 439 drm_dbg_kms(&dev_priv->drm, "\n"); 440 441 /* Enable MIPI PHY transparent latch */ 442 for_each_dsi_port(port, intel_dsi->ports) { 443 intel_de_rmw(dev_priv, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); 444 usleep_range(2000, 2500); 445 } 446 447 /* Clear ULPS and set device ready */ 448 for_each_dsi_port(port, intel_dsi->ports) { 449 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 450 val &= ~ULPS_STATE_MASK; 451 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 452 usleep_range(2000, 2500); 453 val |= DEVICE_READY; 454 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 455 } 456 } 457 458 static void vlv_dsi_device_ready(struct intel_encoder *encoder) 459 { 460 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 461 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 462 enum port port; 463 464 drm_dbg_kms(&dev_priv->drm, "\n"); 465 466 vlv_flisdsi_get(dev_priv); 467 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms 468 * needed everytime after power gate */ 469 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); 470 vlv_flisdsi_put(dev_priv); 471 472 /* bandgap reset is needed after everytime we do power gate */ 473 band_gap_reset(dev_priv); 474 475 for_each_dsi_port(port, intel_dsi->ports) { 476 477 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 478 ULPS_STATE_ENTER); 479 usleep_range(2500, 3000); 480 481 /* Enable MIPI PHY transparent latch 482 * Common bit for both MIPI Port A & MIPI Port C 483 * No similar bit in MIPI Port C reg 484 */ 485 intel_de_rmw(dev_priv, MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); 486 usleep_range(1000, 1500); 487 488 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 489 ULPS_STATE_EXIT); 490 usleep_range(2500, 3000); 491 492 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 493 DEVICE_READY); 494 usleep_range(2500, 3000); 495 } 496 } 497 498 static void intel_dsi_device_ready(struct intel_encoder *encoder) 499 { 500 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 501 502 if (IS_GEMINILAKE(dev_priv)) 503 glk_dsi_device_ready(encoder); 504 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 505 bxt_dsi_device_ready(encoder); 506 else 507 vlv_dsi_device_ready(encoder); 508 } 509 510 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) 511 { 512 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 513 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 514 enum port port; 515 516 /* Enter ULPS */ 517 for_each_dsi_port(port, intel_dsi->ports) 518 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), 519 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); 520 521 /* Wait for MIPI PHY status bit to unset */ 522 for_each_dsi_port(port, intel_dsi->ports) { 523 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 524 GLK_PHY_STATUS_PORT_READY, 20)) 525 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); 526 } 527 528 /* Wait for Pwr ACK bit to unset */ 529 for_each_dsi_port(port, intel_dsi->ports) { 530 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 531 GLK_MIPIIO_PORT_POWERED, 20)) 532 drm_err(&dev_priv->drm, 533 "MIPI IO Port is not powergated\n"); 534 } 535 } 536 537 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) 538 { 539 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 540 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 541 enum port port; 542 543 /* Put the IO into reset */ 544 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); 545 546 /* Wait for MIPI PHY status bit to unset */ 547 for_each_dsi_port(port, intel_dsi->ports) { 548 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 549 GLK_PHY_STATUS_PORT_READY, 20)) 550 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); 551 } 552 553 /* Clear MIPI mode */ 554 for_each_dsi_port(port, intel_dsi->ports) 555 intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_ENABLE, 0); 556 } 557 558 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) 559 { 560 glk_dsi_enter_low_power_mode(encoder); 561 glk_dsi_disable_mipi_io(encoder); 562 } 563 564 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) 565 { 566 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 567 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 568 enum port port; 569 570 drm_dbg_kms(&dev_priv->drm, "\n"); 571 for_each_dsi_port(port, intel_dsi->ports) { 572 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ 573 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? 574 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); 575 576 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 577 DEVICE_READY | ULPS_STATE_ENTER); 578 usleep_range(2000, 2500); 579 580 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 581 DEVICE_READY | ULPS_STATE_EXIT); 582 usleep_range(2000, 2500); 583 584 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 585 DEVICE_READY | ULPS_STATE_ENTER); 586 usleep_range(2000, 2500); 587 588 /* 589 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI 590 * Port A only. MIPI Port C has no similar bit for checking. 591 */ 592 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) && 593 intel_de_wait_for_clear(dev_priv, port_ctrl, 594 AFE_LATCHOUT, 30)) 595 drm_err(&dev_priv->drm, "DSI LP not going Low\n"); 596 597 /* Disable MIPI PHY transparent latch */ 598 intel_de_rmw(dev_priv, port_ctrl, LP_OUTPUT_HOLD, 0); 599 usleep_range(1000, 1500); 600 601 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); 602 usleep_range(2000, 2500); 603 } 604 } 605 606 static void intel_dsi_port_enable(struct intel_encoder *encoder, 607 const struct intel_crtc_state *crtc_state) 608 { 609 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 610 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 611 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 612 enum port port; 613 614 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 615 u32 temp = intel_dsi->pixel_overlap; 616 617 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 618 for_each_dsi_port(port, intel_dsi->ports) 619 intel_de_rmw(dev_priv, MIPI_CTRL(port), 620 BXT_PIXEL_OVERLAP_CNT_MASK, 621 temp << BXT_PIXEL_OVERLAP_CNT_SHIFT); 622 } else { 623 intel_de_rmw(dev_priv, VLV_CHICKEN_3, 624 PIXEL_OVERLAP_CNT_MASK, 625 temp << PIXEL_OVERLAP_CNT_SHIFT); 626 } 627 } 628 629 for_each_dsi_port(port, intel_dsi->ports) { 630 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? 631 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 632 u32 temp; 633 634 temp = intel_de_read(dev_priv, port_ctrl); 635 636 temp &= ~LANE_CONFIGURATION_MASK; 637 temp &= ~DUAL_LINK_MODE_MASK; 638 639 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { 640 temp |= (intel_dsi->dual_link - 1) 641 << DUAL_LINK_MODE_SHIFT; 642 if (IS_BROXTON(dev_priv)) 643 temp |= LANE_CONFIGURATION_DUAL_LINK_A; 644 else 645 temp |= crtc->pipe ? 646 LANE_CONFIGURATION_DUAL_LINK_B : 647 LANE_CONFIGURATION_DUAL_LINK_A; 648 } 649 650 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) 651 temp |= DITHERING_ENABLE; 652 653 /* assert ip_tg_enable signal */ 654 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); 655 intel_de_posting_read(dev_priv, port_ctrl); 656 } 657 } 658 659 static void intel_dsi_port_disable(struct intel_encoder *encoder) 660 { 661 struct drm_device *dev = encoder->base.dev; 662 struct drm_i915_private *dev_priv = to_i915(dev); 663 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 664 enum port port; 665 666 for_each_dsi_port(port, intel_dsi->ports) { 667 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? 668 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 669 670 /* de-assert ip_tg_enable signal */ 671 intel_de_rmw(dev_priv, port_ctrl, DPI_ENABLE, 0); 672 intel_de_posting_read(dev_priv, port_ctrl); 673 } 674 } 675 676 static void intel_dsi_wait_panel_power_cycle(struct intel_dsi *intel_dsi) 677 { 678 ktime_t panel_power_on_time; 679 s64 panel_power_off_duration; 680 681 panel_power_on_time = ktime_get_boottime(); 682 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, 683 intel_dsi->panel_power_off_time); 684 685 if (panel_power_off_duration < (s64)intel_dsi->panel_pwr_cycle_delay) 686 msleep(intel_dsi->panel_pwr_cycle_delay - panel_power_off_duration); 687 } 688 689 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 690 const struct intel_crtc_state *pipe_config); 691 static void intel_dsi_unprepare(struct intel_encoder *encoder); 692 693 /* 694 * Panel enable/disable sequences from the VBT spec. 695 * 696 * Note the spec has AssertReset / DeassertReset swapped from their 697 * usual naming. We use the normal names to avoid confusion (so below 698 * they are swapped compared to the spec). 699 * 700 * Steps starting with MIPI refer to VBT sequences, note that for v2 701 * VBTs several steps which have a VBT in v2 are expected to be handled 702 * directly by the driver, by directly driving gpios for example. 703 * 704 * v2 video mode seq v3 video mode seq command mode seq 705 * - power on - MIPIPanelPowerOn - power on 706 * - wait t1+t2 - wait t1+t2 707 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin 708 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 709 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds 710 * - MIPITearOn 711 * - MIPIDisplayOn 712 * - turn on DPI - turn on DPI - set pipe to dsr mode 713 * - MIPIDisplayOn - MIPIDisplayOn 714 * - wait t5 - wait t5 715 * - backlight on - MIPIBacklightOn - backlight on 716 * ... ... ... issue mem cmds ... 717 * - backlight off - MIPIBacklightOff - backlight off 718 * - wait t6 - wait t6 719 * - MIPIDisplayOff 720 * - turn off DPI - turn off DPI - disable pipe dsr mode 721 * - MIPITearOff 722 * - MIPIDisplayOff - MIPIDisplayOff 723 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 724 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin 725 * - wait t3 - wait t3 726 * - power off - MIPIPanelPowerOff - power off 727 * - wait t4 - wait t4 728 */ 729 730 /* 731 * DSI port enable has to be done before pipe and plane enable, so we do it in 732 * the pre_enable hook instead of the enable hook. 733 */ 734 static void intel_dsi_pre_enable(struct intel_atomic_state *state, 735 struct intel_encoder *encoder, 736 const struct intel_crtc_state *pipe_config, 737 const struct drm_connector_state *conn_state) 738 { 739 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 740 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 741 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 742 enum pipe pipe = crtc->pipe; 743 enum port port; 744 bool glk_cold_boot = false; 745 746 drm_dbg_kms(&dev_priv->drm, "\n"); 747 748 intel_dsi_wait_panel_power_cycle(intel_dsi); 749 750 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 751 752 /* 753 * The BIOS may leave the PLL in a wonky state where it doesn't 754 * lock. It needs to be fully powered down to fix it. 755 */ 756 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 757 bxt_dsi_pll_disable(encoder); 758 bxt_dsi_pll_enable(encoder, pipe_config); 759 } else { 760 vlv_dsi_pll_disable(encoder); 761 vlv_dsi_pll_enable(encoder, pipe_config); 762 } 763 764 if (IS_BROXTON(dev_priv)) { 765 /* Add MIPI IO reset programming for modeset */ 766 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL); 767 768 /* Power up DSI regulator */ 769 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 770 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); 771 } 772 773 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 774 /* Disable DPOunit clock gating, can stall pipe */ 775 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), 776 0, DPOUNIT_CLOCK_GATE_DISABLE); 777 } 778 779 if (!IS_GEMINILAKE(dev_priv)) 780 intel_dsi_prepare(encoder, pipe_config); 781 782 /* Give the panel time to power-on and then deassert its reset */ 783 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 784 msleep(intel_dsi->panel_on_delay); 785 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 786 787 if (IS_GEMINILAKE(dev_priv)) { 788 glk_cold_boot = glk_dsi_enable_io(encoder); 789 790 /* Prepare port in cold boot(s3/s4) scenario */ 791 if (glk_cold_boot) 792 intel_dsi_prepare(encoder, pipe_config); 793 } 794 795 /* Put device in ready state (LP-11) */ 796 intel_dsi_device_ready(encoder); 797 798 /* Prepare port in normal boot scenario */ 799 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) 800 intel_dsi_prepare(encoder, pipe_config); 801 802 /* Send initialization commands in LP mode */ 803 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 804 805 /* 806 * Enable port in pre-enable phase itself because as per hw team 807 * recommendation, port should be enabled before plane & pipe 808 */ 809 if (is_cmd_mode(intel_dsi)) { 810 for_each_dsi_port(port, intel_dsi->ports) 811 intel_de_write(dev_priv, 812 MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); 813 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); 814 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 815 } else { 816 msleep(20); /* XXX */ 817 for_each_dsi_port(port, intel_dsi->ports) 818 dpi_send_cmd(intel_dsi, TURN_ON, false, port); 819 msleep(100); 820 821 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 822 823 intel_dsi_port_enable(encoder, pipe_config); 824 } 825 826 intel_backlight_enable(pipe_config, conn_state); 827 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 828 } 829 830 static void bxt_dsi_enable(struct intel_atomic_state *state, 831 struct intel_encoder *encoder, 832 const struct intel_crtc_state *crtc_state, 833 const struct drm_connector_state *conn_state) 834 { 835 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 836 837 intel_crtc_vblank_on(crtc_state); 838 } 839 840 /* 841 * DSI port disable has to be done after pipe and plane disable, so we do it in 842 * the post_disable hook. 843 */ 844 static void intel_dsi_disable(struct intel_atomic_state *state, 845 struct intel_encoder *encoder, 846 const struct intel_crtc_state *old_crtc_state, 847 const struct drm_connector_state *old_conn_state) 848 { 849 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 850 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 851 enum port port; 852 853 drm_dbg_kms(&i915->drm, "\n"); 854 855 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 856 intel_backlight_disable(old_conn_state); 857 858 /* 859 * According to the spec we should send SHUTDOWN before 860 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing 861 * has shown that the v3 sequence works for v2 VBTs too 862 */ 863 if (is_vid_mode(intel_dsi)) { 864 /* Send Shutdown command to the panel in LP mode */ 865 for_each_dsi_port(port, intel_dsi->ports) 866 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); 867 msleep(10); 868 } 869 } 870 871 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 872 { 873 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 874 875 if (IS_GEMINILAKE(dev_priv)) 876 glk_dsi_clear_device_ready(encoder); 877 else 878 vlv_dsi_clear_device_ready(encoder); 879 } 880 881 static void intel_dsi_post_disable(struct intel_atomic_state *state, 882 struct intel_encoder *encoder, 883 const struct intel_crtc_state *old_crtc_state, 884 const struct drm_connector_state *old_conn_state) 885 { 886 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 887 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 888 enum port port; 889 890 drm_dbg_kms(&dev_priv->drm, "\n"); 891 892 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 893 intel_crtc_vblank_off(old_crtc_state); 894 895 skl_scaler_disable(old_crtc_state); 896 } 897 898 if (is_vid_mode(intel_dsi)) { 899 for_each_dsi_port(port, intel_dsi->ports) 900 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 901 902 intel_dsi_port_disable(encoder); 903 usleep_range(2000, 5000); 904 } 905 906 intel_dsi_unprepare(encoder); 907 908 /* 909 * if disable packets are sent before sending shutdown packet then in 910 * some next enable sequence send turn on packet error is observed 911 */ 912 if (is_cmd_mode(intel_dsi)) 913 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF); 914 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 915 916 /* Transition to LP-00 */ 917 intel_dsi_clear_device_ready(encoder); 918 919 if (IS_BROXTON(dev_priv)) { 920 /* Power down DSI regulator to save power */ 921 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 922 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 923 HS_IO_CTRL_SELECT); 924 925 /* Add MIPI IO reset programming for modeset */ 926 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0); 927 } 928 929 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 930 bxt_dsi_pll_disable(encoder); 931 } else { 932 vlv_dsi_pll_disable(encoder); 933 934 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), 935 DPOUNIT_CLOCK_GATE_DISABLE, 0); 936 } 937 938 /* Assert reset */ 939 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 940 941 msleep(intel_dsi->panel_off_delay); 942 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 943 944 intel_dsi->panel_power_off_time = ktime_get_boottime(); 945 } 946 947 static void intel_dsi_shutdown(struct intel_encoder *encoder) 948 { 949 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 950 951 intel_dsi_wait_panel_power_cycle(intel_dsi); 952 } 953 954 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 955 enum pipe *pipe) 956 { 957 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 958 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 959 intel_wakeref_t wakeref; 960 enum port port; 961 bool active = false; 962 963 drm_dbg_kms(&dev_priv->drm, "\n"); 964 965 wakeref = intel_display_power_get_if_enabled(dev_priv, 966 encoder->power_domain); 967 if (!wakeref) 968 return false; 969 970 /* 971 * On Broxton the PLL needs to be enabled with a valid divider 972 * configuration, otherwise accessing DSI registers will hang the 973 * machine. See BSpec North Display Engine registers/MIPI[BXT]. 974 */ 975 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 976 !bxt_dsi_pll_is_enabled(dev_priv)) 977 goto out_put_power; 978 979 /* XXX: this only works for one DSI output */ 980 for_each_dsi_port(port, intel_dsi->ports) { 981 i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? 982 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 983 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE; 984 985 /* 986 * Due to some hardware limitations on VLV/CHV, the DPI enable 987 * bit in port C control register does not get set. As a 988 * workaround, check pipe B conf instead. 989 */ 990 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 991 port == PORT_C) 992 enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; 993 994 /* Try command mode if video mode not enabled */ 995 if (!enabled) { 996 u32 tmp = intel_de_read(dev_priv, 997 MIPI_DSI_FUNC_PRG(port)); 998 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; 999 } 1000 1001 if (!enabled) 1002 continue; 1003 1004 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) 1005 continue; 1006 1007 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1008 u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1009 tmp &= BXT_PIPE_SELECT_MASK; 1010 tmp >>= BXT_PIPE_SELECT_SHIFT; 1011 1012 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) 1013 continue; 1014 1015 *pipe = tmp; 1016 } else { 1017 *pipe = port == PORT_A ? PIPE_A : PIPE_B; 1018 } 1019 1020 active = true; 1021 break; 1022 } 1023 1024 out_put_power: 1025 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1026 1027 return active; 1028 } 1029 1030 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, 1031 struct intel_crtc_state *pipe_config) 1032 { 1033 struct drm_device *dev = encoder->base.dev; 1034 struct drm_i915_private *dev_priv = to_i915(dev); 1035 struct drm_display_mode *adjusted_mode = 1036 &pipe_config->hw.adjusted_mode; 1037 struct drm_display_mode *adjusted_mode_sw; 1038 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1039 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1040 unsigned int lane_count = intel_dsi->lane_count; 1041 unsigned int bpp, fmt; 1042 enum port port; 1043 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1044 u16 hfp_sw, hsync_sw, hbp_sw; 1045 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, 1046 crtc_hblank_start_sw, crtc_hblank_end_sw; 1047 1048 /* FIXME: hw readout should not depend on SW state */ 1049 adjusted_mode_sw = &crtc->config->hw.adjusted_mode; 1050 1051 /* 1052 * Atleast one port is active as encoder->get_config called only if 1053 * encoder->get_hw_state() returns true. 1054 */ 1055 for_each_dsi_port(port, intel_dsi->ports) { 1056 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) 1057 break; 1058 } 1059 1060 fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; 1061 bpp = mipi_dsi_pixel_format_to_bpp( 1062 pixel_format_from_register_bits(fmt)); 1063 1064 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); 1065 1066 /* Enable Frame time stamo based scanline reporting */ 1067 pipe_config->mode_flags |= 1068 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 1069 1070 /* In terms of pixels */ 1071 adjusted_mode->crtc_hdisplay = 1072 intel_de_read(dev_priv, 1073 BXT_MIPI_TRANS_HACTIVE(port)); 1074 adjusted_mode->crtc_vdisplay = 1075 intel_de_read(dev_priv, 1076 BXT_MIPI_TRANS_VACTIVE(port)); 1077 adjusted_mode->crtc_vtotal = 1078 intel_de_read(dev_priv, 1079 BXT_MIPI_TRANS_VTOTAL(port)); 1080 1081 hactive = adjusted_mode->crtc_hdisplay; 1082 hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); 1083 1084 /* 1085 * Meaningful for video mode non-burst sync pulse mode only, 1086 * can be zero for non-burst sync events and burst modes 1087 */ 1088 hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); 1089 hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); 1090 1091 /* harizontal values are in terms of high speed byte clock */ 1092 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, 1093 intel_dsi->burst_mode_ratio); 1094 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, 1095 intel_dsi->burst_mode_ratio); 1096 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, 1097 intel_dsi->burst_mode_ratio); 1098 1099 if (intel_dsi->dual_link) { 1100 hfp *= 2; 1101 hsync *= 2; 1102 hbp *= 2; 1103 } 1104 1105 /* vertical values are in terms of lines */ 1106 vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); 1107 vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); 1108 vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port)); 1109 1110 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; 1111 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; 1112 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; 1113 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1114 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1115 1116 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; 1117 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; 1118 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1119 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1120 1121 /* 1122 * In BXT DSI there is no regs programmed with few horizontal timings 1123 * in Pixels but txbyteclkhs.. So retrieval process adds some 1124 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. 1125 * Actually here for the given adjusted_mode, we are calculating the 1126 * value programmed to the port and then back to the horizontal timing 1127 * param in pixels. This is the expected value, including roundup errors 1128 * And if that is same as retrieved value from port, then 1129 * (HW state) adjusted_mode's horizontal timings are corrected to 1130 * match with SW state to nullify the errors. 1131 */ 1132 /* Calculating the value programmed to the Port register */ 1133 hfp_sw = adjusted_mode_sw->crtc_hsync_start - 1134 adjusted_mode_sw->crtc_hdisplay; 1135 hsync_sw = adjusted_mode_sw->crtc_hsync_end - 1136 adjusted_mode_sw->crtc_hsync_start; 1137 hbp_sw = adjusted_mode_sw->crtc_htotal - 1138 adjusted_mode_sw->crtc_hsync_end; 1139 1140 if (intel_dsi->dual_link) { 1141 hfp_sw /= 2; 1142 hsync_sw /= 2; 1143 hbp_sw /= 2; 1144 } 1145 1146 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, 1147 intel_dsi->burst_mode_ratio); 1148 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, 1149 intel_dsi->burst_mode_ratio); 1150 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, 1151 intel_dsi->burst_mode_ratio); 1152 1153 /* Reverse calculating the adjusted mode parameters from port reg vals*/ 1154 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, 1155 intel_dsi->burst_mode_ratio); 1156 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, 1157 intel_dsi->burst_mode_ratio); 1158 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, 1159 intel_dsi->burst_mode_ratio); 1160 1161 if (intel_dsi->dual_link) { 1162 hfp_sw *= 2; 1163 hsync_sw *= 2; 1164 hbp_sw *= 2; 1165 } 1166 1167 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + 1168 hsync_sw + hbp_sw; 1169 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; 1170 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; 1171 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; 1172 crtc_hblank_end_sw = crtc_htotal_sw; 1173 1174 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) 1175 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; 1176 1177 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) 1178 adjusted_mode->crtc_hsync_start = 1179 adjusted_mode_sw->crtc_hsync_start; 1180 1181 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) 1182 adjusted_mode->crtc_hsync_end = 1183 adjusted_mode_sw->crtc_hsync_end; 1184 1185 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) 1186 adjusted_mode->crtc_hblank_start = 1187 adjusted_mode_sw->crtc_hblank_start; 1188 1189 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) 1190 adjusted_mode->crtc_hblank_end = 1191 adjusted_mode_sw->crtc_hblank_end; 1192 } 1193 1194 static void intel_dsi_get_config(struct intel_encoder *encoder, 1195 struct intel_crtc_state *pipe_config) 1196 { 1197 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1198 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1199 u32 pclk; 1200 1201 drm_dbg_kms(&dev_priv->drm, "\n"); 1202 1203 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1204 1205 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1206 bxt_dsi_get_pipe_config(encoder, pipe_config); 1207 pclk = bxt_dsi_get_pclk(encoder, pipe_config); 1208 } else { 1209 pclk = vlv_dsi_get_pclk(encoder, pipe_config); 1210 } 1211 1212 pipe_config->port_clock = pclk; 1213 1214 /* FIXME definitely not right for burst/cmd mode/pixel overlap */ 1215 pipe_config->hw.adjusted_mode.crtc_clock = pclk; 1216 if (intel_dsi->dual_link) 1217 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1218 } 1219 1220 /* return txclkesc cycles in terms of divider and duration in us */ 1221 static u16 txclkesc(u32 divider, unsigned int us) 1222 { 1223 switch (divider) { 1224 case ESCAPE_CLOCK_DIVIDER_1: 1225 default: 1226 return 20 * us; 1227 case ESCAPE_CLOCK_DIVIDER_2: 1228 return 10 * us; 1229 case ESCAPE_CLOCK_DIVIDER_4: 1230 return 5 * us; 1231 } 1232 } 1233 1234 static void set_dsi_timings(struct drm_encoder *encoder, 1235 const struct drm_display_mode *adjusted_mode) 1236 { 1237 struct drm_device *dev = encoder->dev; 1238 struct drm_i915_private *dev_priv = to_i915(dev); 1239 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1240 enum port port; 1241 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1242 unsigned int lane_count = intel_dsi->lane_count; 1243 1244 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1245 1246 hactive = adjusted_mode->crtc_hdisplay; 1247 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; 1248 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1249 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; 1250 1251 if (intel_dsi->dual_link) { 1252 hactive /= 2; 1253 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1254 hactive += intel_dsi->pixel_overlap; 1255 hfp /= 2; 1256 hsync /= 2; 1257 hbp /= 2; 1258 } 1259 1260 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; 1261 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; 1262 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; 1263 1264 /* horizontal values are in terms of high speed byte clock */ 1265 hactive = txbyteclkhs(hactive, bpp, lane_count, 1266 intel_dsi->burst_mode_ratio); 1267 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1268 hsync = txbyteclkhs(hsync, bpp, lane_count, 1269 intel_dsi->burst_mode_ratio); 1270 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1271 1272 for_each_dsi_port(port, intel_dsi->ports) { 1273 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1274 /* 1275 * Program hdisplay and vdisplay on MIPI transcoder. 1276 * This is different from calculated hactive and 1277 * vactive, as they are calculated per channel basis, 1278 * whereas these values should be based on resolution. 1279 */ 1280 intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), 1281 adjusted_mode->crtc_hdisplay); 1282 intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), 1283 adjusted_mode->crtc_vdisplay); 1284 intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), 1285 adjusted_mode->crtc_vtotal); 1286 } 1287 1288 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), 1289 hactive); 1290 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); 1291 1292 /* meaningful for video mode non-burst sync pulse mode only, 1293 * can be zero for non-burst sync events and burst modes */ 1294 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), 1295 hsync); 1296 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); 1297 1298 /* vertical values are in terms of lines */ 1299 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); 1300 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), 1301 vsync); 1302 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); 1303 } 1304 } 1305 1306 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) 1307 { 1308 switch (fmt) { 1309 case MIPI_DSI_FMT_RGB888: 1310 return VID_MODE_FORMAT_RGB888; 1311 case MIPI_DSI_FMT_RGB666: 1312 return VID_MODE_FORMAT_RGB666; 1313 case MIPI_DSI_FMT_RGB666_PACKED: 1314 return VID_MODE_FORMAT_RGB666_PACKED; 1315 case MIPI_DSI_FMT_RGB565: 1316 return VID_MODE_FORMAT_RGB565; 1317 default: 1318 MISSING_CASE(fmt); 1319 return VID_MODE_FORMAT_RGB666; 1320 } 1321 } 1322 1323 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 1324 const struct intel_crtc_state *pipe_config) 1325 { 1326 struct drm_encoder *encoder = &intel_encoder->base; 1327 struct drm_device *dev = encoder->dev; 1328 struct drm_i915_private *dev_priv = to_i915(dev); 1329 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1330 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1331 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1332 enum port port; 1333 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1334 u32 val, tmp; 1335 u16 mode_hdisplay; 1336 1337 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe)); 1338 1339 mode_hdisplay = adjusted_mode->crtc_hdisplay; 1340 1341 if (intel_dsi->dual_link) { 1342 mode_hdisplay /= 2; 1343 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1344 mode_hdisplay += intel_dsi->pixel_overlap; 1345 } 1346 1347 for_each_dsi_port(port, intel_dsi->ports) { 1348 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1349 /* 1350 * escape clock divider, 20MHz, shared for A and C. 1351 * device ready must be off when doing this! txclkesc? 1352 */ 1353 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 1354 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 1355 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), 1356 tmp | ESCAPE_CLOCK_DIVIDER_1); 1357 1358 /* read request priority is per pipe */ 1359 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1360 tmp &= ~READ_REQUEST_PRIORITY_MASK; 1361 intel_de_write(dev_priv, MIPI_CTRL(port), 1362 tmp | READ_REQUEST_PRIORITY_HIGH); 1363 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1364 enum pipe pipe = crtc->pipe; 1365 1366 intel_de_rmw(dev_priv, MIPI_CTRL(port), 1367 BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe)); 1368 } 1369 1370 /* XXX: why here, why like this? handling in irq handler?! */ 1371 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); 1372 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); 1373 1374 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), 1375 intel_dsi->dphy_reg); 1376 1377 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), 1378 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); 1379 } 1380 1381 set_dsi_timings(encoder, adjusted_mode); 1382 1383 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; 1384 if (is_cmd_mode(intel_dsi)) { 1385 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; 1386 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ 1387 } else { 1388 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; 1389 val |= pixel_format_to_reg(intel_dsi->pixel_format); 1390 } 1391 1392 tmp = 0; 1393 if (intel_dsi->eotp_pkt == 0) 1394 tmp |= EOT_DISABLE; 1395 if (intel_dsi->clock_stop) 1396 tmp |= CLOCKSTOP; 1397 1398 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1399 tmp |= BXT_DPHY_DEFEATURE_EN; 1400 if (!is_cmd_mode(intel_dsi)) 1401 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; 1402 } 1403 1404 for_each_dsi_port(port, intel_dsi->ports) { 1405 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); 1406 1407 /* timeouts for recovery. one frame IIUC. if counter expires, 1408 * EOT and stop state. */ 1409 1410 /* 1411 * In burst mode, value greater than one DPI line Time in byte 1412 * clock (txbyteclkhs) To timeout this timer 1+ of the above 1413 * said value is recommended. 1414 * 1415 * In non-burst mode, Value greater than one DPI frame time in 1416 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1417 * said value is recommended. 1418 * 1419 * In DBI only mode, value greater than one DBI frame time in 1420 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1421 * said value is recommended. 1422 */ 1423 1424 if (is_vid_mode(intel_dsi) && 1425 intel_dsi->video_mode == BURST_MODE) { 1426 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), 1427 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1428 } else { 1429 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), 1430 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1431 } 1432 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), 1433 intel_dsi->lp_rx_timeout); 1434 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), 1435 intel_dsi->turn_arnd_val); 1436 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), 1437 intel_dsi->rst_timer_val); 1438 1439 /* dphy stuff */ 1440 1441 /* in terms of low power clock */ 1442 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), 1443 txclkesc(intel_dsi->escape_clk_div, 100)); 1444 1445 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1446 !intel_dsi->dual_link) { 1447 /* 1448 * BXT spec says write MIPI_INIT_COUNT for 1449 * both the ports, even if only one is 1450 * getting used. So write the other port 1451 * if not in dual link mode. 1452 */ 1453 intel_de_write(dev_priv, 1454 MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A), 1455 intel_dsi->init_count); 1456 } 1457 1458 /* recovery disables */ 1459 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); 1460 1461 /* in terms of low power clock */ 1462 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), 1463 intel_dsi->init_count); 1464 1465 /* in terms of txbyteclkhs. actual high to low switch + 1466 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. 1467 * 1468 * XXX: write MIPI_STOP_STATE_STALL? 1469 */ 1470 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), 1471 intel_dsi->hs_to_lp_count); 1472 1473 /* XXX: low power clock equivalence in terms of byte clock. 1474 * the number of byte clocks occupied in one low power clock. 1475 * based on txbyteclkhs and txclkesc. 1476 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL 1477 * ) / 105.??? 1478 */ 1479 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), 1480 intel_dsi->lp_byte_clk); 1481 1482 if (IS_GEMINILAKE(dev_priv)) { 1483 intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), 1484 intel_dsi->lp_byte_clk); 1485 /* Shadow of DPHY reg */ 1486 intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), 1487 intel_dsi->dphy_reg); 1488 } 1489 1490 /* the bw essential for transmitting 16 long packets containing 1491 * 252 bytes meant for dcs write memory command is programmed in 1492 * this register in terms of byte clocks. based on dsi transfer 1493 * rate and the number of lanes configured the time taken to 1494 * transmit 16 long packets in a dsi stream varies. */ 1495 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), 1496 intel_dsi->bw_timer); 1497 1498 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), 1499 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); 1500 1501 if (is_vid_mode(intel_dsi)) { 1502 u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG; 1503 1504 /* 1505 * Some panels might have resolution which is not a 1506 * multiple of 64 like 1366 x 768. Enable RANDOM 1507 * resolution support for such panels by default. 1508 */ 1509 fmt |= RANDOM_DPI_DISPLAY_RESOLUTION; 1510 1511 switch (intel_dsi->video_mode) { 1512 default: 1513 MISSING_CASE(intel_dsi->video_mode); 1514 fallthrough; 1515 case NON_BURST_SYNC_EVENTS: 1516 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS; 1517 break; 1518 case NON_BURST_SYNC_PULSE: 1519 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE; 1520 break; 1521 case BURST_MODE: 1522 fmt |= VIDEO_MODE_BURST; 1523 break; 1524 } 1525 1526 intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt); 1527 } 1528 } 1529 } 1530 1531 static void intel_dsi_unprepare(struct intel_encoder *encoder) 1532 { 1533 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1534 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1535 enum port port; 1536 1537 if (IS_GEMINILAKE(dev_priv)) 1538 return; 1539 1540 for_each_dsi_port(port, intel_dsi->ports) { 1541 /* Panel commands can be sent when clock is in LP11 */ 1542 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); 1543 1544 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1545 bxt_dsi_reset_clocks(encoder, port); 1546 else 1547 vlv_dsi_reset_clocks(encoder, port); 1548 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); 1549 1550 intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(port), VID_MODE_FORMAT_MASK, 0); 1551 1552 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); 1553 } 1554 } 1555 1556 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) 1557 { 1558 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1559 1560 intel_dsi_vbt_gpio_cleanup(intel_dsi); 1561 intel_encoder_destroy(encoder); 1562 } 1563 1564 static const struct drm_encoder_funcs intel_dsi_funcs = { 1565 .destroy = intel_dsi_encoder_destroy, 1566 }; 1567 1568 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 1569 .get_modes = intel_dsi_get_modes, 1570 .mode_valid = intel_dsi_mode_valid, 1571 .atomic_check = intel_digital_connector_atomic_check, 1572 }; 1573 1574 static const struct drm_connector_funcs intel_dsi_connector_funcs = { 1575 .detect = intel_panel_detect, 1576 .late_register = intel_connector_register, 1577 .early_unregister = intel_connector_unregister, 1578 .destroy = intel_connector_destroy, 1579 .fill_modes = drm_helper_probe_single_connector_modes, 1580 .atomic_get_property = intel_digital_connector_atomic_get_property, 1581 .atomic_set_property = intel_digital_connector_atomic_set_property, 1582 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1583 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1584 }; 1585 1586 static void vlv_dsi_add_properties(struct intel_connector *connector) 1587 { 1588 const struct drm_display_mode *fixed_mode = 1589 intel_panel_preferred_fixed_mode(connector); 1590 1591 intel_attach_scaling_mode_property(&connector->base); 1592 1593 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1594 intel_dsi_get_panel_orientation(connector), 1595 fixed_mode->hdisplay, 1596 fixed_mode->vdisplay); 1597 } 1598 1599 #define NS_KHZ_RATIO 1000000 1600 1601 #define PREPARE_CNT_MAX 0x3F 1602 #define EXIT_ZERO_CNT_MAX 0x3F 1603 #define CLK_ZERO_CNT_MAX 0xFF 1604 #define TRAIL_CNT_MAX 0x1F 1605 1606 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) 1607 { 1608 struct drm_device *dev = intel_dsi->base.base.dev; 1609 struct drm_i915_private *dev_priv = to_i915(dev); 1610 struct intel_connector *connector = intel_dsi->attached_connector; 1611 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1612 u32 tlpx_ns, extra_byte_count, tlpx_ui; 1613 u32 ui_num, ui_den; 1614 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1615 u32 ths_prepare_ns, tclk_trail_ns; 1616 u32 tclk_prepare_clkzero, ths_prepare_hszero; 1617 u32 lp_to_hs_switch, hs_to_lp_switch; 1618 u32 mul; 1619 1620 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1621 1622 switch (intel_dsi->lane_count) { 1623 case 1: 1624 case 2: 1625 extra_byte_count = 2; 1626 break; 1627 case 3: 1628 extra_byte_count = 4; 1629 break; 1630 case 4: 1631 default: 1632 extra_byte_count = 3; 1633 break; 1634 } 1635 1636 /* in Kbps */ 1637 ui_num = NS_KHZ_RATIO; 1638 ui_den = intel_dsi_bitrate(intel_dsi); 1639 1640 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; 1641 ths_prepare_hszero = mipi_config->ths_prepare_hszero; 1642 1643 /* 1644 * B060 1645 * LP byte clock = TLPX/ (8UI) 1646 */ 1647 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); 1648 1649 /* DDR clock period = 2 * UI 1650 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ) 1651 * UI(nsec) = 10^6 / bitrate 1652 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate 1653 * DDR clock count = ns_value / DDR clock period 1654 * 1655 * For GEMINILAKE dphy_param_reg will be programmed in terms of 1656 * HS byte clock count for other platform in HS ddr clock count 1657 */ 1658 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; 1659 ths_prepare_ns = max(mipi_config->ths_prepare, 1660 mipi_config->tclk_prepare); 1661 1662 /* prepare count */ 1663 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul); 1664 1665 if (prepare_cnt > PREPARE_CNT_MAX) { 1666 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", 1667 prepare_cnt); 1668 prepare_cnt = PREPARE_CNT_MAX; 1669 } 1670 1671 /* exit zero count */ 1672 exit_zero_cnt = DIV_ROUND_UP( 1673 (ths_prepare_hszero - ths_prepare_ns) * ui_den, 1674 ui_num * mul 1675 ); 1676 1677 /* 1678 * Exit zero is unified val ths_zero and ths_exit 1679 * minimum value for ths_exit = 110ns 1680 * min (exit_zero_cnt * 2) = 110/UI 1681 * exit_zero_cnt = 55/UI 1682 */ 1683 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num) 1684 exit_zero_cnt += 1; 1685 1686 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) { 1687 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", 1688 exit_zero_cnt); 1689 exit_zero_cnt = EXIT_ZERO_CNT_MAX; 1690 } 1691 1692 /* clk zero count */ 1693 clk_zero_cnt = DIV_ROUND_UP( 1694 (tclk_prepare_clkzero - ths_prepare_ns) 1695 * ui_den, ui_num * mul); 1696 1697 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) { 1698 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", 1699 clk_zero_cnt); 1700 clk_zero_cnt = CLK_ZERO_CNT_MAX; 1701 } 1702 1703 /* trail count */ 1704 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1705 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul); 1706 1707 if (trail_cnt > TRAIL_CNT_MAX) { 1708 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", 1709 trail_cnt); 1710 trail_cnt = TRAIL_CNT_MAX; 1711 } 1712 1713 /* B080 */ 1714 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | 1715 clk_zero_cnt << 8 | prepare_cnt; 1716 1717 /* 1718 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT * 1719 * mul + 10UI + Extra Byte Count 1720 * 1721 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count 1722 * Extra Byte Count is calculated according to number of lanes. 1723 * High Low Switch Count is the Max of LP to HS and 1724 * HS to LP switch count 1725 * 1726 */ 1727 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); 1728 1729 /* B044 */ 1730 /* FIXME: 1731 * The comment above does not match with the code */ 1732 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul + 1733 exit_zero_cnt * mul + 10, 8); 1734 1735 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); 1736 1737 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); 1738 intel_dsi->hs_to_lp_count += extra_byte_count; 1739 1740 /* B088 */ 1741 /* LP -> HS for clock lanes 1742 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + 1743 * extra byte count 1744 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * 1745 * 2(in UI) + extra byte count 1746 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / 1747 * 8 + extra byte count 1748 */ 1749 intel_dsi->clk_lp_to_hs_count = 1750 DIV_ROUND_UP( 1751 4 * tlpx_ui + prepare_cnt * 2 + 1752 clk_zero_cnt * 2, 1753 8); 1754 1755 intel_dsi->clk_lp_to_hs_count += extra_byte_count; 1756 1757 /* HS->LP for Clock Lanes 1758 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + 1759 * Extra byte count 1760 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count 1761 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + 1762 * Extra byte count 1763 */ 1764 intel_dsi->clk_hs_to_lp_count = 1765 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, 1766 8); 1767 intel_dsi->clk_hs_to_lp_count += extra_byte_count; 1768 1769 intel_dsi_log_params(intel_dsi); 1770 } 1771 1772 void vlv_dsi_init(struct drm_i915_private *dev_priv) 1773 { 1774 struct intel_dsi *intel_dsi; 1775 struct intel_encoder *intel_encoder; 1776 struct drm_encoder *encoder; 1777 struct intel_connector *intel_connector; 1778 struct drm_connector *connector; 1779 struct drm_display_mode *current_mode; 1780 enum port port; 1781 enum pipe pipe; 1782 1783 drm_dbg_kms(&dev_priv->drm, "\n"); 1784 1785 /* There is no detection method for MIPI so rely on VBT */ 1786 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1787 return; 1788 1789 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1790 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE; 1791 else 1792 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE; 1793 1794 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1795 if (!intel_dsi) 1796 return; 1797 1798 intel_connector = intel_connector_alloc(); 1799 if (!intel_connector) { 1800 kfree(intel_dsi); 1801 return; 1802 } 1803 1804 intel_encoder = &intel_dsi->base; 1805 encoder = &intel_encoder->base; 1806 intel_dsi->attached_connector = intel_connector; 1807 1808 connector = &intel_connector->base; 1809 1810 drm_encoder_init(&dev_priv->drm, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, 1811 "DSI %c", port_name(port)); 1812 1813 intel_encoder->compute_config = intel_dsi_compute_config; 1814 intel_encoder->pre_enable = intel_dsi_pre_enable; 1815 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1816 intel_encoder->enable = bxt_dsi_enable; 1817 intel_encoder->disable = intel_dsi_disable; 1818 intel_encoder->post_disable = intel_dsi_post_disable; 1819 intel_encoder->get_hw_state = intel_dsi_get_hw_state; 1820 intel_encoder->get_config = intel_dsi_get_config; 1821 intel_encoder->update_pipe = intel_backlight_update; 1822 intel_encoder->shutdown = intel_dsi_shutdown; 1823 1824 intel_connector->get_hw_state = intel_connector_get_hw_state; 1825 1826 intel_encoder->port = port; 1827 intel_encoder->type = INTEL_OUTPUT_DSI; 1828 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1829 intel_encoder->cloneable = 0; 1830 1831 /* 1832 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI 1833 * port C. BXT isn't limited like this. 1834 */ 1835 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1836 intel_encoder->pipe_mask = ~0; 1837 else if (port == PORT_A) 1838 intel_encoder->pipe_mask = BIT(PIPE_A); 1839 else 1840 intel_encoder->pipe_mask = BIT(PIPE_B); 1841 1842 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1843 1844 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL, NULL); 1845 1846 if (intel_connector->panel.vbt.dsi.config->dual_link) 1847 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); 1848 else 1849 intel_dsi->ports = BIT(port); 1850 1851 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 1852 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 1853 1854 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 1855 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 1856 1857 /* Create a DSI host (and a device) for each port. */ 1858 for_each_dsi_port(port, intel_dsi->ports) { 1859 struct intel_dsi_host *host; 1860 1861 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops, 1862 port); 1863 if (!host) 1864 goto err; 1865 1866 intel_dsi->dsi_hosts[port] = host; 1867 } 1868 1869 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1870 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 1871 goto err; 1872 } 1873 1874 /* Use clock read-back from current hw-state for fastboot */ 1875 current_mode = intel_encoder_current_mode(intel_encoder); 1876 if (current_mode) { 1877 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", 1878 intel_dsi->pclk, current_mode->clock); 1879 if (intel_fuzzy_clock_check(intel_dsi->pclk, 1880 current_mode->clock)) { 1881 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); 1882 intel_dsi->pclk = current_mode->clock; 1883 } 1884 1885 kfree(current_mode); 1886 } 1887 1888 vlv_dphy_param_init(intel_dsi); 1889 1890 intel_dsi_vbt_gpio_init(intel_dsi, 1891 intel_dsi_get_hw_state(intel_encoder, &pipe)); 1892 1893 drm_connector_init(&dev_priv->drm, connector, &intel_dsi_connector_funcs, 1894 DRM_MODE_CONNECTOR_DSI); 1895 1896 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); 1897 1898 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ 1899 1900 intel_connector_attach_encoder(intel_connector, intel_encoder); 1901 1902 mutex_lock(&dev_priv->drm.mode_config.mutex); 1903 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 1904 mutex_unlock(&dev_priv->drm.mode_config.mutex); 1905 1906 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 1907 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); 1908 goto err_cleanup_connector; 1909 } 1910 1911 intel_panel_init(intel_connector, NULL); 1912 1913 intel_backlight_setup(intel_connector, INVALID_PIPE); 1914 1915 vlv_dsi_add_properties(intel_connector); 1916 1917 return; 1918 1919 err_cleanup_connector: 1920 drm_connector_cleanup(&intel_connector->base); 1921 err: 1922 drm_encoder_cleanup(&intel_encoder->base); 1923 kfree(intel_dsi); 1924 kfree(intel_connector); 1925 } 1926