1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Jani Nikula <jani.nikula@intel.com> 24 */ 25 26 #include <linux/slab.h> 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_crtc.h> 30 #include <drm/drm_edid.h> 31 #include <drm/drm_mipi_dsi.h> 32 33 #include "i915_drv.h" 34 #include "intel_atomic.h" 35 #include "intel_connector.h" 36 #include "intel_display_types.h" 37 #include "intel_dsi.h" 38 #include "intel_fifo_underrun.h" 39 #include "intel_panel.h" 40 #include "intel_sideband.h" 41 42 /* return pixels in terms of txbyteclkhs */ 43 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, 44 u16 burst_mode_ratio) 45 { 46 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, 47 8 * 100), lane_count); 48 } 49 50 /* return pixels equvalent to txbyteclkhs */ 51 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, 52 u16 burst_mode_ratio) 53 { 54 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), 55 (bpp * burst_mode_ratio)); 56 } 57 58 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 59 { 60 /* It just so happens the VBT matches register contents. */ 61 switch (fmt) { 62 case VID_MODE_FORMAT_RGB888: 63 return MIPI_DSI_FMT_RGB888; 64 case VID_MODE_FORMAT_RGB666: 65 return MIPI_DSI_FMT_RGB666; 66 case VID_MODE_FORMAT_RGB666_PACKED: 67 return MIPI_DSI_FMT_RGB666_PACKED; 68 case VID_MODE_FORMAT_RGB565: 69 return MIPI_DSI_FMT_RGB565; 70 default: 71 MISSING_CASE(fmt); 72 return MIPI_DSI_FMT_RGB666; 73 } 74 } 75 76 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) 77 { 78 struct drm_encoder *encoder = &intel_dsi->base.base; 79 struct drm_device *dev = encoder->dev; 80 struct drm_i915_private *dev_priv = to_i915(dev); 81 u32 mask; 82 83 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | 84 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; 85 86 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), 87 mask, 100)) 88 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); 89 } 90 91 static void write_data(struct drm_i915_private *dev_priv, 92 i915_reg_t reg, 93 const u8 *data, u32 len) 94 { 95 u32 i, j; 96 97 for (i = 0; i < len; i += 4) { 98 u32 val = 0; 99 100 for (j = 0; j < min_t(u32, len - i, 4); j++) 101 val |= *data++ << 8 * j; 102 103 intel_de_write(dev_priv, reg, val); 104 } 105 } 106 107 static void read_data(struct drm_i915_private *dev_priv, 108 i915_reg_t reg, 109 u8 *data, u32 len) 110 { 111 u32 i, j; 112 113 for (i = 0; i < len; i += 4) { 114 u32 val = intel_de_read(dev_priv, reg); 115 116 for (j = 0; j < min_t(u32, len - i, 4); j++) 117 *data++ = val >> 8 * j; 118 } 119 } 120 121 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, 122 const struct mipi_dsi_msg *msg) 123 { 124 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 125 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; 126 struct drm_i915_private *dev_priv = to_i915(dev); 127 enum port port = intel_dsi_host->port; 128 struct mipi_dsi_packet packet; 129 ssize_t ret; 130 const u8 *header, *data; 131 i915_reg_t data_reg, ctrl_reg; 132 u32 data_mask, ctrl_mask; 133 134 ret = mipi_dsi_create_packet(&packet, msg); 135 if (ret < 0) 136 return ret; 137 138 header = packet.header; 139 data = packet.payload; 140 141 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 142 data_reg = MIPI_LP_GEN_DATA(port); 143 data_mask = LP_DATA_FIFO_FULL; 144 ctrl_reg = MIPI_LP_GEN_CTRL(port); 145 ctrl_mask = LP_CTRL_FIFO_FULL; 146 } else { 147 data_reg = MIPI_HS_GEN_DATA(port); 148 data_mask = HS_DATA_FIFO_FULL; 149 ctrl_reg = MIPI_HS_GEN_CTRL(port); 150 ctrl_mask = HS_CTRL_FIFO_FULL; 151 } 152 153 /* note: this is never true for reads */ 154 if (packet.payload_length) { 155 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 156 data_mask, 50)) 157 drm_err(&dev_priv->drm, 158 "Timeout waiting for HS/LP DATA FIFO !full\n"); 159 160 write_data(dev_priv, data_reg, packet.payload, 161 packet.payload_length); 162 } 163 164 if (msg->rx_len) { 165 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 166 GEN_READ_DATA_AVAIL); 167 } 168 169 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 170 ctrl_mask, 50)) { 171 drm_err(&dev_priv->drm, 172 "Timeout waiting for HS/LP CTRL FIFO !full\n"); 173 } 174 175 intel_de_write(dev_priv, ctrl_reg, 176 header[2] << 16 | header[1] << 8 | header[0]); 177 178 /* ->rx_len is set only for reads */ 179 if (msg->rx_len) { 180 data_mask = GEN_READ_DATA_AVAIL; 181 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), 182 data_mask, 50)) 183 drm_err(&dev_priv->drm, 184 "Timeout waiting for read data.\n"); 185 186 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); 187 } 188 189 /* XXX: fix for reads and writes */ 190 return 4 + packet.payload_length; 191 } 192 193 static int intel_dsi_host_attach(struct mipi_dsi_host *host, 194 struct mipi_dsi_device *dsi) 195 { 196 return 0; 197 } 198 199 static int intel_dsi_host_detach(struct mipi_dsi_host *host, 200 struct mipi_dsi_device *dsi) 201 { 202 return 0; 203 } 204 205 static const struct mipi_dsi_host_ops intel_dsi_host_ops = { 206 .attach = intel_dsi_host_attach, 207 .detach = intel_dsi_host_detach, 208 .transfer = intel_dsi_host_transfer, 209 }; 210 211 /* 212 * send a video mode command 213 * 214 * XXX: commands with data in MIPI_DPI_DATA? 215 */ 216 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, 217 enum port port) 218 { 219 struct drm_encoder *encoder = &intel_dsi->base.base; 220 struct drm_device *dev = encoder->dev; 221 struct drm_i915_private *dev_priv = to_i915(dev); 222 u32 mask; 223 224 /* XXX: pipe, hs */ 225 if (hs) 226 cmd &= ~DPI_LP_MODE; 227 else 228 cmd |= DPI_LP_MODE; 229 230 /* clear bit */ 231 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); 232 233 /* XXX: old code skips write if control unchanged */ 234 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) 235 drm_dbg_kms(&dev_priv->drm, 236 "Same special packet %02x twice in a row.\n", cmd); 237 238 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); 239 240 mask = SPL_PKT_SENT_INTERRUPT; 241 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) 242 drm_err(&dev_priv->drm, 243 "Video mode command 0x%08x send failed.\n", cmd); 244 245 return 0; 246 } 247 248 static void band_gap_reset(struct drm_i915_private *dev_priv) 249 { 250 vlv_flisdsi_get(dev_priv); 251 252 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); 253 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); 254 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); 255 udelay(150); 256 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); 257 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); 258 259 vlv_flisdsi_put(dev_priv); 260 } 261 262 static int intel_dsi_compute_config(struct intel_encoder *encoder, 263 struct intel_crtc_state *pipe_config, 264 struct drm_connector_state *conn_state) 265 { 266 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 267 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 268 base); 269 struct intel_connector *intel_connector = intel_dsi->attached_connector; 270 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 271 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 272 int ret; 273 274 drm_dbg_kms(&dev_priv->drm, "\n"); 275 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 276 277 if (fixed_mode) { 278 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 279 280 if (HAS_GMCH(dev_priv)) 281 ret = intel_gmch_panel_fitting(pipe_config, conn_state); 282 else 283 ret = intel_pch_panel_fitting(pipe_config, conn_state); 284 if (ret) 285 return ret; 286 } 287 288 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 289 return -EINVAL; 290 291 /* DSI uses short packets for sync events, so clear mode flags for DSI */ 292 adjusted_mode->flags = 0; 293 294 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 295 pipe_config->pipe_bpp = 24; 296 else 297 pipe_config->pipe_bpp = 18; 298 299 if (IS_GEN9_LP(dev_priv)) { 300 /* Enable Frame time stamp based scanline reporting */ 301 pipe_config->mode_flags |= 302 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 303 304 /* Dual link goes to DSI transcoder A. */ 305 if (intel_dsi->ports == BIT(PORT_C)) 306 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; 307 else 308 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; 309 310 ret = bxt_dsi_pll_compute(encoder, pipe_config); 311 if (ret) 312 return -EINVAL; 313 } else { 314 ret = vlv_dsi_pll_compute(encoder, pipe_config); 315 if (ret) 316 return -EINVAL; 317 } 318 319 pipe_config->clock_set = true; 320 321 return 0; 322 } 323 324 static bool glk_dsi_enable_io(struct intel_encoder *encoder) 325 { 326 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 327 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 328 enum port port; 329 u32 tmp; 330 bool cold_boot = false; 331 332 /* Set the MIPI mode 333 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. 334 * Power ON MIPI IO first and then write into IO reset and LP wake bits 335 */ 336 for_each_dsi_port(port, intel_dsi->ports) { 337 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 338 intel_de_write(dev_priv, MIPI_CTRL(port), 339 tmp | GLK_MIPIIO_ENABLE); 340 } 341 342 /* Put the IO into reset */ 343 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 344 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 345 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); 346 347 /* Program LP Wake */ 348 for_each_dsi_port(port, intel_dsi->ports) { 349 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 350 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) 351 tmp &= ~GLK_LP_WAKE; 352 else 353 tmp |= GLK_LP_WAKE; 354 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); 355 } 356 357 /* Wait for Pwr ACK */ 358 for_each_dsi_port(port, intel_dsi->ports) { 359 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 360 GLK_MIPIIO_PORT_POWERED, 20)) 361 drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); 362 } 363 364 /* Check for cold boot scenario */ 365 for_each_dsi_port(port, intel_dsi->ports) { 366 cold_boot |= 367 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); 368 } 369 370 return cold_boot; 371 } 372 373 static void glk_dsi_device_ready(struct intel_encoder *encoder) 374 { 375 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 376 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 377 enum port port; 378 u32 val; 379 380 /* Wait for MIPI PHY status bit to set */ 381 for_each_dsi_port(port, intel_dsi->ports) { 382 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 383 GLK_PHY_STATUS_PORT_READY, 20)) 384 drm_err(&dev_priv->drm, "PHY is not ON\n"); 385 } 386 387 /* Get IO out of reset */ 388 val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 389 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), 390 val | GLK_MIPIIO_RESET_RELEASED); 391 392 /* Get IO out of Low power state*/ 393 for_each_dsi_port(port, intel_dsi->ports) { 394 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { 395 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 396 val &= ~ULPS_STATE_MASK; 397 val |= DEVICE_READY; 398 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 399 usleep_range(10, 15); 400 } else { 401 /* Enter ULPS */ 402 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 403 val &= ~ULPS_STATE_MASK; 404 val |= (ULPS_STATE_ENTER | DEVICE_READY); 405 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 406 407 /* Wait for ULPS active */ 408 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 409 GLK_ULPS_NOT_ACTIVE, 20)) 410 drm_err(&dev_priv->drm, "ULPS not active\n"); 411 412 /* Exit ULPS */ 413 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 414 val &= ~ULPS_STATE_MASK; 415 val |= (ULPS_STATE_EXIT | DEVICE_READY); 416 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 417 418 /* Enter Normal Mode */ 419 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 420 val &= ~ULPS_STATE_MASK; 421 val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); 422 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 423 424 val = intel_de_read(dev_priv, MIPI_CTRL(port)); 425 val &= ~GLK_LP_WAKE; 426 intel_de_write(dev_priv, MIPI_CTRL(port), val); 427 } 428 } 429 430 /* Wait for Stop state */ 431 for_each_dsi_port(port, intel_dsi->ports) { 432 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 433 GLK_DATA_LANE_STOP_STATE, 20)) 434 drm_err(&dev_priv->drm, 435 "Date lane not in STOP state\n"); 436 } 437 438 /* Wait for AFE LATCH */ 439 for_each_dsi_port(port, intel_dsi->ports) { 440 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), 441 AFE_LATCHOUT, 20)) 442 drm_err(&dev_priv->drm, 443 "D-PHY not entering LP-11 state\n"); 444 } 445 } 446 447 static void bxt_dsi_device_ready(struct intel_encoder *encoder) 448 { 449 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 450 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 451 enum port port; 452 u32 val; 453 454 drm_dbg_kms(&dev_priv->drm, "\n"); 455 456 /* Enable MIPI PHY transparent latch */ 457 for_each_dsi_port(port, intel_dsi->ports) { 458 val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 459 intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port), 460 val | LP_OUTPUT_HOLD); 461 usleep_range(2000, 2500); 462 } 463 464 /* Clear ULPS and set device ready */ 465 for_each_dsi_port(port, intel_dsi->ports) { 466 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 467 val &= ~ULPS_STATE_MASK; 468 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 469 usleep_range(2000, 2500); 470 val |= DEVICE_READY; 471 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 472 } 473 } 474 475 static void vlv_dsi_device_ready(struct intel_encoder *encoder) 476 { 477 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 478 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 479 enum port port; 480 u32 val; 481 482 drm_dbg_kms(&dev_priv->drm, "\n"); 483 484 vlv_flisdsi_get(dev_priv); 485 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms 486 * needed everytime after power gate */ 487 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); 488 vlv_flisdsi_put(dev_priv); 489 490 /* bandgap reset is needed after everytime we do power gate */ 491 band_gap_reset(dev_priv); 492 493 for_each_dsi_port(port, intel_dsi->ports) { 494 495 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 496 ULPS_STATE_ENTER); 497 usleep_range(2500, 3000); 498 499 /* Enable MIPI PHY transparent latch 500 * Common bit for both MIPI Port A & MIPI Port C 501 * No similar bit in MIPI Port C reg 502 */ 503 val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A)); 504 intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A), 505 val | LP_OUTPUT_HOLD); 506 usleep_range(1000, 1500); 507 508 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 509 ULPS_STATE_EXIT); 510 usleep_range(2500, 3000); 511 512 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 513 DEVICE_READY); 514 usleep_range(2500, 3000); 515 } 516 } 517 518 static void intel_dsi_device_ready(struct intel_encoder *encoder) 519 { 520 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 521 522 if (IS_GEMINILAKE(dev_priv)) 523 glk_dsi_device_ready(encoder); 524 else if (IS_GEN9_LP(dev_priv)) 525 bxt_dsi_device_ready(encoder); 526 else 527 vlv_dsi_device_ready(encoder); 528 } 529 530 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) 531 { 532 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 533 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 534 enum port port; 535 u32 val; 536 537 /* Enter ULPS */ 538 for_each_dsi_port(port, intel_dsi->ports) { 539 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 540 val &= ~ULPS_STATE_MASK; 541 val |= (ULPS_STATE_ENTER | DEVICE_READY); 542 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 543 } 544 545 /* Wait for MIPI PHY status bit to unset */ 546 for_each_dsi_port(port, intel_dsi->ports) { 547 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 548 GLK_PHY_STATUS_PORT_READY, 20)) 549 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); 550 } 551 552 /* Wait for Pwr ACK bit to unset */ 553 for_each_dsi_port(port, intel_dsi->ports) { 554 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 555 GLK_MIPIIO_PORT_POWERED, 20)) 556 drm_err(&dev_priv->drm, 557 "MIPI IO Port is not powergated\n"); 558 } 559 } 560 561 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) 562 { 563 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 564 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 565 enum port port; 566 u32 tmp; 567 568 /* Put the IO into reset */ 569 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 570 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 571 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); 572 573 /* Wait for MIPI PHY status bit to unset */ 574 for_each_dsi_port(port, intel_dsi->ports) { 575 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 576 GLK_PHY_STATUS_PORT_READY, 20)) 577 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); 578 } 579 580 /* Clear MIPI mode */ 581 for_each_dsi_port(port, intel_dsi->ports) { 582 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 583 tmp &= ~GLK_MIPIIO_ENABLE; 584 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); 585 } 586 } 587 588 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) 589 { 590 glk_dsi_enter_low_power_mode(encoder); 591 glk_dsi_disable_mipi_io(encoder); 592 } 593 594 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) 595 { 596 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 597 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 598 enum port port; 599 600 drm_dbg_kms(&dev_priv->drm, "\n"); 601 for_each_dsi_port(port, intel_dsi->ports) { 602 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ 603 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 604 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); 605 u32 val; 606 607 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 608 DEVICE_READY | ULPS_STATE_ENTER); 609 usleep_range(2000, 2500); 610 611 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 612 DEVICE_READY | ULPS_STATE_EXIT); 613 usleep_range(2000, 2500); 614 615 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 616 DEVICE_READY | ULPS_STATE_ENTER); 617 usleep_range(2000, 2500); 618 619 /* 620 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI 621 * Port A only. MIPI Port C has no similar bit for checking. 622 */ 623 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && 624 intel_de_wait_for_clear(dev_priv, port_ctrl, 625 AFE_LATCHOUT, 30)) 626 drm_err(&dev_priv->drm, "DSI LP not going Low\n"); 627 628 /* Disable MIPI PHY transparent latch */ 629 val = intel_de_read(dev_priv, port_ctrl); 630 intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD); 631 usleep_range(1000, 1500); 632 633 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); 634 usleep_range(2000, 2500); 635 } 636 } 637 638 static void intel_dsi_port_enable(struct intel_encoder *encoder, 639 const struct intel_crtc_state *crtc_state) 640 { 641 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 642 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 643 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 644 enum port port; 645 646 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 647 u32 temp; 648 if (IS_GEN9_LP(dev_priv)) { 649 for_each_dsi_port(port, intel_dsi->ports) { 650 temp = intel_de_read(dev_priv, 651 MIPI_CTRL(port)); 652 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | 653 intel_dsi->pixel_overlap << 654 BXT_PIXEL_OVERLAP_CNT_SHIFT; 655 intel_de_write(dev_priv, MIPI_CTRL(port), 656 temp); 657 } 658 } else { 659 temp = intel_de_read(dev_priv, VLV_CHICKEN_3); 660 temp &= ~PIXEL_OVERLAP_CNT_MASK | 661 intel_dsi->pixel_overlap << 662 PIXEL_OVERLAP_CNT_SHIFT; 663 intel_de_write(dev_priv, VLV_CHICKEN_3, temp); 664 } 665 } 666 667 for_each_dsi_port(port, intel_dsi->ports) { 668 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 669 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 670 u32 temp; 671 672 temp = intel_de_read(dev_priv, port_ctrl); 673 674 temp &= ~LANE_CONFIGURATION_MASK; 675 temp &= ~DUAL_LINK_MODE_MASK; 676 677 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { 678 temp |= (intel_dsi->dual_link - 1) 679 << DUAL_LINK_MODE_SHIFT; 680 if (IS_BROXTON(dev_priv)) 681 temp |= LANE_CONFIGURATION_DUAL_LINK_A; 682 else 683 temp |= crtc->pipe ? 684 LANE_CONFIGURATION_DUAL_LINK_B : 685 LANE_CONFIGURATION_DUAL_LINK_A; 686 } 687 688 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) 689 temp |= DITHERING_ENABLE; 690 691 /* assert ip_tg_enable signal */ 692 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); 693 intel_de_posting_read(dev_priv, port_ctrl); 694 } 695 } 696 697 static void intel_dsi_port_disable(struct intel_encoder *encoder) 698 { 699 struct drm_device *dev = encoder->base.dev; 700 struct drm_i915_private *dev_priv = to_i915(dev); 701 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 702 enum port port; 703 704 for_each_dsi_port(port, intel_dsi->ports) { 705 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 706 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 707 u32 temp; 708 709 /* de-assert ip_tg_enable signal */ 710 temp = intel_de_read(dev_priv, port_ctrl); 711 intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE); 712 intel_de_posting_read(dev_priv, port_ctrl); 713 } 714 } 715 716 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 717 const struct intel_crtc_state *pipe_config); 718 static void intel_dsi_unprepare(struct intel_encoder *encoder); 719 720 /* 721 * Panel enable/disable sequences from the VBT spec. 722 * 723 * Note the spec has AssertReset / DeassertReset swapped from their 724 * usual naming. We use the normal names to avoid confusion (so below 725 * they are swapped compared to the spec). 726 * 727 * Steps starting with MIPI refer to VBT sequences, note that for v2 728 * VBTs several steps which have a VBT in v2 are expected to be handled 729 * directly by the driver, by directly driving gpios for example. 730 * 731 * v2 video mode seq v3 video mode seq command mode seq 732 * - power on - MIPIPanelPowerOn - power on 733 * - wait t1+t2 - wait t1+t2 734 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin 735 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 736 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds 737 * - MIPITearOn 738 * - MIPIDisplayOn 739 * - turn on DPI - turn on DPI - set pipe to dsr mode 740 * - MIPIDisplayOn - MIPIDisplayOn 741 * - wait t5 - wait t5 742 * - backlight on - MIPIBacklightOn - backlight on 743 * ... ... ... issue mem cmds ... 744 * - backlight off - MIPIBacklightOff - backlight off 745 * - wait t6 - wait t6 746 * - MIPIDisplayOff 747 * - turn off DPI - turn off DPI - disable pipe dsr mode 748 * - MIPITearOff 749 * - MIPIDisplayOff - MIPIDisplayOff 750 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 751 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin 752 * - wait t3 - wait t3 753 * - power off - MIPIPanelPowerOff - power off 754 * - wait t4 - wait t4 755 */ 756 757 /* 758 * DSI port enable has to be done before pipe and plane enable, so we do it in 759 * the pre_enable hook instead of the enable hook. 760 */ 761 static void intel_dsi_pre_enable(struct intel_atomic_state *state, 762 struct intel_encoder *encoder, 763 const struct intel_crtc_state *pipe_config, 764 const struct drm_connector_state *conn_state) 765 { 766 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 767 struct drm_crtc *crtc = pipe_config->uapi.crtc; 768 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 770 enum pipe pipe = intel_crtc->pipe; 771 enum port port; 772 u32 val; 773 bool glk_cold_boot = false; 774 775 drm_dbg_kms(&dev_priv->drm, "\n"); 776 777 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 778 779 /* 780 * The BIOS may leave the PLL in a wonky state where it doesn't 781 * lock. It needs to be fully powered down to fix it. 782 */ 783 if (IS_GEN9_LP(dev_priv)) { 784 bxt_dsi_pll_disable(encoder); 785 bxt_dsi_pll_enable(encoder, pipe_config); 786 } else { 787 vlv_dsi_pll_disable(encoder); 788 vlv_dsi_pll_enable(encoder, pipe_config); 789 } 790 791 if (IS_BROXTON(dev_priv)) { 792 /* Add MIPI IO reset programming for modeset */ 793 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); 794 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, 795 val | MIPIO_RST_CTRL); 796 797 /* Power up DSI regulator */ 798 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 799 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); 800 } 801 802 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 803 u32 val; 804 805 /* Disable DPOunit clock gating, can stall pipe */ 806 val = intel_de_read(dev_priv, DSPCLK_GATE_D); 807 val |= DPOUNIT_CLOCK_GATE_DISABLE; 808 intel_de_write(dev_priv, DSPCLK_GATE_D, val); 809 } 810 811 if (!IS_GEMINILAKE(dev_priv)) 812 intel_dsi_prepare(encoder, pipe_config); 813 814 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 815 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 816 817 /* Deassert reset */ 818 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 819 820 if (IS_GEMINILAKE(dev_priv)) { 821 glk_cold_boot = glk_dsi_enable_io(encoder); 822 823 /* Prepare port in cold boot(s3/s4) scenario */ 824 if (glk_cold_boot) 825 intel_dsi_prepare(encoder, pipe_config); 826 } 827 828 /* Put device in ready state (LP-11) */ 829 intel_dsi_device_ready(encoder); 830 831 /* Prepare port in normal boot scenario */ 832 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) 833 intel_dsi_prepare(encoder, pipe_config); 834 835 /* Send initialization commands in LP mode */ 836 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 837 838 /* Enable port in pre-enable phase itself because as per hw team 839 * recommendation, port should be enabled befor plane & pipe */ 840 if (is_cmd_mode(intel_dsi)) { 841 for_each_dsi_port(port, intel_dsi->ports) 842 intel_de_write(dev_priv, 843 MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); 844 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); 845 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 846 } else { 847 msleep(20); /* XXX */ 848 for_each_dsi_port(port, intel_dsi->ports) 849 dpi_send_cmd(intel_dsi, TURN_ON, false, port); 850 intel_dsi_msleep(intel_dsi, 100); 851 852 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 853 854 intel_dsi_port_enable(encoder, pipe_config); 855 } 856 857 intel_panel_enable_backlight(pipe_config, conn_state); 858 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 859 } 860 861 static void bxt_dsi_enable(struct intel_atomic_state *state, 862 struct intel_encoder *encoder, 863 const struct intel_crtc_state *crtc_state, 864 const struct drm_connector_state *conn_state) 865 { 866 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 867 868 intel_crtc_vblank_on(crtc_state); 869 } 870 871 /* 872 * DSI port disable has to be done after pipe and plane disable, so we do it in 873 * the post_disable hook. 874 */ 875 static void intel_dsi_disable(struct intel_atomic_state *state, 876 struct intel_encoder *encoder, 877 const struct intel_crtc_state *old_crtc_state, 878 const struct drm_connector_state *old_conn_state) 879 { 880 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 881 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 882 enum port port; 883 884 drm_dbg_kms(&i915->drm, "\n"); 885 886 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 887 intel_panel_disable_backlight(old_conn_state); 888 889 /* 890 * According to the spec we should send SHUTDOWN before 891 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing 892 * has shown that the v3 sequence works for v2 VBTs too 893 */ 894 if (is_vid_mode(intel_dsi)) { 895 /* Send Shutdown command to the panel in LP mode */ 896 for_each_dsi_port(port, intel_dsi->ports) 897 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); 898 msleep(10); 899 } 900 } 901 902 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 903 { 904 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 905 906 if (IS_GEMINILAKE(dev_priv)) 907 glk_dsi_clear_device_ready(encoder); 908 else 909 vlv_dsi_clear_device_ready(encoder); 910 } 911 912 static void intel_dsi_post_disable(struct intel_atomic_state *state, 913 struct intel_encoder *encoder, 914 const struct intel_crtc_state *old_crtc_state, 915 const struct drm_connector_state *old_conn_state) 916 { 917 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 918 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 919 enum port port; 920 u32 val; 921 922 drm_dbg_kms(&dev_priv->drm, "\n"); 923 924 if (IS_GEN9_LP(dev_priv)) { 925 intel_crtc_vblank_off(old_crtc_state); 926 927 skl_scaler_disable(old_crtc_state); 928 } 929 930 if (is_vid_mode(intel_dsi)) { 931 for_each_dsi_port(port, intel_dsi->ports) 932 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 933 934 intel_dsi_port_disable(encoder); 935 usleep_range(2000, 5000); 936 } 937 938 intel_dsi_unprepare(encoder); 939 940 /* 941 * if disable packets are sent before sending shutdown packet then in 942 * some next enable sequence send turn on packet error is observed 943 */ 944 if (is_cmd_mode(intel_dsi)) 945 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF); 946 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 947 948 /* Transition to LP-00 */ 949 intel_dsi_clear_device_ready(encoder); 950 951 if (IS_BROXTON(dev_priv)) { 952 /* Power down DSI regulator to save power */ 953 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 954 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 955 HS_IO_CTRL_SELECT); 956 957 /* Add MIPI IO reset programming for modeset */ 958 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); 959 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, 960 val & ~MIPIO_RST_CTRL); 961 } 962 963 if (IS_GEN9_LP(dev_priv)) { 964 bxt_dsi_pll_disable(encoder); 965 } else { 966 u32 val; 967 968 vlv_dsi_pll_disable(encoder); 969 970 val = intel_de_read(dev_priv, DSPCLK_GATE_D); 971 val &= ~DPOUNIT_CLOCK_GATE_DISABLE; 972 intel_de_write(dev_priv, DSPCLK_GATE_D, val); 973 } 974 975 /* Assert reset */ 976 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 977 978 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); 979 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 980 981 /* 982 * FIXME As we do with eDP, just make a note of the time here 983 * and perform the wait before the next panel power on. 984 */ 985 intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay); 986 } 987 988 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 989 enum pipe *pipe) 990 { 991 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 992 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 993 intel_wakeref_t wakeref; 994 enum port port; 995 bool active = false; 996 997 drm_dbg_kms(&dev_priv->drm, "\n"); 998 999 wakeref = intel_display_power_get_if_enabled(dev_priv, 1000 encoder->power_domain); 1001 if (!wakeref) 1002 return false; 1003 1004 /* 1005 * On Broxton the PLL needs to be enabled with a valid divider 1006 * configuration, otherwise accessing DSI registers will hang the 1007 * machine. See BSpec North Display Engine registers/MIPI[BXT]. 1008 */ 1009 if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv)) 1010 goto out_put_power; 1011 1012 /* XXX: this only works for one DSI output */ 1013 for_each_dsi_port(port, intel_dsi->ports) { 1014 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? 1015 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 1016 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE; 1017 1018 /* 1019 * Due to some hardware limitations on VLV/CHV, the DPI enable 1020 * bit in port C control register does not get set. As a 1021 * workaround, check pipe B conf instead. 1022 */ 1023 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1024 port == PORT_C) 1025 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; 1026 1027 /* Try command mode if video mode not enabled */ 1028 if (!enabled) { 1029 u32 tmp = intel_de_read(dev_priv, 1030 MIPI_DSI_FUNC_PRG(port)); 1031 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; 1032 } 1033 1034 if (!enabled) 1035 continue; 1036 1037 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) 1038 continue; 1039 1040 if (IS_GEN9_LP(dev_priv)) { 1041 u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1042 tmp &= BXT_PIPE_SELECT_MASK; 1043 tmp >>= BXT_PIPE_SELECT_SHIFT; 1044 1045 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) 1046 continue; 1047 1048 *pipe = tmp; 1049 } else { 1050 *pipe = port == PORT_A ? PIPE_A : PIPE_B; 1051 } 1052 1053 active = true; 1054 break; 1055 } 1056 1057 out_put_power: 1058 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1059 1060 return active; 1061 } 1062 1063 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, 1064 struct intel_crtc_state *pipe_config) 1065 { 1066 struct drm_device *dev = encoder->base.dev; 1067 struct drm_i915_private *dev_priv = to_i915(dev); 1068 struct drm_display_mode *adjusted_mode = 1069 &pipe_config->hw.adjusted_mode; 1070 struct drm_display_mode *adjusted_mode_sw; 1071 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1072 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1073 unsigned int lane_count = intel_dsi->lane_count; 1074 unsigned int bpp, fmt; 1075 enum port port; 1076 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1077 u16 hfp_sw, hsync_sw, hbp_sw; 1078 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, 1079 crtc_hblank_start_sw, crtc_hblank_end_sw; 1080 1081 /* FIXME: hw readout should not depend on SW state */ 1082 adjusted_mode_sw = &crtc->config->hw.adjusted_mode; 1083 1084 /* 1085 * Atleast one port is active as encoder->get_config called only if 1086 * encoder->get_hw_state() returns true. 1087 */ 1088 for_each_dsi_port(port, intel_dsi->ports) { 1089 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) 1090 break; 1091 } 1092 1093 fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; 1094 bpp = mipi_dsi_pixel_format_to_bpp( 1095 pixel_format_from_register_bits(fmt)); 1096 1097 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1098 1099 /* Enable Frame time stamo based scanline reporting */ 1100 pipe_config->mode_flags |= 1101 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 1102 1103 /* In terms of pixels */ 1104 adjusted_mode->crtc_hdisplay = 1105 intel_de_read(dev_priv, 1106 BXT_MIPI_TRANS_HACTIVE(port)); 1107 adjusted_mode->crtc_vdisplay = 1108 intel_de_read(dev_priv, 1109 BXT_MIPI_TRANS_VACTIVE(port)); 1110 adjusted_mode->crtc_vtotal = 1111 intel_de_read(dev_priv, 1112 BXT_MIPI_TRANS_VTOTAL(port)); 1113 1114 hactive = adjusted_mode->crtc_hdisplay; 1115 hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); 1116 1117 /* 1118 * Meaningful for video mode non-burst sync pulse mode only, 1119 * can be zero for non-burst sync events and burst modes 1120 */ 1121 hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); 1122 hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); 1123 1124 /* harizontal values are in terms of high speed byte clock */ 1125 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, 1126 intel_dsi->burst_mode_ratio); 1127 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, 1128 intel_dsi->burst_mode_ratio); 1129 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, 1130 intel_dsi->burst_mode_ratio); 1131 1132 if (intel_dsi->dual_link) { 1133 hfp *= 2; 1134 hsync *= 2; 1135 hbp *= 2; 1136 } 1137 1138 /* vertical values are in terms of lines */ 1139 vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); 1140 vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); 1141 vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port)); 1142 1143 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; 1144 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; 1145 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; 1146 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1147 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1148 1149 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; 1150 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; 1151 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1152 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1153 1154 /* 1155 * In BXT DSI there is no regs programmed with few horizontal timings 1156 * in Pixels but txbyteclkhs.. So retrieval process adds some 1157 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. 1158 * Actually here for the given adjusted_mode, we are calculating the 1159 * value programmed to the port and then back to the horizontal timing 1160 * param in pixels. This is the expected value, including roundup errors 1161 * And if that is same as retrieved value from port, then 1162 * (HW state) adjusted_mode's horizontal timings are corrected to 1163 * match with SW state to nullify the errors. 1164 */ 1165 /* Calculating the value programmed to the Port register */ 1166 hfp_sw = adjusted_mode_sw->crtc_hsync_start - 1167 adjusted_mode_sw->crtc_hdisplay; 1168 hsync_sw = adjusted_mode_sw->crtc_hsync_end - 1169 adjusted_mode_sw->crtc_hsync_start; 1170 hbp_sw = adjusted_mode_sw->crtc_htotal - 1171 adjusted_mode_sw->crtc_hsync_end; 1172 1173 if (intel_dsi->dual_link) { 1174 hfp_sw /= 2; 1175 hsync_sw /= 2; 1176 hbp_sw /= 2; 1177 } 1178 1179 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, 1180 intel_dsi->burst_mode_ratio); 1181 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, 1182 intel_dsi->burst_mode_ratio); 1183 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, 1184 intel_dsi->burst_mode_ratio); 1185 1186 /* Reverse calculating the adjusted mode parameters from port reg vals*/ 1187 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, 1188 intel_dsi->burst_mode_ratio); 1189 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, 1190 intel_dsi->burst_mode_ratio); 1191 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, 1192 intel_dsi->burst_mode_ratio); 1193 1194 if (intel_dsi->dual_link) { 1195 hfp_sw *= 2; 1196 hsync_sw *= 2; 1197 hbp_sw *= 2; 1198 } 1199 1200 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + 1201 hsync_sw + hbp_sw; 1202 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; 1203 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; 1204 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; 1205 crtc_hblank_end_sw = crtc_htotal_sw; 1206 1207 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) 1208 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; 1209 1210 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) 1211 adjusted_mode->crtc_hsync_start = 1212 adjusted_mode_sw->crtc_hsync_start; 1213 1214 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) 1215 adjusted_mode->crtc_hsync_end = 1216 adjusted_mode_sw->crtc_hsync_end; 1217 1218 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) 1219 adjusted_mode->crtc_hblank_start = 1220 adjusted_mode_sw->crtc_hblank_start; 1221 1222 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) 1223 adjusted_mode->crtc_hblank_end = 1224 adjusted_mode_sw->crtc_hblank_end; 1225 } 1226 1227 static void intel_dsi_get_config(struct intel_encoder *encoder, 1228 struct intel_crtc_state *pipe_config) 1229 { 1230 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1231 u32 pclk; 1232 drm_dbg_kms(&dev_priv->drm, "\n"); 1233 1234 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1235 1236 if (IS_GEN9_LP(dev_priv)) { 1237 bxt_dsi_get_pipe_config(encoder, pipe_config); 1238 pclk = bxt_dsi_get_pclk(encoder, pipe_config); 1239 } else { 1240 pclk = vlv_dsi_get_pclk(encoder, pipe_config); 1241 } 1242 1243 if (pclk) { 1244 pipe_config->hw.adjusted_mode.crtc_clock = pclk; 1245 pipe_config->port_clock = pclk; 1246 } 1247 } 1248 1249 /* return txclkesc cycles in terms of divider and duration in us */ 1250 static u16 txclkesc(u32 divider, unsigned int us) 1251 { 1252 switch (divider) { 1253 case ESCAPE_CLOCK_DIVIDER_1: 1254 default: 1255 return 20 * us; 1256 case ESCAPE_CLOCK_DIVIDER_2: 1257 return 10 * us; 1258 case ESCAPE_CLOCK_DIVIDER_4: 1259 return 5 * us; 1260 } 1261 } 1262 1263 static void set_dsi_timings(struct drm_encoder *encoder, 1264 const struct drm_display_mode *adjusted_mode) 1265 { 1266 struct drm_device *dev = encoder->dev; 1267 struct drm_i915_private *dev_priv = to_i915(dev); 1268 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1269 enum port port; 1270 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1271 unsigned int lane_count = intel_dsi->lane_count; 1272 1273 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1274 1275 hactive = adjusted_mode->crtc_hdisplay; 1276 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; 1277 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1278 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; 1279 1280 if (intel_dsi->dual_link) { 1281 hactive /= 2; 1282 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1283 hactive += intel_dsi->pixel_overlap; 1284 hfp /= 2; 1285 hsync /= 2; 1286 hbp /= 2; 1287 } 1288 1289 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; 1290 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; 1291 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; 1292 1293 /* horizontal values are in terms of high speed byte clock */ 1294 hactive = txbyteclkhs(hactive, bpp, lane_count, 1295 intel_dsi->burst_mode_ratio); 1296 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1297 hsync = txbyteclkhs(hsync, bpp, lane_count, 1298 intel_dsi->burst_mode_ratio); 1299 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1300 1301 for_each_dsi_port(port, intel_dsi->ports) { 1302 if (IS_GEN9_LP(dev_priv)) { 1303 /* 1304 * Program hdisplay and vdisplay on MIPI transcoder. 1305 * This is different from calculated hactive and 1306 * vactive, as they are calculated per channel basis, 1307 * whereas these values should be based on resolution. 1308 */ 1309 intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), 1310 adjusted_mode->crtc_hdisplay); 1311 intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), 1312 adjusted_mode->crtc_vdisplay); 1313 intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), 1314 adjusted_mode->crtc_vtotal); 1315 } 1316 1317 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), 1318 hactive); 1319 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); 1320 1321 /* meaningful for video mode non-burst sync pulse mode only, 1322 * can be zero for non-burst sync events and burst modes */ 1323 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), 1324 hsync); 1325 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); 1326 1327 /* vertical values are in terms of lines */ 1328 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); 1329 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), 1330 vsync); 1331 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); 1332 } 1333 } 1334 1335 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) 1336 { 1337 switch (fmt) { 1338 case MIPI_DSI_FMT_RGB888: 1339 return VID_MODE_FORMAT_RGB888; 1340 case MIPI_DSI_FMT_RGB666: 1341 return VID_MODE_FORMAT_RGB666; 1342 case MIPI_DSI_FMT_RGB666_PACKED: 1343 return VID_MODE_FORMAT_RGB666_PACKED; 1344 case MIPI_DSI_FMT_RGB565: 1345 return VID_MODE_FORMAT_RGB565; 1346 default: 1347 MISSING_CASE(fmt); 1348 return VID_MODE_FORMAT_RGB666; 1349 } 1350 } 1351 1352 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 1353 const struct intel_crtc_state *pipe_config) 1354 { 1355 struct drm_encoder *encoder = &intel_encoder->base; 1356 struct drm_device *dev = encoder->dev; 1357 struct drm_i915_private *dev_priv = to_i915(dev); 1358 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 1359 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1360 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1361 enum port port; 1362 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1363 u32 val, tmp; 1364 u16 mode_hdisplay; 1365 1366 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(intel_crtc->pipe)); 1367 1368 mode_hdisplay = adjusted_mode->crtc_hdisplay; 1369 1370 if (intel_dsi->dual_link) { 1371 mode_hdisplay /= 2; 1372 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1373 mode_hdisplay += intel_dsi->pixel_overlap; 1374 } 1375 1376 for_each_dsi_port(port, intel_dsi->ports) { 1377 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1378 /* 1379 * escape clock divider, 20MHz, shared for A and C. 1380 * device ready must be off when doing this! txclkesc? 1381 */ 1382 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 1383 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 1384 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), 1385 tmp | ESCAPE_CLOCK_DIVIDER_1); 1386 1387 /* read request priority is per pipe */ 1388 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1389 tmp &= ~READ_REQUEST_PRIORITY_MASK; 1390 intel_de_write(dev_priv, MIPI_CTRL(port), 1391 tmp | READ_REQUEST_PRIORITY_HIGH); 1392 } else if (IS_GEN9_LP(dev_priv)) { 1393 enum pipe pipe = intel_crtc->pipe; 1394 1395 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1396 tmp &= ~BXT_PIPE_SELECT_MASK; 1397 1398 tmp |= BXT_PIPE_SELECT(pipe); 1399 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); 1400 } 1401 1402 /* XXX: why here, why like this? handling in irq handler?! */ 1403 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); 1404 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); 1405 1406 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), 1407 intel_dsi->dphy_reg); 1408 1409 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), 1410 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); 1411 } 1412 1413 set_dsi_timings(encoder, adjusted_mode); 1414 1415 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; 1416 if (is_cmd_mode(intel_dsi)) { 1417 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; 1418 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ 1419 } else { 1420 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; 1421 val |= pixel_format_to_reg(intel_dsi->pixel_format); 1422 } 1423 1424 tmp = 0; 1425 if (intel_dsi->eotp_pkt == 0) 1426 tmp |= EOT_DISABLE; 1427 if (intel_dsi->clock_stop) 1428 tmp |= CLOCKSTOP; 1429 1430 if (IS_GEN9_LP(dev_priv)) { 1431 tmp |= BXT_DPHY_DEFEATURE_EN; 1432 if (!is_cmd_mode(intel_dsi)) 1433 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; 1434 } 1435 1436 for_each_dsi_port(port, intel_dsi->ports) { 1437 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); 1438 1439 /* timeouts for recovery. one frame IIUC. if counter expires, 1440 * EOT and stop state. */ 1441 1442 /* 1443 * In burst mode, value greater than one DPI line Time in byte 1444 * clock (txbyteclkhs) To timeout this timer 1+ of the above 1445 * said value is recommended. 1446 * 1447 * In non-burst mode, Value greater than one DPI frame time in 1448 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1449 * said value is recommended. 1450 * 1451 * In DBI only mode, value greater than one DBI frame time in 1452 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1453 * said value is recommended. 1454 */ 1455 1456 if (is_vid_mode(intel_dsi) && 1457 intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 1458 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), 1459 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1460 } else { 1461 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), 1462 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1463 } 1464 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), 1465 intel_dsi->lp_rx_timeout); 1466 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), 1467 intel_dsi->turn_arnd_val); 1468 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), 1469 intel_dsi->rst_timer_val); 1470 1471 /* dphy stuff */ 1472 1473 /* in terms of low power clock */ 1474 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), 1475 txclkesc(intel_dsi->escape_clk_div, 100)); 1476 1477 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { 1478 /* 1479 * BXT spec says write MIPI_INIT_COUNT for 1480 * both the ports, even if only one is 1481 * getting used. So write the other port 1482 * if not in dual link mode. 1483 */ 1484 intel_de_write(dev_priv, 1485 MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A), 1486 intel_dsi->init_count); 1487 } 1488 1489 /* recovery disables */ 1490 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); 1491 1492 /* in terms of low power clock */ 1493 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), 1494 intel_dsi->init_count); 1495 1496 /* in terms of txbyteclkhs. actual high to low switch + 1497 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. 1498 * 1499 * XXX: write MIPI_STOP_STATE_STALL? 1500 */ 1501 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), 1502 intel_dsi->hs_to_lp_count); 1503 1504 /* XXX: low power clock equivalence in terms of byte clock. 1505 * the number of byte clocks occupied in one low power clock. 1506 * based on txbyteclkhs and txclkesc. 1507 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL 1508 * ) / 105.??? 1509 */ 1510 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), 1511 intel_dsi->lp_byte_clk); 1512 1513 if (IS_GEMINILAKE(dev_priv)) { 1514 intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), 1515 intel_dsi->lp_byte_clk); 1516 /* Shadow of DPHY reg */ 1517 intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), 1518 intel_dsi->dphy_reg); 1519 } 1520 1521 /* the bw essential for transmitting 16 long packets containing 1522 * 252 bytes meant for dcs write memory command is programmed in 1523 * this register in terms of byte clocks. based on dsi transfer 1524 * rate and the number of lanes configured the time taken to 1525 * transmit 16 long packets in a dsi stream varies. */ 1526 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), 1527 intel_dsi->bw_timer); 1528 1529 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), 1530 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); 1531 1532 if (is_vid_mode(intel_dsi)) 1533 /* Some panels might have resolution which is not a 1534 * multiple of 64 like 1366 x 768. Enable RANDOM 1535 * resolution support for such panels by default */ 1536 intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), 1537 intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_format | IP_TG_CONFIG | RANDOM_DPI_DISPLAY_RESOLUTION); 1538 } 1539 } 1540 1541 static void intel_dsi_unprepare(struct intel_encoder *encoder) 1542 { 1543 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1544 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1545 enum port port; 1546 u32 val; 1547 1548 if (IS_GEMINILAKE(dev_priv)) 1549 return; 1550 1551 for_each_dsi_port(port, intel_dsi->ports) { 1552 /* Panel commands can be sent when clock is in LP11 */ 1553 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); 1554 1555 if (IS_GEN9_LP(dev_priv)) 1556 bxt_dsi_reset_clocks(encoder, port); 1557 else 1558 vlv_dsi_reset_clocks(encoder, port); 1559 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); 1560 1561 val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)); 1562 val &= ~VID_MODE_FORMAT_MASK; 1563 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); 1564 1565 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); 1566 } 1567 } 1568 1569 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) 1570 { 1571 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1572 1573 intel_dsi_vbt_gpio_cleanup(intel_dsi); 1574 intel_encoder_destroy(encoder); 1575 } 1576 1577 static const struct drm_encoder_funcs intel_dsi_funcs = { 1578 .destroy = intel_dsi_encoder_destroy, 1579 }; 1580 1581 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 1582 .get_modes = intel_dsi_get_modes, 1583 .mode_valid = intel_dsi_mode_valid, 1584 .atomic_check = intel_digital_connector_atomic_check, 1585 }; 1586 1587 static const struct drm_connector_funcs intel_dsi_connector_funcs = { 1588 .late_register = intel_connector_register, 1589 .early_unregister = intel_connector_unregister, 1590 .destroy = intel_connector_destroy, 1591 .fill_modes = drm_helper_probe_single_connector_modes, 1592 .atomic_get_property = intel_digital_connector_atomic_get_property, 1593 .atomic_set_property = intel_digital_connector_atomic_set_property, 1594 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1595 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1596 }; 1597 1598 static void vlv_dsi_add_properties(struct intel_connector *connector) 1599 { 1600 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1601 1602 if (connector->panel.fixed_mode) { 1603 u32 allowed_scalers; 1604 1605 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); 1606 if (!HAS_GMCH(dev_priv)) 1607 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); 1608 1609 drm_connector_attach_scaling_mode_property(&connector->base, 1610 allowed_scalers); 1611 1612 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1613 1614 drm_connector_set_panel_orientation_with_quirk( 1615 &connector->base, 1616 intel_dsi_get_panel_orientation(connector), 1617 connector->panel.fixed_mode->hdisplay, 1618 connector->panel.fixed_mode->vdisplay); 1619 } 1620 } 1621 1622 #define NS_KHZ_RATIO 1000000 1623 1624 #define PREPARE_CNT_MAX 0x3F 1625 #define EXIT_ZERO_CNT_MAX 0x3F 1626 #define CLK_ZERO_CNT_MAX 0xFF 1627 #define TRAIL_CNT_MAX 0x1F 1628 1629 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) 1630 { 1631 struct drm_device *dev = intel_dsi->base.base.dev; 1632 struct drm_i915_private *dev_priv = to_i915(dev); 1633 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1634 u32 tlpx_ns, extra_byte_count, tlpx_ui; 1635 u32 ui_num, ui_den; 1636 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1637 u32 ths_prepare_ns, tclk_trail_ns; 1638 u32 tclk_prepare_clkzero, ths_prepare_hszero; 1639 u32 lp_to_hs_switch, hs_to_lp_switch; 1640 u32 mul; 1641 1642 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1643 1644 switch (intel_dsi->lane_count) { 1645 case 1: 1646 case 2: 1647 extra_byte_count = 2; 1648 break; 1649 case 3: 1650 extra_byte_count = 4; 1651 break; 1652 case 4: 1653 default: 1654 extra_byte_count = 3; 1655 break; 1656 } 1657 1658 /* in Kbps */ 1659 ui_num = NS_KHZ_RATIO; 1660 ui_den = intel_dsi_bitrate(intel_dsi); 1661 1662 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; 1663 ths_prepare_hszero = mipi_config->ths_prepare_hszero; 1664 1665 /* 1666 * B060 1667 * LP byte clock = TLPX/ (8UI) 1668 */ 1669 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); 1670 1671 /* DDR clock period = 2 * UI 1672 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ) 1673 * UI(nsec) = 10^6 / bitrate 1674 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate 1675 * DDR clock count = ns_value / DDR clock period 1676 * 1677 * For GEMINILAKE dphy_param_reg will be programmed in terms of 1678 * HS byte clock count for other platform in HS ddr clock count 1679 */ 1680 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; 1681 ths_prepare_ns = max(mipi_config->ths_prepare, 1682 mipi_config->tclk_prepare); 1683 1684 /* prepare count */ 1685 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul); 1686 1687 if (prepare_cnt > PREPARE_CNT_MAX) { 1688 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", 1689 prepare_cnt); 1690 prepare_cnt = PREPARE_CNT_MAX; 1691 } 1692 1693 /* exit zero count */ 1694 exit_zero_cnt = DIV_ROUND_UP( 1695 (ths_prepare_hszero - ths_prepare_ns) * ui_den, 1696 ui_num * mul 1697 ); 1698 1699 /* 1700 * Exit zero is unified val ths_zero and ths_exit 1701 * minimum value for ths_exit = 110ns 1702 * min (exit_zero_cnt * 2) = 110/UI 1703 * exit_zero_cnt = 55/UI 1704 */ 1705 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num) 1706 exit_zero_cnt += 1; 1707 1708 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) { 1709 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", 1710 exit_zero_cnt); 1711 exit_zero_cnt = EXIT_ZERO_CNT_MAX; 1712 } 1713 1714 /* clk zero count */ 1715 clk_zero_cnt = DIV_ROUND_UP( 1716 (tclk_prepare_clkzero - ths_prepare_ns) 1717 * ui_den, ui_num * mul); 1718 1719 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) { 1720 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", 1721 clk_zero_cnt); 1722 clk_zero_cnt = CLK_ZERO_CNT_MAX; 1723 } 1724 1725 /* trail count */ 1726 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1727 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul); 1728 1729 if (trail_cnt > TRAIL_CNT_MAX) { 1730 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", 1731 trail_cnt); 1732 trail_cnt = TRAIL_CNT_MAX; 1733 } 1734 1735 /* B080 */ 1736 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | 1737 clk_zero_cnt << 8 | prepare_cnt; 1738 1739 /* 1740 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT * 1741 * mul + 10UI + Extra Byte Count 1742 * 1743 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count 1744 * Extra Byte Count is calculated according to number of lanes. 1745 * High Low Switch Count is the Max of LP to HS and 1746 * HS to LP switch count 1747 * 1748 */ 1749 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); 1750 1751 /* B044 */ 1752 /* FIXME: 1753 * The comment above does not match with the code */ 1754 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul + 1755 exit_zero_cnt * mul + 10, 8); 1756 1757 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); 1758 1759 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); 1760 intel_dsi->hs_to_lp_count += extra_byte_count; 1761 1762 /* B088 */ 1763 /* LP -> HS for clock lanes 1764 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + 1765 * extra byte count 1766 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * 1767 * 2(in UI) + extra byte count 1768 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / 1769 * 8 + extra byte count 1770 */ 1771 intel_dsi->clk_lp_to_hs_count = 1772 DIV_ROUND_UP( 1773 4 * tlpx_ui + prepare_cnt * 2 + 1774 clk_zero_cnt * 2, 1775 8); 1776 1777 intel_dsi->clk_lp_to_hs_count += extra_byte_count; 1778 1779 /* HS->LP for Clock Lanes 1780 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + 1781 * Extra byte count 1782 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count 1783 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + 1784 * Extra byte count 1785 */ 1786 intel_dsi->clk_hs_to_lp_count = 1787 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, 1788 8); 1789 intel_dsi->clk_hs_to_lp_count += extra_byte_count; 1790 1791 intel_dsi_log_params(intel_dsi); 1792 } 1793 1794 void vlv_dsi_init(struct drm_i915_private *dev_priv) 1795 { 1796 struct drm_device *dev = &dev_priv->drm; 1797 struct intel_dsi *intel_dsi; 1798 struct intel_encoder *intel_encoder; 1799 struct drm_encoder *encoder; 1800 struct intel_connector *intel_connector; 1801 struct drm_connector *connector; 1802 struct drm_display_mode *current_mode, *fixed_mode; 1803 enum port port; 1804 enum pipe pipe; 1805 1806 drm_dbg_kms(&dev_priv->drm, "\n"); 1807 1808 /* There is no detection method for MIPI so rely on VBT */ 1809 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1810 return; 1811 1812 if (IS_GEN9_LP(dev_priv)) 1813 dev_priv->mipi_mmio_base = BXT_MIPI_BASE; 1814 else 1815 dev_priv->mipi_mmio_base = VLV_MIPI_BASE; 1816 1817 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1818 if (!intel_dsi) 1819 return; 1820 1821 intel_connector = intel_connector_alloc(); 1822 if (!intel_connector) { 1823 kfree(intel_dsi); 1824 return; 1825 } 1826 1827 intel_encoder = &intel_dsi->base; 1828 encoder = &intel_encoder->base; 1829 intel_dsi->attached_connector = intel_connector; 1830 1831 connector = &intel_connector->base; 1832 1833 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, 1834 "DSI %c", port_name(port)); 1835 1836 intel_encoder->compute_config = intel_dsi_compute_config; 1837 intel_encoder->pre_enable = intel_dsi_pre_enable; 1838 if (IS_GEN9_LP(dev_priv)) 1839 intel_encoder->enable = bxt_dsi_enable; 1840 intel_encoder->disable = intel_dsi_disable; 1841 intel_encoder->post_disable = intel_dsi_post_disable; 1842 intel_encoder->get_hw_state = intel_dsi_get_hw_state; 1843 intel_encoder->get_config = intel_dsi_get_config; 1844 intel_encoder->update_pipe = intel_panel_update_backlight; 1845 1846 intel_connector->get_hw_state = intel_connector_get_hw_state; 1847 1848 intel_encoder->port = port; 1849 intel_encoder->type = INTEL_OUTPUT_DSI; 1850 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1851 intel_encoder->cloneable = 0; 1852 1853 /* 1854 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI 1855 * port C. BXT isn't limited like this. 1856 */ 1857 if (IS_GEN9_LP(dev_priv)) 1858 intel_encoder->pipe_mask = ~0; 1859 else if (port == PORT_A) 1860 intel_encoder->pipe_mask = BIT(PIPE_A); 1861 else 1862 intel_encoder->pipe_mask = BIT(PIPE_B); 1863 1864 if (dev_priv->vbt.dsi.config->dual_link) 1865 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); 1866 else 1867 intel_dsi->ports = BIT(port); 1868 1869 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 1870 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 1871 1872 /* Create a DSI host (and a device) for each port. */ 1873 for_each_dsi_port(port, intel_dsi->ports) { 1874 struct intel_dsi_host *host; 1875 1876 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops, 1877 port); 1878 if (!host) 1879 goto err; 1880 1881 intel_dsi->dsi_hosts[port] = host; 1882 } 1883 1884 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1885 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 1886 goto err; 1887 } 1888 1889 /* Use clock read-back from current hw-state for fastboot */ 1890 current_mode = intel_encoder_current_mode(intel_encoder); 1891 if (current_mode) { 1892 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", 1893 intel_dsi->pclk, current_mode->clock); 1894 if (intel_fuzzy_clock_check(intel_dsi->pclk, 1895 current_mode->clock)) { 1896 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); 1897 intel_dsi->pclk = current_mode->clock; 1898 } 1899 1900 kfree(current_mode); 1901 } 1902 1903 vlv_dphy_param_init(intel_dsi); 1904 1905 intel_dsi_vbt_gpio_init(intel_dsi, 1906 intel_dsi_get_hw_state(intel_encoder, &pipe)); 1907 1908 drm_connector_init(dev, connector, &intel_dsi_connector_funcs, 1909 DRM_MODE_CONNECTOR_DSI); 1910 1911 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); 1912 1913 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ 1914 connector->interlace_allowed = false; 1915 connector->doublescan_allowed = false; 1916 1917 intel_connector_attach_encoder(intel_connector, intel_encoder); 1918 1919 mutex_lock(&dev->mode_config.mutex); 1920 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 1921 mutex_unlock(&dev->mode_config.mutex); 1922 1923 if (!fixed_mode) { 1924 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); 1925 goto err_cleanup_connector; 1926 } 1927 1928 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 1929 intel_panel_setup_backlight(connector, INVALID_PIPE); 1930 1931 vlv_dsi_add_properties(intel_connector); 1932 1933 return; 1934 1935 err_cleanup_connector: 1936 drm_connector_cleanup(&intel_connector->base); 1937 err: 1938 drm_encoder_cleanup(&intel_encoder->base); 1939 kfree(intel_dsi); 1940 kfree(intel_connector); 1941 } 1942