1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Jani Nikula <jani.nikula@intel.com> 24 */ 25 26 #include <linux/slab.h> 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_crtc.h> 30 #include <drm/drm_edid.h> 31 #include <drm/drm_mipi_dsi.h> 32 33 #include "i915_drv.h" 34 #include "intel_atomic.h" 35 #include "intel_connector.h" 36 #include "intel_display_types.h" 37 #include "intel_dsi.h" 38 #include "intel_fifo_underrun.h" 39 #include "intel_panel.h" 40 #include "intel_sideband.h" 41 42 /* return pixels in terms of txbyteclkhs */ 43 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, 44 u16 burst_mode_ratio) 45 { 46 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, 47 8 * 100), lane_count); 48 } 49 50 /* return pixels equvalent to txbyteclkhs */ 51 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, 52 u16 burst_mode_ratio) 53 { 54 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), 55 (bpp * burst_mode_ratio)); 56 } 57 58 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 59 { 60 /* It just so happens the VBT matches register contents. */ 61 switch (fmt) { 62 case VID_MODE_FORMAT_RGB888: 63 return MIPI_DSI_FMT_RGB888; 64 case VID_MODE_FORMAT_RGB666: 65 return MIPI_DSI_FMT_RGB666; 66 case VID_MODE_FORMAT_RGB666_PACKED: 67 return MIPI_DSI_FMT_RGB666_PACKED; 68 case VID_MODE_FORMAT_RGB565: 69 return MIPI_DSI_FMT_RGB565; 70 default: 71 MISSING_CASE(fmt); 72 return MIPI_DSI_FMT_RGB666; 73 } 74 } 75 76 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) 77 { 78 struct drm_encoder *encoder = &intel_dsi->base.base; 79 struct drm_device *dev = encoder->dev; 80 struct drm_i915_private *dev_priv = to_i915(dev); 81 u32 mask; 82 83 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | 84 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; 85 86 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), 87 mask, 100)) 88 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); 89 } 90 91 static void write_data(struct drm_i915_private *dev_priv, 92 i915_reg_t reg, 93 const u8 *data, u32 len) 94 { 95 u32 i, j; 96 97 for (i = 0; i < len; i += 4) { 98 u32 val = 0; 99 100 for (j = 0; j < min_t(u32, len - i, 4); j++) 101 val |= *data++ << 8 * j; 102 103 intel_de_write(dev_priv, reg, val); 104 } 105 } 106 107 static void read_data(struct drm_i915_private *dev_priv, 108 i915_reg_t reg, 109 u8 *data, u32 len) 110 { 111 u32 i, j; 112 113 for (i = 0; i < len; i += 4) { 114 u32 val = intel_de_read(dev_priv, reg); 115 116 for (j = 0; j < min_t(u32, len - i, 4); j++) 117 *data++ = val >> 8 * j; 118 } 119 } 120 121 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, 122 const struct mipi_dsi_msg *msg) 123 { 124 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 125 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; 126 struct drm_i915_private *dev_priv = to_i915(dev); 127 enum port port = intel_dsi_host->port; 128 struct mipi_dsi_packet packet; 129 ssize_t ret; 130 const u8 *header, *data; 131 i915_reg_t data_reg, ctrl_reg; 132 u32 data_mask, ctrl_mask; 133 134 ret = mipi_dsi_create_packet(&packet, msg); 135 if (ret < 0) 136 return ret; 137 138 header = packet.header; 139 data = packet.payload; 140 141 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 142 data_reg = MIPI_LP_GEN_DATA(port); 143 data_mask = LP_DATA_FIFO_FULL; 144 ctrl_reg = MIPI_LP_GEN_CTRL(port); 145 ctrl_mask = LP_CTRL_FIFO_FULL; 146 } else { 147 data_reg = MIPI_HS_GEN_DATA(port); 148 data_mask = HS_DATA_FIFO_FULL; 149 ctrl_reg = MIPI_HS_GEN_CTRL(port); 150 ctrl_mask = HS_CTRL_FIFO_FULL; 151 } 152 153 /* note: this is never true for reads */ 154 if (packet.payload_length) { 155 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 156 data_mask, 50)) 157 drm_err(&dev_priv->drm, 158 "Timeout waiting for HS/LP DATA FIFO !full\n"); 159 160 write_data(dev_priv, data_reg, packet.payload, 161 packet.payload_length); 162 } 163 164 if (msg->rx_len) { 165 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 166 GEN_READ_DATA_AVAIL); 167 } 168 169 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 170 ctrl_mask, 50)) { 171 drm_err(&dev_priv->drm, 172 "Timeout waiting for HS/LP CTRL FIFO !full\n"); 173 } 174 175 intel_de_write(dev_priv, ctrl_reg, 176 header[2] << 16 | header[1] << 8 | header[0]); 177 178 /* ->rx_len is set only for reads */ 179 if (msg->rx_len) { 180 data_mask = GEN_READ_DATA_AVAIL; 181 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), 182 data_mask, 50)) 183 drm_err(&dev_priv->drm, 184 "Timeout waiting for read data.\n"); 185 186 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); 187 } 188 189 /* XXX: fix for reads and writes */ 190 return 4 + packet.payload_length; 191 } 192 193 static int intel_dsi_host_attach(struct mipi_dsi_host *host, 194 struct mipi_dsi_device *dsi) 195 { 196 return 0; 197 } 198 199 static int intel_dsi_host_detach(struct mipi_dsi_host *host, 200 struct mipi_dsi_device *dsi) 201 { 202 return 0; 203 } 204 205 static const struct mipi_dsi_host_ops intel_dsi_host_ops = { 206 .attach = intel_dsi_host_attach, 207 .detach = intel_dsi_host_detach, 208 .transfer = intel_dsi_host_transfer, 209 }; 210 211 /* 212 * send a video mode command 213 * 214 * XXX: commands with data in MIPI_DPI_DATA? 215 */ 216 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, 217 enum port port) 218 { 219 struct drm_encoder *encoder = &intel_dsi->base.base; 220 struct drm_device *dev = encoder->dev; 221 struct drm_i915_private *dev_priv = to_i915(dev); 222 u32 mask; 223 224 /* XXX: pipe, hs */ 225 if (hs) 226 cmd &= ~DPI_LP_MODE; 227 else 228 cmd |= DPI_LP_MODE; 229 230 /* clear bit */ 231 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); 232 233 /* XXX: old code skips write if control unchanged */ 234 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) 235 drm_dbg_kms(&dev_priv->drm, 236 "Same special packet %02x twice in a row.\n", cmd); 237 238 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); 239 240 mask = SPL_PKT_SENT_INTERRUPT; 241 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) 242 drm_err(&dev_priv->drm, 243 "Video mode command 0x%08x send failed.\n", cmd); 244 245 return 0; 246 } 247 248 static void band_gap_reset(struct drm_i915_private *dev_priv) 249 { 250 vlv_flisdsi_get(dev_priv); 251 252 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); 253 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); 254 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); 255 udelay(150); 256 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); 257 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); 258 259 vlv_flisdsi_put(dev_priv); 260 } 261 262 static int intel_dsi_compute_config(struct intel_encoder *encoder, 263 struct intel_crtc_state *pipe_config, 264 struct drm_connector_state *conn_state) 265 { 266 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 267 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 268 base); 269 struct intel_connector *intel_connector = intel_dsi->attached_connector; 270 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 271 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 272 int ret; 273 274 drm_dbg_kms(&dev_priv->drm, "\n"); 275 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 276 277 if (fixed_mode) { 278 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 279 280 if (HAS_GMCH(dev_priv)) 281 ret = intel_gmch_panel_fitting(pipe_config, conn_state); 282 else 283 ret = intel_pch_panel_fitting(pipe_config, conn_state); 284 if (ret) 285 return ret; 286 } 287 288 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 289 return -EINVAL; 290 291 /* DSI uses short packets for sync events, so clear mode flags for DSI */ 292 adjusted_mode->flags = 0; 293 294 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 295 pipe_config->pipe_bpp = 24; 296 else 297 pipe_config->pipe_bpp = 18; 298 299 if (IS_GEN9_LP(dev_priv)) { 300 /* Enable Frame time stamp based scanline reporting */ 301 pipe_config->mode_flags |= 302 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 303 304 /* Dual link goes to DSI transcoder A. */ 305 if (intel_dsi->ports == BIT(PORT_C)) 306 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; 307 else 308 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; 309 310 ret = bxt_dsi_pll_compute(encoder, pipe_config); 311 if (ret) 312 return -EINVAL; 313 } else { 314 ret = vlv_dsi_pll_compute(encoder, pipe_config); 315 if (ret) 316 return -EINVAL; 317 } 318 319 pipe_config->clock_set = true; 320 321 return 0; 322 } 323 324 static bool glk_dsi_enable_io(struct intel_encoder *encoder) 325 { 326 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 327 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 328 enum port port; 329 u32 tmp; 330 bool cold_boot = false; 331 332 /* Set the MIPI mode 333 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. 334 * Power ON MIPI IO first and then write into IO reset and LP wake bits 335 */ 336 for_each_dsi_port(port, intel_dsi->ports) { 337 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 338 intel_de_write(dev_priv, MIPI_CTRL(port), 339 tmp | GLK_MIPIIO_ENABLE); 340 } 341 342 /* Put the IO into reset */ 343 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 344 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 345 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); 346 347 /* Program LP Wake */ 348 for_each_dsi_port(port, intel_dsi->ports) { 349 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 350 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) 351 tmp &= ~GLK_LP_WAKE; 352 else 353 tmp |= GLK_LP_WAKE; 354 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); 355 } 356 357 /* Wait for Pwr ACK */ 358 for_each_dsi_port(port, intel_dsi->ports) { 359 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 360 GLK_MIPIIO_PORT_POWERED, 20)) 361 drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); 362 } 363 364 /* Check for cold boot scenario */ 365 for_each_dsi_port(port, intel_dsi->ports) { 366 cold_boot |= 367 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); 368 } 369 370 return cold_boot; 371 } 372 373 static void glk_dsi_device_ready(struct intel_encoder *encoder) 374 { 375 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 376 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 377 enum port port; 378 u32 val; 379 380 /* Wait for MIPI PHY status bit to set */ 381 for_each_dsi_port(port, intel_dsi->ports) { 382 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 383 GLK_PHY_STATUS_PORT_READY, 20)) 384 drm_err(&dev_priv->drm, "PHY is not ON\n"); 385 } 386 387 /* Get IO out of reset */ 388 val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 389 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), 390 val | GLK_MIPIIO_RESET_RELEASED); 391 392 /* Get IO out of Low power state*/ 393 for_each_dsi_port(port, intel_dsi->ports) { 394 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { 395 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 396 val &= ~ULPS_STATE_MASK; 397 val |= DEVICE_READY; 398 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 399 usleep_range(10, 15); 400 } else { 401 /* Enter ULPS */ 402 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 403 val &= ~ULPS_STATE_MASK; 404 val |= (ULPS_STATE_ENTER | DEVICE_READY); 405 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 406 407 /* Wait for ULPS active */ 408 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 409 GLK_ULPS_NOT_ACTIVE, 20)) 410 drm_err(&dev_priv->drm, "ULPS not active\n"); 411 412 /* Exit ULPS */ 413 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 414 val &= ~ULPS_STATE_MASK; 415 val |= (ULPS_STATE_EXIT | DEVICE_READY); 416 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 417 418 /* Enter Normal Mode */ 419 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 420 val &= ~ULPS_STATE_MASK; 421 val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); 422 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 423 424 val = intel_de_read(dev_priv, MIPI_CTRL(port)); 425 val &= ~GLK_LP_WAKE; 426 intel_de_write(dev_priv, MIPI_CTRL(port), val); 427 } 428 } 429 430 /* Wait for Stop state */ 431 for_each_dsi_port(port, intel_dsi->ports) { 432 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 433 GLK_DATA_LANE_STOP_STATE, 20)) 434 drm_err(&dev_priv->drm, 435 "Date lane not in STOP state\n"); 436 } 437 438 /* Wait for AFE LATCH */ 439 for_each_dsi_port(port, intel_dsi->ports) { 440 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), 441 AFE_LATCHOUT, 20)) 442 drm_err(&dev_priv->drm, 443 "D-PHY not entering LP-11 state\n"); 444 } 445 } 446 447 static void bxt_dsi_device_ready(struct intel_encoder *encoder) 448 { 449 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 450 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 451 enum port port; 452 u32 val; 453 454 drm_dbg_kms(&dev_priv->drm, "\n"); 455 456 /* Enable MIPI PHY transparent latch */ 457 for_each_dsi_port(port, intel_dsi->ports) { 458 val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 459 intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port), 460 val | LP_OUTPUT_HOLD); 461 usleep_range(2000, 2500); 462 } 463 464 /* Clear ULPS and set device ready */ 465 for_each_dsi_port(port, intel_dsi->ports) { 466 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 467 val &= ~ULPS_STATE_MASK; 468 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 469 usleep_range(2000, 2500); 470 val |= DEVICE_READY; 471 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 472 } 473 } 474 475 static void vlv_dsi_device_ready(struct intel_encoder *encoder) 476 { 477 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 478 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 479 enum port port; 480 u32 val; 481 482 drm_dbg_kms(&dev_priv->drm, "\n"); 483 484 vlv_flisdsi_get(dev_priv); 485 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms 486 * needed everytime after power gate */ 487 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); 488 vlv_flisdsi_put(dev_priv); 489 490 /* bandgap reset is needed after everytime we do power gate */ 491 band_gap_reset(dev_priv); 492 493 for_each_dsi_port(port, intel_dsi->ports) { 494 495 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 496 ULPS_STATE_ENTER); 497 usleep_range(2500, 3000); 498 499 /* Enable MIPI PHY transparent latch 500 * Common bit for both MIPI Port A & MIPI Port C 501 * No similar bit in MIPI Port C reg 502 */ 503 val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A)); 504 intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A), 505 val | LP_OUTPUT_HOLD); 506 usleep_range(1000, 1500); 507 508 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 509 ULPS_STATE_EXIT); 510 usleep_range(2500, 3000); 511 512 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 513 DEVICE_READY); 514 usleep_range(2500, 3000); 515 } 516 } 517 518 static void intel_dsi_device_ready(struct intel_encoder *encoder) 519 { 520 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 521 522 if (IS_GEMINILAKE(dev_priv)) 523 glk_dsi_device_ready(encoder); 524 else if (IS_GEN9_LP(dev_priv)) 525 bxt_dsi_device_ready(encoder); 526 else 527 vlv_dsi_device_ready(encoder); 528 } 529 530 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) 531 { 532 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 533 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 534 enum port port; 535 u32 val; 536 537 /* Enter ULPS */ 538 for_each_dsi_port(port, intel_dsi->ports) { 539 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 540 val &= ~ULPS_STATE_MASK; 541 val |= (ULPS_STATE_ENTER | DEVICE_READY); 542 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 543 } 544 545 /* Wait for MIPI PHY status bit to unset */ 546 for_each_dsi_port(port, intel_dsi->ports) { 547 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 548 GLK_PHY_STATUS_PORT_READY, 20)) 549 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); 550 } 551 552 /* Wait for Pwr ACK bit to unset */ 553 for_each_dsi_port(port, intel_dsi->ports) { 554 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 555 GLK_MIPIIO_PORT_POWERED, 20)) 556 drm_err(&dev_priv->drm, 557 "MIPI IO Port is not powergated\n"); 558 } 559 } 560 561 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) 562 { 563 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 564 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 565 enum port port; 566 u32 tmp; 567 568 /* Put the IO into reset */ 569 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 570 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 571 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); 572 573 /* Wait for MIPI PHY status bit to unset */ 574 for_each_dsi_port(port, intel_dsi->ports) { 575 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 576 GLK_PHY_STATUS_PORT_READY, 20)) 577 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); 578 } 579 580 /* Clear MIPI mode */ 581 for_each_dsi_port(port, intel_dsi->ports) { 582 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 583 tmp &= ~GLK_MIPIIO_ENABLE; 584 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); 585 } 586 } 587 588 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) 589 { 590 glk_dsi_enter_low_power_mode(encoder); 591 glk_dsi_disable_mipi_io(encoder); 592 } 593 594 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) 595 { 596 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 597 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 598 enum port port; 599 600 drm_dbg_kms(&dev_priv->drm, "\n"); 601 for_each_dsi_port(port, intel_dsi->ports) { 602 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ 603 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 604 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); 605 u32 val; 606 607 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 608 DEVICE_READY | ULPS_STATE_ENTER); 609 usleep_range(2000, 2500); 610 611 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 612 DEVICE_READY | ULPS_STATE_EXIT); 613 usleep_range(2000, 2500); 614 615 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 616 DEVICE_READY | ULPS_STATE_ENTER); 617 usleep_range(2000, 2500); 618 619 /* 620 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI 621 * Port A only. MIPI Port C has no similar bit for checking. 622 */ 623 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && 624 intel_de_wait_for_clear(dev_priv, port_ctrl, 625 AFE_LATCHOUT, 30)) 626 drm_err(&dev_priv->drm, "DSI LP not going Low\n"); 627 628 /* Disable MIPI PHY transparent latch */ 629 val = intel_de_read(dev_priv, port_ctrl); 630 intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD); 631 usleep_range(1000, 1500); 632 633 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); 634 usleep_range(2000, 2500); 635 } 636 } 637 638 static void intel_dsi_port_enable(struct intel_encoder *encoder, 639 const struct intel_crtc_state *crtc_state) 640 { 641 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 642 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 643 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 644 enum port port; 645 646 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 647 u32 temp; 648 if (IS_GEN9_LP(dev_priv)) { 649 for_each_dsi_port(port, intel_dsi->ports) { 650 temp = intel_de_read(dev_priv, 651 MIPI_CTRL(port)); 652 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | 653 intel_dsi->pixel_overlap << 654 BXT_PIXEL_OVERLAP_CNT_SHIFT; 655 intel_de_write(dev_priv, MIPI_CTRL(port), 656 temp); 657 } 658 } else { 659 temp = intel_de_read(dev_priv, VLV_CHICKEN_3); 660 temp &= ~PIXEL_OVERLAP_CNT_MASK | 661 intel_dsi->pixel_overlap << 662 PIXEL_OVERLAP_CNT_SHIFT; 663 intel_de_write(dev_priv, VLV_CHICKEN_3, temp); 664 } 665 } 666 667 for_each_dsi_port(port, intel_dsi->ports) { 668 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 669 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 670 u32 temp; 671 672 temp = intel_de_read(dev_priv, port_ctrl); 673 674 temp &= ~LANE_CONFIGURATION_MASK; 675 temp &= ~DUAL_LINK_MODE_MASK; 676 677 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { 678 temp |= (intel_dsi->dual_link - 1) 679 << DUAL_LINK_MODE_SHIFT; 680 if (IS_BROXTON(dev_priv)) 681 temp |= LANE_CONFIGURATION_DUAL_LINK_A; 682 else 683 temp |= crtc->pipe ? 684 LANE_CONFIGURATION_DUAL_LINK_B : 685 LANE_CONFIGURATION_DUAL_LINK_A; 686 } 687 688 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) 689 temp |= DITHERING_ENABLE; 690 691 /* assert ip_tg_enable signal */ 692 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); 693 intel_de_posting_read(dev_priv, port_ctrl); 694 } 695 } 696 697 static void intel_dsi_port_disable(struct intel_encoder *encoder) 698 { 699 struct drm_device *dev = encoder->base.dev; 700 struct drm_i915_private *dev_priv = to_i915(dev); 701 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 702 enum port port; 703 704 for_each_dsi_port(port, intel_dsi->ports) { 705 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 706 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 707 u32 temp; 708 709 /* de-assert ip_tg_enable signal */ 710 temp = intel_de_read(dev_priv, port_ctrl); 711 intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE); 712 intel_de_posting_read(dev_priv, port_ctrl); 713 } 714 } 715 716 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 717 const struct intel_crtc_state *pipe_config); 718 static void intel_dsi_unprepare(struct intel_encoder *encoder); 719 720 /* 721 * Panel enable/disable sequences from the VBT spec. 722 * 723 * Note the spec has AssertReset / DeassertReset swapped from their 724 * usual naming. We use the normal names to avoid confusion (so below 725 * they are swapped compared to the spec). 726 * 727 * Steps starting with MIPI refer to VBT sequences, note that for v2 728 * VBTs several steps which have a VBT in v2 are expected to be handled 729 * directly by the driver, by directly driving gpios for example. 730 * 731 * v2 video mode seq v3 video mode seq command mode seq 732 * - power on - MIPIPanelPowerOn - power on 733 * - wait t1+t2 - wait t1+t2 734 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin 735 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 736 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds 737 * - MIPITearOn 738 * - MIPIDisplayOn 739 * - turn on DPI - turn on DPI - set pipe to dsr mode 740 * - MIPIDisplayOn - MIPIDisplayOn 741 * - wait t5 - wait t5 742 * - backlight on - MIPIBacklightOn - backlight on 743 * ... ... ... issue mem cmds ... 744 * - backlight off - MIPIBacklightOff - backlight off 745 * - wait t6 - wait t6 746 * - MIPIDisplayOff 747 * - turn off DPI - turn off DPI - disable pipe dsr mode 748 * - MIPITearOff 749 * - MIPIDisplayOff - MIPIDisplayOff 750 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 751 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin 752 * - wait t3 - wait t3 753 * - power off - MIPIPanelPowerOff - power off 754 * - wait t4 - wait t4 755 */ 756 757 /* 758 * DSI port enable has to be done before pipe and plane enable, so we do it in 759 * the pre_enable hook instead of the enable hook. 760 */ 761 static void intel_dsi_pre_enable(struct intel_atomic_state *state, 762 struct intel_encoder *encoder, 763 const struct intel_crtc_state *pipe_config, 764 const struct drm_connector_state *conn_state) 765 { 766 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 767 struct drm_crtc *crtc = pipe_config->uapi.crtc; 768 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 770 enum pipe pipe = intel_crtc->pipe; 771 enum port port; 772 u32 val; 773 bool glk_cold_boot = false; 774 775 drm_dbg_kms(&dev_priv->drm, "\n"); 776 777 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 778 779 /* 780 * The BIOS may leave the PLL in a wonky state where it doesn't 781 * lock. It needs to be fully powered down to fix it. 782 */ 783 if (IS_GEN9_LP(dev_priv)) { 784 bxt_dsi_pll_disable(encoder); 785 bxt_dsi_pll_enable(encoder, pipe_config); 786 } else { 787 vlv_dsi_pll_disable(encoder); 788 vlv_dsi_pll_enable(encoder, pipe_config); 789 } 790 791 if (IS_BROXTON(dev_priv)) { 792 /* Add MIPI IO reset programming for modeset */ 793 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); 794 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, 795 val | MIPIO_RST_CTRL); 796 797 /* Power up DSI regulator */ 798 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 799 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); 800 } 801 802 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 803 u32 val; 804 805 /* Disable DPOunit clock gating, can stall pipe */ 806 val = intel_de_read(dev_priv, DSPCLK_GATE_D); 807 val |= DPOUNIT_CLOCK_GATE_DISABLE; 808 intel_de_write(dev_priv, DSPCLK_GATE_D, val); 809 } 810 811 if (!IS_GEMINILAKE(dev_priv)) 812 intel_dsi_prepare(encoder, pipe_config); 813 814 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 815 816 /* 817 * Give the panel time to power-on and then deassert its reset. 818 * Depending on the VBT MIPI sequences version the deassert-seq 819 * may contain the necessary delay, intel_dsi_msleep() will skip 820 * the delay in that case. If there is no deassert-seq, then an 821 * unconditional msleep is used to give the panel time to power-on. 822 */ 823 if (dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) { 824 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 825 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 826 } else { 827 msleep(intel_dsi->panel_on_delay); 828 } 829 830 if (IS_GEMINILAKE(dev_priv)) { 831 glk_cold_boot = glk_dsi_enable_io(encoder); 832 833 /* Prepare port in cold boot(s3/s4) scenario */ 834 if (glk_cold_boot) 835 intel_dsi_prepare(encoder, pipe_config); 836 } 837 838 /* Put device in ready state (LP-11) */ 839 intel_dsi_device_ready(encoder); 840 841 /* Prepare port in normal boot scenario */ 842 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) 843 intel_dsi_prepare(encoder, pipe_config); 844 845 /* Send initialization commands in LP mode */ 846 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 847 848 /* Enable port in pre-enable phase itself because as per hw team 849 * recommendation, port should be enabled befor plane & pipe */ 850 if (is_cmd_mode(intel_dsi)) { 851 for_each_dsi_port(port, intel_dsi->ports) 852 intel_de_write(dev_priv, 853 MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); 854 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); 855 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 856 } else { 857 msleep(20); /* XXX */ 858 for_each_dsi_port(port, intel_dsi->ports) 859 dpi_send_cmd(intel_dsi, TURN_ON, false, port); 860 intel_dsi_msleep(intel_dsi, 100); 861 862 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 863 864 intel_dsi_port_enable(encoder, pipe_config); 865 } 866 867 intel_panel_enable_backlight(pipe_config, conn_state); 868 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 869 } 870 871 static void bxt_dsi_enable(struct intel_atomic_state *state, 872 struct intel_encoder *encoder, 873 const struct intel_crtc_state *crtc_state, 874 const struct drm_connector_state *conn_state) 875 { 876 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 877 878 intel_crtc_vblank_on(crtc_state); 879 } 880 881 /* 882 * DSI port disable has to be done after pipe and plane disable, so we do it in 883 * the post_disable hook. 884 */ 885 static void intel_dsi_disable(struct intel_atomic_state *state, 886 struct intel_encoder *encoder, 887 const struct intel_crtc_state *old_crtc_state, 888 const struct drm_connector_state *old_conn_state) 889 { 890 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 891 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 892 enum port port; 893 894 drm_dbg_kms(&i915->drm, "\n"); 895 896 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 897 intel_panel_disable_backlight(old_conn_state); 898 899 /* 900 * According to the spec we should send SHUTDOWN before 901 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing 902 * has shown that the v3 sequence works for v2 VBTs too 903 */ 904 if (is_vid_mode(intel_dsi)) { 905 /* Send Shutdown command to the panel in LP mode */ 906 for_each_dsi_port(port, intel_dsi->ports) 907 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); 908 msleep(10); 909 } 910 } 911 912 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 913 { 914 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 915 916 if (IS_GEMINILAKE(dev_priv)) 917 glk_dsi_clear_device_ready(encoder); 918 else 919 vlv_dsi_clear_device_ready(encoder); 920 } 921 922 static void intel_dsi_post_disable(struct intel_atomic_state *state, 923 struct intel_encoder *encoder, 924 const struct intel_crtc_state *old_crtc_state, 925 const struct drm_connector_state *old_conn_state) 926 { 927 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 928 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 929 enum port port; 930 u32 val; 931 932 drm_dbg_kms(&dev_priv->drm, "\n"); 933 934 if (IS_GEN9_LP(dev_priv)) { 935 intel_crtc_vblank_off(old_crtc_state); 936 937 skl_scaler_disable(old_crtc_state); 938 } 939 940 if (is_vid_mode(intel_dsi)) { 941 for_each_dsi_port(port, intel_dsi->ports) 942 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 943 944 intel_dsi_port_disable(encoder); 945 usleep_range(2000, 5000); 946 } 947 948 intel_dsi_unprepare(encoder); 949 950 /* 951 * if disable packets are sent before sending shutdown packet then in 952 * some next enable sequence send turn on packet error is observed 953 */ 954 if (is_cmd_mode(intel_dsi)) 955 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF); 956 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 957 958 /* Transition to LP-00 */ 959 intel_dsi_clear_device_ready(encoder); 960 961 if (IS_BROXTON(dev_priv)) { 962 /* Power down DSI regulator to save power */ 963 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 964 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 965 HS_IO_CTRL_SELECT); 966 967 /* Add MIPI IO reset programming for modeset */ 968 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); 969 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, 970 val & ~MIPIO_RST_CTRL); 971 } 972 973 if (IS_GEN9_LP(dev_priv)) { 974 bxt_dsi_pll_disable(encoder); 975 } else { 976 u32 val; 977 978 vlv_dsi_pll_disable(encoder); 979 980 val = intel_de_read(dev_priv, DSPCLK_GATE_D); 981 val &= ~DPOUNIT_CLOCK_GATE_DISABLE; 982 intel_de_write(dev_priv, DSPCLK_GATE_D, val); 983 } 984 985 /* Assert reset */ 986 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 987 988 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); 989 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 990 991 /* 992 * FIXME As we do with eDP, just make a note of the time here 993 * and perform the wait before the next panel power on. 994 */ 995 intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay); 996 } 997 998 static void intel_dsi_shutdown(struct intel_encoder *encoder) 999 { 1000 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1001 1002 intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay); 1003 } 1004 1005 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 1006 enum pipe *pipe) 1007 { 1008 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1009 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1010 intel_wakeref_t wakeref; 1011 enum port port; 1012 bool active = false; 1013 1014 drm_dbg_kms(&dev_priv->drm, "\n"); 1015 1016 wakeref = intel_display_power_get_if_enabled(dev_priv, 1017 encoder->power_domain); 1018 if (!wakeref) 1019 return false; 1020 1021 /* 1022 * On Broxton the PLL needs to be enabled with a valid divider 1023 * configuration, otherwise accessing DSI registers will hang the 1024 * machine. See BSpec North Display Engine registers/MIPI[BXT]. 1025 */ 1026 if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv)) 1027 goto out_put_power; 1028 1029 /* XXX: this only works for one DSI output */ 1030 for_each_dsi_port(port, intel_dsi->ports) { 1031 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? 1032 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 1033 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE; 1034 1035 /* 1036 * Due to some hardware limitations on VLV/CHV, the DPI enable 1037 * bit in port C control register does not get set. As a 1038 * workaround, check pipe B conf instead. 1039 */ 1040 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1041 port == PORT_C) 1042 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; 1043 1044 /* Try command mode if video mode not enabled */ 1045 if (!enabled) { 1046 u32 tmp = intel_de_read(dev_priv, 1047 MIPI_DSI_FUNC_PRG(port)); 1048 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; 1049 } 1050 1051 if (!enabled) 1052 continue; 1053 1054 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) 1055 continue; 1056 1057 if (IS_GEN9_LP(dev_priv)) { 1058 u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1059 tmp &= BXT_PIPE_SELECT_MASK; 1060 tmp >>= BXT_PIPE_SELECT_SHIFT; 1061 1062 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) 1063 continue; 1064 1065 *pipe = tmp; 1066 } else { 1067 *pipe = port == PORT_A ? PIPE_A : PIPE_B; 1068 } 1069 1070 active = true; 1071 break; 1072 } 1073 1074 out_put_power: 1075 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1076 1077 return active; 1078 } 1079 1080 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, 1081 struct intel_crtc_state *pipe_config) 1082 { 1083 struct drm_device *dev = encoder->base.dev; 1084 struct drm_i915_private *dev_priv = to_i915(dev); 1085 struct drm_display_mode *adjusted_mode = 1086 &pipe_config->hw.adjusted_mode; 1087 struct drm_display_mode *adjusted_mode_sw; 1088 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1089 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1090 unsigned int lane_count = intel_dsi->lane_count; 1091 unsigned int bpp, fmt; 1092 enum port port; 1093 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1094 u16 hfp_sw, hsync_sw, hbp_sw; 1095 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, 1096 crtc_hblank_start_sw, crtc_hblank_end_sw; 1097 1098 /* FIXME: hw readout should not depend on SW state */ 1099 adjusted_mode_sw = &crtc->config->hw.adjusted_mode; 1100 1101 /* 1102 * Atleast one port is active as encoder->get_config called only if 1103 * encoder->get_hw_state() returns true. 1104 */ 1105 for_each_dsi_port(port, intel_dsi->ports) { 1106 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) 1107 break; 1108 } 1109 1110 fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; 1111 bpp = mipi_dsi_pixel_format_to_bpp( 1112 pixel_format_from_register_bits(fmt)); 1113 1114 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1115 1116 /* Enable Frame time stamo based scanline reporting */ 1117 pipe_config->mode_flags |= 1118 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 1119 1120 /* In terms of pixels */ 1121 adjusted_mode->crtc_hdisplay = 1122 intel_de_read(dev_priv, 1123 BXT_MIPI_TRANS_HACTIVE(port)); 1124 adjusted_mode->crtc_vdisplay = 1125 intel_de_read(dev_priv, 1126 BXT_MIPI_TRANS_VACTIVE(port)); 1127 adjusted_mode->crtc_vtotal = 1128 intel_de_read(dev_priv, 1129 BXT_MIPI_TRANS_VTOTAL(port)); 1130 1131 hactive = adjusted_mode->crtc_hdisplay; 1132 hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); 1133 1134 /* 1135 * Meaningful for video mode non-burst sync pulse mode only, 1136 * can be zero for non-burst sync events and burst modes 1137 */ 1138 hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); 1139 hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); 1140 1141 /* harizontal values are in terms of high speed byte clock */ 1142 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, 1143 intel_dsi->burst_mode_ratio); 1144 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, 1145 intel_dsi->burst_mode_ratio); 1146 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, 1147 intel_dsi->burst_mode_ratio); 1148 1149 if (intel_dsi->dual_link) { 1150 hfp *= 2; 1151 hsync *= 2; 1152 hbp *= 2; 1153 } 1154 1155 /* vertical values are in terms of lines */ 1156 vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); 1157 vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); 1158 vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port)); 1159 1160 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; 1161 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; 1162 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; 1163 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1164 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1165 1166 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; 1167 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; 1168 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1169 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1170 1171 /* 1172 * In BXT DSI there is no regs programmed with few horizontal timings 1173 * in Pixels but txbyteclkhs.. So retrieval process adds some 1174 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. 1175 * Actually here for the given adjusted_mode, we are calculating the 1176 * value programmed to the port and then back to the horizontal timing 1177 * param in pixels. This is the expected value, including roundup errors 1178 * And if that is same as retrieved value from port, then 1179 * (HW state) adjusted_mode's horizontal timings are corrected to 1180 * match with SW state to nullify the errors. 1181 */ 1182 /* Calculating the value programmed to the Port register */ 1183 hfp_sw = adjusted_mode_sw->crtc_hsync_start - 1184 adjusted_mode_sw->crtc_hdisplay; 1185 hsync_sw = adjusted_mode_sw->crtc_hsync_end - 1186 adjusted_mode_sw->crtc_hsync_start; 1187 hbp_sw = adjusted_mode_sw->crtc_htotal - 1188 adjusted_mode_sw->crtc_hsync_end; 1189 1190 if (intel_dsi->dual_link) { 1191 hfp_sw /= 2; 1192 hsync_sw /= 2; 1193 hbp_sw /= 2; 1194 } 1195 1196 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, 1197 intel_dsi->burst_mode_ratio); 1198 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, 1199 intel_dsi->burst_mode_ratio); 1200 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, 1201 intel_dsi->burst_mode_ratio); 1202 1203 /* Reverse calculating the adjusted mode parameters from port reg vals*/ 1204 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, 1205 intel_dsi->burst_mode_ratio); 1206 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, 1207 intel_dsi->burst_mode_ratio); 1208 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, 1209 intel_dsi->burst_mode_ratio); 1210 1211 if (intel_dsi->dual_link) { 1212 hfp_sw *= 2; 1213 hsync_sw *= 2; 1214 hbp_sw *= 2; 1215 } 1216 1217 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + 1218 hsync_sw + hbp_sw; 1219 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; 1220 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; 1221 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; 1222 crtc_hblank_end_sw = crtc_htotal_sw; 1223 1224 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) 1225 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; 1226 1227 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) 1228 adjusted_mode->crtc_hsync_start = 1229 adjusted_mode_sw->crtc_hsync_start; 1230 1231 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) 1232 adjusted_mode->crtc_hsync_end = 1233 adjusted_mode_sw->crtc_hsync_end; 1234 1235 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) 1236 adjusted_mode->crtc_hblank_start = 1237 adjusted_mode_sw->crtc_hblank_start; 1238 1239 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) 1240 adjusted_mode->crtc_hblank_end = 1241 adjusted_mode_sw->crtc_hblank_end; 1242 } 1243 1244 static void intel_dsi_get_config(struct intel_encoder *encoder, 1245 struct intel_crtc_state *pipe_config) 1246 { 1247 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1248 u32 pclk; 1249 drm_dbg_kms(&dev_priv->drm, "\n"); 1250 1251 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1252 1253 if (IS_GEN9_LP(dev_priv)) { 1254 bxt_dsi_get_pipe_config(encoder, pipe_config); 1255 pclk = bxt_dsi_get_pclk(encoder, pipe_config); 1256 } else { 1257 pclk = vlv_dsi_get_pclk(encoder, pipe_config); 1258 } 1259 1260 if (pclk) { 1261 pipe_config->hw.adjusted_mode.crtc_clock = pclk; 1262 pipe_config->port_clock = pclk; 1263 } 1264 } 1265 1266 /* return txclkesc cycles in terms of divider and duration in us */ 1267 static u16 txclkesc(u32 divider, unsigned int us) 1268 { 1269 switch (divider) { 1270 case ESCAPE_CLOCK_DIVIDER_1: 1271 default: 1272 return 20 * us; 1273 case ESCAPE_CLOCK_DIVIDER_2: 1274 return 10 * us; 1275 case ESCAPE_CLOCK_DIVIDER_4: 1276 return 5 * us; 1277 } 1278 } 1279 1280 static void set_dsi_timings(struct drm_encoder *encoder, 1281 const struct drm_display_mode *adjusted_mode) 1282 { 1283 struct drm_device *dev = encoder->dev; 1284 struct drm_i915_private *dev_priv = to_i915(dev); 1285 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1286 enum port port; 1287 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1288 unsigned int lane_count = intel_dsi->lane_count; 1289 1290 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1291 1292 hactive = adjusted_mode->crtc_hdisplay; 1293 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; 1294 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1295 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; 1296 1297 if (intel_dsi->dual_link) { 1298 hactive /= 2; 1299 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1300 hactive += intel_dsi->pixel_overlap; 1301 hfp /= 2; 1302 hsync /= 2; 1303 hbp /= 2; 1304 } 1305 1306 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; 1307 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; 1308 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; 1309 1310 /* horizontal values are in terms of high speed byte clock */ 1311 hactive = txbyteclkhs(hactive, bpp, lane_count, 1312 intel_dsi->burst_mode_ratio); 1313 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1314 hsync = txbyteclkhs(hsync, bpp, lane_count, 1315 intel_dsi->burst_mode_ratio); 1316 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1317 1318 for_each_dsi_port(port, intel_dsi->ports) { 1319 if (IS_GEN9_LP(dev_priv)) { 1320 /* 1321 * Program hdisplay and vdisplay on MIPI transcoder. 1322 * This is different from calculated hactive and 1323 * vactive, as they are calculated per channel basis, 1324 * whereas these values should be based on resolution. 1325 */ 1326 intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), 1327 adjusted_mode->crtc_hdisplay); 1328 intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), 1329 adjusted_mode->crtc_vdisplay); 1330 intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), 1331 adjusted_mode->crtc_vtotal); 1332 } 1333 1334 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), 1335 hactive); 1336 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); 1337 1338 /* meaningful for video mode non-burst sync pulse mode only, 1339 * can be zero for non-burst sync events and burst modes */ 1340 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), 1341 hsync); 1342 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); 1343 1344 /* vertical values are in terms of lines */ 1345 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); 1346 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), 1347 vsync); 1348 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); 1349 } 1350 } 1351 1352 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) 1353 { 1354 switch (fmt) { 1355 case MIPI_DSI_FMT_RGB888: 1356 return VID_MODE_FORMAT_RGB888; 1357 case MIPI_DSI_FMT_RGB666: 1358 return VID_MODE_FORMAT_RGB666; 1359 case MIPI_DSI_FMT_RGB666_PACKED: 1360 return VID_MODE_FORMAT_RGB666_PACKED; 1361 case MIPI_DSI_FMT_RGB565: 1362 return VID_MODE_FORMAT_RGB565; 1363 default: 1364 MISSING_CASE(fmt); 1365 return VID_MODE_FORMAT_RGB666; 1366 } 1367 } 1368 1369 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 1370 const struct intel_crtc_state *pipe_config) 1371 { 1372 struct drm_encoder *encoder = &intel_encoder->base; 1373 struct drm_device *dev = encoder->dev; 1374 struct drm_i915_private *dev_priv = to_i915(dev); 1375 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 1376 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1377 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1378 enum port port; 1379 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1380 u32 val, tmp; 1381 u16 mode_hdisplay; 1382 1383 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(intel_crtc->pipe)); 1384 1385 mode_hdisplay = adjusted_mode->crtc_hdisplay; 1386 1387 if (intel_dsi->dual_link) { 1388 mode_hdisplay /= 2; 1389 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1390 mode_hdisplay += intel_dsi->pixel_overlap; 1391 } 1392 1393 for_each_dsi_port(port, intel_dsi->ports) { 1394 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1395 /* 1396 * escape clock divider, 20MHz, shared for A and C. 1397 * device ready must be off when doing this! txclkesc? 1398 */ 1399 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 1400 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 1401 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), 1402 tmp | ESCAPE_CLOCK_DIVIDER_1); 1403 1404 /* read request priority is per pipe */ 1405 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1406 tmp &= ~READ_REQUEST_PRIORITY_MASK; 1407 intel_de_write(dev_priv, MIPI_CTRL(port), 1408 tmp | READ_REQUEST_PRIORITY_HIGH); 1409 } else if (IS_GEN9_LP(dev_priv)) { 1410 enum pipe pipe = intel_crtc->pipe; 1411 1412 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1413 tmp &= ~BXT_PIPE_SELECT_MASK; 1414 1415 tmp |= BXT_PIPE_SELECT(pipe); 1416 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); 1417 } 1418 1419 /* XXX: why here, why like this? handling in irq handler?! */ 1420 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); 1421 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); 1422 1423 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), 1424 intel_dsi->dphy_reg); 1425 1426 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), 1427 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); 1428 } 1429 1430 set_dsi_timings(encoder, adjusted_mode); 1431 1432 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; 1433 if (is_cmd_mode(intel_dsi)) { 1434 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; 1435 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ 1436 } else { 1437 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; 1438 val |= pixel_format_to_reg(intel_dsi->pixel_format); 1439 } 1440 1441 tmp = 0; 1442 if (intel_dsi->eotp_pkt == 0) 1443 tmp |= EOT_DISABLE; 1444 if (intel_dsi->clock_stop) 1445 tmp |= CLOCKSTOP; 1446 1447 if (IS_GEN9_LP(dev_priv)) { 1448 tmp |= BXT_DPHY_DEFEATURE_EN; 1449 if (!is_cmd_mode(intel_dsi)) 1450 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; 1451 } 1452 1453 for_each_dsi_port(port, intel_dsi->ports) { 1454 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); 1455 1456 /* timeouts for recovery. one frame IIUC. if counter expires, 1457 * EOT and stop state. */ 1458 1459 /* 1460 * In burst mode, value greater than one DPI line Time in byte 1461 * clock (txbyteclkhs) To timeout this timer 1+ of the above 1462 * said value is recommended. 1463 * 1464 * In non-burst mode, Value greater than one DPI frame time in 1465 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1466 * said value is recommended. 1467 * 1468 * In DBI only mode, value greater than one DBI frame time in 1469 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1470 * said value is recommended. 1471 */ 1472 1473 if (is_vid_mode(intel_dsi) && 1474 intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 1475 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), 1476 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1477 } else { 1478 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), 1479 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1480 } 1481 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), 1482 intel_dsi->lp_rx_timeout); 1483 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), 1484 intel_dsi->turn_arnd_val); 1485 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), 1486 intel_dsi->rst_timer_val); 1487 1488 /* dphy stuff */ 1489 1490 /* in terms of low power clock */ 1491 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), 1492 txclkesc(intel_dsi->escape_clk_div, 100)); 1493 1494 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { 1495 /* 1496 * BXT spec says write MIPI_INIT_COUNT for 1497 * both the ports, even if only one is 1498 * getting used. So write the other port 1499 * if not in dual link mode. 1500 */ 1501 intel_de_write(dev_priv, 1502 MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A), 1503 intel_dsi->init_count); 1504 } 1505 1506 /* recovery disables */ 1507 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); 1508 1509 /* in terms of low power clock */ 1510 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), 1511 intel_dsi->init_count); 1512 1513 /* in terms of txbyteclkhs. actual high to low switch + 1514 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. 1515 * 1516 * XXX: write MIPI_STOP_STATE_STALL? 1517 */ 1518 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), 1519 intel_dsi->hs_to_lp_count); 1520 1521 /* XXX: low power clock equivalence in terms of byte clock. 1522 * the number of byte clocks occupied in one low power clock. 1523 * based on txbyteclkhs and txclkesc. 1524 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL 1525 * ) / 105.??? 1526 */ 1527 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), 1528 intel_dsi->lp_byte_clk); 1529 1530 if (IS_GEMINILAKE(dev_priv)) { 1531 intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), 1532 intel_dsi->lp_byte_clk); 1533 /* Shadow of DPHY reg */ 1534 intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), 1535 intel_dsi->dphy_reg); 1536 } 1537 1538 /* the bw essential for transmitting 16 long packets containing 1539 * 252 bytes meant for dcs write memory command is programmed in 1540 * this register in terms of byte clocks. based on dsi transfer 1541 * rate and the number of lanes configured the time taken to 1542 * transmit 16 long packets in a dsi stream varies. */ 1543 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), 1544 intel_dsi->bw_timer); 1545 1546 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), 1547 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); 1548 1549 if (is_vid_mode(intel_dsi)) 1550 /* Some panels might have resolution which is not a 1551 * multiple of 64 like 1366 x 768. Enable RANDOM 1552 * resolution support for such panels by default */ 1553 intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), 1554 intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_format | IP_TG_CONFIG | RANDOM_DPI_DISPLAY_RESOLUTION); 1555 } 1556 } 1557 1558 static void intel_dsi_unprepare(struct intel_encoder *encoder) 1559 { 1560 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1561 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1562 enum port port; 1563 u32 val; 1564 1565 if (IS_GEMINILAKE(dev_priv)) 1566 return; 1567 1568 for_each_dsi_port(port, intel_dsi->ports) { 1569 /* Panel commands can be sent when clock is in LP11 */ 1570 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); 1571 1572 if (IS_GEN9_LP(dev_priv)) 1573 bxt_dsi_reset_clocks(encoder, port); 1574 else 1575 vlv_dsi_reset_clocks(encoder, port); 1576 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); 1577 1578 val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)); 1579 val &= ~VID_MODE_FORMAT_MASK; 1580 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); 1581 1582 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); 1583 } 1584 } 1585 1586 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) 1587 { 1588 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1589 1590 intel_dsi_vbt_gpio_cleanup(intel_dsi); 1591 intel_encoder_destroy(encoder); 1592 } 1593 1594 static const struct drm_encoder_funcs intel_dsi_funcs = { 1595 .destroy = intel_dsi_encoder_destroy, 1596 }; 1597 1598 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 1599 .get_modes = intel_dsi_get_modes, 1600 .mode_valid = intel_dsi_mode_valid, 1601 .atomic_check = intel_digital_connector_atomic_check, 1602 }; 1603 1604 static const struct drm_connector_funcs intel_dsi_connector_funcs = { 1605 .detect = intel_panel_detect, 1606 .late_register = intel_connector_register, 1607 .early_unregister = intel_connector_unregister, 1608 .destroy = intel_connector_destroy, 1609 .fill_modes = drm_helper_probe_single_connector_modes, 1610 .atomic_get_property = intel_digital_connector_atomic_get_property, 1611 .atomic_set_property = intel_digital_connector_atomic_set_property, 1612 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1613 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1614 }; 1615 1616 static void vlv_dsi_add_properties(struct intel_connector *connector) 1617 { 1618 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1619 1620 if (connector->panel.fixed_mode) { 1621 u32 allowed_scalers; 1622 1623 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); 1624 if (!HAS_GMCH(dev_priv)) 1625 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); 1626 1627 drm_connector_attach_scaling_mode_property(&connector->base, 1628 allowed_scalers); 1629 1630 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1631 1632 drm_connector_set_panel_orientation_with_quirk( 1633 &connector->base, 1634 intel_dsi_get_panel_orientation(connector), 1635 connector->panel.fixed_mode->hdisplay, 1636 connector->panel.fixed_mode->vdisplay); 1637 } 1638 } 1639 1640 #define NS_KHZ_RATIO 1000000 1641 1642 #define PREPARE_CNT_MAX 0x3F 1643 #define EXIT_ZERO_CNT_MAX 0x3F 1644 #define CLK_ZERO_CNT_MAX 0xFF 1645 #define TRAIL_CNT_MAX 0x1F 1646 1647 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) 1648 { 1649 struct drm_device *dev = intel_dsi->base.base.dev; 1650 struct drm_i915_private *dev_priv = to_i915(dev); 1651 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1652 u32 tlpx_ns, extra_byte_count, tlpx_ui; 1653 u32 ui_num, ui_den; 1654 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1655 u32 ths_prepare_ns, tclk_trail_ns; 1656 u32 tclk_prepare_clkzero, ths_prepare_hszero; 1657 u32 lp_to_hs_switch, hs_to_lp_switch; 1658 u32 mul; 1659 1660 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1661 1662 switch (intel_dsi->lane_count) { 1663 case 1: 1664 case 2: 1665 extra_byte_count = 2; 1666 break; 1667 case 3: 1668 extra_byte_count = 4; 1669 break; 1670 case 4: 1671 default: 1672 extra_byte_count = 3; 1673 break; 1674 } 1675 1676 /* in Kbps */ 1677 ui_num = NS_KHZ_RATIO; 1678 ui_den = intel_dsi_bitrate(intel_dsi); 1679 1680 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; 1681 ths_prepare_hszero = mipi_config->ths_prepare_hszero; 1682 1683 /* 1684 * B060 1685 * LP byte clock = TLPX/ (8UI) 1686 */ 1687 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); 1688 1689 /* DDR clock period = 2 * UI 1690 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ) 1691 * UI(nsec) = 10^6 / bitrate 1692 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate 1693 * DDR clock count = ns_value / DDR clock period 1694 * 1695 * For GEMINILAKE dphy_param_reg will be programmed in terms of 1696 * HS byte clock count for other platform in HS ddr clock count 1697 */ 1698 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; 1699 ths_prepare_ns = max(mipi_config->ths_prepare, 1700 mipi_config->tclk_prepare); 1701 1702 /* prepare count */ 1703 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul); 1704 1705 if (prepare_cnt > PREPARE_CNT_MAX) { 1706 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", 1707 prepare_cnt); 1708 prepare_cnt = PREPARE_CNT_MAX; 1709 } 1710 1711 /* exit zero count */ 1712 exit_zero_cnt = DIV_ROUND_UP( 1713 (ths_prepare_hszero - ths_prepare_ns) * ui_den, 1714 ui_num * mul 1715 ); 1716 1717 /* 1718 * Exit zero is unified val ths_zero and ths_exit 1719 * minimum value for ths_exit = 110ns 1720 * min (exit_zero_cnt * 2) = 110/UI 1721 * exit_zero_cnt = 55/UI 1722 */ 1723 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num) 1724 exit_zero_cnt += 1; 1725 1726 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) { 1727 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", 1728 exit_zero_cnt); 1729 exit_zero_cnt = EXIT_ZERO_CNT_MAX; 1730 } 1731 1732 /* clk zero count */ 1733 clk_zero_cnt = DIV_ROUND_UP( 1734 (tclk_prepare_clkzero - ths_prepare_ns) 1735 * ui_den, ui_num * mul); 1736 1737 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) { 1738 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", 1739 clk_zero_cnt); 1740 clk_zero_cnt = CLK_ZERO_CNT_MAX; 1741 } 1742 1743 /* trail count */ 1744 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1745 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul); 1746 1747 if (trail_cnt > TRAIL_CNT_MAX) { 1748 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", 1749 trail_cnt); 1750 trail_cnt = TRAIL_CNT_MAX; 1751 } 1752 1753 /* B080 */ 1754 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | 1755 clk_zero_cnt << 8 | prepare_cnt; 1756 1757 /* 1758 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT * 1759 * mul + 10UI + Extra Byte Count 1760 * 1761 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count 1762 * Extra Byte Count is calculated according to number of lanes. 1763 * High Low Switch Count is the Max of LP to HS and 1764 * HS to LP switch count 1765 * 1766 */ 1767 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); 1768 1769 /* B044 */ 1770 /* FIXME: 1771 * The comment above does not match with the code */ 1772 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul + 1773 exit_zero_cnt * mul + 10, 8); 1774 1775 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); 1776 1777 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); 1778 intel_dsi->hs_to_lp_count += extra_byte_count; 1779 1780 /* B088 */ 1781 /* LP -> HS for clock lanes 1782 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + 1783 * extra byte count 1784 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * 1785 * 2(in UI) + extra byte count 1786 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / 1787 * 8 + extra byte count 1788 */ 1789 intel_dsi->clk_lp_to_hs_count = 1790 DIV_ROUND_UP( 1791 4 * tlpx_ui + prepare_cnt * 2 + 1792 clk_zero_cnt * 2, 1793 8); 1794 1795 intel_dsi->clk_lp_to_hs_count += extra_byte_count; 1796 1797 /* HS->LP for Clock Lanes 1798 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + 1799 * Extra byte count 1800 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count 1801 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + 1802 * Extra byte count 1803 */ 1804 intel_dsi->clk_hs_to_lp_count = 1805 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, 1806 8); 1807 intel_dsi->clk_hs_to_lp_count += extra_byte_count; 1808 1809 intel_dsi_log_params(intel_dsi); 1810 } 1811 1812 void vlv_dsi_init(struct drm_i915_private *dev_priv) 1813 { 1814 struct drm_device *dev = &dev_priv->drm; 1815 struct intel_dsi *intel_dsi; 1816 struct intel_encoder *intel_encoder; 1817 struct drm_encoder *encoder; 1818 struct intel_connector *intel_connector; 1819 struct drm_connector *connector; 1820 struct drm_display_mode *current_mode, *fixed_mode; 1821 enum port port; 1822 enum pipe pipe; 1823 1824 drm_dbg_kms(&dev_priv->drm, "\n"); 1825 1826 /* There is no detection method for MIPI so rely on VBT */ 1827 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1828 return; 1829 1830 if (IS_GEN9_LP(dev_priv)) 1831 dev_priv->mipi_mmio_base = BXT_MIPI_BASE; 1832 else 1833 dev_priv->mipi_mmio_base = VLV_MIPI_BASE; 1834 1835 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1836 if (!intel_dsi) 1837 return; 1838 1839 intel_connector = intel_connector_alloc(); 1840 if (!intel_connector) { 1841 kfree(intel_dsi); 1842 return; 1843 } 1844 1845 intel_encoder = &intel_dsi->base; 1846 encoder = &intel_encoder->base; 1847 intel_dsi->attached_connector = intel_connector; 1848 1849 connector = &intel_connector->base; 1850 1851 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, 1852 "DSI %c", port_name(port)); 1853 1854 intel_encoder->compute_config = intel_dsi_compute_config; 1855 intel_encoder->pre_enable = intel_dsi_pre_enable; 1856 if (IS_GEN9_LP(dev_priv)) 1857 intel_encoder->enable = bxt_dsi_enable; 1858 intel_encoder->disable = intel_dsi_disable; 1859 intel_encoder->post_disable = intel_dsi_post_disable; 1860 intel_encoder->get_hw_state = intel_dsi_get_hw_state; 1861 intel_encoder->get_config = intel_dsi_get_config; 1862 intel_encoder->update_pipe = intel_panel_update_backlight; 1863 intel_encoder->shutdown = intel_dsi_shutdown; 1864 1865 intel_connector->get_hw_state = intel_connector_get_hw_state; 1866 1867 intel_encoder->port = port; 1868 intel_encoder->type = INTEL_OUTPUT_DSI; 1869 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1870 intel_encoder->cloneable = 0; 1871 1872 /* 1873 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI 1874 * port C. BXT isn't limited like this. 1875 */ 1876 if (IS_GEN9_LP(dev_priv)) 1877 intel_encoder->pipe_mask = ~0; 1878 else if (port == PORT_A) 1879 intel_encoder->pipe_mask = BIT(PIPE_A); 1880 else 1881 intel_encoder->pipe_mask = BIT(PIPE_B); 1882 1883 if (dev_priv->vbt.dsi.config->dual_link) 1884 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); 1885 else 1886 intel_dsi->ports = BIT(port); 1887 1888 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 1889 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 1890 1891 /* Create a DSI host (and a device) for each port. */ 1892 for_each_dsi_port(port, intel_dsi->ports) { 1893 struct intel_dsi_host *host; 1894 1895 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops, 1896 port); 1897 if (!host) 1898 goto err; 1899 1900 intel_dsi->dsi_hosts[port] = host; 1901 } 1902 1903 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1904 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 1905 goto err; 1906 } 1907 1908 /* Use clock read-back from current hw-state for fastboot */ 1909 current_mode = intel_encoder_current_mode(intel_encoder); 1910 if (current_mode) { 1911 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", 1912 intel_dsi->pclk, current_mode->clock); 1913 if (intel_fuzzy_clock_check(intel_dsi->pclk, 1914 current_mode->clock)) { 1915 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); 1916 intel_dsi->pclk = current_mode->clock; 1917 } 1918 1919 kfree(current_mode); 1920 } 1921 1922 vlv_dphy_param_init(intel_dsi); 1923 1924 intel_dsi_vbt_gpio_init(intel_dsi, 1925 intel_dsi_get_hw_state(intel_encoder, &pipe)); 1926 1927 drm_connector_init(dev, connector, &intel_dsi_connector_funcs, 1928 DRM_MODE_CONNECTOR_DSI); 1929 1930 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); 1931 1932 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ 1933 connector->interlace_allowed = false; 1934 connector->doublescan_allowed = false; 1935 1936 intel_connector_attach_encoder(intel_connector, intel_encoder); 1937 1938 mutex_lock(&dev->mode_config.mutex); 1939 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 1940 mutex_unlock(&dev->mode_config.mutex); 1941 1942 if (!fixed_mode) { 1943 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); 1944 goto err_cleanup_connector; 1945 } 1946 1947 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 1948 intel_panel_setup_backlight(connector, INVALID_PIPE); 1949 1950 vlv_dsi_add_properties(intel_connector); 1951 1952 return; 1953 1954 err_cleanup_connector: 1955 drm_connector_cleanup(&intel_connector->base); 1956 err: 1957 drm_encoder_cleanup(&intel_encoder->base); 1958 kfree(intel_dsi); 1959 kfree(intel_connector); 1960 } 1961