1 /*
2  * Copyright © 2013 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Author: Jani Nikula <jani.nikula@intel.com>
24  */
25 
26 #include <linux/slab.h>
27 
28 #include <drm/drm_atomic_helper.h>
29 #include <drm/drm_crtc.h>
30 #include <drm/drm_edid.h>
31 #include <drm/drm_mipi_dsi.h>
32 
33 #include "i915_drv.h"
34 #include "i915_reg.h"
35 #include "intel_atomic.h"
36 #include "intel_backlight.h"
37 #include "intel_connector.h"
38 #include "intel_crtc.h"
39 #include "intel_de.h"
40 #include "intel_display_types.h"
41 #include "intel_dsi.h"
42 #include "intel_dsi_vbt.h"
43 #include "intel_fifo_underrun.h"
44 #include "intel_panel.h"
45 #include "skl_scaler.h"
46 #include "vlv_dsi.h"
47 #include "vlv_dsi_pll.h"
48 #include "vlv_dsi_regs.h"
49 #include "vlv_sideband.h"
50 
51 /* return pixels in terms of txbyteclkhs */
52 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
53 		       u16 burst_mode_ratio)
54 {
55 	return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
56 					 8 * 100), lane_count);
57 }
58 
59 /* return pixels equvalent to txbyteclkhs */
60 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
61 			u16 burst_mode_ratio)
62 {
63 	return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
64 						(bpp * burst_mode_ratio));
65 }
66 
67 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
68 {
69 	/* It just so happens the VBT matches register contents. */
70 	switch (fmt) {
71 	case VID_MODE_FORMAT_RGB888:
72 		return MIPI_DSI_FMT_RGB888;
73 	case VID_MODE_FORMAT_RGB666:
74 		return MIPI_DSI_FMT_RGB666;
75 	case VID_MODE_FORMAT_RGB666_PACKED:
76 		return MIPI_DSI_FMT_RGB666_PACKED;
77 	case VID_MODE_FORMAT_RGB565:
78 		return MIPI_DSI_FMT_RGB565;
79 	default:
80 		MISSING_CASE(fmt);
81 		return MIPI_DSI_FMT_RGB666;
82 	}
83 }
84 
85 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
86 {
87 	struct drm_encoder *encoder = &intel_dsi->base.base;
88 	struct drm_device *dev = encoder->dev;
89 	struct drm_i915_private *dev_priv = to_i915(dev);
90 	u32 mask;
91 
92 	mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
93 		LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
94 
95 	if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
96 				  mask, 100))
97 		drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
98 }
99 
100 static void write_data(struct drm_i915_private *dev_priv,
101 		       i915_reg_t reg,
102 		       const u8 *data, u32 len)
103 {
104 	u32 i, j;
105 
106 	for (i = 0; i < len; i += 4) {
107 		u32 val = 0;
108 
109 		for (j = 0; j < min_t(u32, len - i, 4); j++)
110 			val |= *data++ << 8 * j;
111 
112 		intel_de_write(dev_priv, reg, val);
113 	}
114 }
115 
116 static void read_data(struct drm_i915_private *dev_priv,
117 		      i915_reg_t reg,
118 		      u8 *data, u32 len)
119 {
120 	u32 i, j;
121 
122 	for (i = 0; i < len; i += 4) {
123 		u32 val = intel_de_read(dev_priv, reg);
124 
125 		for (j = 0; j < min_t(u32, len - i, 4); j++)
126 			*data++ = val >> 8 * j;
127 	}
128 }
129 
130 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
131 				       const struct mipi_dsi_msg *msg)
132 {
133 	struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
134 	struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
135 	struct drm_i915_private *dev_priv = to_i915(dev);
136 	enum port port = intel_dsi_host->port;
137 	struct mipi_dsi_packet packet;
138 	ssize_t ret;
139 	const u8 *header, *data;
140 	i915_reg_t data_reg, ctrl_reg;
141 	u32 data_mask, ctrl_mask;
142 
143 	ret = mipi_dsi_create_packet(&packet, msg);
144 	if (ret < 0)
145 		return ret;
146 
147 	header = packet.header;
148 	data = packet.payload;
149 
150 	if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
151 		data_reg = MIPI_LP_GEN_DATA(port);
152 		data_mask = LP_DATA_FIFO_FULL;
153 		ctrl_reg = MIPI_LP_GEN_CTRL(port);
154 		ctrl_mask = LP_CTRL_FIFO_FULL;
155 	} else {
156 		data_reg = MIPI_HS_GEN_DATA(port);
157 		data_mask = HS_DATA_FIFO_FULL;
158 		ctrl_reg = MIPI_HS_GEN_CTRL(port);
159 		ctrl_mask = HS_CTRL_FIFO_FULL;
160 	}
161 
162 	/* note: this is never true for reads */
163 	if (packet.payload_length) {
164 		if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
165 					    data_mask, 50))
166 			drm_err(&dev_priv->drm,
167 				"Timeout waiting for HS/LP DATA FIFO !full\n");
168 
169 		write_data(dev_priv, data_reg, packet.payload,
170 			   packet.payload_length);
171 	}
172 
173 	if (msg->rx_len) {
174 		intel_de_write(dev_priv, MIPI_INTR_STAT(port),
175 			       GEN_READ_DATA_AVAIL);
176 	}
177 
178 	if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
179 				    ctrl_mask, 50)) {
180 		drm_err(&dev_priv->drm,
181 			"Timeout waiting for HS/LP CTRL FIFO !full\n");
182 	}
183 
184 	intel_de_write(dev_priv, ctrl_reg,
185 		       header[2] << 16 | header[1] << 8 | header[0]);
186 
187 	/* ->rx_len is set only for reads */
188 	if (msg->rx_len) {
189 		data_mask = GEN_READ_DATA_AVAIL;
190 		if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
191 					  data_mask, 50))
192 			drm_err(&dev_priv->drm,
193 				"Timeout waiting for read data.\n");
194 
195 		read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
196 	}
197 
198 	/* XXX: fix for reads and writes */
199 	return 4 + packet.payload_length;
200 }
201 
202 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
203 				 struct mipi_dsi_device *dsi)
204 {
205 	return 0;
206 }
207 
208 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
209 				 struct mipi_dsi_device *dsi)
210 {
211 	return 0;
212 }
213 
214 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
215 	.attach = intel_dsi_host_attach,
216 	.detach = intel_dsi_host_detach,
217 	.transfer = intel_dsi_host_transfer,
218 };
219 
220 /*
221  * send a video mode command
222  *
223  * XXX: commands with data in MIPI_DPI_DATA?
224  */
225 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
226 			enum port port)
227 {
228 	struct drm_encoder *encoder = &intel_dsi->base.base;
229 	struct drm_device *dev = encoder->dev;
230 	struct drm_i915_private *dev_priv = to_i915(dev);
231 	u32 mask;
232 
233 	/* XXX: pipe, hs */
234 	if (hs)
235 		cmd &= ~DPI_LP_MODE;
236 	else
237 		cmd |= DPI_LP_MODE;
238 
239 	/* clear bit */
240 	intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
241 
242 	/* XXX: old code skips write if control unchanged */
243 	if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port)))
244 		drm_dbg_kms(&dev_priv->drm,
245 			    "Same special packet %02x twice in a row.\n", cmd);
246 
247 	intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd);
248 
249 	mask = SPL_PKT_SENT_INTERRUPT;
250 	if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
251 		drm_err(&dev_priv->drm,
252 			"Video mode command 0x%08x send failed.\n", cmd);
253 
254 	return 0;
255 }
256 
257 static void band_gap_reset(struct drm_i915_private *dev_priv)
258 {
259 	vlv_flisdsi_get(dev_priv);
260 
261 	vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
262 	vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
263 	vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
264 	udelay(150);
265 	vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
266 	vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
267 
268 	vlv_flisdsi_put(dev_priv);
269 }
270 
271 static int intel_dsi_compute_config(struct intel_encoder *encoder,
272 				    struct intel_crtc_state *pipe_config,
273 				    struct drm_connector_state *conn_state)
274 {
275 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
276 	struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
277 						   base);
278 	struct intel_connector *intel_connector = intel_dsi->attached_connector;
279 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
280 	int ret;
281 
282 	drm_dbg_kms(&dev_priv->drm, "\n");
283 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
284 
285 	ret = intel_panel_compute_config(intel_connector, adjusted_mode);
286 	if (ret)
287 		return ret;
288 
289 	ret = intel_panel_fitting(pipe_config, conn_state);
290 	if (ret)
291 		return ret;
292 
293 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
294 		return -EINVAL;
295 
296 	/* DSI uses short packets for sync events, so clear mode flags for DSI */
297 	adjusted_mode->flags = 0;
298 
299 	if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
300 		pipe_config->pipe_bpp = 24;
301 	else
302 		pipe_config->pipe_bpp = 18;
303 
304 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
305 		/* Enable Frame time stamp based scanline reporting */
306 		pipe_config->mode_flags |=
307 			I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
308 
309 		/* Dual link goes to DSI transcoder A. */
310 		if (intel_dsi->ports == BIT(PORT_C))
311 			pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
312 		else
313 			pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
314 
315 		ret = bxt_dsi_pll_compute(encoder, pipe_config);
316 		if (ret)
317 			return -EINVAL;
318 	} else {
319 		ret = vlv_dsi_pll_compute(encoder, pipe_config);
320 		if (ret)
321 			return -EINVAL;
322 	}
323 
324 	pipe_config->clock_set = true;
325 
326 	return 0;
327 }
328 
329 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
330 {
331 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
332 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
333 	enum port port;
334 	bool cold_boot = false;
335 
336 	/* Set the MIPI mode
337 	 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
338 	 * Power ON MIPI IO first and then write into IO reset and LP wake bits
339 	 */
340 	for_each_dsi_port(port, intel_dsi->ports)
341 		intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE);
342 
343 	/* Put the IO into reset */
344 	intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
345 
346 	/* Program LP Wake */
347 	for_each_dsi_port(port, intel_dsi->ports) {
348 		u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
349 		intel_de_rmw(dev_priv, MIPI_CTRL(port),
350 			     GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0);
351 	}
352 
353 	/* Wait for Pwr ACK */
354 	for_each_dsi_port(port, intel_dsi->ports) {
355 		if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
356 					  GLK_MIPIIO_PORT_POWERED, 20))
357 			drm_err(&dev_priv->drm, "MIPIO port is powergated\n");
358 	}
359 
360 	/* Check for cold boot scenario */
361 	for_each_dsi_port(port, intel_dsi->ports) {
362 		cold_boot |=
363 			!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY);
364 	}
365 
366 	return cold_boot;
367 }
368 
369 static void glk_dsi_device_ready(struct intel_encoder *encoder)
370 {
371 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
372 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
373 	enum port port;
374 
375 	/* Wait for MIPI PHY status bit to set */
376 	for_each_dsi_port(port, intel_dsi->ports) {
377 		if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
378 					  GLK_PHY_STATUS_PORT_READY, 20))
379 			drm_err(&dev_priv->drm, "PHY is not ON\n");
380 	}
381 
382 	/* Get IO out of reset */
383 	intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);
384 
385 	/* Get IO out of Low power state*/
386 	for_each_dsi_port(port, intel_dsi->ports) {
387 		if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
388 			intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
389 				     ULPS_STATE_MASK, DEVICE_READY);
390 			usleep_range(10, 15);
391 		} else {
392 			/* Enter ULPS */
393 			intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
394 				     ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
395 
396 			/* Wait for ULPS active */
397 			if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
398 						    GLK_ULPS_NOT_ACTIVE, 20))
399 				drm_err(&dev_priv->drm, "ULPS not active\n");
400 
401 			/* Exit ULPS */
402 			intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
403 				     ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY);
404 
405 			/* Enter Normal Mode */
406 			intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
407 				     ULPS_STATE_MASK,
408 				     ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
409 
410 			intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0);
411 		}
412 	}
413 
414 	/* Wait for Stop state */
415 	for_each_dsi_port(port, intel_dsi->ports) {
416 		if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
417 					  GLK_DATA_LANE_STOP_STATE, 20))
418 			drm_err(&dev_priv->drm,
419 				"Date lane not in STOP state\n");
420 	}
421 
422 	/* Wait for AFE LATCH */
423 	for_each_dsi_port(port, intel_dsi->ports) {
424 		if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
425 					  AFE_LATCHOUT, 20))
426 			drm_err(&dev_priv->drm,
427 				"D-PHY not entering LP-11 state\n");
428 	}
429 }
430 
431 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
432 {
433 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
434 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
435 	enum port port;
436 	u32 val;
437 
438 	drm_dbg_kms(&dev_priv->drm, "\n");
439 
440 	/* Enable MIPI PHY transparent latch */
441 	for_each_dsi_port(port, intel_dsi->ports) {
442 		intel_de_rmw(dev_priv, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD);
443 		usleep_range(2000, 2500);
444 	}
445 
446 	/* Clear ULPS and set device ready */
447 	for_each_dsi_port(port, intel_dsi->ports) {
448 		val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
449 		val &= ~ULPS_STATE_MASK;
450 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
451 		usleep_range(2000, 2500);
452 		val |= DEVICE_READY;
453 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
454 	}
455 }
456 
457 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
458 {
459 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
460 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
461 	enum port port;
462 
463 	drm_dbg_kms(&dev_priv->drm, "\n");
464 
465 	vlv_flisdsi_get(dev_priv);
466 	/* program rcomp for compliance, reduce from 50 ohms to 45 ohms
467 	 * needed everytime after power gate */
468 	vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
469 	vlv_flisdsi_put(dev_priv);
470 
471 	/* bandgap reset is needed after everytime we do power gate */
472 	band_gap_reset(dev_priv);
473 
474 	for_each_dsi_port(port, intel_dsi->ports) {
475 
476 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
477 			       ULPS_STATE_ENTER);
478 		usleep_range(2500, 3000);
479 
480 		/* Enable MIPI PHY transparent latch
481 		 * Common bit for both MIPI Port A & MIPI Port C
482 		 * No similar bit in MIPI Port C reg
483 		 */
484 		intel_de_rmw(dev_priv, MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);
485 		usleep_range(1000, 1500);
486 
487 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
488 			       ULPS_STATE_EXIT);
489 		usleep_range(2500, 3000);
490 
491 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
492 			       DEVICE_READY);
493 		usleep_range(2500, 3000);
494 	}
495 }
496 
497 static void intel_dsi_device_ready(struct intel_encoder *encoder)
498 {
499 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
500 
501 	if (IS_GEMINILAKE(dev_priv))
502 		glk_dsi_device_ready(encoder);
503 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
504 		bxt_dsi_device_ready(encoder);
505 	else
506 		vlv_dsi_device_ready(encoder);
507 }
508 
509 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
510 {
511 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
512 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
513 	enum port port;
514 
515 	/* Enter ULPS */
516 	for_each_dsi_port(port, intel_dsi->ports)
517 		intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
518 			     ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
519 
520 	/* Wait for MIPI PHY status bit to unset */
521 	for_each_dsi_port(port, intel_dsi->ports) {
522 		if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
523 					    GLK_PHY_STATUS_PORT_READY, 20))
524 			drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
525 	}
526 
527 	/* Wait for Pwr ACK bit to unset */
528 	for_each_dsi_port(port, intel_dsi->ports) {
529 		if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
530 					    GLK_MIPIIO_PORT_POWERED, 20))
531 			drm_err(&dev_priv->drm,
532 				"MIPI IO Port is not powergated\n");
533 	}
534 }
535 
536 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
537 {
538 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
539 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
540 	enum port port;
541 
542 	/* Put the IO into reset */
543 	intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
544 
545 	/* Wait for MIPI PHY status bit to unset */
546 	for_each_dsi_port(port, intel_dsi->ports) {
547 		if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
548 					    GLK_PHY_STATUS_PORT_READY, 20))
549 			drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
550 	}
551 
552 	/* Clear MIPI mode */
553 	for_each_dsi_port(port, intel_dsi->ports)
554 		intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_ENABLE, 0);
555 }
556 
557 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
558 {
559 	glk_dsi_enter_low_power_mode(encoder);
560 	glk_dsi_disable_mipi_io(encoder);
561 }
562 
563 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
564 {
565 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
566 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
567 	enum port port;
568 
569 	drm_dbg_kms(&dev_priv->drm, "\n");
570 	for_each_dsi_port(port, intel_dsi->ports) {
571 		/* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
572 		i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
573 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
574 
575 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
576 			       DEVICE_READY | ULPS_STATE_ENTER);
577 		usleep_range(2000, 2500);
578 
579 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
580 			       DEVICE_READY | ULPS_STATE_EXIT);
581 		usleep_range(2000, 2500);
582 
583 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
584 			       DEVICE_READY | ULPS_STATE_ENTER);
585 		usleep_range(2000, 2500);
586 
587 		/*
588 		 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
589 		 * Port A only. MIPI Port C has no similar bit for checking.
590 		 */
591 		if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) &&
592 		    intel_de_wait_for_clear(dev_priv, port_ctrl,
593 					    AFE_LATCHOUT, 30))
594 			drm_err(&dev_priv->drm, "DSI LP not going Low\n");
595 
596 		/* Disable MIPI PHY transparent latch */
597 		intel_de_rmw(dev_priv, port_ctrl, LP_OUTPUT_HOLD, 0);
598 		usleep_range(1000, 1500);
599 
600 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00);
601 		usleep_range(2000, 2500);
602 	}
603 }
604 
605 static void intel_dsi_port_enable(struct intel_encoder *encoder,
606 				  const struct intel_crtc_state *crtc_state)
607 {
608 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
609 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
610 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
611 	enum port port;
612 
613 	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
614 		u32 temp = intel_dsi->pixel_overlap;
615 
616 		if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
617 			for_each_dsi_port(port, intel_dsi->ports)
618 				intel_de_rmw(dev_priv, MIPI_CTRL(port),
619 					     BXT_PIXEL_OVERLAP_CNT_MASK,
620 					     temp << BXT_PIXEL_OVERLAP_CNT_SHIFT);
621 		} else {
622 			intel_de_rmw(dev_priv, VLV_CHICKEN_3,
623 				     PIXEL_OVERLAP_CNT_MASK,
624 				     temp << PIXEL_OVERLAP_CNT_SHIFT);
625 		}
626 	}
627 
628 	for_each_dsi_port(port, intel_dsi->ports) {
629 		i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
630 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
631 		u32 temp;
632 
633 		temp = intel_de_read(dev_priv, port_ctrl);
634 
635 		temp &= ~LANE_CONFIGURATION_MASK;
636 		temp &= ~DUAL_LINK_MODE_MASK;
637 
638 		if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
639 			temp |= (intel_dsi->dual_link - 1)
640 						<< DUAL_LINK_MODE_SHIFT;
641 			if (IS_BROXTON(dev_priv))
642 				temp |= LANE_CONFIGURATION_DUAL_LINK_A;
643 			else
644 				temp |= crtc->pipe ?
645 					LANE_CONFIGURATION_DUAL_LINK_B :
646 					LANE_CONFIGURATION_DUAL_LINK_A;
647 		}
648 
649 		if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
650 			temp |= DITHERING_ENABLE;
651 
652 		/* assert ip_tg_enable signal */
653 		intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE);
654 		intel_de_posting_read(dev_priv, port_ctrl);
655 	}
656 }
657 
658 static void intel_dsi_port_disable(struct intel_encoder *encoder)
659 {
660 	struct drm_device *dev = encoder->base.dev;
661 	struct drm_i915_private *dev_priv = to_i915(dev);
662 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
663 	enum port port;
664 
665 	for_each_dsi_port(port, intel_dsi->ports) {
666 		i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
667 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
668 
669 		/* de-assert ip_tg_enable signal */
670 		intel_de_rmw(dev_priv, port_ctrl, DPI_ENABLE, 0);
671 		intel_de_posting_read(dev_priv, port_ctrl);
672 	}
673 }
674 
675 static void intel_dsi_wait_panel_power_cycle(struct intel_dsi *intel_dsi)
676 {
677 	ktime_t panel_power_on_time;
678 	s64 panel_power_off_duration;
679 
680 	panel_power_on_time = ktime_get_boottime();
681 	panel_power_off_duration = ktime_ms_delta(panel_power_on_time,
682 						  intel_dsi->panel_power_off_time);
683 
684 	if (panel_power_off_duration < (s64)intel_dsi->panel_pwr_cycle_delay)
685 		msleep(intel_dsi->panel_pwr_cycle_delay - panel_power_off_duration);
686 }
687 
688 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
689 			      const struct intel_crtc_state *pipe_config);
690 static void intel_dsi_unprepare(struct intel_encoder *encoder);
691 
692 /*
693  * Panel enable/disable sequences from the VBT spec.
694  *
695  * Note the spec has AssertReset / DeassertReset swapped from their
696  * usual naming. We use the normal names to avoid confusion (so below
697  * they are swapped compared to the spec).
698  *
699  * Steps starting with MIPI refer to VBT sequences, note that for v2
700  * VBTs several steps which have a VBT in v2 are expected to be handled
701  * directly by the driver, by directly driving gpios for example.
702  *
703  * v2 video mode seq         v3 video mode seq         command mode seq
704  * - power on                - MIPIPanelPowerOn        - power on
705  * - wait t1+t2                                        - wait t1+t2
706  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
707  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
708  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
709  *                                                     - MIPITearOn
710  *                                                     - MIPIDisplayOn
711  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
712  * - MIPIDisplayOn           - MIPIDisplayOn
713  * - wait t5                                           - wait t5
714  * - backlight on            - MIPIBacklightOn         - backlight on
715  * ...                       ...                       ... issue mem cmds ...
716  * - backlight off           - MIPIBacklightOff        - backlight off
717  * - wait t6                                           - wait t6
718  * - MIPIDisplayOff
719  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
720  *                                                     - MIPITearOff
721  *                           - MIPIDisplayOff          - MIPIDisplayOff
722  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
723  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
724  * - wait t3                                           - wait t3
725  * - power off               - MIPIPanelPowerOff       - power off
726  * - wait t4                                           - wait t4
727  */
728 
729 /*
730  * DSI port enable has to be done before pipe and plane enable, so we do it in
731  * the pre_enable hook instead of the enable hook.
732  */
733 static void intel_dsi_pre_enable(struct intel_atomic_state *state,
734 				 struct intel_encoder *encoder,
735 				 const struct intel_crtc_state *pipe_config,
736 				 const struct drm_connector_state *conn_state)
737 {
738 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
739 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
740 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
741 	enum pipe pipe = crtc->pipe;
742 	enum port port;
743 	bool glk_cold_boot = false;
744 
745 	drm_dbg_kms(&dev_priv->drm, "\n");
746 
747 	intel_dsi_wait_panel_power_cycle(intel_dsi);
748 
749 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
750 
751 	/*
752 	 * The BIOS may leave the PLL in a wonky state where it doesn't
753 	 * lock. It needs to be fully powered down to fix it.
754 	 */
755 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
756 		bxt_dsi_pll_disable(encoder);
757 		bxt_dsi_pll_enable(encoder, pipe_config);
758 	} else {
759 		vlv_dsi_pll_disable(encoder);
760 		vlv_dsi_pll_enable(encoder, pipe_config);
761 	}
762 
763 	if (IS_BROXTON(dev_priv)) {
764 		/* Add MIPI IO reset programming for modeset */
765 		intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL);
766 
767 		/* Power up DSI regulator */
768 		intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
769 		intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0);
770 	}
771 
772 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
773 		/* Disable DPOunit clock gating, can stall pipe */
774 		intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv),
775 			     0, DPOUNIT_CLOCK_GATE_DISABLE);
776 	}
777 
778 	if (!IS_GEMINILAKE(dev_priv))
779 		intel_dsi_prepare(encoder, pipe_config);
780 
781 	/* Give the panel time to power-on and then deassert its reset */
782 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
783 	msleep(intel_dsi->panel_on_delay);
784 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
785 
786 	if (IS_GEMINILAKE(dev_priv)) {
787 		glk_cold_boot = glk_dsi_enable_io(encoder);
788 
789 		/* Prepare port in cold boot(s3/s4) scenario */
790 		if (glk_cold_boot)
791 			intel_dsi_prepare(encoder, pipe_config);
792 	}
793 
794 	/* Put device in ready state (LP-11) */
795 	intel_dsi_device_ready(encoder);
796 
797 	/* Prepare port in normal boot scenario */
798 	if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
799 		intel_dsi_prepare(encoder, pipe_config);
800 
801 	/* Send initialization commands in LP mode */
802 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
803 
804 	/*
805 	 * Enable port in pre-enable phase itself because as per hw team
806 	 * recommendation, port should be enabled before plane & pipe
807 	 */
808 	if (is_cmd_mode(intel_dsi)) {
809 		for_each_dsi_port(port, intel_dsi->ports)
810 			intel_de_write(dev_priv,
811 				       MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
812 		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
813 		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
814 	} else {
815 		msleep(20); /* XXX */
816 		for_each_dsi_port(port, intel_dsi->ports)
817 			dpi_send_cmd(intel_dsi, TURN_ON, false, port);
818 		msleep(100);
819 
820 		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
821 
822 		intel_dsi_port_enable(encoder, pipe_config);
823 	}
824 
825 	intel_backlight_enable(pipe_config, conn_state);
826 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
827 }
828 
829 static void bxt_dsi_enable(struct intel_atomic_state *state,
830 			   struct intel_encoder *encoder,
831 			   const struct intel_crtc_state *crtc_state,
832 			   const struct drm_connector_state *conn_state)
833 {
834 	drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
835 
836 	intel_crtc_vblank_on(crtc_state);
837 }
838 
839 /*
840  * DSI port disable has to be done after pipe and plane disable, so we do it in
841  * the post_disable hook.
842  */
843 static void intel_dsi_disable(struct intel_atomic_state *state,
844 			      struct intel_encoder *encoder,
845 			      const struct intel_crtc_state *old_crtc_state,
846 			      const struct drm_connector_state *old_conn_state)
847 {
848 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
849 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
850 	enum port port;
851 
852 	drm_dbg_kms(&i915->drm, "\n");
853 
854 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
855 	intel_backlight_disable(old_conn_state);
856 
857 	/*
858 	 * According to the spec we should send SHUTDOWN before
859 	 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
860 	 * has shown that the v3 sequence works for v2 VBTs too
861 	 */
862 	if (is_vid_mode(intel_dsi)) {
863 		/* Send Shutdown command to the panel in LP mode */
864 		for_each_dsi_port(port, intel_dsi->ports)
865 			dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
866 		msleep(10);
867 	}
868 }
869 
870 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
871 {
872 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
873 
874 	if (IS_GEMINILAKE(dev_priv))
875 		glk_dsi_clear_device_ready(encoder);
876 	else
877 		vlv_dsi_clear_device_ready(encoder);
878 }
879 
880 static void intel_dsi_post_disable(struct intel_atomic_state *state,
881 				   struct intel_encoder *encoder,
882 				   const struct intel_crtc_state *old_crtc_state,
883 				   const struct drm_connector_state *old_conn_state)
884 {
885 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
886 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
887 	enum port port;
888 
889 	drm_dbg_kms(&dev_priv->drm, "\n");
890 
891 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
892 		intel_crtc_vblank_off(old_crtc_state);
893 
894 		skl_scaler_disable(old_crtc_state);
895 	}
896 
897 	if (is_vid_mode(intel_dsi)) {
898 		for_each_dsi_port(port, intel_dsi->ports)
899 			vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
900 
901 		intel_dsi_port_disable(encoder);
902 		usleep_range(2000, 5000);
903 	}
904 
905 	intel_dsi_unprepare(encoder);
906 
907 	/*
908 	 * if disable packets are sent before sending shutdown packet then in
909 	 * some next enable sequence send turn on packet error is observed
910 	 */
911 	if (is_cmd_mode(intel_dsi))
912 		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
913 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
914 
915 	/* Transition to LP-00 */
916 	intel_dsi_clear_device_ready(encoder);
917 
918 	if (IS_BROXTON(dev_priv)) {
919 		/* Power down DSI regulator to save power */
920 		intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
921 		intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL,
922 			       HS_IO_CTRL_SELECT);
923 
924 		/* Add MIPI IO reset programming for modeset */
925 		intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0);
926 	}
927 
928 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
929 		bxt_dsi_pll_disable(encoder);
930 	} else {
931 		vlv_dsi_pll_disable(encoder);
932 
933 		intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv),
934 			     DPOUNIT_CLOCK_GATE_DISABLE, 0);
935 	}
936 
937 	/* Assert reset */
938 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
939 
940 	msleep(intel_dsi->panel_off_delay);
941 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
942 
943 	intel_dsi->panel_power_off_time = ktime_get_boottime();
944 }
945 
946 static void intel_dsi_shutdown(struct intel_encoder *encoder)
947 {
948 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
949 
950 	intel_dsi_wait_panel_power_cycle(intel_dsi);
951 }
952 
953 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
954 				   enum pipe *pipe)
955 {
956 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
957 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
958 	intel_wakeref_t wakeref;
959 	enum port port;
960 	bool active = false;
961 
962 	drm_dbg_kms(&dev_priv->drm, "\n");
963 
964 	wakeref = intel_display_power_get_if_enabled(dev_priv,
965 						     encoder->power_domain);
966 	if (!wakeref)
967 		return false;
968 
969 	/*
970 	 * On Broxton the PLL needs to be enabled with a valid divider
971 	 * configuration, otherwise accessing DSI registers will hang the
972 	 * machine. See BSpec North Display Engine registers/MIPI[BXT].
973 	 */
974 	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
975 	    !bxt_dsi_pll_is_enabled(dev_priv))
976 		goto out_put_power;
977 
978 	/* XXX: this only works for one DSI output */
979 	for_each_dsi_port(port, intel_dsi->ports) {
980 		i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
981 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
982 		bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE;
983 
984 		/*
985 		 * Due to some hardware limitations on VLV/CHV, the DPI enable
986 		 * bit in port C control register does not get set. As a
987 		 * workaround, check pipe B conf instead.
988 		 */
989 		if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
990 		    port == PORT_C)
991 			enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
992 
993 		/* Try command mode if video mode not enabled */
994 		if (!enabled) {
995 			u32 tmp = intel_de_read(dev_priv,
996 						MIPI_DSI_FUNC_PRG(port));
997 			enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
998 		}
999 
1000 		if (!enabled)
1001 			continue;
1002 
1003 		if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
1004 			continue;
1005 
1006 		if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1007 			u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1008 			tmp &= BXT_PIPE_SELECT_MASK;
1009 			tmp >>= BXT_PIPE_SELECT_SHIFT;
1010 
1011 			if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C))
1012 				continue;
1013 
1014 			*pipe = tmp;
1015 		} else {
1016 			*pipe = port == PORT_A ? PIPE_A : PIPE_B;
1017 		}
1018 
1019 		active = true;
1020 		break;
1021 	}
1022 
1023 out_put_power:
1024 	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1025 
1026 	return active;
1027 }
1028 
1029 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1030 				    struct intel_crtc_state *pipe_config)
1031 {
1032 	struct drm_device *dev = encoder->base.dev;
1033 	struct drm_i915_private *dev_priv = to_i915(dev);
1034 	struct drm_display_mode *adjusted_mode =
1035 					&pipe_config->hw.adjusted_mode;
1036 	struct drm_display_mode *adjusted_mode_sw;
1037 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1038 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1039 	unsigned int lane_count = intel_dsi->lane_count;
1040 	unsigned int bpp, fmt;
1041 	enum port port;
1042 	u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1043 	u16 hfp_sw, hsync_sw, hbp_sw;
1044 	u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1045 				crtc_hblank_start_sw, crtc_hblank_end_sw;
1046 
1047 	/* FIXME: hw readout should not depend on SW state */
1048 	adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1049 
1050 	/*
1051 	 * Atleast one port is active as encoder->get_config called only if
1052 	 * encoder->get_hw_state() returns true.
1053 	 */
1054 	for_each_dsi_port(port, intel_dsi->ports) {
1055 		if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1056 			break;
1057 	}
1058 
1059 	fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1060 	bpp = mipi_dsi_pixel_format_to_bpp(
1061 			pixel_format_from_register_bits(fmt));
1062 
1063 	pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
1064 
1065 	/* Enable Frame time stamo based scanline reporting */
1066 	pipe_config->mode_flags |=
1067 		I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1068 
1069 	/* In terms of pixels */
1070 	adjusted_mode->crtc_hdisplay =
1071 				intel_de_read(dev_priv,
1072 				              BXT_MIPI_TRANS_HACTIVE(port));
1073 	adjusted_mode->crtc_vdisplay =
1074 				intel_de_read(dev_priv,
1075 				              BXT_MIPI_TRANS_VACTIVE(port));
1076 	adjusted_mode->crtc_vtotal =
1077 				intel_de_read(dev_priv,
1078 				              BXT_MIPI_TRANS_VTOTAL(port));
1079 
1080 	hactive = adjusted_mode->crtc_hdisplay;
1081 	hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port));
1082 
1083 	/*
1084 	 * Meaningful for video mode non-burst sync pulse mode only,
1085 	 * can be zero for non-burst sync events and burst modes
1086 	 */
1087 	hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port));
1088 	hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port));
1089 
1090 	/* harizontal values are in terms of high speed byte clock */
1091 	hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1092 						intel_dsi->burst_mode_ratio);
1093 	hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1094 						intel_dsi->burst_mode_ratio);
1095 	hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1096 						intel_dsi->burst_mode_ratio);
1097 
1098 	if (intel_dsi->dual_link) {
1099 		hfp *= 2;
1100 		hsync *= 2;
1101 		hbp *= 2;
1102 	}
1103 
1104 	/* vertical values are in terms of lines */
1105 	vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port));
1106 	vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port));
1107 	vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port));
1108 
1109 	adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1110 	adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1111 	adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1112 	adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1113 	adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1114 
1115 	adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1116 	adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1117 	adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1118 	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1119 
1120 	/*
1121 	 * In BXT DSI there is no regs programmed with few horizontal timings
1122 	 * in Pixels but txbyteclkhs.. So retrieval process adds some
1123 	 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1124 	 * Actually here for the given adjusted_mode, we are calculating the
1125 	 * value programmed to the port and then back to the horizontal timing
1126 	 * param in pixels. This is the expected value, including roundup errors
1127 	 * And if that is same as retrieved value from port, then
1128 	 * (HW state) adjusted_mode's horizontal timings are corrected to
1129 	 * match with SW state to nullify the errors.
1130 	 */
1131 	/* Calculating the value programmed to the Port register */
1132 	hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1133 					adjusted_mode_sw->crtc_hdisplay;
1134 	hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1135 					adjusted_mode_sw->crtc_hsync_start;
1136 	hbp_sw = adjusted_mode_sw->crtc_htotal -
1137 					adjusted_mode_sw->crtc_hsync_end;
1138 
1139 	if (intel_dsi->dual_link) {
1140 		hfp_sw /= 2;
1141 		hsync_sw /= 2;
1142 		hbp_sw /= 2;
1143 	}
1144 
1145 	hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1146 						intel_dsi->burst_mode_ratio);
1147 	hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1148 			    intel_dsi->burst_mode_ratio);
1149 	hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1150 						intel_dsi->burst_mode_ratio);
1151 
1152 	/* Reverse calculating the adjusted mode parameters from port reg vals*/
1153 	hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1154 						intel_dsi->burst_mode_ratio);
1155 	hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1156 						intel_dsi->burst_mode_ratio);
1157 	hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1158 						intel_dsi->burst_mode_ratio);
1159 
1160 	if (intel_dsi->dual_link) {
1161 		hfp_sw *= 2;
1162 		hsync_sw *= 2;
1163 		hbp_sw *= 2;
1164 	}
1165 
1166 	crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1167 							hsync_sw + hbp_sw;
1168 	crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1169 	crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1170 	crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1171 	crtc_hblank_end_sw = crtc_htotal_sw;
1172 
1173 	if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1174 		adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1175 
1176 	if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1177 		adjusted_mode->crtc_hsync_start =
1178 					adjusted_mode_sw->crtc_hsync_start;
1179 
1180 	if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1181 		adjusted_mode->crtc_hsync_end =
1182 					adjusted_mode_sw->crtc_hsync_end;
1183 
1184 	if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1185 		adjusted_mode->crtc_hblank_start =
1186 					adjusted_mode_sw->crtc_hblank_start;
1187 
1188 	if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1189 		adjusted_mode->crtc_hblank_end =
1190 					adjusted_mode_sw->crtc_hblank_end;
1191 }
1192 
1193 static void intel_dsi_get_config(struct intel_encoder *encoder,
1194 				 struct intel_crtc_state *pipe_config)
1195 {
1196 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1197 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1198 	u32 pclk;
1199 
1200 	drm_dbg_kms(&dev_priv->drm, "\n");
1201 
1202 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1203 
1204 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1205 		bxt_dsi_get_pipe_config(encoder, pipe_config);
1206 		pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1207 	} else {
1208 		pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1209 	}
1210 
1211 	pipe_config->port_clock = pclk;
1212 
1213 	/* FIXME definitely not right for burst/cmd mode/pixel overlap */
1214 	pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1215 	if (intel_dsi->dual_link)
1216 		pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1217 }
1218 
1219 /* return txclkesc cycles in terms of divider and duration in us */
1220 static u16 txclkesc(u32 divider, unsigned int us)
1221 {
1222 	switch (divider) {
1223 	case ESCAPE_CLOCK_DIVIDER_1:
1224 	default:
1225 		return 20 * us;
1226 	case ESCAPE_CLOCK_DIVIDER_2:
1227 		return 10 * us;
1228 	case ESCAPE_CLOCK_DIVIDER_4:
1229 		return 5 * us;
1230 	}
1231 }
1232 
1233 static void set_dsi_timings(struct drm_encoder *encoder,
1234 			    const struct drm_display_mode *adjusted_mode)
1235 {
1236 	struct drm_device *dev = encoder->dev;
1237 	struct drm_i915_private *dev_priv = to_i915(dev);
1238 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1239 	enum port port;
1240 	unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1241 	unsigned int lane_count = intel_dsi->lane_count;
1242 
1243 	u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1244 
1245 	hactive = adjusted_mode->crtc_hdisplay;
1246 	hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1247 	hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1248 	hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1249 
1250 	if (intel_dsi->dual_link) {
1251 		hactive /= 2;
1252 		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1253 			hactive += intel_dsi->pixel_overlap;
1254 		hfp /= 2;
1255 		hsync /= 2;
1256 		hbp /= 2;
1257 	}
1258 
1259 	vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1260 	vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1261 	vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1262 
1263 	/* horizontal values are in terms of high speed byte clock */
1264 	hactive = txbyteclkhs(hactive, bpp, lane_count,
1265 			      intel_dsi->burst_mode_ratio);
1266 	hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1267 	hsync = txbyteclkhs(hsync, bpp, lane_count,
1268 			    intel_dsi->burst_mode_ratio);
1269 	hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1270 
1271 	for_each_dsi_port(port, intel_dsi->ports) {
1272 		if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1273 			/*
1274 			 * Program hdisplay and vdisplay on MIPI transcoder.
1275 			 * This is different from calculated hactive and
1276 			 * vactive, as they are calculated per channel basis,
1277 			 * whereas these values should be based on resolution.
1278 			 */
1279 			intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port),
1280 				       adjusted_mode->crtc_hdisplay);
1281 			intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port),
1282 				       adjusted_mode->crtc_vdisplay);
1283 			intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port),
1284 				       adjusted_mode->crtc_vtotal);
1285 		}
1286 
1287 		intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port),
1288 			       hactive);
1289 		intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp);
1290 
1291 		/* meaningful for video mode non-burst sync pulse mode only,
1292 		 * can be zero for non-burst sync events and burst modes */
1293 		intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port),
1294 			       hsync);
1295 		intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp);
1296 
1297 		/* vertical values are in terms of lines */
1298 		intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp);
1299 		intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port),
1300 			       vsync);
1301 		intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp);
1302 	}
1303 }
1304 
1305 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1306 {
1307 	switch (fmt) {
1308 	case MIPI_DSI_FMT_RGB888:
1309 		return VID_MODE_FORMAT_RGB888;
1310 	case MIPI_DSI_FMT_RGB666:
1311 		return VID_MODE_FORMAT_RGB666;
1312 	case MIPI_DSI_FMT_RGB666_PACKED:
1313 		return VID_MODE_FORMAT_RGB666_PACKED;
1314 	case MIPI_DSI_FMT_RGB565:
1315 		return VID_MODE_FORMAT_RGB565;
1316 	default:
1317 		MISSING_CASE(fmt);
1318 		return VID_MODE_FORMAT_RGB666;
1319 	}
1320 }
1321 
1322 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1323 			      const struct intel_crtc_state *pipe_config)
1324 {
1325 	struct drm_encoder *encoder = &intel_encoder->base;
1326 	struct drm_device *dev = encoder->dev;
1327 	struct drm_i915_private *dev_priv = to_i915(dev);
1328 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1329 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1330 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1331 	enum port port;
1332 	unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1333 	u32 val, tmp;
1334 	u16 mode_hdisplay;
1335 
1336 	drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe));
1337 
1338 	mode_hdisplay = adjusted_mode->crtc_hdisplay;
1339 
1340 	if (intel_dsi->dual_link) {
1341 		mode_hdisplay /= 2;
1342 		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1343 			mode_hdisplay += intel_dsi->pixel_overlap;
1344 	}
1345 
1346 	for_each_dsi_port(port, intel_dsi->ports) {
1347 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1348 			/*
1349 			 * escape clock divider, 20MHz, shared for A and C.
1350 			 * device ready must be off when doing this! txclkesc?
1351 			 */
1352 			tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
1353 			tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1354 			intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
1355 				       tmp | ESCAPE_CLOCK_DIVIDER_1);
1356 
1357 			/* read request priority is per pipe */
1358 			tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1359 			tmp &= ~READ_REQUEST_PRIORITY_MASK;
1360 			intel_de_write(dev_priv, MIPI_CTRL(port),
1361 				       tmp | READ_REQUEST_PRIORITY_HIGH);
1362 		} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1363 			enum pipe pipe = crtc->pipe;
1364 
1365 			intel_de_rmw(dev_priv, MIPI_CTRL(port),
1366 				     BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe));
1367 		}
1368 
1369 		/* XXX: why here, why like this? handling in irq handler?! */
1370 		intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff);
1371 		intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff);
1372 
1373 		intel_de_write(dev_priv, MIPI_DPHY_PARAM(port),
1374 			       intel_dsi->dphy_reg);
1375 
1376 		intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port),
1377 			       adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1378 	}
1379 
1380 	set_dsi_timings(encoder, adjusted_mode);
1381 
1382 	val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1383 	if (is_cmd_mode(intel_dsi)) {
1384 		val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1385 		val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1386 	} else {
1387 		val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1388 		val |= pixel_format_to_reg(intel_dsi->pixel_format);
1389 	}
1390 
1391 	tmp = 0;
1392 	if (intel_dsi->eotp_pkt == 0)
1393 		tmp |= EOT_DISABLE;
1394 	if (intel_dsi->clock_stop)
1395 		tmp |= CLOCKSTOP;
1396 
1397 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1398 		tmp |= BXT_DPHY_DEFEATURE_EN;
1399 		if (!is_cmd_mode(intel_dsi))
1400 			tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1401 	}
1402 
1403 	for_each_dsi_port(port, intel_dsi->ports) {
1404 		intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1405 
1406 		/* timeouts for recovery. one frame IIUC. if counter expires,
1407 		 * EOT and stop state. */
1408 
1409 		/*
1410 		 * In burst mode, value greater than one DPI line Time in byte
1411 		 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1412 		 * said value is recommended.
1413 		 *
1414 		 * In non-burst mode, Value greater than one DPI frame time in
1415 		 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1416 		 * said value is recommended.
1417 		 *
1418 		 * In DBI only mode, value greater than one DBI frame time in
1419 		 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1420 		 * said value is recommended.
1421 		 */
1422 
1423 		if (is_vid_mode(intel_dsi) &&
1424 			intel_dsi->video_mode == BURST_MODE) {
1425 			intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1426 				       txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1427 		} else {
1428 			intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1429 				       txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1430 		}
1431 		intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port),
1432 			       intel_dsi->lp_rx_timeout);
1433 		intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port),
1434 			       intel_dsi->turn_arnd_val);
1435 		intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port),
1436 			       intel_dsi->rst_timer_val);
1437 
1438 		/* dphy stuff */
1439 
1440 		/* in terms of low power clock */
1441 		intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1442 			       txclkesc(intel_dsi->escape_clk_div, 100));
1443 
1444 		if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1445 		    !intel_dsi->dual_link) {
1446 			/*
1447 			 * BXT spec says write MIPI_INIT_COUNT for
1448 			 * both the ports, even if only one is
1449 			 * getting used. So write the other port
1450 			 * if not in dual link mode.
1451 			 */
1452 			intel_de_write(dev_priv,
1453 				       MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A),
1454 				       intel_dsi->init_count);
1455 		}
1456 
1457 		/* recovery disables */
1458 		intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp);
1459 
1460 		/* in terms of low power clock */
1461 		intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1462 			       intel_dsi->init_count);
1463 
1464 		/* in terms of txbyteclkhs. actual high to low switch +
1465 		 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1466 		 *
1467 		 * XXX: write MIPI_STOP_STATE_STALL?
1468 		 */
1469 		intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port),
1470 			       intel_dsi->hs_to_lp_count);
1471 
1472 		/* XXX: low power clock equivalence in terms of byte clock.
1473 		 * the number of byte clocks occupied in one low power clock.
1474 		 * based on txbyteclkhs and txclkesc.
1475 		 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1476 		 * ) / 105.???
1477 		 */
1478 		intel_de_write(dev_priv, MIPI_LP_BYTECLK(port),
1479 			       intel_dsi->lp_byte_clk);
1480 
1481 		if (IS_GEMINILAKE(dev_priv)) {
1482 			intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port),
1483 				       intel_dsi->lp_byte_clk);
1484 			/* Shadow of DPHY reg */
1485 			intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port),
1486 				       intel_dsi->dphy_reg);
1487 		}
1488 
1489 		/* the bw essential for transmitting 16 long packets containing
1490 		 * 252 bytes meant for dcs write memory command is programmed in
1491 		 * this register in terms of byte clocks. based on dsi transfer
1492 		 * rate and the number of lanes configured the time taken to
1493 		 * transmit 16 long packets in a dsi stream varies. */
1494 		intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port),
1495 			       intel_dsi->bw_timer);
1496 
1497 		intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1498 			       intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1499 
1500 		if (is_vid_mode(intel_dsi)) {
1501 			u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG;
1502 
1503 			/*
1504 			 * Some panels might have resolution which is not a
1505 			 * multiple of 64 like 1366 x 768. Enable RANDOM
1506 			 * resolution support for such panels by default.
1507 			 */
1508 			fmt |= RANDOM_DPI_DISPLAY_RESOLUTION;
1509 
1510 			switch (intel_dsi->video_mode) {
1511 			default:
1512 				MISSING_CASE(intel_dsi->video_mode);
1513 				fallthrough;
1514 			case NON_BURST_SYNC_EVENTS:
1515 				fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS;
1516 				break;
1517 			case NON_BURST_SYNC_PULSE:
1518 				fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE;
1519 				break;
1520 			case BURST_MODE:
1521 				fmt |= VIDEO_MODE_BURST;
1522 				break;
1523 			}
1524 
1525 			intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt);
1526 		}
1527 	}
1528 }
1529 
1530 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1531 {
1532 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1533 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1534 	enum port port;
1535 
1536 	if (IS_GEMINILAKE(dev_priv))
1537 		return;
1538 
1539 	for_each_dsi_port(port, intel_dsi->ports) {
1540 		/* Panel commands can be sent when clock is in LP11 */
1541 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0);
1542 
1543 		if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1544 			bxt_dsi_reset_clocks(encoder, port);
1545 		else
1546 			vlv_dsi_reset_clocks(encoder, port);
1547 		intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
1548 
1549 		intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(port), VID_MODE_FORMAT_MASK, 0);
1550 
1551 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1);
1552 	}
1553 }
1554 
1555 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1556 {
1557 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1558 
1559 	intel_dsi_vbt_gpio_cleanup(intel_dsi);
1560 	intel_encoder_destroy(encoder);
1561 }
1562 
1563 static const struct drm_encoder_funcs intel_dsi_funcs = {
1564 	.destroy = intel_dsi_encoder_destroy,
1565 };
1566 
1567 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1568 	.get_modes = intel_dsi_get_modes,
1569 	.mode_valid = intel_dsi_mode_valid,
1570 	.atomic_check = intel_digital_connector_atomic_check,
1571 };
1572 
1573 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1574 	.detect = intel_panel_detect,
1575 	.late_register = intel_connector_register,
1576 	.early_unregister = intel_connector_unregister,
1577 	.destroy = intel_connector_destroy,
1578 	.fill_modes = drm_helper_probe_single_connector_modes,
1579 	.atomic_get_property = intel_digital_connector_atomic_get_property,
1580 	.atomic_set_property = intel_digital_connector_atomic_set_property,
1581 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1582 	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
1583 };
1584 
1585 static void vlv_dsi_add_properties(struct intel_connector *connector)
1586 {
1587 	const struct drm_display_mode *fixed_mode =
1588 		intel_panel_preferred_fixed_mode(connector);
1589 
1590 	intel_attach_scaling_mode_property(&connector->base);
1591 
1592 	drm_connector_set_panel_orientation_with_quirk(&connector->base,
1593 						       intel_dsi_get_panel_orientation(connector),
1594 						       fixed_mode->hdisplay,
1595 						       fixed_mode->vdisplay);
1596 }
1597 
1598 #define NS_KHZ_RATIO		1000000
1599 
1600 #define PREPARE_CNT_MAX		0x3F
1601 #define EXIT_ZERO_CNT_MAX	0x3F
1602 #define CLK_ZERO_CNT_MAX	0xFF
1603 #define TRAIL_CNT_MAX		0x1F
1604 
1605 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1606 {
1607 	struct drm_device *dev = intel_dsi->base.base.dev;
1608 	struct drm_i915_private *dev_priv = to_i915(dev);
1609 	struct intel_connector *connector = intel_dsi->attached_connector;
1610 	struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1611 	u32 tlpx_ns, extra_byte_count, tlpx_ui;
1612 	u32 ui_num, ui_den;
1613 	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1614 	u32 ths_prepare_ns, tclk_trail_ns;
1615 	u32 tclk_prepare_clkzero, ths_prepare_hszero;
1616 	u32 lp_to_hs_switch, hs_to_lp_switch;
1617 	u32 mul;
1618 
1619 	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1620 
1621 	switch (intel_dsi->lane_count) {
1622 	case 1:
1623 	case 2:
1624 		extra_byte_count = 2;
1625 		break;
1626 	case 3:
1627 		extra_byte_count = 4;
1628 		break;
1629 	case 4:
1630 	default:
1631 		extra_byte_count = 3;
1632 		break;
1633 	}
1634 
1635 	/* in Kbps */
1636 	ui_num = NS_KHZ_RATIO;
1637 	ui_den = intel_dsi_bitrate(intel_dsi);
1638 
1639 	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1640 	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1641 
1642 	/*
1643 	 * B060
1644 	 * LP byte clock = TLPX/ (8UI)
1645 	 */
1646 	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1647 
1648 	/* DDR clock period = 2 * UI
1649 	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1650 	 * UI(nsec) = 10^6 / bitrate
1651 	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1652 	 * DDR clock count  = ns_value / DDR clock period
1653 	 *
1654 	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
1655 	 * HS byte clock count for other platform in HS ddr clock count
1656 	 */
1657 	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1658 	ths_prepare_ns = max(mipi_config->ths_prepare,
1659 			     mipi_config->tclk_prepare);
1660 
1661 	/* prepare count */
1662 	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1663 
1664 	if (prepare_cnt > PREPARE_CNT_MAX) {
1665 		drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",
1666 			    prepare_cnt);
1667 		prepare_cnt = PREPARE_CNT_MAX;
1668 	}
1669 
1670 	/* exit zero count */
1671 	exit_zero_cnt = DIV_ROUND_UP(
1672 				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
1673 				ui_num * mul
1674 				);
1675 
1676 	/*
1677 	 * Exit zero is unified val ths_zero and ths_exit
1678 	 * minimum value for ths_exit = 110ns
1679 	 * min (exit_zero_cnt * 2) = 110/UI
1680 	 * exit_zero_cnt = 55/UI
1681 	 */
1682 	if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1683 		exit_zero_cnt += 1;
1684 
1685 	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1686 		drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",
1687 			    exit_zero_cnt);
1688 		exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1689 	}
1690 
1691 	/* clk zero count */
1692 	clk_zero_cnt = DIV_ROUND_UP(
1693 				(tclk_prepare_clkzero -	ths_prepare_ns)
1694 				* ui_den, ui_num * mul);
1695 
1696 	if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1697 		drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",
1698 			    clk_zero_cnt);
1699 		clk_zero_cnt = CLK_ZERO_CNT_MAX;
1700 	}
1701 
1702 	/* trail count */
1703 	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1704 	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1705 
1706 	if (trail_cnt > TRAIL_CNT_MAX) {
1707 		drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",
1708 			    trail_cnt);
1709 		trail_cnt = TRAIL_CNT_MAX;
1710 	}
1711 
1712 	/* B080 */
1713 	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1714 						clk_zero_cnt << 8 | prepare_cnt;
1715 
1716 	/*
1717 	 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1718 	 *					mul + 10UI + Extra Byte Count
1719 	 *
1720 	 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1721 	 * Extra Byte Count is calculated according to number of lanes.
1722 	 * High Low Switch Count is the Max of LP to HS and
1723 	 * HS to LP switch count
1724 	 *
1725 	 */
1726 	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1727 
1728 	/* B044 */
1729 	/* FIXME:
1730 	 * The comment above does not match with the code */
1731 	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1732 						exit_zero_cnt * mul + 10, 8);
1733 
1734 	hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1735 
1736 	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1737 	intel_dsi->hs_to_lp_count += extra_byte_count;
1738 
1739 	/* B088 */
1740 	/* LP -> HS for clock lanes
1741 	 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1742 	 *						extra byte count
1743 	 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1744 	 *					2(in UI) + extra byte count
1745 	 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1746 	 *					8 + extra byte count
1747 	 */
1748 	intel_dsi->clk_lp_to_hs_count =
1749 		DIV_ROUND_UP(
1750 			4 * tlpx_ui + prepare_cnt * 2 +
1751 			clk_zero_cnt * 2,
1752 			8);
1753 
1754 	intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1755 
1756 	/* HS->LP for Clock Lanes
1757 	 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1758 	 *						Extra byte count
1759 	 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1760 	 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1761 	 *						Extra byte count
1762 	 */
1763 	intel_dsi->clk_hs_to_lp_count =
1764 		DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1765 			8);
1766 	intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1767 
1768 	intel_dsi_log_params(intel_dsi);
1769 }
1770 
1771 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1772 {
1773 	struct intel_dsi *intel_dsi;
1774 	struct intel_encoder *intel_encoder;
1775 	struct drm_encoder *encoder;
1776 	struct intel_connector *intel_connector;
1777 	struct drm_connector *connector;
1778 	struct drm_display_mode *current_mode;
1779 	enum port port;
1780 	enum pipe pipe;
1781 
1782 	drm_dbg_kms(&dev_priv->drm, "\n");
1783 
1784 	/* There is no detection method for MIPI so rely on VBT */
1785 	if (!intel_bios_is_dsi_present(dev_priv, &port))
1786 		return;
1787 
1788 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1789 		dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;
1790 	else
1791 		dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;
1792 
1793 	intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1794 	if (!intel_dsi)
1795 		return;
1796 
1797 	intel_connector = intel_connector_alloc();
1798 	if (!intel_connector) {
1799 		kfree(intel_dsi);
1800 		return;
1801 	}
1802 
1803 	intel_encoder = &intel_dsi->base;
1804 	encoder = &intel_encoder->base;
1805 	intel_dsi->attached_connector = intel_connector;
1806 
1807 	connector = &intel_connector->base;
1808 
1809 	drm_encoder_init(&dev_priv->drm, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1810 			 "DSI %c", port_name(port));
1811 
1812 	intel_encoder->compute_config = intel_dsi_compute_config;
1813 	intel_encoder->pre_enable = intel_dsi_pre_enable;
1814 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1815 		intel_encoder->enable = bxt_dsi_enable;
1816 	intel_encoder->disable = intel_dsi_disable;
1817 	intel_encoder->post_disable = intel_dsi_post_disable;
1818 	intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1819 	intel_encoder->get_config = intel_dsi_get_config;
1820 	intel_encoder->update_pipe = intel_backlight_update;
1821 	intel_encoder->shutdown = intel_dsi_shutdown;
1822 
1823 	intel_connector->get_hw_state = intel_connector_get_hw_state;
1824 
1825 	intel_encoder->port = port;
1826 	intel_encoder->type = INTEL_OUTPUT_DSI;
1827 	intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1828 	intel_encoder->cloneable = 0;
1829 
1830 	/*
1831 	 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1832 	 * port C. BXT isn't limited like this.
1833 	 */
1834 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1835 		intel_encoder->pipe_mask = ~0;
1836 	else if (port == PORT_A)
1837 		intel_encoder->pipe_mask = BIT(PIPE_A);
1838 	else
1839 		intel_encoder->pipe_mask = BIT(PIPE_B);
1840 
1841 	intel_dsi->panel_power_off_time = ktime_get_boottime();
1842 
1843 	intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL, NULL);
1844 
1845 	if (intel_connector->panel.vbt.dsi.config->dual_link)
1846 		intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1847 	else
1848 		intel_dsi->ports = BIT(port);
1849 
1850 	if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
1851 		intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
1852 
1853 	if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
1854 		intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
1855 
1856 	/* Create a DSI host (and a device) for each port. */
1857 	for_each_dsi_port(port, intel_dsi->ports) {
1858 		struct intel_dsi_host *host;
1859 
1860 		host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1861 					   port);
1862 		if (!host)
1863 			goto err;
1864 
1865 		intel_dsi->dsi_hosts[port] = host;
1866 	}
1867 
1868 	if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1869 		drm_dbg_kms(&dev_priv->drm, "no device found\n");
1870 		goto err;
1871 	}
1872 
1873 	/* Use clock read-back from current hw-state for fastboot */
1874 	current_mode = intel_encoder_current_mode(intel_encoder);
1875 	if (current_mode) {
1876 		drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",
1877 			    intel_dsi->pclk, current_mode->clock);
1878 		if (intel_fuzzy_clock_check(intel_dsi->pclk,
1879 					    current_mode->clock)) {
1880 			drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n");
1881 			intel_dsi->pclk = current_mode->clock;
1882 		}
1883 
1884 		kfree(current_mode);
1885 	}
1886 
1887 	vlv_dphy_param_init(intel_dsi);
1888 
1889 	intel_dsi_vbt_gpio_init(intel_dsi,
1890 				intel_dsi_get_hw_state(intel_encoder, &pipe));
1891 
1892 	drm_connector_init(&dev_priv->drm, connector, &intel_dsi_connector_funcs,
1893 			   DRM_MODE_CONNECTOR_DSI);
1894 
1895 	drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1896 
1897 	connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1898 
1899 	intel_connector_attach_encoder(intel_connector, intel_encoder);
1900 
1901 	mutex_lock(&dev_priv->drm.mode_config.mutex);
1902 	intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
1903 	mutex_unlock(&dev_priv->drm.mode_config.mutex);
1904 
1905 	if (!intel_panel_preferred_fixed_mode(intel_connector)) {
1906 		drm_dbg_kms(&dev_priv->drm, "no fixed mode\n");
1907 		goto err_cleanup_connector;
1908 	}
1909 
1910 	intel_panel_init(intel_connector, NULL);
1911 
1912 	intel_backlight_setup(intel_connector, INVALID_PIPE);
1913 
1914 	vlv_dsi_add_properties(intel_connector);
1915 
1916 	return;
1917 
1918 err_cleanup_connector:
1919 	drm_connector_cleanup(&intel_connector->base);
1920 err:
1921 	drm_encoder_cleanup(&intel_encoder->base);
1922 	kfree(intel_dsi);
1923 	kfree(intel_connector);
1924 }
1925