1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Jani Nikula <jani.nikula@intel.com> 24 */ 25 26 #include <linux/gpio/consumer.h> 27 #include <linux/slab.h> 28 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_crtc.h> 31 #include <drm/drm_edid.h> 32 #include <drm/drm_mipi_dsi.h> 33 34 #include "i915_drv.h" 35 #include "intel_atomic.h" 36 #include "intel_connector.h" 37 #include "intel_drv.h" 38 #include "intel_dsi.h" 39 #include "intel_fifo_underrun.h" 40 #include "intel_panel.h" 41 #include "intel_sideband.h" 42 43 /* return pixels in terms of txbyteclkhs */ 44 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, 45 u16 burst_mode_ratio) 46 { 47 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, 48 8 * 100), lane_count); 49 } 50 51 /* return pixels equvalent to txbyteclkhs */ 52 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, 53 u16 burst_mode_ratio) 54 { 55 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), 56 (bpp * burst_mode_ratio)); 57 } 58 59 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 60 { 61 /* It just so happens the VBT matches register contents. */ 62 switch (fmt) { 63 case VID_MODE_FORMAT_RGB888: 64 return MIPI_DSI_FMT_RGB888; 65 case VID_MODE_FORMAT_RGB666: 66 return MIPI_DSI_FMT_RGB666; 67 case VID_MODE_FORMAT_RGB666_PACKED: 68 return MIPI_DSI_FMT_RGB666_PACKED; 69 case VID_MODE_FORMAT_RGB565: 70 return MIPI_DSI_FMT_RGB565; 71 default: 72 MISSING_CASE(fmt); 73 return MIPI_DSI_FMT_RGB666; 74 } 75 } 76 77 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) 78 { 79 struct drm_encoder *encoder = &intel_dsi->base.base; 80 struct drm_device *dev = encoder->dev; 81 struct drm_i915_private *dev_priv = to_i915(dev); 82 u32 mask; 83 84 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | 85 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; 86 87 if (intel_wait_for_register(&dev_priv->uncore, 88 MIPI_GEN_FIFO_STAT(port), mask, mask, 89 100)) 90 DRM_ERROR("DPI FIFOs are not empty\n"); 91 } 92 93 static void write_data(struct drm_i915_private *dev_priv, 94 i915_reg_t reg, 95 const u8 *data, u32 len) 96 { 97 u32 i, j; 98 99 for (i = 0; i < len; i += 4) { 100 u32 val = 0; 101 102 for (j = 0; j < min_t(u32, len - i, 4); j++) 103 val |= *data++ << 8 * j; 104 105 I915_WRITE(reg, val); 106 } 107 } 108 109 static void read_data(struct drm_i915_private *dev_priv, 110 i915_reg_t reg, 111 u8 *data, u32 len) 112 { 113 u32 i, j; 114 115 for (i = 0; i < len; i += 4) { 116 u32 val = I915_READ(reg); 117 118 for (j = 0; j < min_t(u32, len - i, 4); j++) 119 *data++ = val >> 8 * j; 120 } 121 } 122 123 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, 124 const struct mipi_dsi_msg *msg) 125 { 126 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 127 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; 128 struct drm_i915_private *dev_priv = to_i915(dev); 129 enum port port = intel_dsi_host->port; 130 struct mipi_dsi_packet packet; 131 ssize_t ret; 132 const u8 *header, *data; 133 i915_reg_t data_reg, ctrl_reg; 134 u32 data_mask, ctrl_mask; 135 136 ret = mipi_dsi_create_packet(&packet, msg); 137 if (ret < 0) 138 return ret; 139 140 header = packet.header; 141 data = packet.payload; 142 143 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 144 data_reg = MIPI_LP_GEN_DATA(port); 145 data_mask = LP_DATA_FIFO_FULL; 146 ctrl_reg = MIPI_LP_GEN_CTRL(port); 147 ctrl_mask = LP_CTRL_FIFO_FULL; 148 } else { 149 data_reg = MIPI_HS_GEN_DATA(port); 150 data_mask = HS_DATA_FIFO_FULL; 151 ctrl_reg = MIPI_HS_GEN_CTRL(port); 152 ctrl_mask = HS_CTRL_FIFO_FULL; 153 } 154 155 /* note: this is never true for reads */ 156 if (packet.payload_length) { 157 if (intel_wait_for_register(&dev_priv->uncore, 158 MIPI_GEN_FIFO_STAT(port), 159 data_mask, 0, 160 50)) 161 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); 162 163 write_data(dev_priv, data_reg, packet.payload, 164 packet.payload_length); 165 } 166 167 if (msg->rx_len) { 168 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); 169 } 170 171 if (intel_wait_for_register(&dev_priv->uncore, 172 MIPI_GEN_FIFO_STAT(port), 173 ctrl_mask, 0, 174 50)) { 175 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); 176 } 177 178 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); 179 180 /* ->rx_len is set only for reads */ 181 if (msg->rx_len) { 182 data_mask = GEN_READ_DATA_AVAIL; 183 if (intel_wait_for_register(&dev_priv->uncore, 184 MIPI_INTR_STAT(port), 185 data_mask, data_mask, 186 50)) 187 DRM_ERROR("Timeout waiting for read data.\n"); 188 189 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); 190 } 191 192 /* XXX: fix for reads and writes */ 193 return 4 + packet.payload_length; 194 } 195 196 static int intel_dsi_host_attach(struct mipi_dsi_host *host, 197 struct mipi_dsi_device *dsi) 198 { 199 return 0; 200 } 201 202 static int intel_dsi_host_detach(struct mipi_dsi_host *host, 203 struct mipi_dsi_device *dsi) 204 { 205 return 0; 206 } 207 208 static const struct mipi_dsi_host_ops intel_dsi_host_ops = { 209 .attach = intel_dsi_host_attach, 210 .detach = intel_dsi_host_detach, 211 .transfer = intel_dsi_host_transfer, 212 }; 213 214 /* 215 * send a video mode command 216 * 217 * XXX: commands with data in MIPI_DPI_DATA? 218 */ 219 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, 220 enum port port) 221 { 222 struct drm_encoder *encoder = &intel_dsi->base.base; 223 struct drm_device *dev = encoder->dev; 224 struct drm_i915_private *dev_priv = to_i915(dev); 225 u32 mask; 226 227 /* XXX: pipe, hs */ 228 if (hs) 229 cmd &= ~DPI_LP_MODE; 230 else 231 cmd |= DPI_LP_MODE; 232 233 /* clear bit */ 234 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); 235 236 /* XXX: old code skips write if control unchanged */ 237 if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) 238 DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd); 239 240 I915_WRITE(MIPI_DPI_CONTROL(port), cmd); 241 242 mask = SPL_PKT_SENT_INTERRUPT; 243 if (intel_wait_for_register(&dev_priv->uncore, 244 MIPI_INTR_STAT(port), mask, mask, 245 100)) 246 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); 247 248 return 0; 249 } 250 251 static void band_gap_reset(struct drm_i915_private *dev_priv) 252 { 253 vlv_flisdsi_get(dev_priv); 254 255 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); 256 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); 257 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); 258 udelay(150); 259 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); 260 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); 261 262 vlv_flisdsi_put(dev_priv); 263 } 264 265 static int intel_dsi_compute_config(struct intel_encoder *encoder, 266 struct intel_crtc_state *pipe_config, 267 struct drm_connector_state *conn_state) 268 { 269 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 270 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 271 base); 272 struct intel_connector *intel_connector = intel_dsi->attached_connector; 273 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 274 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 275 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 276 int ret; 277 278 DRM_DEBUG_KMS("\n"); 279 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 280 281 if (fixed_mode) { 282 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 283 284 if (HAS_GMCH(dev_priv)) 285 intel_gmch_panel_fitting(crtc, pipe_config, 286 conn_state->scaling_mode); 287 else 288 intel_pch_panel_fitting(crtc, pipe_config, 289 conn_state->scaling_mode); 290 } 291 292 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 293 return -EINVAL; 294 295 /* DSI uses short packets for sync events, so clear mode flags for DSI */ 296 adjusted_mode->flags = 0; 297 298 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 299 pipe_config->pipe_bpp = 24; 300 else 301 pipe_config->pipe_bpp = 18; 302 303 if (IS_GEN9_LP(dev_priv)) { 304 /* Enable Frame time stamp based scanline reporting */ 305 adjusted_mode->private_flags |= 306 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 307 308 /* Dual link goes to DSI transcoder A. */ 309 if (intel_dsi->ports == BIT(PORT_C)) 310 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; 311 else 312 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; 313 314 ret = bxt_dsi_pll_compute(encoder, pipe_config); 315 if (ret) 316 return -EINVAL; 317 } else { 318 ret = vlv_dsi_pll_compute(encoder, pipe_config); 319 if (ret) 320 return -EINVAL; 321 } 322 323 pipe_config->clock_set = true; 324 325 return 0; 326 } 327 328 static bool glk_dsi_enable_io(struct intel_encoder *encoder) 329 { 330 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 331 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 332 enum port port; 333 u32 tmp; 334 bool cold_boot = false; 335 336 /* Set the MIPI mode 337 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. 338 * Power ON MIPI IO first and then write into IO reset and LP wake bits 339 */ 340 for_each_dsi_port(port, intel_dsi->ports) { 341 tmp = I915_READ(MIPI_CTRL(port)); 342 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); 343 } 344 345 /* Put the IO into reset */ 346 tmp = I915_READ(MIPI_CTRL(PORT_A)); 347 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 348 I915_WRITE(MIPI_CTRL(PORT_A), tmp); 349 350 /* Program LP Wake */ 351 for_each_dsi_port(port, intel_dsi->ports) { 352 tmp = I915_READ(MIPI_CTRL(port)); 353 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) 354 tmp &= ~GLK_LP_WAKE; 355 else 356 tmp |= GLK_LP_WAKE; 357 I915_WRITE(MIPI_CTRL(port), tmp); 358 } 359 360 /* Wait for Pwr ACK */ 361 for_each_dsi_port(port, intel_dsi->ports) { 362 if (intel_wait_for_register(&dev_priv->uncore, 363 MIPI_CTRL(port), 364 GLK_MIPIIO_PORT_POWERED, 365 GLK_MIPIIO_PORT_POWERED, 366 20)) 367 DRM_ERROR("MIPIO port is powergated\n"); 368 } 369 370 /* Check for cold boot scenario */ 371 for_each_dsi_port(port, intel_dsi->ports) { 372 cold_boot |= 373 !(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY); 374 } 375 376 return cold_boot; 377 } 378 379 static void glk_dsi_device_ready(struct intel_encoder *encoder) 380 { 381 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 382 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 383 enum port port; 384 u32 val; 385 386 /* Wait for MIPI PHY status bit to set */ 387 for_each_dsi_port(port, intel_dsi->ports) { 388 if (intel_wait_for_register(&dev_priv->uncore, 389 MIPI_CTRL(port), 390 GLK_PHY_STATUS_PORT_READY, 391 GLK_PHY_STATUS_PORT_READY, 392 20)) 393 DRM_ERROR("PHY is not ON\n"); 394 } 395 396 /* Get IO out of reset */ 397 val = I915_READ(MIPI_CTRL(PORT_A)); 398 I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED); 399 400 /* Get IO out of Low power state*/ 401 for_each_dsi_port(port, intel_dsi->ports) { 402 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { 403 val = I915_READ(MIPI_DEVICE_READY(port)); 404 val &= ~ULPS_STATE_MASK; 405 val |= DEVICE_READY; 406 I915_WRITE(MIPI_DEVICE_READY(port), val); 407 usleep_range(10, 15); 408 } else { 409 /* Enter ULPS */ 410 val = I915_READ(MIPI_DEVICE_READY(port)); 411 val &= ~ULPS_STATE_MASK; 412 val |= (ULPS_STATE_ENTER | DEVICE_READY); 413 I915_WRITE(MIPI_DEVICE_READY(port), val); 414 415 /* Wait for ULPS active */ 416 if (intel_wait_for_register(&dev_priv->uncore, 417 MIPI_CTRL(port), 418 GLK_ULPS_NOT_ACTIVE, 419 0, 420 20)) 421 DRM_ERROR("ULPS not active\n"); 422 423 /* Exit ULPS */ 424 val = I915_READ(MIPI_DEVICE_READY(port)); 425 val &= ~ULPS_STATE_MASK; 426 val |= (ULPS_STATE_EXIT | DEVICE_READY); 427 I915_WRITE(MIPI_DEVICE_READY(port), val); 428 429 /* Enter Normal Mode */ 430 val = I915_READ(MIPI_DEVICE_READY(port)); 431 val &= ~ULPS_STATE_MASK; 432 val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); 433 I915_WRITE(MIPI_DEVICE_READY(port), val); 434 435 val = I915_READ(MIPI_CTRL(port)); 436 val &= ~GLK_LP_WAKE; 437 I915_WRITE(MIPI_CTRL(port), val); 438 } 439 } 440 441 /* Wait for Stop state */ 442 for_each_dsi_port(port, intel_dsi->ports) { 443 if (intel_wait_for_register(&dev_priv->uncore, 444 MIPI_CTRL(port), 445 GLK_DATA_LANE_STOP_STATE, 446 GLK_DATA_LANE_STOP_STATE, 447 20)) 448 DRM_ERROR("Date lane not in STOP state\n"); 449 } 450 451 /* Wait for AFE LATCH */ 452 for_each_dsi_port(port, intel_dsi->ports) { 453 if (intel_wait_for_register(&dev_priv->uncore, 454 BXT_MIPI_PORT_CTRL(port), 455 AFE_LATCHOUT, 456 AFE_LATCHOUT, 457 20)) 458 DRM_ERROR("D-PHY not entering LP-11 state\n"); 459 } 460 } 461 462 static void bxt_dsi_device_ready(struct intel_encoder *encoder) 463 { 464 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 465 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 466 enum port port; 467 u32 val; 468 469 DRM_DEBUG_KMS("\n"); 470 471 /* Enable MIPI PHY transparent latch */ 472 for_each_dsi_port(port, intel_dsi->ports) { 473 val = I915_READ(BXT_MIPI_PORT_CTRL(port)); 474 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); 475 usleep_range(2000, 2500); 476 } 477 478 /* Clear ULPS and set device ready */ 479 for_each_dsi_port(port, intel_dsi->ports) { 480 val = I915_READ(MIPI_DEVICE_READY(port)); 481 val &= ~ULPS_STATE_MASK; 482 I915_WRITE(MIPI_DEVICE_READY(port), val); 483 usleep_range(2000, 2500); 484 val |= DEVICE_READY; 485 I915_WRITE(MIPI_DEVICE_READY(port), val); 486 } 487 } 488 489 static void vlv_dsi_device_ready(struct intel_encoder *encoder) 490 { 491 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 492 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 493 enum port port; 494 u32 val; 495 496 DRM_DEBUG_KMS("\n"); 497 498 vlv_flisdsi_get(dev_priv); 499 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms 500 * needed everytime after power gate */ 501 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); 502 vlv_flisdsi_put(dev_priv); 503 504 /* bandgap reset is needed after everytime we do power gate */ 505 band_gap_reset(dev_priv); 506 507 for_each_dsi_port(port, intel_dsi->ports) { 508 509 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); 510 usleep_range(2500, 3000); 511 512 /* Enable MIPI PHY transparent latch 513 * Common bit for both MIPI Port A & MIPI Port C 514 * No similar bit in MIPI Port C reg 515 */ 516 val = I915_READ(MIPI_PORT_CTRL(PORT_A)); 517 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); 518 usleep_range(1000, 1500); 519 520 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); 521 usleep_range(2500, 3000); 522 523 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); 524 usleep_range(2500, 3000); 525 } 526 } 527 528 static void intel_dsi_device_ready(struct intel_encoder *encoder) 529 { 530 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 531 532 if (IS_GEMINILAKE(dev_priv)) 533 glk_dsi_device_ready(encoder); 534 else if (IS_GEN9_LP(dev_priv)) 535 bxt_dsi_device_ready(encoder); 536 else 537 vlv_dsi_device_ready(encoder); 538 } 539 540 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) 541 { 542 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 543 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 544 enum port port; 545 u32 val; 546 547 /* Enter ULPS */ 548 for_each_dsi_port(port, intel_dsi->ports) { 549 val = I915_READ(MIPI_DEVICE_READY(port)); 550 val &= ~ULPS_STATE_MASK; 551 val |= (ULPS_STATE_ENTER | DEVICE_READY); 552 I915_WRITE(MIPI_DEVICE_READY(port), val); 553 } 554 555 /* Wait for MIPI PHY status bit to unset */ 556 for_each_dsi_port(port, intel_dsi->ports) { 557 if (intel_wait_for_register(&dev_priv->uncore, 558 MIPI_CTRL(port), 559 GLK_PHY_STATUS_PORT_READY, 0, 20)) 560 DRM_ERROR("PHY is not turning OFF\n"); 561 } 562 563 /* Wait for Pwr ACK bit to unset */ 564 for_each_dsi_port(port, intel_dsi->ports) { 565 if (intel_wait_for_register(&dev_priv->uncore, 566 MIPI_CTRL(port), 567 GLK_MIPIIO_PORT_POWERED, 0, 20)) 568 DRM_ERROR("MIPI IO Port is not powergated\n"); 569 } 570 } 571 572 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) 573 { 574 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 575 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 576 enum port port; 577 u32 tmp; 578 579 /* Put the IO into reset */ 580 tmp = I915_READ(MIPI_CTRL(PORT_A)); 581 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 582 I915_WRITE(MIPI_CTRL(PORT_A), tmp); 583 584 /* Wait for MIPI PHY status bit to unset */ 585 for_each_dsi_port(port, intel_dsi->ports) { 586 if (intel_wait_for_register(&dev_priv->uncore, 587 MIPI_CTRL(port), 588 GLK_PHY_STATUS_PORT_READY, 0, 20)) 589 DRM_ERROR("PHY is not turning OFF\n"); 590 } 591 592 /* Clear MIPI mode */ 593 for_each_dsi_port(port, intel_dsi->ports) { 594 tmp = I915_READ(MIPI_CTRL(port)); 595 tmp &= ~GLK_MIPIIO_ENABLE; 596 I915_WRITE(MIPI_CTRL(port), tmp); 597 } 598 } 599 600 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) 601 { 602 glk_dsi_enter_low_power_mode(encoder); 603 glk_dsi_disable_mipi_io(encoder); 604 } 605 606 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) 607 { 608 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 609 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 610 enum port port; 611 612 DRM_DEBUG_KMS("\n"); 613 for_each_dsi_port(port, intel_dsi->ports) { 614 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ 615 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 616 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); 617 u32 val; 618 619 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | 620 ULPS_STATE_ENTER); 621 usleep_range(2000, 2500); 622 623 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | 624 ULPS_STATE_EXIT); 625 usleep_range(2000, 2500); 626 627 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | 628 ULPS_STATE_ENTER); 629 usleep_range(2000, 2500); 630 631 /* 632 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI 633 * Port A only. MIPI Port C has no similar bit for checking. 634 */ 635 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && 636 intel_wait_for_register(&dev_priv->uncore, 637 port_ctrl, AFE_LATCHOUT, 0, 638 30)) 639 DRM_ERROR("DSI LP not going Low\n"); 640 641 /* Disable MIPI PHY transparent latch */ 642 val = I915_READ(port_ctrl); 643 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); 644 usleep_range(1000, 1500); 645 646 I915_WRITE(MIPI_DEVICE_READY(port), 0x00); 647 usleep_range(2000, 2500); 648 } 649 } 650 651 static void intel_dsi_port_enable(struct intel_encoder *encoder, 652 const struct intel_crtc_state *crtc_state) 653 { 654 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 655 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 656 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 657 enum port port; 658 659 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 660 u32 temp; 661 if (IS_GEN9_LP(dev_priv)) { 662 for_each_dsi_port(port, intel_dsi->ports) { 663 temp = I915_READ(MIPI_CTRL(port)); 664 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | 665 intel_dsi->pixel_overlap << 666 BXT_PIXEL_OVERLAP_CNT_SHIFT; 667 I915_WRITE(MIPI_CTRL(port), temp); 668 } 669 } else { 670 temp = I915_READ(VLV_CHICKEN_3); 671 temp &= ~PIXEL_OVERLAP_CNT_MASK | 672 intel_dsi->pixel_overlap << 673 PIXEL_OVERLAP_CNT_SHIFT; 674 I915_WRITE(VLV_CHICKEN_3, temp); 675 } 676 } 677 678 for_each_dsi_port(port, intel_dsi->ports) { 679 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 680 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 681 u32 temp; 682 683 temp = I915_READ(port_ctrl); 684 685 temp &= ~LANE_CONFIGURATION_MASK; 686 temp &= ~DUAL_LINK_MODE_MASK; 687 688 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { 689 temp |= (intel_dsi->dual_link - 1) 690 << DUAL_LINK_MODE_SHIFT; 691 if (IS_BROXTON(dev_priv)) 692 temp |= LANE_CONFIGURATION_DUAL_LINK_A; 693 else 694 temp |= crtc->pipe ? 695 LANE_CONFIGURATION_DUAL_LINK_B : 696 LANE_CONFIGURATION_DUAL_LINK_A; 697 } 698 699 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) 700 temp |= DITHERING_ENABLE; 701 702 /* assert ip_tg_enable signal */ 703 I915_WRITE(port_ctrl, temp | DPI_ENABLE); 704 POSTING_READ(port_ctrl); 705 } 706 } 707 708 static void intel_dsi_port_disable(struct intel_encoder *encoder) 709 { 710 struct drm_device *dev = encoder->base.dev; 711 struct drm_i915_private *dev_priv = to_i915(dev); 712 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 713 enum port port; 714 715 for_each_dsi_port(port, intel_dsi->ports) { 716 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 717 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 718 u32 temp; 719 720 /* de-assert ip_tg_enable signal */ 721 temp = I915_READ(port_ctrl); 722 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); 723 POSTING_READ(port_ctrl); 724 } 725 } 726 727 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 728 const struct intel_crtc_state *pipe_config); 729 static void intel_dsi_unprepare(struct intel_encoder *encoder); 730 731 /* 732 * Panel enable/disable sequences from the VBT spec. 733 * 734 * Note the spec has AssertReset / DeassertReset swapped from their 735 * usual naming. We use the normal names to avoid confusion (so below 736 * they are swapped compared to the spec). 737 * 738 * Steps starting with MIPI refer to VBT sequences, note that for v2 739 * VBTs several steps which have a VBT in v2 are expected to be handled 740 * directly by the driver, by directly driving gpios for example. 741 * 742 * v2 video mode seq v3 video mode seq command mode seq 743 * - power on - MIPIPanelPowerOn - power on 744 * - wait t1+t2 - wait t1+t2 745 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin 746 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 747 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds 748 * - MIPITearOn 749 * - MIPIDisplayOn 750 * - turn on DPI - turn on DPI - set pipe to dsr mode 751 * - MIPIDisplayOn - MIPIDisplayOn 752 * - wait t5 - wait t5 753 * - backlight on - MIPIBacklightOn - backlight on 754 * ... ... ... issue mem cmds ... 755 * - backlight off - MIPIBacklightOff - backlight off 756 * - wait t6 - wait t6 757 * - MIPIDisplayOff 758 * - turn off DPI - turn off DPI - disable pipe dsr mode 759 * - MIPITearOff 760 * - MIPIDisplayOff - MIPIDisplayOff 761 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 762 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin 763 * - wait t3 - wait t3 764 * - power off - MIPIPanelPowerOff - power off 765 * - wait t4 - wait t4 766 */ 767 768 /* 769 * DSI port enable has to be done before pipe and plane enable, so we do it in 770 * the pre_enable hook instead of the enable hook. 771 */ 772 static void intel_dsi_pre_enable(struct intel_encoder *encoder, 773 const struct intel_crtc_state *pipe_config, 774 const struct drm_connector_state *conn_state) 775 { 776 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 777 struct drm_crtc *crtc = pipe_config->base.crtc; 778 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 780 int pipe = intel_crtc->pipe; 781 enum port port; 782 u32 val; 783 bool glk_cold_boot = false; 784 785 DRM_DEBUG_KMS("\n"); 786 787 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 788 789 /* 790 * The BIOS may leave the PLL in a wonky state where it doesn't 791 * lock. It needs to be fully powered down to fix it. 792 */ 793 if (IS_GEN9_LP(dev_priv)) { 794 bxt_dsi_pll_disable(encoder); 795 bxt_dsi_pll_enable(encoder, pipe_config); 796 } else { 797 vlv_dsi_pll_disable(encoder); 798 vlv_dsi_pll_enable(encoder, pipe_config); 799 } 800 801 if (IS_BROXTON(dev_priv)) { 802 /* Add MIPI IO reset programming for modeset */ 803 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 804 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 805 val | MIPIO_RST_CTRL); 806 807 /* Power up DSI regulator */ 808 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 809 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0); 810 } 811 812 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 813 u32 val; 814 815 /* Disable DPOunit clock gating, can stall pipe */ 816 val = I915_READ(DSPCLK_GATE_D); 817 val |= DPOUNIT_CLOCK_GATE_DISABLE; 818 I915_WRITE(DSPCLK_GATE_D, val); 819 } 820 821 if (!IS_GEMINILAKE(dev_priv)) 822 intel_dsi_prepare(encoder, pipe_config); 823 824 /* Power on, try both CRC pmic gpio and VBT */ 825 if (intel_dsi->gpio_panel) 826 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 827 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 828 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 829 830 /* Deassert reset */ 831 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 832 833 if (IS_GEMINILAKE(dev_priv)) { 834 glk_cold_boot = glk_dsi_enable_io(encoder); 835 836 /* Prepare port in cold boot(s3/s4) scenario */ 837 if (glk_cold_boot) 838 intel_dsi_prepare(encoder, pipe_config); 839 } 840 841 /* Put device in ready state (LP-11) */ 842 intel_dsi_device_ready(encoder); 843 844 /* Prepare port in normal boot scenario */ 845 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) 846 intel_dsi_prepare(encoder, pipe_config); 847 848 /* Send initialization commands in LP mode */ 849 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 850 851 /* Enable port in pre-enable phase itself because as per hw team 852 * recommendation, port should be enabled befor plane & pipe */ 853 if (is_cmd_mode(intel_dsi)) { 854 for_each_dsi_port(port, intel_dsi->ports) 855 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); 856 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); 857 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 858 } else { 859 msleep(20); /* XXX */ 860 for_each_dsi_port(port, intel_dsi->ports) 861 dpi_send_cmd(intel_dsi, TURN_ON, false, port); 862 intel_dsi_msleep(intel_dsi, 100); 863 864 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 865 866 intel_dsi_port_enable(encoder, pipe_config); 867 } 868 869 intel_panel_enable_backlight(pipe_config, conn_state); 870 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 871 } 872 873 /* 874 * DSI port disable has to be done after pipe and plane disable, so we do it in 875 * the post_disable hook. 876 */ 877 static void intel_dsi_disable(struct intel_encoder *encoder, 878 const struct intel_crtc_state *old_crtc_state, 879 const struct drm_connector_state *old_conn_state) 880 { 881 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 882 enum port port; 883 884 DRM_DEBUG_KMS("\n"); 885 886 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 887 intel_panel_disable_backlight(old_conn_state); 888 889 /* 890 * According to the spec we should send SHUTDOWN before 891 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing 892 * has shown that the v3 sequence works for v2 VBTs too 893 */ 894 if (is_vid_mode(intel_dsi)) { 895 /* Send Shutdown command to the panel in LP mode */ 896 for_each_dsi_port(port, intel_dsi->ports) 897 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); 898 msleep(10); 899 } 900 } 901 902 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 903 { 904 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 905 906 if (IS_GEMINILAKE(dev_priv)) 907 glk_dsi_clear_device_ready(encoder); 908 else 909 vlv_dsi_clear_device_ready(encoder); 910 } 911 912 static void intel_dsi_post_disable(struct intel_encoder *encoder, 913 const struct intel_crtc_state *pipe_config, 914 const struct drm_connector_state *conn_state) 915 { 916 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 917 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 918 enum port port; 919 u32 val; 920 921 DRM_DEBUG_KMS("\n"); 922 923 if (is_vid_mode(intel_dsi)) { 924 for_each_dsi_port(port, intel_dsi->ports) 925 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 926 927 intel_dsi_port_disable(encoder); 928 usleep_range(2000, 5000); 929 } 930 931 intel_dsi_unprepare(encoder); 932 933 /* 934 * if disable packets are sent before sending shutdown packet then in 935 * some next enable sequence send turn on packet error is observed 936 */ 937 if (is_cmd_mode(intel_dsi)) 938 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF); 939 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 940 941 /* Transition to LP-00 */ 942 intel_dsi_clear_device_ready(encoder); 943 944 if (IS_BROXTON(dev_priv)) { 945 /* Power down DSI regulator to save power */ 946 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 947 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT); 948 949 /* Add MIPI IO reset programming for modeset */ 950 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 951 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 952 val & ~MIPIO_RST_CTRL); 953 } 954 955 if (IS_GEN9_LP(dev_priv)) { 956 bxt_dsi_pll_disable(encoder); 957 } else { 958 u32 val; 959 960 vlv_dsi_pll_disable(encoder); 961 962 val = I915_READ(DSPCLK_GATE_D); 963 val &= ~DPOUNIT_CLOCK_GATE_DISABLE; 964 I915_WRITE(DSPCLK_GATE_D, val); 965 } 966 967 /* Assert reset */ 968 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 969 970 /* Power off, try both CRC pmic gpio and VBT */ 971 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); 972 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 973 if (intel_dsi->gpio_panel) 974 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 975 976 /* 977 * FIXME As we do with eDP, just make a note of the time here 978 * and perform the wait before the next panel power on. 979 */ 980 intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay); 981 } 982 983 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 984 enum pipe *pipe) 985 { 986 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 987 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 988 intel_wakeref_t wakeref; 989 enum port port; 990 bool active = false; 991 992 DRM_DEBUG_KMS("\n"); 993 994 wakeref = intel_display_power_get_if_enabled(dev_priv, 995 encoder->power_domain); 996 if (!wakeref) 997 return false; 998 999 /* 1000 * On Broxton the PLL needs to be enabled with a valid divider 1001 * configuration, otherwise accessing DSI registers will hang the 1002 * machine. See BSpec North Display Engine registers/MIPI[BXT]. 1003 */ 1004 if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv)) 1005 goto out_put_power; 1006 1007 /* XXX: this only works for one DSI output */ 1008 for_each_dsi_port(port, intel_dsi->ports) { 1009 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? 1010 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 1011 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; 1012 1013 /* 1014 * Due to some hardware limitations on VLV/CHV, the DPI enable 1015 * bit in port C control register does not get set. As a 1016 * workaround, check pipe B conf instead. 1017 */ 1018 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1019 port == PORT_C) 1020 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; 1021 1022 /* Try command mode if video mode not enabled */ 1023 if (!enabled) { 1024 u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); 1025 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; 1026 } 1027 1028 if (!enabled) 1029 continue; 1030 1031 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) 1032 continue; 1033 1034 if (IS_GEN9_LP(dev_priv)) { 1035 u32 tmp = I915_READ(MIPI_CTRL(port)); 1036 tmp &= BXT_PIPE_SELECT_MASK; 1037 tmp >>= BXT_PIPE_SELECT_SHIFT; 1038 1039 if (WARN_ON(tmp > PIPE_C)) 1040 continue; 1041 1042 *pipe = tmp; 1043 } else { 1044 *pipe = port == PORT_A ? PIPE_A : PIPE_B; 1045 } 1046 1047 active = true; 1048 break; 1049 } 1050 1051 out_put_power: 1052 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1053 1054 return active; 1055 } 1056 1057 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, 1058 struct intel_crtc_state *pipe_config) 1059 { 1060 struct drm_device *dev = encoder->base.dev; 1061 struct drm_i915_private *dev_priv = to_i915(dev); 1062 struct drm_display_mode *adjusted_mode = 1063 &pipe_config->base.adjusted_mode; 1064 struct drm_display_mode *adjusted_mode_sw; 1065 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 1066 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1067 unsigned int lane_count = intel_dsi->lane_count; 1068 unsigned int bpp, fmt; 1069 enum port port; 1070 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1071 u16 hfp_sw, hsync_sw, hbp_sw; 1072 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, 1073 crtc_hblank_start_sw, crtc_hblank_end_sw; 1074 1075 /* FIXME: hw readout should not depend on SW state */ 1076 adjusted_mode_sw = &crtc->config->base.adjusted_mode; 1077 1078 /* 1079 * Atleast one port is active as encoder->get_config called only if 1080 * encoder->get_hw_state() returns true. 1081 */ 1082 for_each_dsi_port(port, intel_dsi->ports) { 1083 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) 1084 break; 1085 } 1086 1087 fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; 1088 bpp = mipi_dsi_pixel_format_to_bpp( 1089 pixel_format_from_register_bits(fmt)); 1090 1091 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1092 1093 /* Enable Frame time stamo based scanline reporting */ 1094 adjusted_mode->private_flags |= 1095 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 1096 1097 /* In terms of pixels */ 1098 adjusted_mode->crtc_hdisplay = 1099 I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); 1100 adjusted_mode->crtc_vdisplay = 1101 I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); 1102 adjusted_mode->crtc_vtotal = 1103 I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); 1104 1105 hactive = adjusted_mode->crtc_hdisplay; 1106 hfp = I915_READ(MIPI_HFP_COUNT(port)); 1107 1108 /* 1109 * Meaningful for video mode non-burst sync pulse mode only, 1110 * can be zero for non-burst sync events and burst modes 1111 */ 1112 hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port)); 1113 hbp = I915_READ(MIPI_HBP_COUNT(port)); 1114 1115 /* harizontal values are in terms of high speed byte clock */ 1116 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, 1117 intel_dsi->burst_mode_ratio); 1118 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, 1119 intel_dsi->burst_mode_ratio); 1120 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, 1121 intel_dsi->burst_mode_ratio); 1122 1123 if (intel_dsi->dual_link) { 1124 hfp *= 2; 1125 hsync *= 2; 1126 hbp *= 2; 1127 } 1128 1129 /* vertical values are in terms of lines */ 1130 vfp = I915_READ(MIPI_VFP_COUNT(port)); 1131 vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); 1132 vbp = I915_READ(MIPI_VBP_COUNT(port)); 1133 1134 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; 1135 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; 1136 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; 1137 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1138 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1139 1140 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; 1141 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; 1142 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1143 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1144 1145 /* 1146 * In BXT DSI there is no regs programmed with few horizontal timings 1147 * in Pixels but txbyteclkhs.. So retrieval process adds some 1148 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. 1149 * Actually here for the given adjusted_mode, we are calculating the 1150 * value programmed to the port and then back to the horizontal timing 1151 * param in pixels. This is the expected value, including roundup errors 1152 * And if that is same as retrieved value from port, then 1153 * (HW state) adjusted_mode's horizontal timings are corrected to 1154 * match with SW state to nullify the errors. 1155 */ 1156 /* Calculating the value programmed to the Port register */ 1157 hfp_sw = adjusted_mode_sw->crtc_hsync_start - 1158 adjusted_mode_sw->crtc_hdisplay; 1159 hsync_sw = adjusted_mode_sw->crtc_hsync_end - 1160 adjusted_mode_sw->crtc_hsync_start; 1161 hbp_sw = adjusted_mode_sw->crtc_htotal - 1162 adjusted_mode_sw->crtc_hsync_end; 1163 1164 if (intel_dsi->dual_link) { 1165 hfp_sw /= 2; 1166 hsync_sw /= 2; 1167 hbp_sw /= 2; 1168 } 1169 1170 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, 1171 intel_dsi->burst_mode_ratio); 1172 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, 1173 intel_dsi->burst_mode_ratio); 1174 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, 1175 intel_dsi->burst_mode_ratio); 1176 1177 /* Reverse calculating the adjusted mode parameters from port reg vals*/ 1178 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, 1179 intel_dsi->burst_mode_ratio); 1180 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, 1181 intel_dsi->burst_mode_ratio); 1182 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, 1183 intel_dsi->burst_mode_ratio); 1184 1185 if (intel_dsi->dual_link) { 1186 hfp_sw *= 2; 1187 hsync_sw *= 2; 1188 hbp_sw *= 2; 1189 } 1190 1191 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + 1192 hsync_sw + hbp_sw; 1193 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; 1194 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; 1195 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; 1196 crtc_hblank_end_sw = crtc_htotal_sw; 1197 1198 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) 1199 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; 1200 1201 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) 1202 adjusted_mode->crtc_hsync_start = 1203 adjusted_mode_sw->crtc_hsync_start; 1204 1205 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) 1206 adjusted_mode->crtc_hsync_end = 1207 adjusted_mode_sw->crtc_hsync_end; 1208 1209 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) 1210 adjusted_mode->crtc_hblank_start = 1211 adjusted_mode_sw->crtc_hblank_start; 1212 1213 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) 1214 adjusted_mode->crtc_hblank_end = 1215 adjusted_mode_sw->crtc_hblank_end; 1216 } 1217 1218 static void intel_dsi_get_config(struct intel_encoder *encoder, 1219 struct intel_crtc_state *pipe_config) 1220 { 1221 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1222 u32 pclk; 1223 DRM_DEBUG_KMS("\n"); 1224 1225 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1226 1227 if (IS_GEN9_LP(dev_priv)) { 1228 bxt_dsi_get_pipe_config(encoder, pipe_config); 1229 pclk = bxt_dsi_get_pclk(encoder, pipe_config); 1230 } else { 1231 pclk = vlv_dsi_get_pclk(encoder, pipe_config); 1232 } 1233 1234 if (pclk) { 1235 pipe_config->base.adjusted_mode.crtc_clock = pclk; 1236 pipe_config->port_clock = pclk; 1237 } 1238 } 1239 1240 /* return txclkesc cycles in terms of divider and duration in us */ 1241 static u16 txclkesc(u32 divider, unsigned int us) 1242 { 1243 switch (divider) { 1244 case ESCAPE_CLOCK_DIVIDER_1: 1245 default: 1246 return 20 * us; 1247 case ESCAPE_CLOCK_DIVIDER_2: 1248 return 10 * us; 1249 case ESCAPE_CLOCK_DIVIDER_4: 1250 return 5 * us; 1251 } 1252 } 1253 1254 static void set_dsi_timings(struct drm_encoder *encoder, 1255 const struct drm_display_mode *adjusted_mode) 1256 { 1257 struct drm_device *dev = encoder->dev; 1258 struct drm_i915_private *dev_priv = to_i915(dev); 1259 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1260 enum port port; 1261 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1262 unsigned int lane_count = intel_dsi->lane_count; 1263 1264 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1265 1266 hactive = adjusted_mode->crtc_hdisplay; 1267 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; 1268 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1269 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; 1270 1271 if (intel_dsi->dual_link) { 1272 hactive /= 2; 1273 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1274 hactive += intel_dsi->pixel_overlap; 1275 hfp /= 2; 1276 hsync /= 2; 1277 hbp /= 2; 1278 } 1279 1280 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; 1281 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; 1282 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; 1283 1284 /* horizontal values are in terms of high speed byte clock */ 1285 hactive = txbyteclkhs(hactive, bpp, lane_count, 1286 intel_dsi->burst_mode_ratio); 1287 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1288 hsync = txbyteclkhs(hsync, bpp, lane_count, 1289 intel_dsi->burst_mode_ratio); 1290 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1291 1292 for_each_dsi_port(port, intel_dsi->ports) { 1293 if (IS_GEN9_LP(dev_priv)) { 1294 /* 1295 * Program hdisplay and vdisplay on MIPI transcoder. 1296 * This is different from calculated hactive and 1297 * vactive, as they are calculated per channel basis, 1298 * whereas these values should be based on resolution. 1299 */ 1300 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), 1301 adjusted_mode->crtc_hdisplay); 1302 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), 1303 adjusted_mode->crtc_vdisplay); 1304 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), 1305 adjusted_mode->crtc_vtotal); 1306 } 1307 1308 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); 1309 I915_WRITE(MIPI_HFP_COUNT(port), hfp); 1310 1311 /* meaningful for video mode non-burst sync pulse mode only, 1312 * can be zero for non-burst sync events and burst modes */ 1313 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); 1314 I915_WRITE(MIPI_HBP_COUNT(port), hbp); 1315 1316 /* vertical values are in terms of lines */ 1317 I915_WRITE(MIPI_VFP_COUNT(port), vfp); 1318 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); 1319 I915_WRITE(MIPI_VBP_COUNT(port), vbp); 1320 } 1321 } 1322 1323 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) 1324 { 1325 switch (fmt) { 1326 case MIPI_DSI_FMT_RGB888: 1327 return VID_MODE_FORMAT_RGB888; 1328 case MIPI_DSI_FMT_RGB666: 1329 return VID_MODE_FORMAT_RGB666; 1330 case MIPI_DSI_FMT_RGB666_PACKED: 1331 return VID_MODE_FORMAT_RGB666_PACKED; 1332 case MIPI_DSI_FMT_RGB565: 1333 return VID_MODE_FORMAT_RGB565; 1334 default: 1335 MISSING_CASE(fmt); 1336 return VID_MODE_FORMAT_RGB666; 1337 } 1338 } 1339 1340 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 1341 const struct intel_crtc_state *pipe_config) 1342 { 1343 struct drm_encoder *encoder = &intel_encoder->base; 1344 struct drm_device *dev = encoder->dev; 1345 struct drm_i915_private *dev_priv = to_i915(dev); 1346 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 1347 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1348 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1349 enum port port; 1350 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1351 u32 val, tmp; 1352 u16 mode_hdisplay; 1353 1354 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); 1355 1356 mode_hdisplay = adjusted_mode->crtc_hdisplay; 1357 1358 if (intel_dsi->dual_link) { 1359 mode_hdisplay /= 2; 1360 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1361 mode_hdisplay += intel_dsi->pixel_overlap; 1362 } 1363 1364 for_each_dsi_port(port, intel_dsi->ports) { 1365 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1366 /* 1367 * escape clock divider, 20MHz, shared for A and C. 1368 * device ready must be off when doing this! txclkesc? 1369 */ 1370 tmp = I915_READ(MIPI_CTRL(PORT_A)); 1371 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 1372 I915_WRITE(MIPI_CTRL(PORT_A), tmp | 1373 ESCAPE_CLOCK_DIVIDER_1); 1374 1375 /* read request priority is per pipe */ 1376 tmp = I915_READ(MIPI_CTRL(port)); 1377 tmp &= ~READ_REQUEST_PRIORITY_MASK; 1378 I915_WRITE(MIPI_CTRL(port), tmp | 1379 READ_REQUEST_PRIORITY_HIGH); 1380 } else if (IS_GEN9_LP(dev_priv)) { 1381 enum pipe pipe = intel_crtc->pipe; 1382 1383 tmp = I915_READ(MIPI_CTRL(port)); 1384 tmp &= ~BXT_PIPE_SELECT_MASK; 1385 1386 tmp |= BXT_PIPE_SELECT(pipe); 1387 I915_WRITE(MIPI_CTRL(port), tmp); 1388 } 1389 1390 /* XXX: why here, why like this? handling in irq handler?! */ 1391 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); 1392 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); 1393 1394 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); 1395 1396 I915_WRITE(MIPI_DPI_RESOLUTION(port), 1397 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | 1398 mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); 1399 } 1400 1401 set_dsi_timings(encoder, adjusted_mode); 1402 1403 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; 1404 if (is_cmd_mode(intel_dsi)) { 1405 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; 1406 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ 1407 } else { 1408 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; 1409 val |= pixel_format_to_reg(intel_dsi->pixel_format); 1410 } 1411 1412 tmp = 0; 1413 if (intel_dsi->eotp_pkt == 0) 1414 tmp |= EOT_DISABLE; 1415 if (intel_dsi->clock_stop) 1416 tmp |= CLOCKSTOP; 1417 1418 if (IS_GEN9_LP(dev_priv)) { 1419 tmp |= BXT_DPHY_DEFEATURE_EN; 1420 if (!is_cmd_mode(intel_dsi)) 1421 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; 1422 } 1423 1424 for_each_dsi_port(port, intel_dsi->ports) { 1425 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); 1426 1427 /* timeouts for recovery. one frame IIUC. if counter expires, 1428 * EOT and stop state. */ 1429 1430 /* 1431 * In burst mode, value greater than one DPI line Time in byte 1432 * clock (txbyteclkhs) To timeout this timer 1+ of the above 1433 * said value is recommended. 1434 * 1435 * In non-burst mode, Value greater than one DPI frame time in 1436 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1437 * said value is recommended. 1438 * 1439 * In DBI only mode, value greater than one DBI frame time in 1440 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1441 * said value is recommended. 1442 */ 1443 1444 if (is_vid_mode(intel_dsi) && 1445 intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 1446 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), 1447 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, 1448 intel_dsi->lane_count, 1449 intel_dsi->burst_mode_ratio) + 1); 1450 } else { 1451 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), 1452 txbyteclkhs(adjusted_mode->crtc_vtotal * 1453 adjusted_mode->crtc_htotal, 1454 bpp, intel_dsi->lane_count, 1455 intel_dsi->burst_mode_ratio) + 1); 1456 } 1457 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); 1458 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), 1459 intel_dsi->turn_arnd_val); 1460 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), 1461 intel_dsi->rst_timer_val); 1462 1463 /* dphy stuff */ 1464 1465 /* in terms of low power clock */ 1466 I915_WRITE(MIPI_INIT_COUNT(port), 1467 txclkesc(intel_dsi->escape_clk_div, 100)); 1468 1469 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { 1470 /* 1471 * BXT spec says write MIPI_INIT_COUNT for 1472 * both the ports, even if only one is 1473 * getting used. So write the other port 1474 * if not in dual link mode. 1475 */ 1476 I915_WRITE(MIPI_INIT_COUNT(port == 1477 PORT_A ? PORT_C : PORT_A), 1478 intel_dsi->init_count); 1479 } 1480 1481 /* recovery disables */ 1482 I915_WRITE(MIPI_EOT_DISABLE(port), tmp); 1483 1484 /* in terms of low power clock */ 1485 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); 1486 1487 /* in terms of txbyteclkhs. actual high to low switch + 1488 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. 1489 * 1490 * XXX: write MIPI_STOP_STATE_STALL? 1491 */ 1492 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), 1493 intel_dsi->hs_to_lp_count); 1494 1495 /* XXX: low power clock equivalence in terms of byte clock. 1496 * the number of byte clocks occupied in one low power clock. 1497 * based on txbyteclkhs and txclkesc. 1498 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL 1499 * ) / 105.??? 1500 */ 1501 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); 1502 1503 if (IS_GEMINILAKE(dev_priv)) { 1504 I915_WRITE(MIPI_TLPX_TIME_COUNT(port), 1505 intel_dsi->lp_byte_clk); 1506 /* Shadow of DPHY reg */ 1507 I915_WRITE(MIPI_CLK_LANE_TIMING(port), 1508 intel_dsi->dphy_reg); 1509 } 1510 1511 /* the bw essential for transmitting 16 long packets containing 1512 * 252 bytes meant for dcs write memory command is programmed in 1513 * this register in terms of byte clocks. based on dsi transfer 1514 * rate and the number of lanes configured the time taken to 1515 * transmit 16 long packets in a dsi stream varies. */ 1516 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); 1517 1518 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), 1519 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | 1520 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); 1521 1522 if (is_vid_mode(intel_dsi)) 1523 /* Some panels might have resolution which is not a 1524 * multiple of 64 like 1366 x 768. Enable RANDOM 1525 * resolution support for such panels by default */ 1526 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), 1527 intel_dsi->video_frmt_cfg_bits | 1528 intel_dsi->video_mode_format | 1529 IP_TG_CONFIG | 1530 RANDOM_DPI_DISPLAY_RESOLUTION); 1531 } 1532 } 1533 1534 static void intel_dsi_unprepare(struct intel_encoder *encoder) 1535 { 1536 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1537 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1538 enum port port; 1539 u32 val; 1540 1541 if (IS_GEMINILAKE(dev_priv)) 1542 return; 1543 1544 for_each_dsi_port(port, intel_dsi->ports) { 1545 /* Panel commands can be sent when clock is in LP11 */ 1546 I915_WRITE(MIPI_DEVICE_READY(port), 0x0); 1547 1548 if (IS_GEN9_LP(dev_priv)) 1549 bxt_dsi_reset_clocks(encoder, port); 1550 else 1551 vlv_dsi_reset_clocks(encoder, port); 1552 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); 1553 1554 val = I915_READ(MIPI_DSI_FUNC_PRG(port)); 1555 val &= ~VID_MODE_FORMAT_MASK; 1556 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); 1557 1558 I915_WRITE(MIPI_DEVICE_READY(port), 0x1); 1559 } 1560 } 1561 1562 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) 1563 { 1564 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1565 1566 /* dispose of the gpios */ 1567 if (intel_dsi->gpio_panel) 1568 gpiod_put(intel_dsi->gpio_panel); 1569 1570 intel_encoder_destroy(encoder); 1571 } 1572 1573 static const struct drm_encoder_funcs intel_dsi_funcs = { 1574 .destroy = intel_dsi_encoder_destroy, 1575 }; 1576 1577 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 1578 .get_modes = intel_dsi_get_modes, 1579 .mode_valid = intel_dsi_mode_valid, 1580 .atomic_check = intel_digital_connector_atomic_check, 1581 }; 1582 1583 static const struct drm_connector_funcs intel_dsi_connector_funcs = { 1584 .late_register = intel_connector_register, 1585 .early_unregister = intel_connector_unregister, 1586 .destroy = intel_connector_destroy, 1587 .fill_modes = drm_helper_probe_single_connector_modes, 1588 .atomic_get_property = intel_digital_connector_atomic_get_property, 1589 .atomic_set_property = intel_digital_connector_atomic_set_property, 1590 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1591 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1592 }; 1593 1594 static enum drm_panel_orientation 1595 vlv_dsi_get_hw_panel_orientation(struct intel_connector *connector) 1596 { 1597 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1598 struct intel_encoder *encoder = connector->encoder; 1599 enum intel_display_power_domain power_domain; 1600 enum drm_panel_orientation orientation; 1601 struct intel_plane *plane; 1602 struct intel_crtc *crtc; 1603 intel_wakeref_t wakeref; 1604 enum pipe pipe; 1605 u32 val; 1606 1607 if (!encoder->get_hw_state(encoder, &pipe)) 1608 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN; 1609 1610 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 1611 plane = to_intel_plane(crtc->base.primary); 1612 1613 power_domain = POWER_DOMAIN_PIPE(pipe); 1614 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1615 if (!wakeref) 1616 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN; 1617 1618 val = I915_READ(DSPCNTR(plane->i9xx_plane)); 1619 1620 if (!(val & DISPLAY_PLANE_ENABLE)) 1621 orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; 1622 else if (val & DISPPLANE_ROTATE_180) 1623 orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; 1624 else 1625 orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL; 1626 1627 intel_display_power_put(dev_priv, power_domain, wakeref); 1628 1629 return orientation; 1630 } 1631 1632 static enum drm_panel_orientation 1633 vlv_dsi_get_panel_orientation(struct intel_connector *connector) 1634 { 1635 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1636 enum drm_panel_orientation orientation; 1637 1638 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1639 orientation = vlv_dsi_get_hw_panel_orientation(connector); 1640 if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN) 1641 return orientation; 1642 } 1643 1644 return intel_dsi_get_panel_orientation(connector); 1645 } 1646 1647 static void intel_dsi_add_properties(struct intel_connector *connector) 1648 { 1649 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1650 1651 if (connector->panel.fixed_mode) { 1652 u32 allowed_scalers; 1653 1654 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); 1655 if (!HAS_GMCH(dev_priv)) 1656 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); 1657 1658 drm_connector_attach_scaling_mode_property(&connector->base, 1659 allowed_scalers); 1660 1661 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1662 1663 connector->base.display_info.panel_orientation = 1664 vlv_dsi_get_panel_orientation(connector); 1665 drm_connector_init_panel_orientation_property( 1666 &connector->base, 1667 connector->panel.fixed_mode->hdisplay, 1668 connector->panel.fixed_mode->vdisplay); 1669 } 1670 } 1671 1672 #define NS_KHZ_RATIO 1000000 1673 1674 #define PREPARE_CNT_MAX 0x3F 1675 #define EXIT_ZERO_CNT_MAX 0x3F 1676 #define CLK_ZERO_CNT_MAX 0xFF 1677 #define TRAIL_CNT_MAX 0x1F 1678 1679 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) 1680 { 1681 struct drm_device *dev = intel_dsi->base.base.dev; 1682 struct drm_i915_private *dev_priv = to_i915(dev); 1683 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1684 u32 tlpx_ns, extra_byte_count, tlpx_ui; 1685 u32 ui_num, ui_den; 1686 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1687 u32 ths_prepare_ns, tclk_trail_ns; 1688 u32 tclk_prepare_clkzero, ths_prepare_hszero; 1689 u32 lp_to_hs_switch, hs_to_lp_switch; 1690 u32 mul; 1691 1692 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1693 1694 switch (intel_dsi->lane_count) { 1695 case 1: 1696 case 2: 1697 extra_byte_count = 2; 1698 break; 1699 case 3: 1700 extra_byte_count = 4; 1701 break; 1702 case 4: 1703 default: 1704 extra_byte_count = 3; 1705 break; 1706 } 1707 1708 /* in Kbps */ 1709 ui_num = NS_KHZ_RATIO; 1710 ui_den = intel_dsi_bitrate(intel_dsi); 1711 1712 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; 1713 ths_prepare_hszero = mipi_config->ths_prepare_hszero; 1714 1715 /* 1716 * B060 1717 * LP byte clock = TLPX/ (8UI) 1718 */ 1719 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); 1720 1721 /* DDR clock period = 2 * UI 1722 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ) 1723 * UI(nsec) = 10^6 / bitrate 1724 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate 1725 * DDR clock count = ns_value / DDR clock period 1726 * 1727 * For GEMINILAKE dphy_param_reg will be programmed in terms of 1728 * HS byte clock count for other platform in HS ddr clock count 1729 */ 1730 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; 1731 ths_prepare_ns = max(mipi_config->ths_prepare, 1732 mipi_config->tclk_prepare); 1733 1734 /* prepare count */ 1735 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul); 1736 1737 if (prepare_cnt > PREPARE_CNT_MAX) { 1738 DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt); 1739 prepare_cnt = PREPARE_CNT_MAX; 1740 } 1741 1742 /* exit zero count */ 1743 exit_zero_cnt = DIV_ROUND_UP( 1744 (ths_prepare_hszero - ths_prepare_ns) * ui_den, 1745 ui_num * mul 1746 ); 1747 1748 /* 1749 * Exit zero is unified val ths_zero and ths_exit 1750 * minimum value for ths_exit = 110ns 1751 * min (exit_zero_cnt * 2) = 110/UI 1752 * exit_zero_cnt = 55/UI 1753 */ 1754 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num) 1755 exit_zero_cnt += 1; 1756 1757 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) { 1758 DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt); 1759 exit_zero_cnt = EXIT_ZERO_CNT_MAX; 1760 } 1761 1762 /* clk zero count */ 1763 clk_zero_cnt = DIV_ROUND_UP( 1764 (tclk_prepare_clkzero - ths_prepare_ns) 1765 * ui_den, ui_num * mul); 1766 1767 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) { 1768 DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt); 1769 clk_zero_cnt = CLK_ZERO_CNT_MAX; 1770 } 1771 1772 /* trail count */ 1773 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1774 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul); 1775 1776 if (trail_cnt > TRAIL_CNT_MAX) { 1777 DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt); 1778 trail_cnt = TRAIL_CNT_MAX; 1779 } 1780 1781 /* B080 */ 1782 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | 1783 clk_zero_cnt << 8 | prepare_cnt; 1784 1785 /* 1786 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT * 1787 * mul + 10UI + Extra Byte Count 1788 * 1789 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count 1790 * Extra Byte Count is calculated according to number of lanes. 1791 * High Low Switch Count is the Max of LP to HS and 1792 * HS to LP switch count 1793 * 1794 */ 1795 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); 1796 1797 /* B044 */ 1798 /* FIXME: 1799 * The comment above does not match with the code */ 1800 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul + 1801 exit_zero_cnt * mul + 10, 8); 1802 1803 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); 1804 1805 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); 1806 intel_dsi->hs_to_lp_count += extra_byte_count; 1807 1808 /* B088 */ 1809 /* LP -> HS for clock lanes 1810 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + 1811 * extra byte count 1812 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * 1813 * 2(in UI) + extra byte count 1814 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / 1815 * 8 + extra byte count 1816 */ 1817 intel_dsi->clk_lp_to_hs_count = 1818 DIV_ROUND_UP( 1819 4 * tlpx_ui + prepare_cnt * 2 + 1820 clk_zero_cnt * 2, 1821 8); 1822 1823 intel_dsi->clk_lp_to_hs_count += extra_byte_count; 1824 1825 /* HS->LP for Clock Lanes 1826 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + 1827 * Extra byte count 1828 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count 1829 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + 1830 * Extra byte count 1831 */ 1832 intel_dsi->clk_hs_to_lp_count = 1833 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, 1834 8); 1835 intel_dsi->clk_hs_to_lp_count += extra_byte_count; 1836 1837 intel_dsi_log_params(intel_dsi); 1838 } 1839 1840 void vlv_dsi_init(struct drm_i915_private *dev_priv) 1841 { 1842 struct drm_device *dev = &dev_priv->drm; 1843 struct intel_dsi *intel_dsi; 1844 struct intel_encoder *intel_encoder; 1845 struct drm_encoder *encoder; 1846 struct intel_connector *intel_connector; 1847 struct drm_connector *connector; 1848 struct drm_display_mode *current_mode, *fixed_mode; 1849 enum port port; 1850 1851 DRM_DEBUG_KMS("\n"); 1852 1853 /* There is no detection method for MIPI so rely on VBT */ 1854 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1855 return; 1856 1857 if (IS_GEN9_LP(dev_priv)) 1858 dev_priv->mipi_mmio_base = BXT_MIPI_BASE; 1859 else 1860 dev_priv->mipi_mmio_base = VLV_MIPI_BASE; 1861 1862 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1863 if (!intel_dsi) 1864 return; 1865 1866 intel_connector = intel_connector_alloc(); 1867 if (!intel_connector) { 1868 kfree(intel_dsi); 1869 return; 1870 } 1871 1872 intel_encoder = &intel_dsi->base; 1873 encoder = &intel_encoder->base; 1874 intel_dsi->attached_connector = intel_connector; 1875 1876 connector = &intel_connector->base; 1877 1878 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, 1879 "DSI %c", port_name(port)); 1880 1881 intel_encoder->compute_config = intel_dsi_compute_config; 1882 intel_encoder->pre_enable = intel_dsi_pre_enable; 1883 intel_encoder->disable = intel_dsi_disable; 1884 intel_encoder->post_disable = intel_dsi_post_disable; 1885 intel_encoder->get_hw_state = intel_dsi_get_hw_state; 1886 intel_encoder->get_config = intel_dsi_get_config; 1887 intel_encoder->update_pipe = intel_panel_update_backlight; 1888 1889 intel_connector->get_hw_state = intel_connector_get_hw_state; 1890 1891 intel_encoder->port = port; 1892 intel_encoder->type = INTEL_OUTPUT_DSI; 1893 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1894 intel_encoder->cloneable = 0; 1895 1896 /* 1897 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI 1898 * port C. BXT isn't limited like this. 1899 */ 1900 if (IS_GEN9_LP(dev_priv)) 1901 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); 1902 else if (port == PORT_A) 1903 intel_encoder->crtc_mask = BIT(PIPE_A); 1904 else 1905 intel_encoder->crtc_mask = BIT(PIPE_B); 1906 1907 if (dev_priv->vbt.dsi.config->dual_link) 1908 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); 1909 else 1910 intel_dsi->ports = BIT(port); 1911 1912 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 1913 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 1914 1915 /* Create a DSI host (and a device) for each port. */ 1916 for_each_dsi_port(port, intel_dsi->ports) { 1917 struct intel_dsi_host *host; 1918 1919 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops, 1920 port); 1921 if (!host) 1922 goto err; 1923 1924 intel_dsi->dsi_hosts[port] = host; 1925 } 1926 1927 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1928 DRM_DEBUG_KMS("no device found\n"); 1929 goto err; 1930 } 1931 1932 /* Use clock read-back from current hw-state for fastboot */ 1933 current_mode = intel_encoder_current_mode(intel_encoder); 1934 if (current_mode) { 1935 DRM_DEBUG_KMS("Calculated pclk %d GOP %d\n", 1936 intel_dsi->pclk, current_mode->clock); 1937 if (intel_fuzzy_clock_check(intel_dsi->pclk, 1938 current_mode->clock)) { 1939 DRM_DEBUG_KMS("Using GOP pclk\n"); 1940 intel_dsi->pclk = current_mode->clock; 1941 } 1942 1943 kfree(current_mode); 1944 } 1945 1946 vlv_dphy_param_init(intel_dsi); 1947 1948 /* 1949 * In case of BYT with CRC PMIC, we need to use GPIO for 1950 * Panel control. 1951 */ 1952 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1953 (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) { 1954 intel_dsi->gpio_panel = 1955 gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); 1956 1957 if (IS_ERR(intel_dsi->gpio_panel)) { 1958 DRM_ERROR("Failed to own gpio for panel control\n"); 1959 intel_dsi->gpio_panel = NULL; 1960 } 1961 } 1962 1963 drm_connector_init(dev, connector, &intel_dsi_connector_funcs, 1964 DRM_MODE_CONNECTOR_DSI); 1965 1966 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); 1967 1968 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ 1969 connector->interlace_allowed = false; 1970 connector->doublescan_allowed = false; 1971 1972 intel_connector_attach_encoder(intel_connector, intel_encoder); 1973 1974 mutex_lock(&dev->mode_config.mutex); 1975 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 1976 mutex_unlock(&dev->mode_config.mutex); 1977 1978 if (!fixed_mode) { 1979 DRM_DEBUG_KMS("no fixed mode\n"); 1980 goto err_cleanup_connector; 1981 } 1982 1983 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 1984 intel_panel_setup_backlight(connector, INVALID_PIPE); 1985 1986 intel_dsi_add_properties(intel_connector); 1987 1988 return; 1989 1990 err_cleanup_connector: 1991 drm_connector_cleanup(&intel_connector->base); 1992 err: 1993 drm_encoder_cleanup(&intel_encoder->base); 1994 kfree(intel_dsi); 1995 kfree(intel_connector); 1996 } 1997