1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Jani Nikula <jani.nikula@intel.com> 24 */ 25 26 #include <linux/slab.h> 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_crtc.h> 30 #include <drm/drm_edid.h> 31 #include <drm/drm_mipi_dsi.h> 32 33 #include "i915_drv.h" 34 #include "intel_atomic.h" 35 #include "intel_connector.h" 36 #include "intel_display_types.h" 37 #include "intel_dsi.h" 38 #include "intel_fifo_underrun.h" 39 #include "intel_panel.h" 40 #include "intel_sideband.h" 41 #include "skl_scaler.h" 42 43 /* return pixels in terms of txbyteclkhs */ 44 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, 45 u16 burst_mode_ratio) 46 { 47 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, 48 8 * 100), lane_count); 49 } 50 51 /* return pixels equvalent to txbyteclkhs */ 52 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, 53 u16 burst_mode_ratio) 54 { 55 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), 56 (bpp * burst_mode_ratio)); 57 } 58 59 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 60 { 61 /* It just so happens the VBT matches register contents. */ 62 switch (fmt) { 63 case VID_MODE_FORMAT_RGB888: 64 return MIPI_DSI_FMT_RGB888; 65 case VID_MODE_FORMAT_RGB666: 66 return MIPI_DSI_FMT_RGB666; 67 case VID_MODE_FORMAT_RGB666_PACKED: 68 return MIPI_DSI_FMT_RGB666_PACKED; 69 case VID_MODE_FORMAT_RGB565: 70 return MIPI_DSI_FMT_RGB565; 71 default: 72 MISSING_CASE(fmt); 73 return MIPI_DSI_FMT_RGB666; 74 } 75 } 76 77 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) 78 { 79 struct drm_encoder *encoder = &intel_dsi->base.base; 80 struct drm_device *dev = encoder->dev; 81 struct drm_i915_private *dev_priv = to_i915(dev); 82 u32 mask; 83 84 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | 85 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; 86 87 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), 88 mask, 100)) 89 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); 90 } 91 92 static void write_data(struct drm_i915_private *dev_priv, 93 i915_reg_t reg, 94 const u8 *data, u32 len) 95 { 96 u32 i, j; 97 98 for (i = 0; i < len; i += 4) { 99 u32 val = 0; 100 101 for (j = 0; j < min_t(u32, len - i, 4); j++) 102 val |= *data++ << 8 * j; 103 104 intel_de_write(dev_priv, reg, val); 105 } 106 } 107 108 static void read_data(struct drm_i915_private *dev_priv, 109 i915_reg_t reg, 110 u8 *data, u32 len) 111 { 112 u32 i, j; 113 114 for (i = 0; i < len; i += 4) { 115 u32 val = intel_de_read(dev_priv, reg); 116 117 for (j = 0; j < min_t(u32, len - i, 4); j++) 118 *data++ = val >> 8 * j; 119 } 120 } 121 122 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, 123 const struct mipi_dsi_msg *msg) 124 { 125 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 126 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; 127 struct drm_i915_private *dev_priv = to_i915(dev); 128 enum port port = intel_dsi_host->port; 129 struct mipi_dsi_packet packet; 130 ssize_t ret; 131 const u8 *header, *data; 132 i915_reg_t data_reg, ctrl_reg; 133 u32 data_mask, ctrl_mask; 134 135 ret = mipi_dsi_create_packet(&packet, msg); 136 if (ret < 0) 137 return ret; 138 139 header = packet.header; 140 data = packet.payload; 141 142 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 143 data_reg = MIPI_LP_GEN_DATA(port); 144 data_mask = LP_DATA_FIFO_FULL; 145 ctrl_reg = MIPI_LP_GEN_CTRL(port); 146 ctrl_mask = LP_CTRL_FIFO_FULL; 147 } else { 148 data_reg = MIPI_HS_GEN_DATA(port); 149 data_mask = HS_DATA_FIFO_FULL; 150 ctrl_reg = MIPI_HS_GEN_CTRL(port); 151 ctrl_mask = HS_CTRL_FIFO_FULL; 152 } 153 154 /* note: this is never true for reads */ 155 if (packet.payload_length) { 156 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 157 data_mask, 50)) 158 drm_err(&dev_priv->drm, 159 "Timeout waiting for HS/LP DATA FIFO !full\n"); 160 161 write_data(dev_priv, data_reg, packet.payload, 162 packet.payload_length); 163 } 164 165 if (msg->rx_len) { 166 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 167 GEN_READ_DATA_AVAIL); 168 } 169 170 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 171 ctrl_mask, 50)) { 172 drm_err(&dev_priv->drm, 173 "Timeout waiting for HS/LP CTRL FIFO !full\n"); 174 } 175 176 intel_de_write(dev_priv, ctrl_reg, 177 header[2] << 16 | header[1] << 8 | header[0]); 178 179 /* ->rx_len is set only for reads */ 180 if (msg->rx_len) { 181 data_mask = GEN_READ_DATA_AVAIL; 182 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), 183 data_mask, 50)) 184 drm_err(&dev_priv->drm, 185 "Timeout waiting for read data.\n"); 186 187 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); 188 } 189 190 /* XXX: fix for reads and writes */ 191 return 4 + packet.payload_length; 192 } 193 194 static int intel_dsi_host_attach(struct mipi_dsi_host *host, 195 struct mipi_dsi_device *dsi) 196 { 197 return 0; 198 } 199 200 static int intel_dsi_host_detach(struct mipi_dsi_host *host, 201 struct mipi_dsi_device *dsi) 202 { 203 return 0; 204 } 205 206 static const struct mipi_dsi_host_ops intel_dsi_host_ops = { 207 .attach = intel_dsi_host_attach, 208 .detach = intel_dsi_host_detach, 209 .transfer = intel_dsi_host_transfer, 210 }; 211 212 /* 213 * send a video mode command 214 * 215 * XXX: commands with data in MIPI_DPI_DATA? 216 */ 217 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, 218 enum port port) 219 { 220 struct drm_encoder *encoder = &intel_dsi->base.base; 221 struct drm_device *dev = encoder->dev; 222 struct drm_i915_private *dev_priv = to_i915(dev); 223 u32 mask; 224 225 /* XXX: pipe, hs */ 226 if (hs) 227 cmd &= ~DPI_LP_MODE; 228 else 229 cmd |= DPI_LP_MODE; 230 231 /* clear bit */ 232 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); 233 234 /* XXX: old code skips write if control unchanged */ 235 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) 236 drm_dbg_kms(&dev_priv->drm, 237 "Same special packet %02x twice in a row.\n", cmd); 238 239 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); 240 241 mask = SPL_PKT_SENT_INTERRUPT; 242 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) 243 drm_err(&dev_priv->drm, 244 "Video mode command 0x%08x send failed.\n", cmd); 245 246 return 0; 247 } 248 249 static void band_gap_reset(struct drm_i915_private *dev_priv) 250 { 251 vlv_flisdsi_get(dev_priv); 252 253 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); 254 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); 255 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); 256 udelay(150); 257 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); 258 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); 259 260 vlv_flisdsi_put(dev_priv); 261 } 262 263 static int intel_dsi_compute_config(struct intel_encoder *encoder, 264 struct intel_crtc_state *pipe_config, 265 struct drm_connector_state *conn_state) 266 { 267 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 268 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 269 base); 270 struct intel_connector *intel_connector = intel_dsi->attached_connector; 271 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 272 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 273 int ret; 274 275 drm_dbg_kms(&dev_priv->drm, "\n"); 276 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 277 278 if (fixed_mode) { 279 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 280 281 if (HAS_GMCH(dev_priv)) 282 ret = intel_gmch_panel_fitting(pipe_config, conn_state); 283 else 284 ret = intel_pch_panel_fitting(pipe_config, conn_state); 285 if (ret) 286 return ret; 287 } 288 289 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 290 return -EINVAL; 291 292 /* DSI uses short packets for sync events, so clear mode flags for DSI */ 293 adjusted_mode->flags = 0; 294 295 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 296 pipe_config->pipe_bpp = 24; 297 else 298 pipe_config->pipe_bpp = 18; 299 300 if (IS_GEN9_LP(dev_priv)) { 301 /* Enable Frame time stamp based scanline reporting */ 302 pipe_config->mode_flags |= 303 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 304 305 /* Dual link goes to DSI transcoder A. */ 306 if (intel_dsi->ports == BIT(PORT_C)) 307 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; 308 else 309 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; 310 311 ret = bxt_dsi_pll_compute(encoder, pipe_config); 312 if (ret) 313 return -EINVAL; 314 } else { 315 ret = vlv_dsi_pll_compute(encoder, pipe_config); 316 if (ret) 317 return -EINVAL; 318 } 319 320 pipe_config->clock_set = true; 321 322 return 0; 323 } 324 325 static bool glk_dsi_enable_io(struct intel_encoder *encoder) 326 { 327 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 328 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 329 enum port port; 330 u32 tmp; 331 bool cold_boot = false; 332 333 /* Set the MIPI mode 334 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. 335 * Power ON MIPI IO first and then write into IO reset and LP wake bits 336 */ 337 for_each_dsi_port(port, intel_dsi->ports) { 338 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 339 intel_de_write(dev_priv, MIPI_CTRL(port), 340 tmp | GLK_MIPIIO_ENABLE); 341 } 342 343 /* Put the IO into reset */ 344 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 345 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 346 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); 347 348 /* Program LP Wake */ 349 for_each_dsi_port(port, intel_dsi->ports) { 350 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 351 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) 352 tmp &= ~GLK_LP_WAKE; 353 else 354 tmp |= GLK_LP_WAKE; 355 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); 356 } 357 358 /* Wait for Pwr ACK */ 359 for_each_dsi_port(port, intel_dsi->ports) { 360 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 361 GLK_MIPIIO_PORT_POWERED, 20)) 362 drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); 363 } 364 365 /* Check for cold boot scenario */ 366 for_each_dsi_port(port, intel_dsi->ports) { 367 cold_boot |= 368 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); 369 } 370 371 return cold_boot; 372 } 373 374 static void glk_dsi_device_ready(struct intel_encoder *encoder) 375 { 376 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 377 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 378 enum port port; 379 u32 val; 380 381 /* Wait for MIPI PHY status bit to set */ 382 for_each_dsi_port(port, intel_dsi->ports) { 383 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 384 GLK_PHY_STATUS_PORT_READY, 20)) 385 drm_err(&dev_priv->drm, "PHY is not ON\n"); 386 } 387 388 /* Get IO out of reset */ 389 val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 390 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), 391 val | GLK_MIPIIO_RESET_RELEASED); 392 393 /* Get IO out of Low power state*/ 394 for_each_dsi_port(port, intel_dsi->ports) { 395 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { 396 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 397 val &= ~ULPS_STATE_MASK; 398 val |= DEVICE_READY; 399 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 400 usleep_range(10, 15); 401 } else { 402 /* Enter ULPS */ 403 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 404 val &= ~ULPS_STATE_MASK; 405 val |= (ULPS_STATE_ENTER | DEVICE_READY); 406 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 407 408 /* Wait for ULPS active */ 409 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 410 GLK_ULPS_NOT_ACTIVE, 20)) 411 drm_err(&dev_priv->drm, "ULPS not active\n"); 412 413 /* Exit ULPS */ 414 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 415 val &= ~ULPS_STATE_MASK; 416 val |= (ULPS_STATE_EXIT | DEVICE_READY); 417 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 418 419 /* Enter Normal Mode */ 420 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 421 val &= ~ULPS_STATE_MASK; 422 val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); 423 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 424 425 val = intel_de_read(dev_priv, MIPI_CTRL(port)); 426 val &= ~GLK_LP_WAKE; 427 intel_de_write(dev_priv, MIPI_CTRL(port), val); 428 } 429 } 430 431 /* Wait for Stop state */ 432 for_each_dsi_port(port, intel_dsi->ports) { 433 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 434 GLK_DATA_LANE_STOP_STATE, 20)) 435 drm_err(&dev_priv->drm, 436 "Date lane not in STOP state\n"); 437 } 438 439 /* Wait for AFE LATCH */ 440 for_each_dsi_port(port, intel_dsi->ports) { 441 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), 442 AFE_LATCHOUT, 20)) 443 drm_err(&dev_priv->drm, 444 "D-PHY not entering LP-11 state\n"); 445 } 446 } 447 448 static void bxt_dsi_device_ready(struct intel_encoder *encoder) 449 { 450 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 451 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 452 enum port port; 453 u32 val; 454 455 drm_dbg_kms(&dev_priv->drm, "\n"); 456 457 /* Enable MIPI PHY transparent latch */ 458 for_each_dsi_port(port, intel_dsi->ports) { 459 val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 460 intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port), 461 val | LP_OUTPUT_HOLD); 462 usleep_range(2000, 2500); 463 } 464 465 /* Clear ULPS and set device ready */ 466 for_each_dsi_port(port, intel_dsi->ports) { 467 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 468 val &= ~ULPS_STATE_MASK; 469 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 470 usleep_range(2000, 2500); 471 val |= DEVICE_READY; 472 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 473 } 474 } 475 476 static void vlv_dsi_device_ready(struct intel_encoder *encoder) 477 { 478 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 479 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 480 enum port port; 481 u32 val; 482 483 drm_dbg_kms(&dev_priv->drm, "\n"); 484 485 vlv_flisdsi_get(dev_priv); 486 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms 487 * needed everytime after power gate */ 488 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); 489 vlv_flisdsi_put(dev_priv); 490 491 /* bandgap reset is needed after everytime we do power gate */ 492 band_gap_reset(dev_priv); 493 494 for_each_dsi_port(port, intel_dsi->ports) { 495 496 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 497 ULPS_STATE_ENTER); 498 usleep_range(2500, 3000); 499 500 /* Enable MIPI PHY transparent latch 501 * Common bit for both MIPI Port A & MIPI Port C 502 * No similar bit in MIPI Port C reg 503 */ 504 val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A)); 505 intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A), 506 val | LP_OUTPUT_HOLD); 507 usleep_range(1000, 1500); 508 509 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 510 ULPS_STATE_EXIT); 511 usleep_range(2500, 3000); 512 513 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 514 DEVICE_READY); 515 usleep_range(2500, 3000); 516 } 517 } 518 519 static void intel_dsi_device_ready(struct intel_encoder *encoder) 520 { 521 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 522 523 if (IS_GEMINILAKE(dev_priv)) 524 glk_dsi_device_ready(encoder); 525 else if (IS_GEN9_LP(dev_priv)) 526 bxt_dsi_device_ready(encoder); 527 else 528 vlv_dsi_device_ready(encoder); 529 } 530 531 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) 532 { 533 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 534 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 535 enum port port; 536 u32 val; 537 538 /* Enter ULPS */ 539 for_each_dsi_port(port, intel_dsi->ports) { 540 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 541 val &= ~ULPS_STATE_MASK; 542 val |= (ULPS_STATE_ENTER | DEVICE_READY); 543 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 544 } 545 546 /* Wait for MIPI PHY status bit to unset */ 547 for_each_dsi_port(port, intel_dsi->ports) { 548 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 549 GLK_PHY_STATUS_PORT_READY, 20)) 550 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); 551 } 552 553 /* Wait for Pwr ACK bit to unset */ 554 for_each_dsi_port(port, intel_dsi->ports) { 555 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 556 GLK_MIPIIO_PORT_POWERED, 20)) 557 drm_err(&dev_priv->drm, 558 "MIPI IO Port is not powergated\n"); 559 } 560 } 561 562 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) 563 { 564 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 565 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 566 enum port port; 567 u32 tmp; 568 569 /* Put the IO into reset */ 570 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 571 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 572 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); 573 574 /* Wait for MIPI PHY status bit to unset */ 575 for_each_dsi_port(port, intel_dsi->ports) { 576 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 577 GLK_PHY_STATUS_PORT_READY, 20)) 578 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); 579 } 580 581 /* Clear MIPI mode */ 582 for_each_dsi_port(port, intel_dsi->ports) { 583 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 584 tmp &= ~GLK_MIPIIO_ENABLE; 585 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); 586 } 587 } 588 589 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) 590 { 591 glk_dsi_enter_low_power_mode(encoder); 592 glk_dsi_disable_mipi_io(encoder); 593 } 594 595 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) 596 { 597 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 598 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 599 enum port port; 600 601 drm_dbg_kms(&dev_priv->drm, "\n"); 602 for_each_dsi_port(port, intel_dsi->ports) { 603 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ 604 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 605 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); 606 u32 val; 607 608 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 609 DEVICE_READY | ULPS_STATE_ENTER); 610 usleep_range(2000, 2500); 611 612 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 613 DEVICE_READY | ULPS_STATE_EXIT); 614 usleep_range(2000, 2500); 615 616 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 617 DEVICE_READY | ULPS_STATE_ENTER); 618 usleep_range(2000, 2500); 619 620 /* 621 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI 622 * Port A only. MIPI Port C has no similar bit for checking. 623 */ 624 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && 625 intel_de_wait_for_clear(dev_priv, port_ctrl, 626 AFE_LATCHOUT, 30)) 627 drm_err(&dev_priv->drm, "DSI LP not going Low\n"); 628 629 /* Disable MIPI PHY transparent latch */ 630 val = intel_de_read(dev_priv, port_ctrl); 631 intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD); 632 usleep_range(1000, 1500); 633 634 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); 635 usleep_range(2000, 2500); 636 } 637 } 638 639 static void intel_dsi_port_enable(struct intel_encoder *encoder, 640 const struct intel_crtc_state *crtc_state) 641 { 642 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 643 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 644 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 645 enum port port; 646 647 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 648 u32 temp; 649 if (IS_GEN9_LP(dev_priv)) { 650 for_each_dsi_port(port, intel_dsi->ports) { 651 temp = intel_de_read(dev_priv, 652 MIPI_CTRL(port)); 653 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | 654 intel_dsi->pixel_overlap << 655 BXT_PIXEL_OVERLAP_CNT_SHIFT; 656 intel_de_write(dev_priv, MIPI_CTRL(port), 657 temp); 658 } 659 } else { 660 temp = intel_de_read(dev_priv, VLV_CHICKEN_3); 661 temp &= ~PIXEL_OVERLAP_CNT_MASK | 662 intel_dsi->pixel_overlap << 663 PIXEL_OVERLAP_CNT_SHIFT; 664 intel_de_write(dev_priv, VLV_CHICKEN_3, temp); 665 } 666 } 667 668 for_each_dsi_port(port, intel_dsi->ports) { 669 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 670 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 671 u32 temp; 672 673 temp = intel_de_read(dev_priv, port_ctrl); 674 675 temp &= ~LANE_CONFIGURATION_MASK; 676 temp &= ~DUAL_LINK_MODE_MASK; 677 678 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { 679 temp |= (intel_dsi->dual_link - 1) 680 << DUAL_LINK_MODE_SHIFT; 681 if (IS_BROXTON(dev_priv)) 682 temp |= LANE_CONFIGURATION_DUAL_LINK_A; 683 else 684 temp |= crtc->pipe ? 685 LANE_CONFIGURATION_DUAL_LINK_B : 686 LANE_CONFIGURATION_DUAL_LINK_A; 687 } 688 689 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) 690 temp |= DITHERING_ENABLE; 691 692 /* assert ip_tg_enable signal */ 693 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); 694 intel_de_posting_read(dev_priv, port_ctrl); 695 } 696 } 697 698 static void intel_dsi_port_disable(struct intel_encoder *encoder) 699 { 700 struct drm_device *dev = encoder->base.dev; 701 struct drm_i915_private *dev_priv = to_i915(dev); 702 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 703 enum port port; 704 705 for_each_dsi_port(port, intel_dsi->ports) { 706 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 707 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 708 u32 temp; 709 710 /* de-assert ip_tg_enable signal */ 711 temp = intel_de_read(dev_priv, port_ctrl); 712 intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE); 713 intel_de_posting_read(dev_priv, port_ctrl); 714 } 715 } 716 717 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 718 const struct intel_crtc_state *pipe_config); 719 static void intel_dsi_unprepare(struct intel_encoder *encoder); 720 721 /* 722 * Panel enable/disable sequences from the VBT spec. 723 * 724 * Note the spec has AssertReset / DeassertReset swapped from their 725 * usual naming. We use the normal names to avoid confusion (so below 726 * they are swapped compared to the spec). 727 * 728 * Steps starting with MIPI refer to VBT sequences, note that for v2 729 * VBTs several steps which have a VBT in v2 are expected to be handled 730 * directly by the driver, by directly driving gpios for example. 731 * 732 * v2 video mode seq v3 video mode seq command mode seq 733 * - power on - MIPIPanelPowerOn - power on 734 * - wait t1+t2 - wait t1+t2 735 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin 736 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 737 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds 738 * - MIPITearOn 739 * - MIPIDisplayOn 740 * - turn on DPI - turn on DPI - set pipe to dsr mode 741 * - MIPIDisplayOn - MIPIDisplayOn 742 * - wait t5 - wait t5 743 * - backlight on - MIPIBacklightOn - backlight on 744 * ... ... ... issue mem cmds ... 745 * - backlight off - MIPIBacklightOff - backlight off 746 * - wait t6 - wait t6 747 * - MIPIDisplayOff 748 * - turn off DPI - turn off DPI - disable pipe dsr mode 749 * - MIPITearOff 750 * - MIPIDisplayOff - MIPIDisplayOff 751 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 752 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin 753 * - wait t3 - wait t3 754 * - power off - MIPIPanelPowerOff - power off 755 * - wait t4 - wait t4 756 */ 757 758 /* 759 * DSI port enable has to be done before pipe and plane enable, so we do it in 760 * the pre_enable hook instead of the enable hook. 761 */ 762 static void intel_dsi_pre_enable(struct intel_atomic_state *state, 763 struct intel_encoder *encoder, 764 const struct intel_crtc_state *pipe_config, 765 const struct drm_connector_state *conn_state) 766 { 767 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 768 struct drm_crtc *crtc = pipe_config->uapi.crtc; 769 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 771 enum pipe pipe = intel_crtc->pipe; 772 enum port port; 773 u32 val; 774 bool glk_cold_boot = false; 775 776 drm_dbg_kms(&dev_priv->drm, "\n"); 777 778 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 779 780 /* 781 * The BIOS may leave the PLL in a wonky state where it doesn't 782 * lock. It needs to be fully powered down to fix it. 783 */ 784 if (IS_GEN9_LP(dev_priv)) { 785 bxt_dsi_pll_disable(encoder); 786 bxt_dsi_pll_enable(encoder, pipe_config); 787 } else { 788 vlv_dsi_pll_disable(encoder); 789 vlv_dsi_pll_enable(encoder, pipe_config); 790 } 791 792 if (IS_BROXTON(dev_priv)) { 793 /* Add MIPI IO reset programming for modeset */ 794 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); 795 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, 796 val | MIPIO_RST_CTRL); 797 798 /* Power up DSI regulator */ 799 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 800 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); 801 } 802 803 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 804 u32 val; 805 806 /* Disable DPOunit clock gating, can stall pipe */ 807 val = intel_de_read(dev_priv, DSPCLK_GATE_D); 808 val |= DPOUNIT_CLOCK_GATE_DISABLE; 809 intel_de_write(dev_priv, DSPCLK_GATE_D, val); 810 } 811 812 if (!IS_GEMINILAKE(dev_priv)) 813 intel_dsi_prepare(encoder, pipe_config); 814 815 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 816 817 /* 818 * Give the panel time to power-on and then deassert its reset. 819 * Depending on the VBT MIPI sequences version the deassert-seq 820 * may contain the necessary delay, intel_dsi_msleep() will skip 821 * the delay in that case. If there is no deassert-seq, then an 822 * unconditional msleep is used to give the panel time to power-on. 823 */ 824 if (dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) { 825 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 826 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 827 } else { 828 msleep(intel_dsi->panel_on_delay); 829 } 830 831 if (IS_GEMINILAKE(dev_priv)) { 832 glk_cold_boot = glk_dsi_enable_io(encoder); 833 834 /* Prepare port in cold boot(s3/s4) scenario */ 835 if (glk_cold_boot) 836 intel_dsi_prepare(encoder, pipe_config); 837 } 838 839 /* Put device in ready state (LP-11) */ 840 intel_dsi_device_ready(encoder); 841 842 /* Prepare port in normal boot scenario */ 843 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) 844 intel_dsi_prepare(encoder, pipe_config); 845 846 /* Send initialization commands in LP mode */ 847 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 848 849 /* Enable port in pre-enable phase itself because as per hw team 850 * recommendation, port should be enabled befor plane & pipe */ 851 if (is_cmd_mode(intel_dsi)) { 852 for_each_dsi_port(port, intel_dsi->ports) 853 intel_de_write(dev_priv, 854 MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); 855 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); 856 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 857 } else { 858 msleep(20); /* XXX */ 859 for_each_dsi_port(port, intel_dsi->ports) 860 dpi_send_cmd(intel_dsi, TURN_ON, false, port); 861 intel_dsi_msleep(intel_dsi, 100); 862 863 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 864 865 intel_dsi_port_enable(encoder, pipe_config); 866 } 867 868 intel_panel_enable_backlight(pipe_config, conn_state); 869 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 870 } 871 872 static void bxt_dsi_enable(struct intel_atomic_state *state, 873 struct intel_encoder *encoder, 874 const struct intel_crtc_state *crtc_state, 875 const struct drm_connector_state *conn_state) 876 { 877 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 878 879 intel_crtc_vblank_on(crtc_state); 880 } 881 882 /* 883 * DSI port disable has to be done after pipe and plane disable, so we do it in 884 * the post_disable hook. 885 */ 886 static void intel_dsi_disable(struct intel_atomic_state *state, 887 struct intel_encoder *encoder, 888 const struct intel_crtc_state *old_crtc_state, 889 const struct drm_connector_state *old_conn_state) 890 { 891 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 892 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 893 enum port port; 894 895 drm_dbg_kms(&i915->drm, "\n"); 896 897 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 898 intel_panel_disable_backlight(old_conn_state); 899 900 /* 901 * According to the spec we should send SHUTDOWN before 902 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing 903 * has shown that the v3 sequence works for v2 VBTs too 904 */ 905 if (is_vid_mode(intel_dsi)) { 906 /* Send Shutdown command to the panel in LP mode */ 907 for_each_dsi_port(port, intel_dsi->ports) 908 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); 909 msleep(10); 910 } 911 } 912 913 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 914 { 915 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 916 917 if (IS_GEMINILAKE(dev_priv)) 918 glk_dsi_clear_device_ready(encoder); 919 else 920 vlv_dsi_clear_device_ready(encoder); 921 } 922 923 static void intel_dsi_post_disable(struct intel_atomic_state *state, 924 struct intel_encoder *encoder, 925 const struct intel_crtc_state *old_crtc_state, 926 const struct drm_connector_state *old_conn_state) 927 { 928 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 929 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 930 enum port port; 931 u32 val; 932 933 drm_dbg_kms(&dev_priv->drm, "\n"); 934 935 if (IS_GEN9_LP(dev_priv)) { 936 intel_crtc_vblank_off(old_crtc_state); 937 938 skl_scaler_disable(old_crtc_state); 939 } 940 941 if (is_vid_mode(intel_dsi)) { 942 for_each_dsi_port(port, intel_dsi->ports) 943 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 944 945 intel_dsi_port_disable(encoder); 946 usleep_range(2000, 5000); 947 } 948 949 intel_dsi_unprepare(encoder); 950 951 /* 952 * if disable packets are sent before sending shutdown packet then in 953 * some next enable sequence send turn on packet error is observed 954 */ 955 if (is_cmd_mode(intel_dsi)) 956 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF); 957 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 958 959 /* Transition to LP-00 */ 960 intel_dsi_clear_device_ready(encoder); 961 962 if (IS_BROXTON(dev_priv)) { 963 /* Power down DSI regulator to save power */ 964 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 965 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 966 HS_IO_CTRL_SELECT); 967 968 /* Add MIPI IO reset programming for modeset */ 969 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); 970 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, 971 val & ~MIPIO_RST_CTRL); 972 } 973 974 if (IS_GEN9_LP(dev_priv)) { 975 bxt_dsi_pll_disable(encoder); 976 } else { 977 u32 val; 978 979 vlv_dsi_pll_disable(encoder); 980 981 val = intel_de_read(dev_priv, DSPCLK_GATE_D); 982 val &= ~DPOUNIT_CLOCK_GATE_DISABLE; 983 intel_de_write(dev_priv, DSPCLK_GATE_D, val); 984 } 985 986 /* Assert reset */ 987 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 988 989 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); 990 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 991 992 /* 993 * FIXME As we do with eDP, just make a note of the time here 994 * and perform the wait before the next panel power on. 995 */ 996 msleep(intel_dsi->panel_pwr_cycle_delay); 997 } 998 999 static void intel_dsi_shutdown(struct intel_encoder *encoder) 1000 { 1001 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1002 1003 msleep(intel_dsi->panel_pwr_cycle_delay); 1004 } 1005 1006 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 1007 enum pipe *pipe) 1008 { 1009 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1010 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1011 intel_wakeref_t wakeref; 1012 enum port port; 1013 bool active = false; 1014 1015 drm_dbg_kms(&dev_priv->drm, "\n"); 1016 1017 wakeref = intel_display_power_get_if_enabled(dev_priv, 1018 encoder->power_domain); 1019 if (!wakeref) 1020 return false; 1021 1022 /* 1023 * On Broxton the PLL needs to be enabled with a valid divider 1024 * configuration, otherwise accessing DSI registers will hang the 1025 * machine. See BSpec North Display Engine registers/MIPI[BXT]. 1026 */ 1027 if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv)) 1028 goto out_put_power; 1029 1030 /* XXX: this only works for one DSI output */ 1031 for_each_dsi_port(port, intel_dsi->ports) { 1032 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? 1033 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 1034 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE; 1035 1036 /* 1037 * Due to some hardware limitations on VLV/CHV, the DPI enable 1038 * bit in port C control register does not get set. As a 1039 * workaround, check pipe B conf instead. 1040 */ 1041 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1042 port == PORT_C) 1043 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; 1044 1045 /* Try command mode if video mode not enabled */ 1046 if (!enabled) { 1047 u32 tmp = intel_de_read(dev_priv, 1048 MIPI_DSI_FUNC_PRG(port)); 1049 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; 1050 } 1051 1052 if (!enabled) 1053 continue; 1054 1055 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) 1056 continue; 1057 1058 if (IS_GEN9_LP(dev_priv)) { 1059 u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1060 tmp &= BXT_PIPE_SELECT_MASK; 1061 tmp >>= BXT_PIPE_SELECT_SHIFT; 1062 1063 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) 1064 continue; 1065 1066 *pipe = tmp; 1067 } else { 1068 *pipe = port == PORT_A ? PIPE_A : PIPE_B; 1069 } 1070 1071 active = true; 1072 break; 1073 } 1074 1075 out_put_power: 1076 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1077 1078 return active; 1079 } 1080 1081 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, 1082 struct intel_crtc_state *pipe_config) 1083 { 1084 struct drm_device *dev = encoder->base.dev; 1085 struct drm_i915_private *dev_priv = to_i915(dev); 1086 struct drm_display_mode *adjusted_mode = 1087 &pipe_config->hw.adjusted_mode; 1088 struct drm_display_mode *adjusted_mode_sw; 1089 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1090 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1091 unsigned int lane_count = intel_dsi->lane_count; 1092 unsigned int bpp, fmt; 1093 enum port port; 1094 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1095 u16 hfp_sw, hsync_sw, hbp_sw; 1096 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, 1097 crtc_hblank_start_sw, crtc_hblank_end_sw; 1098 1099 /* FIXME: hw readout should not depend on SW state */ 1100 adjusted_mode_sw = &crtc->config->hw.adjusted_mode; 1101 1102 /* 1103 * Atleast one port is active as encoder->get_config called only if 1104 * encoder->get_hw_state() returns true. 1105 */ 1106 for_each_dsi_port(port, intel_dsi->ports) { 1107 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) 1108 break; 1109 } 1110 1111 fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; 1112 bpp = mipi_dsi_pixel_format_to_bpp( 1113 pixel_format_from_register_bits(fmt)); 1114 1115 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1116 1117 /* Enable Frame time stamo based scanline reporting */ 1118 pipe_config->mode_flags |= 1119 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 1120 1121 /* In terms of pixels */ 1122 adjusted_mode->crtc_hdisplay = 1123 intel_de_read(dev_priv, 1124 BXT_MIPI_TRANS_HACTIVE(port)); 1125 adjusted_mode->crtc_vdisplay = 1126 intel_de_read(dev_priv, 1127 BXT_MIPI_TRANS_VACTIVE(port)); 1128 adjusted_mode->crtc_vtotal = 1129 intel_de_read(dev_priv, 1130 BXT_MIPI_TRANS_VTOTAL(port)); 1131 1132 hactive = adjusted_mode->crtc_hdisplay; 1133 hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); 1134 1135 /* 1136 * Meaningful for video mode non-burst sync pulse mode only, 1137 * can be zero for non-burst sync events and burst modes 1138 */ 1139 hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); 1140 hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); 1141 1142 /* harizontal values are in terms of high speed byte clock */ 1143 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, 1144 intel_dsi->burst_mode_ratio); 1145 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, 1146 intel_dsi->burst_mode_ratio); 1147 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, 1148 intel_dsi->burst_mode_ratio); 1149 1150 if (intel_dsi->dual_link) { 1151 hfp *= 2; 1152 hsync *= 2; 1153 hbp *= 2; 1154 } 1155 1156 /* vertical values are in terms of lines */ 1157 vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); 1158 vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); 1159 vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port)); 1160 1161 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; 1162 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; 1163 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; 1164 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1165 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1166 1167 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; 1168 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; 1169 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1170 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1171 1172 /* 1173 * In BXT DSI there is no regs programmed with few horizontal timings 1174 * in Pixels but txbyteclkhs.. So retrieval process adds some 1175 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. 1176 * Actually here for the given adjusted_mode, we are calculating the 1177 * value programmed to the port and then back to the horizontal timing 1178 * param in pixels. This is the expected value, including roundup errors 1179 * And if that is same as retrieved value from port, then 1180 * (HW state) adjusted_mode's horizontal timings are corrected to 1181 * match with SW state to nullify the errors. 1182 */ 1183 /* Calculating the value programmed to the Port register */ 1184 hfp_sw = adjusted_mode_sw->crtc_hsync_start - 1185 adjusted_mode_sw->crtc_hdisplay; 1186 hsync_sw = adjusted_mode_sw->crtc_hsync_end - 1187 adjusted_mode_sw->crtc_hsync_start; 1188 hbp_sw = adjusted_mode_sw->crtc_htotal - 1189 adjusted_mode_sw->crtc_hsync_end; 1190 1191 if (intel_dsi->dual_link) { 1192 hfp_sw /= 2; 1193 hsync_sw /= 2; 1194 hbp_sw /= 2; 1195 } 1196 1197 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, 1198 intel_dsi->burst_mode_ratio); 1199 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, 1200 intel_dsi->burst_mode_ratio); 1201 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, 1202 intel_dsi->burst_mode_ratio); 1203 1204 /* Reverse calculating the adjusted mode parameters from port reg vals*/ 1205 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, 1206 intel_dsi->burst_mode_ratio); 1207 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, 1208 intel_dsi->burst_mode_ratio); 1209 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, 1210 intel_dsi->burst_mode_ratio); 1211 1212 if (intel_dsi->dual_link) { 1213 hfp_sw *= 2; 1214 hsync_sw *= 2; 1215 hbp_sw *= 2; 1216 } 1217 1218 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + 1219 hsync_sw + hbp_sw; 1220 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; 1221 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; 1222 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; 1223 crtc_hblank_end_sw = crtc_htotal_sw; 1224 1225 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) 1226 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; 1227 1228 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) 1229 adjusted_mode->crtc_hsync_start = 1230 adjusted_mode_sw->crtc_hsync_start; 1231 1232 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) 1233 adjusted_mode->crtc_hsync_end = 1234 adjusted_mode_sw->crtc_hsync_end; 1235 1236 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) 1237 adjusted_mode->crtc_hblank_start = 1238 adjusted_mode_sw->crtc_hblank_start; 1239 1240 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) 1241 adjusted_mode->crtc_hblank_end = 1242 adjusted_mode_sw->crtc_hblank_end; 1243 } 1244 1245 static void intel_dsi_get_config(struct intel_encoder *encoder, 1246 struct intel_crtc_state *pipe_config) 1247 { 1248 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1249 u32 pclk; 1250 drm_dbg_kms(&dev_priv->drm, "\n"); 1251 1252 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1253 1254 if (IS_GEN9_LP(dev_priv)) { 1255 bxt_dsi_get_pipe_config(encoder, pipe_config); 1256 pclk = bxt_dsi_get_pclk(encoder, pipe_config); 1257 } else { 1258 pclk = vlv_dsi_get_pclk(encoder, pipe_config); 1259 } 1260 1261 if (pclk) { 1262 pipe_config->hw.adjusted_mode.crtc_clock = pclk; 1263 pipe_config->port_clock = pclk; 1264 } 1265 } 1266 1267 /* return txclkesc cycles in terms of divider and duration in us */ 1268 static u16 txclkesc(u32 divider, unsigned int us) 1269 { 1270 switch (divider) { 1271 case ESCAPE_CLOCK_DIVIDER_1: 1272 default: 1273 return 20 * us; 1274 case ESCAPE_CLOCK_DIVIDER_2: 1275 return 10 * us; 1276 case ESCAPE_CLOCK_DIVIDER_4: 1277 return 5 * us; 1278 } 1279 } 1280 1281 static void set_dsi_timings(struct drm_encoder *encoder, 1282 const struct drm_display_mode *adjusted_mode) 1283 { 1284 struct drm_device *dev = encoder->dev; 1285 struct drm_i915_private *dev_priv = to_i915(dev); 1286 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1287 enum port port; 1288 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1289 unsigned int lane_count = intel_dsi->lane_count; 1290 1291 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1292 1293 hactive = adjusted_mode->crtc_hdisplay; 1294 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; 1295 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1296 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; 1297 1298 if (intel_dsi->dual_link) { 1299 hactive /= 2; 1300 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1301 hactive += intel_dsi->pixel_overlap; 1302 hfp /= 2; 1303 hsync /= 2; 1304 hbp /= 2; 1305 } 1306 1307 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; 1308 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; 1309 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; 1310 1311 /* horizontal values are in terms of high speed byte clock */ 1312 hactive = txbyteclkhs(hactive, bpp, lane_count, 1313 intel_dsi->burst_mode_ratio); 1314 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1315 hsync = txbyteclkhs(hsync, bpp, lane_count, 1316 intel_dsi->burst_mode_ratio); 1317 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1318 1319 for_each_dsi_port(port, intel_dsi->ports) { 1320 if (IS_GEN9_LP(dev_priv)) { 1321 /* 1322 * Program hdisplay and vdisplay on MIPI transcoder. 1323 * This is different from calculated hactive and 1324 * vactive, as they are calculated per channel basis, 1325 * whereas these values should be based on resolution. 1326 */ 1327 intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), 1328 adjusted_mode->crtc_hdisplay); 1329 intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), 1330 adjusted_mode->crtc_vdisplay); 1331 intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), 1332 adjusted_mode->crtc_vtotal); 1333 } 1334 1335 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), 1336 hactive); 1337 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); 1338 1339 /* meaningful for video mode non-burst sync pulse mode only, 1340 * can be zero for non-burst sync events and burst modes */ 1341 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), 1342 hsync); 1343 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); 1344 1345 /* vertical values are in terms of lines */ 1346 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); 1347 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), 1348 vsync); 1349 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); 1350 } 1351 } 1352 1353 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) 1354 { 1355 switch (fmt) { 1356 case MIPI_DSI_FMT_RGB888: 1357 return VID_MODE_FORMAT_RGB888; 1358 case MIPI_DSI_FMT_RGB666: 1359 return VID_MODE_FORMAT_RGB666; 1360 case MIPI_DSI_FMT_RGB666_PACKED: 1361 return VID_MODE_FORMAT_RGB666_PACKED; 1362 case MIPI_DSI_FMT_RGB565: 1363 return VID_MODE_FORMAT_RGB565; 1364 default: 1365 MISSING_CASE(fmt); 1366 return VID_MODE_FORMAT_RGB666; 1367 } 1368 } 1369 1370 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 1371 const struct intel_crtc_state *pipe_config) 1372 { 1373 struct drm_encoder *encoder = &intel_encoder->base; 1374 struct drm_device *dev = encoder->dev; 1375 struct drm_i915_private *dev_priv = to_i915(dev); 1376 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 1377 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1378 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1379 enum port port; 1380 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1381 u32 val, tmp; 1382 u16 mode_hdisplay; 1383 1384 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(intel_crtc->pipe)); 1385 1386 mode_hdisplay = adjusted_mode->crtc_hdisplay; 1387 1388 if (intel_dsi->dual_link) { 1389 mode_hdisplay /= 2; 1390 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1391 mode_hdisplay += intel_dsi->pixel_overlap; 1392 } 1393 1394 for_each_dsi_port(port, intel_dsi->ports) { 1395 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1396 /* 1397 * escape clock divider, 20MHz, shared for A and C. 1398 * device ready must be off when doing this! txclkesc? 1399 */ 1400 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 1401 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 1402 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), 1403 tmp | ESCAPE_CLOCK_DIVIDER_1); 1404 1405 /* read request priority is per pipe */ 1406 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1407 tmp &= ~READ_REQUEST_PRIORITY_MASK; 1408 intel_de_write(dev_priv, MIPI_CTRL(port), 1409 tmp | READ_REQUEST_PRIORITY_HIGH); 1410 } else if (IS_GEN9_LP(dev_priv)) { 1411 enum pipe pipe = intel_crtc->pipe; 1412 1413 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1414 tmp &= ~BXT_PIPE_SELECT_MASK; 1415 1416 tmp |= BXT_PIPE_SELECT(pipe); 1417 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); 1418 } 1419 1420 /* XXX: why here, why like this? handling in irq handler?! */ 1421 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); 1422 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); 1423 1424 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), 1425 intel_dsi->dphy_reg); 1426 1427 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), 1428 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); 1429 } 1430 1431 set_dsi_timings(encoder, adjusted_mode); 1432 1433 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; 1434 if (is_cmd_mode(intel_dsi)) { 1435 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; 1436 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ 1437 } else { 1438 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; 1439 val |= pixel_format_to_reg(intel_dsi->pixel_format); 1440 } 1441 1442 tmp = 0; 1443 if (intel_dsi->eotp_pkt == 0) 1444 tmp |= EOT_DISABLE; 1445 if (intel_dsi->clock_stop) 1446 tmp |= CLOCKSTOP; 1447 1448 if (IS_GEN9_LP(dev_priv)) { 1449 tmp |= BXT_DPHY_DEFEATURE_EN; 1450 if (!is_cmd_mode(intel_dsi)) 1451 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; 1452 } 1453 1454 for_each_dsi_port(port, intel_dsi->ports) { 1455 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); 1456 1457 /* timeouts for recovery. one frame IIUC. if counter expires, 1458 * EOT and stop state. */ 1459 1460 /* 1461 * In burst mode, value greater than one DPI line Time in byte 1462 * clock (txbyteclkhs) To timeout this timer 1+ of the above 1463 * said value is recommended. 1464 * 1465 * In non-burst mode, Value greater than one DPI frame time in 1466 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1467 * said value is recommended. 1468 * 1469 * In DBI only mode, value greater than one DBI frame time in 1470 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1471 * said value is recommended. 1472 */ 1473 1474 if (is_vid_mode(intel_dsi) && 1475 intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 1476 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), 1477 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1478 } else { 1479 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), 1480 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1481 } 1482 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), 1483 intel_dsi->lp_rx_timeout); 1484 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), 1485 intel_dsi->turn_arnd_val); 1486 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), 1487 intel_dsi->rst_timer_val); 1488 1489 /* dphy stuff */ 1490 1491 /* in terms of low power clock */ 1492 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), 1493 txclkesc(intel_dsi->escape_clk_div, 100)); 1494 1495 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { 1496 /* 1497 * BXT spec says write MIPI_INIT_COUNT for 1498 * both the ports, even if only one is 1499 * getting used. So write the other port 1500 * if not in dual link mode. 1501 */ 1502 intel_de_write(dev_priv, 1503 MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A), 1504 intel_dsi->init_count); 1505 } 1506 1507 /* recovery disables */ 1508 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); 1509 1510 /* in terms of low power clock */ 1511 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), 1512 intel_dsi->init_count); 1513 1514 /* in terms of txbyteclkhs. actual high to low switch + 1515 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. 1516 * 1517 * XXX: write MIPI_STOP_STATE_STALL? 1518 */ 1519 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), 1520 intel_dsi->hs_to_lp_count); 1521 1522 /* XXX: low power clock equivalence in terms of byte clock. 1523 * the number of byte clocks occupied in one low power clock. 1524 * based on txbyteclkhs and txclkesc. 1525 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL 1526 * ) / 105.??? 1527 */ 1528 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), 1529 intel_dsi->lp_byte_clk); 1530 1531 if (IS_GEMINILAKE(dev_priv)) { 1532 intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), 1533 intel_dsi->lp_byte_clk); 1534 /* Shadow of DPHY reg */ 1535 intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), 1536 intel_dsi->dphy_reg); 1537 } 1538 1539 /* the bw essential for transmitting 16 long packets containing 1540 * 252 bytes meant for dcs write memory command is programmed in 1541 * this register in terms of byte clocks. based on dsi transfer 1542 * rate and the number of lanes configured the time taken to 1543 * transmit 16 long packets in a dsi stream varies. */ 1544 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), 1545 intel_dsi->bw_timer); 1546 1547 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), 1548 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); 1549 1550 if (is_vid_mode(intel_dsi)) 1551 /* Some panels might have resolution which is not a 1552 * multiple of 64 like 1366 x 768. Enable RANDOM 1553 * resolution support for such panels by default */ 1554 intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), 1555 intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_format | IP_TG_CONFIG | RANDOM_DPI_DISPLAY_RESOLUTION); 1556 } 1557 } 1558 1559 static void intel_dsi_unprepare(struct intel_encoder *encoder) 1560 { 1561 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1562 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1563 enum port port; 1564 u32 val; 1565 1566 if (IS_GEMINILAKE(dev_priv)) 1567 return; 1568 1569 for_each_dsi_port(port, intel_dsi->ports) { 1570 /* Panel commands can be sent when clock is in LP11 */ 1571 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); 1572 1573 if (IS_GEN9_LP(dev_priv)) 1574 bxt_dsi_reset_clocks(encoder, port); 1575 else 1576 vlv_dsi_reset_clocks(encoder, port); 1577 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); 1578 1579 val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)); 1580 val &= ~VID_MODE_FORMAT_MASK; 1581 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); 1582 1583 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); 1584 } 1585 } 1586 1587 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) 1588 { 1589 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1590 1591 intel_dsi_vbt_gpio_cleanup(intel_dsi); 1592 intel_encoder_destroy(encoder); 1593 } 1594 1595 static const struct drm_encoder_funcs intel_dsi_funcs = { 1596 .destroy = intel_dsi_encoder_destroy, 1597 }; 1598 1599 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 1600 .get_modes = intel_dsi_get_modes, 1601 .mode_valid = intel_dsi_mode_valid, 1602 .atomic_check = intel_digital_connector_atomic_check, 1603 }; 1604 1605 static const struct drm_connector_funcs intel_dsi_connector_funcs = { 1606 .detect = intel_panel_detect, 1607 .late_register = intel_connector_register, 1608 .early_unregister = intel_connector_unregister, 1609 .destroy = intel_connector_destroy, 1610 .fill_modes = drm_helper_probe_single_connector_modes, 1611 .atomic_get_property = intel_digital_connector_atomic_get_property, 1612 .atomic_set_property = intel_digital_connector_atomic_set_property, 1613 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1614 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1615 }; 1616 1617 static void vlv_dsi_add_properties(struct intel_connector *connector) 1618 { 1619 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1620 1621 if (connector->panel.fixed_mode) { 1622 u32 allowed_scalers; 1623 1624 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); 1625 if (!HAS_GMCH(dev_priv)) 1626 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); 1627 1628 drm_connector_attach_scaling_mode_property(&connector->base, 1629 allowed_scalers); 1630 1631 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1632 1633 drm_connector_set_panel_orientation_with_quirk( 1634 &connector->base, 1635 intel_dsi_get_panel_orientation(connector), 1636 connector->panel.fixed_mode->hdisplay, 1637 connector->panel.fixed_mode->vdisplay); 1638 } 1639 } 1640 1641 #define NS_KHZ_RATIO 1000000 1642 1643 #define PREPARE_CNT_MAX 0x3F 1644 #define EXIT_ZERO_CNT_MAX 0x3F 1645 #define CLK_ZERO_CNT_MAX 0xFF 1646 #define TRAIL_CNT_MAX 0x1F 1647 1648 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) 1649 { 1650 struct drm_device *dev = intel_dsi->base.base.dev; 1651 struct drm_i915_private *dev_priv = to_i915(dev); 1652 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1653 u32 tlpx_ns, extra_byte_count, tlpx_ui; 1654 u32 ui_num, ui_den; 1655 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1656 u32 ths_prepare_ns, tclk_trail_ns; 1657 u32 tclk_prepare_clkzero, ths_prepare_hszero; 1658 u32 lp_to_hs_switch, hs_to_lp_switch; 1659 u32 mul; 1660 1661 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1662 1663 switch (intel_dsi->lane_count) { 1664 case 1: 1665 case 2: 1666 extra_byte_count = 2; 1667 break; 1668 case 3: 1669 extra_byte_count = 4; 1670 break; 1671 case 4: 1672 default: 1673 extra_byte_count = 3; 1674 break; 1675 } 1676 1677 /* in Kbps */ 1678 ui_num = NS_KHZ_RATIO; 1679 ui_den = intel_dsi_bitrate(intel_dsi); 1680 1681 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; 1682 ths_prepare_hszero = mipi_config->ths_prepare_hszero; 1683 1684 /* 1685 * B060 1686 * LP byte clock = TLPX/ (8UI) 1687 */ 1688 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); 1689 1690 /* DDR clock period = 2 * UI 1691 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ) 1692 * UI(nsec) = 10^6 / bitrate 1693 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate 1694 * DDR clock count = ns_value / DDR clock period 1695 * 1696 * For GEMINILAKE dphy_param_reg will be programmed in terms of 1697 * HS byte clock count for other platform in HS ddr clock count 1698 */ 1699 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; 1700 ths_prepare_ns = max(mipi_config->ths_prepare, 1701 mipi_config->tclk_prepare); 1702 1703 /* prepare count */ 1704 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul); 1705 1706 if (prepare_cnt > PREPARE_CNT_MAX) { 1707 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", 1708 prepare_cnt); 1709 prepare_cnt = PREPARE_CNT_MAX; 1710 } 1711 1712 /* exit zero count */ 1713 exit_zero_cnt = DIV_ROUND_UP( 1714 (ths_prepare_hszero - ths_prepare_ns) * ui_den, 1715 ui_num * mul 1716 ); 1717 1718 /* 1719 * Exit zero is unified val ths_zero and ths_exit 1720 * minimum value for ths_exit = 110ns 1721 * min (exit_zero_cnt * 2) = 110/UI 1722 * exit_zero_cnt = 55/UI 1723 */ 1724 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num) 1725 exit_zero_cnt += 1; 1726 1727 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) { 1728 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", 1729 exit_zero_cnt); 1730 exit_zero_cnt = EXIT_ZERO_CNT_MAX; 1731 } 1732 1733 /* clk zero count */ 1734 clk_zero_cnt = DIV_ROUND_UP( 1735 (tclk_prepare_clkzero - ths_prepare_ns) 1736 * ui_den, ui_num * mul); 1737 1738 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) { 1739 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", 1740 clk_zero_cnt); 1741 clk_zero_cnt = CLK_ZERO_CNT_MAX; 1742 } 1743 1744 /* trail count */ 1745 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1746 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul); 1747 1748 if (trail_cnt > TRAIL_CNT_MAX) { 1749 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", 1750 trail_cnt); 1751 trail_cnt = TRAIL_CNT_MAX; 1752 } 1753 1754 /* B080 */ 1755 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | 1756 clk_zero_cnt << 8 | prepare_cnt; 1757 1758 /* 1759 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT * 1760 * mul + 10UI + Extra Byte Count 1761 * 1762 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count 1763 * Extra Byte Count is calculated according to number of lanes. 1764 * High Low Switch Count is the Max of LP to HS and 1765 * HS to LP switch count 1766 * 1767 */ 1768 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); 1769 1770 /* B044 */ 1771 /* FIXME: 1772 * The comment above does not match with the code */ 1773 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul + 1774 exit_zero_cnt * mul + 10, 8); 1775 1776 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); 1777 1778 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); 1779 intel_dsi->hs_to_lp_count += extra_byte_count; 1780 1781 /* B088 */ 1782 /* LP -> HS for clock lanes 1783 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + 1784 * extra byte count 1785 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * 1786 * 2(in UI) + extra byte count 1787 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / 1788 * 8 + extra byte count 1789 */ 1790 intel_dsi->clk_lp_to_hs_count = 1791 DIV_ROUND_UP( 1792 4 * tlpx_ui + prepare_cnt * 2 + 1793 clk_zero_cnt * 2, 1794 8); 1795 1796 intel_dsi->clk_lp_to_hs_count += extra_byte_count; 1797 1798 /* HS->LP for Clock Lanes 1799 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + 1800 * Extra byte count 1801 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count 1802 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + 1803 * Extra byte count 1804 */ 1805 intel_dsi->clk_hs_to_lp_count = 1806 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, 1807 8); 1808 intel_dsi->clk_hs_to_lp_count += extra_byte_count; 1809 1810 intel_dsi_log_params(intel_dsi); 1811 } 1812 1813 void vlv_dsi_init(struct drm_i915_private *dev_priv) 1814 { 1815 struct drm_device *dev = &dev_priv->drm; 1816 struct intel_dsi *intel_dsi; 1817 struct intel_encoder *intel_encoder; 1818 struct drm_encoder *encoder; 1819 struct intel_connector *intel_connector; 1820 struct drm_connector *connector; 1821 struct drm_display_mode *current_mode, *fixed_mode; 1822 enum port port; 1823 enum pipe pipe; 1824 1825 drm_dbg_kms(&dev_priv->drm, "\n"); 1826 1827 /* There is no detection method for MIPI so rely on VBT */ 1828 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1829 return; 1830 1831 if (IS_GEN9_LP(dev_priv)) 1832 dev_priv->mipi_mmio_base = BXT_MIPI_BASE; 1833 else 1834 dev_priv->mipi_mmio_base = VLV_MIPI_BASE; 1835 1836 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1837 if (!intel_dsi) 1838 return; 1839 1840 intel_connector = intel_connector_alloc(); 1841 if (!intel_connector) { 1842 kfree(intel_dsi); 1843 return; 1844 } 1845 1846 intel_encoder = &intel_dsi->base; 1847 encoder = &intel_encoder->base; 1848 intel_dsi->attached_connector = intel_connector; 1849 1850 connector = &intel_connector->base; 1851 1852 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, 1853 "DSI %c", port_name(port)); 1854 1855 intel_encoder->compute_config = intel_dsi_compute_config; 1856 intel_encoder->pre_enable = intel_dsi_pre_enable; 1857 if (IS_GEN9_LP(dev_priv)) 1858 intel_encoder->enable = bxt_dsi_enable; 1859 intel_encoder->disable = intel_dsi_disable; 1860 intel_encoder->post_disable = intel_dsi_post_disable; 1861 intel_encoder->get_hw_state = intel_dsi_get_hw_state; 1862 intel_encoder->get_config = intel_dsi_get_config; 1863 intel_encoder->update_pipe = intel_panel_update_backlight; 1864 intel_encoder->shutdown = intel_dsi_shutdown; 1865 1866 intel_connector->get_hw_state = intel_connector_get_hw_state; 1867 1868 intel_encoder->port = port; 1869 intel_encoder->type = INTEL_OUTPUT_DSI; 1870 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1871 intel_encoder->cloneable = 0; 1872 1873 /* 1874 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI 1875 * port C. BXT isn't limited like this. 1876 */ 1877 if (IS_GEN9_LP(dev_priv)) 1878 intel_encoder->pipe_mask = ~0; 1879 else if (port == PORT_A) 1880 intel_encoder->pipe_mask = BIT(PIPE_A); 1881 else 1882 intel_encoder->pipe_mask = BIT(PIPE_B); 1883 1884 if (dev_priv->vbt.dsi.config->dual_link) 1885 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); 1886 else 1887 intel_dsi->ports = BIT(port); 1888 1889 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 1890 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 1891 1892 /* Create a DSI host (and a device) for each port. */ 1893 for_each_dsi_port(port, intel_dsi->ports) { 1894 struct intel_dsi_host *host; 1895 1896 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops, 1897 port); 1898 if (!host) 1899 goto err; 1900 1901 intel_dsi->dsi_hosts[port] = host; 1902 } 1903 1904 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1905 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 1906 goto err; 1907 } 1908 1909 /* Use clock read-back from current hw-state for fastboot */ 1910 current_mode = intel_encoder_current_mode(intel_encoder); 1911 if (current_mode) { 1912 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", 1913 intel_dsi->pclk, current_mode->clock); 1914 if (intel_fuzzy_clock_check(intel_dsi->pclk, 1915 current_mode->clock)) { 1916 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); 1917 intel_dsi->pclk = current_mode->clock; 1918 } 1919 1920 kfree(current_mode); 1921 } 1922 1923 vlv_dphy_param_init(intel_dsi); 1924 1925 intel_dsi_vbt_gpio_init(intel_dsi, 1926 intel_dsi_get_hw_state(intel_encoder, &pipe)); 1927 1928 drm_connector_init(dev, connector, &intel_dsi_connector_funcs, 1929 DRM_MODE_CONNECTOR_DSI); 1930 1931 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); 1932 1933 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ 1934 connector->interlace_allowed = false; 1935 connector->doublescan_allowed = false; 1936 1937 intel_connector_attach_encoder(intel_connector, intel_encoder); 1938 1939 mutex_lock(&dev->mode_config.mutex); 1940 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 1941 mutex_unlock(&dev->mode_config.mutex); 1942 1943 if (!fixed_mode) { 1944 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); 1945 goto err_cleanup_connector; 1946 } 1947 1948 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 1949 intel_panel_setup_backlight(connector, INVALID_PIPE); 1950 1951 vlv_dsi_add_properties(intel_connector); 1952 1953 return; 1954 1955 err_cleanup_connector: 1956 drm_connector_cleanup(&intel_connector->base); 1957 err: 1958 drm_encoder_cleanup(&intel_encoder->base); 1959 kfree(intel_dsi); 1960 kfree(intel_connector); 1961 } 1962