1 /*
2  * Copyright © 2013 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Author: Jani Nikula <jani.nikula@intel.com>
24  */
25 
26 #include <linux/slab.h>
27 
28 #include <drm/drm_atomic_helper.h>
29 #include <drm/drm_crtc.h>
30 #include <drm/drm_edid.h>
31 #include <drm/drm_mipi_dsi.h>
32 
33 #include "i915_drv.h"
34 #include "i915_reg.h"
35 #include "intel_atomic.h"
36 #include "intel_backlight.h"
37 #include "intel_connector.h"
38 #include "intel_crtc.h"
39 #include "intel_de.h"
40 #include "intel_display_types.h"
41 #include "intel_dsi.h"
42 #include "intel_dsi_vbt.h"
43 #include "intel_fifo_underrun.h"
44 #include "intel_panel.h"
45 #include "skl_scaler.h"
46 #include "vlv_dsi.h"
47 #include "vlv_dsi_pll.h"
48 #include "vlv_dsi_regs.h"
49 #include "vlv_sideband.h"
50 
51 /* return pixels in terms of txbyteclkhs */
52 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
53 		       u16 burst_mode_ratio)
54 {
55 	return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
56 					 8 * 100), lane_count);
57 }
58 
59 /* return pixels equvalent to txbyteclkhs */
60 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
61 			u16 burst_mode_ratio)
62 {
63 	return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
64 						(bpp * burst_mode_ratio));
65 }
66 
67 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
68 {
69 	/* It just so happens the VBT matches register contents. */
70 	switch (fmt) {
71 	case VID_MODE_FORMAT_RGB888:
72 		return MIPI_DSI_FMT_RGB888;
73 	case VID_MODE_FORMAT_RGB666:
74 		return MIPI_DSI_FMT_RGB666;
75 	case VID_MODE_FORMAT_RGB666_PACKED:
76 		return MIPI_DSI_FMT_RGB666_PACKED;
77 	case VID_MODE_FORMAT_RGB565:
78 		return MIPI_DSI_FMT_RGB565;
79 	default:
80 		MISSING_CASE(fmt);
81 		return MIPI_DSI_FMT_RGB666;
82 	}
83 }
84 
85 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
86 {
87 	struct drm_encoder *encoder = &intel_dsi->base.base;
88 	struct drm_device *dev = encoder->dev;
89 	struct drm_i915_private *dev_priv = to_i915(dev);
90 	u32 mask;
91 
92 	mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
93 		LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
94 
95 	if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
96 				  mask, 100))
97 		drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
98 }
99 
100 static void write_data(struct drm_i915_private *dev_priv,
101 		       i915_reg_t reg,
102 		       const u8 *data, u32 len)
103 {
104 	u32 i, j;
105 
106 	for (i = 0; i < len; i += 4) {
107 		u32 val = 0;
108 
109 		for (j = 0; j < min_t(u32, len - i, 4); j++)
110 			val |= *data++ << 8 * j;
111 
112 		intel_de_write(dev_priv, reg, val);
113 	}
114 }
115 
116 static void read_data(struct drm_i915_private *dev_priv,
117 		      i915_reg_t reg,
118 		      u8 *data, u32 len)
119 {
120 	u32 i, j;
121 
122 	for (i = 0; i < len; i += 4) {
123 		u32 val = intel_de_read(dev_priv, reg);
124 
125 		for (j = 0; j < min_t(u32, len - i, 4); j++)
126 			*data++ = val >> 8 * j;
127 	}
128 }
129 
130 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
131 				       const struct mipi_dsi_msg *msg)
132 {
133 	struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
134 	struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
135 	struct drm_i915_private *dev_priv = to_i915(dev);
136 	enum port port = intel_dsi_host->port;
137 	struct mipi_dsi_packet packet;
138 	ssize_t ret;
139 	const u8 *header;
140 	i915_reg_t data_reg, ctrl_reg;
141 	u32 data_mask, ctrl_mask;
142 
143 	ret = mipi_dsi_create_packet(&packet, msg);
144 	if (ret < 0)
145 		return ret;
146 
147 	header = packet.header;
148 
149 	if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
150 		data_reg = MIPI_LP_GEN_DATA(port);
151 		data_mask = LP_DATA_FIFO_FULL;
152 		ctrl_reg = MIPI_LP_GEN_CTRL(port);
153 		ctrl_mask = LP_CTRL_FIFO_FULL;
154 	} else {
155 		data_reg = MIPI_HS_GEN_DATA(port);
156 		data_mask = HS_DATA_FIFO_FULL;
157 		ctrl_reg = MIPI_HS_GEN_CTRL(port);
158 		ctrl_mask = HS_CTRL_FIFO_FULL;
159 	}
160 
161 	/* note: this is never true for reads */
162 	if (packet.payload_length) {
163 		if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
164 					    data_mask, 50))
165 			drm_err(&dev_priv->drm,
166 				"Timeout waiting for HS/LP DATA FIFO !full\n");
167 
168 		write_data(dev_priv, data_reg, packet.payload,
169 			   packet.payload_length);
170 	}
171 
172 	if (msg->rx_len) {
173 		intel_de_write(dev_priv, MIPI_INTR_STAT(port),
174 			       GEN_READ_DATA_AVAIL);
175 	}
176 
177 	if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
178 				    ctrl_mask, 50)) {
179 		drm_err(&dev_priv->drm,
180 			"Timeout waiting for HS/LP CTRL FIFO !full\n");
181 	}
182 
183 	intel_de_write(dev_priv, ctrl_reg,
184 		       header[2] << 16 | header[1] << 8 | header[0]);
185 
186 	/* ->rx_len is set only for reads */
187 	if (msg->rx_len) {
188 		data_mask = GEN_READ_DATA_AVAIL;
189 		if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
190 					  data_mask, 50))
191 			drm_err(&dev_priv->drm,
192 				"Timeout waiting for read data.\n");
193 
194 		read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
195 	}
196 
197 	/* XXX: fix for reads and writes */
198 	return 4 + packet.payload_length;
199 }
200 
201 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
202 				 struct mipi_dsi_device *dsi)
203 {
204 	return 0;
205 }
206 
207 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
208 				 struct mipi_dsi_device *dsi)
209 {
210 	return 0;
211 }
212 
213 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
214 	.attach = intel_dsi_host_attach,
215 	.detach = intel_dsi_host_detach,
216 	.transfer = intel_dsi_host_transfer,
217 };
218 
219 /*
220  * send a video mode command
221  *
222  * XXX: commands with data in MIPI_DPI_DATA?
223  */
224 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
225 			enum port port)
226 {
227 	struct drm_encoder *encoder = &intel_dsi->base.base;
228 	struct drm_device *dev = encoder->dev;
229 	struct drm_i915_private *dev_priv = to_i915(dev);
230 	u32 mask;
231 
232 	/* XXX: pipe, hs */
233 	if (hs)
234 		cmd &= ~DPI_LP_MODE;
235 	else
236 		cmd |= DPI_LP_MODE;
237 
238 	/* clear bit */
239 	intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
240 
241 	/* XXX: old code skips write if control unchanged */
242 	if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port)))
243 		drm_dbg_kms(&dev_priv->drm,
244 			    "Same special packet %02x twice in a row.\n", cmd);
245 
246 	intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd);
247 
248 	mask = SPL_PKT_SENT_INTERRUPT;
249 	if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
250 		drm_err(&dev_priv->drm,
251 			"Video mode command 0x%08x send failed.\n", cmd);
252 
253 	return 0;
254 }
255 
256 static void band_gap_reset(struct drm_i915_private *dev_priv)
257 {
258 	vlv_flisdsi_get(dev_priv);
259 
260 	vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
261 	vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
262 	vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
263 	udelay(150);
264 	vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
265 	vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
266 
267 	vlv_flisdsi_put(dev_priv);
268 }
269 
270 static int intel_dsi_compute_config(struct intel_encoder *encoder,
271 				    struct intel_crtc_state *pipe_config,
272 				    struct drm_connector_state *conn_state)
273 {
274 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
275 	struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
276 						   base);
277 	struct intel_connector *intel_connector = intel_dsi->attached_connector;
278 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
279 	int ret;
280 
281 	drm_dbg_kms(&dev_priv->drm, "\n");
282 	pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
283 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
284 
285 	ret = intel_panel_compute_config(intel_connector, adjusted_mode);
286 	if (ret)
287 		return ret;
288 
289 	ret = intel_panel_fitting(pipe_config, conn_state);
290 	if (ret)
291 		return ret;
292 
293 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
294 		return -EINVAL;
295 
296 	/* DSI uses short packets for sync events, so clear mode flags for DSI */
297 	adjusted_mode->flags = 0;
298 
299 	if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
300 		pipe_config->pipe_bpp = 24;
301 	else
302 		pipe_config->pipe_bpp = 18;
303 
304 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
305 		/* Enable Frame time stamp based scanline reporting */
306 		pipe_config->mode_flags |=
307 			I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
308 
309 		/* Dual link goes to DSI transcoder A. */
310 		if (intel_dsi->ports == BIT(PORT_C))
311 			pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
312 		else
313 			pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
314 
315 		ret = bxt_dsi_pll_compute(encoder, pipe_config);
316 		if (ret)
317 			return -EINVAL;
318 	} else {
319 		ret = vlv_dsi_pll_compute(encoder, pipe_config);
320 		if (ret)
321 			return -EINVAL;
322 	}
323 
324 	pipe_config->clock_set = true;
325 
326 	return 0;
327 }
328 
329 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
330 {
331 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
332 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
333 	enum port port;
334 	bool cold_boot = false;
335 
336 	/* Set the MIPI mode
337 	 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
338 	 * Power ON MIPI IO first and then write into IO reset and LP wake bits
339 	 */
340 	for_each_dsi_port(port, intel_dsi->ports)
341 		intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE);
342 
343 	/* Put the IO into reset */
344 	intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
345 
346 	/* Program LP Wake */
347 	for_each_dsi_port(port, intel_dsi->ports) {
348 		u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
349 		intel_de_rmw(dev_priv, MIPI_CTRL(port),
350 			     GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0);
351 	}
352 
353 	/* Wait for Pwr ACK */
354 	for_each_dsi_port(port, intel_dsi->ports) {
355 		if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
356 					  GLK_MIPIIO_PORT_POWERED, 20))
357 			drm_err(&dev_priv->drm, "MIPIO port is powergated\n");
358 	}
359 
360 	/* Check for cold boot scenario */
361 	for_each_dsi_port(port, intel_dsi->ports) {
362 		cold_boot |=
363 			!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY);
364 	}
365 
366 	return cold_boot;
367 }
368 
369 static void glk_dsi_device_ready(struct intel_encoder *encoder)
370 {
371 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
372 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
373 	enum port port;
374 
375 	/* Wait for MIPI PHY status bit to set */
376 	for_each_dsi_port(port, intel_dsi->ports) {
377 		if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
378 					  GLK_PHY_STATUS_PORT_READY, 20))
379 			drm_err(&dev_priv->drm, "PHY is not ON\n");
380 	}
381 
382 	/* Get IO out of reset */
383 	intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);
384 
385 	/* Get IO out of Low power state*/
386 	for_each_dsi_port(port, intel_dsi->ports) {
387 		if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
388 			intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
389 				     ULPS_STATE_MASK, DEVICE_READY);
390 			usleep_range(10, 15);
391 		} else {
392 			/* Enter ULPS */
393 			intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
394 				     ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
395 
396 			/* Wait for ULPS active */
397 			if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
398 						    GLK_ULPS_NOT_ACTIVE, 20))
399 				drm_err(&dev_priv->drm, "ULPS not active\n");
400 
401 			/* Exit ULPS */
402 			intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
403 				     ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY);
404 
405 			/* Enter Normal Mode */
406 			intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
407 				     ULPS_STATE_MASK,
408 				     ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
409 
410 			intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0);
411 		}
412 	}
413 
414 	/* Wait for Stop state */
415 	for_each_dsi_port(port, intel_dsi->ports) {
416 		if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
417 					  GLK_DATA_LANE_STOP_STATE, 20))
418 			drm_err(&dev_priv->drm,
419 				"Date lane not in STOP state\n");
420 	}
421 
422 	/* Wait for AFE LATCH */
423 	for_each_dsi_port(port, intel_dsi->ports) {
424 		if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
425 					  AFE_LATCHOUT, 20))
426 			drm_err(&dev_priv->drm,
427 				"D-PHY not entering LP-11 state\n");
428 	}
429 }
430 
431 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
432 {
433 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
434 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
435 	enum port port;
436 	u32 val;
437 
438 	drm_dbg_kms(&dev_priv->drm, "\n");
439 
440 	/* Enable MIPI PHY transparent latch */
441 	for_each_dsi_port(port, intel_dsi->ports) {
442 		intel_de_rmw(dev_priv, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD);
443 		usleep_range(2000, 2500);
444 	}
445 
446 	/* Clear ULPS and set device ready */
447 	for_each_dsi_port(port, intel_dsi->ports) {
448 		val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
449 		val &= ~ULPS_STATE_MASK;
450 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
451 		usleep_range(2000, 2500);
452 		val |= DEVICE_READY;
453 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
454 	}
455 }
456 
457 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
458 {
459 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
460 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
461 	enum port port;
462 
463 	drm_dbg_kms(&dev_priv->drm, "\n");
464 
465 	vlv_flisdsi_get(dev_priv);
466 	/* program rcomp for compliance, reduce from 50 ohms to 45 ohms
467 	 * needed everytime after power gate */
468 	vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
469 	vlv_flisdsi_put(dev_priv);
470 
471 	/* bandgap reset is needed after everytime we do power gate */
472 	band_gap_reset(dev_priv);
473 
474 	for_each_dsi_port(port, intel_dsi->ports) {
475 
476 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
477 			       ULPS_STATE_ENTER);
478 		usleep_range(2500, 3000);
479 
480 		/* Enable MIPI PHY transparent latch
481 		 * Common bit for both MIPI Port A & MIPI Port C
482 		 * No similar bit in MIPI Port C reg
483 		 */
484 		intel_de_rmw(dev_priv, MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);
485 		usleep_range(1000, 1500);
486 
487 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
488 			       ULPS_STATE_EXIT);
489 		usleep_range(2500, 3000);
490 
491 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
492 			       DEVICE_READY);
493 		usleep_range(2500, 3000);
494 	}
495 }
496 
497 static void intel_dsi_device_ready(struct intel_encoder *encoder)
498 {
499 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
500 
501 	if (IS_GEMINILAKE(dev_priv))
502 		glk_dsi_device_ready(encoder);
503 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
504 		bxt_dsi_device_ready(encoder);
505 	else
506 		vlv_dsi_device_ready(encoder);
507 }
508 
509 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
510 {
511 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
512 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
513 	enum port port;
514 
515 	/* Enter ULPS */
516 	for_each_dsi_port(port, intel_dsi->ports)
517 		intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
518 			     ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
519 
520 	/* Wait for MIPI PHY status bit to unset */
521 	for_each_dsi_port(port, intel_dsi->ports) {
522 		if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
523 					    GLK_PHY_STATUS_PORT_READY, 20))
524 			drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
525 	}
526 
527 	/* Wait for Pwr ACK bit to unset */
528 	for_each_dsi_port(port, intel_dsi->ports) {
529 		if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
530 					    GLK_MIPIIO_PORT_POWERED, 20))
531 			drm_err(&dev_priv->drm,
532 				"MIPI IO Port is not powergated\n");
533 	}
534 }
535 
536 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
537 {
538 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
539 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
540 	enum port port;
541 
542 	/* Put the IO into reset */
543 	intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
544 
545 	/* Wait for MIPI PHY status bit to unset */
546 	for_each_dsi_port(port, intel_dsi->ports) {
547 		if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
548 					    GLK_PHY_STATUS_PORT_READY, 20))
549 			drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
550 	}
551 
552 	/* Clear MIPI mode */
553 	for_each_dsi_port(port, intel_dsi->ports)
554 		intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_ENABLE, 0);
555 }
556 
557 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
558 {
559 	glk_dsi_enter_low_power_mode(encoder);
560 	glk_dsi_disable_mipi_io(encoder);
561 }
562 
563 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
564 {
565 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
566 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
567 	enum port port;
568 
569 	drm_dbg_kms(&dev_priv->drm, "\n");
570 	for_each_dsi_port(port, intel_dsi->ports) {
571 		/* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
572 		i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
573 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
574 
575 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
576 			       DEVICE_READY | ULPS_STATE_ENTER);
577 		usleep_range(2000, 2500);
578 
579 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
580 			       DEVICE_READY | ULPS_STATE_EXIT);
581 		usleep_range(2000, 2500);
582 
583 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
584 			       DEVICE_READY | ULPS_STATE_ENTER);
585 		usleep_range(2000, 2500);
586 
587 		/*
588 		 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
589 		 * Port A only. MIPI Port C has no similar bit for checking.
590 		 */
591 		if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) &&
592 		    intel_de_wait_for_clear(dev_priv, port_ctrl,
593 					    AFE_LATCHOUT, 30))
594 			drm_err(&dev_priv->drm, "DSI LP not going Low\n");
595 
596 		/* Disable MIPI PHY transparent latch */
597 		intel_de_rmw(dev_priv, port_ctrl, LP_OUTPUT_HOLD, 0);
598 		usleep_range(1000, 1500);
599 
600 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00);
601 		usleep_range(2000, 2500);
602 	}
603 }
604 
605 static void intel_dsi_port_enable(struct intel_encoder *encoder,
606 				  const struct intel_crtc_state *crtc_state)
607 {
608 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
609 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
610 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
611 	enum port port;
612 
613 	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
614 		u32 temp = intel_dsi->pixel_overlap;
615 
616 		if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
617 			for_each_dsi_port(port, intel_dsi->ports)
618 				intel_de_rmw(dev_priv, MIPI_CTRL(port),
619 					     BXT_PIXEL_OVERLAP_CNT_MASK,
620 					     temp << BXT_PIXEL_OVERLAP_CNT_SHIFT);
621 		} else {
622 			intel_de_rmw(dev_priv, VLV_CHICKEN_3,
623 				     PIXEL_OVERLAP_CNT_MASK,
624 				     temp << PIXEL_OVERLAP_CNT_SHIFT);
625 		}
626 	}
627 
628 	for_each_dsi_port(port, intel_dsi->ports) {
629 		i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
630 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
631 		u32 temp;
632 
633 		temp = intel_de_read(dev_priv, port_ctrl);
634 
635 		temp &= ~LANE_CONFIGURATION_MASK;
636 		temp &= ~DUAL_LINK_MODE_MASK;
637 
638 		if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
639 			temp |= (intel_dsi->dual_link - 1)
640 						<< DUAL_LINK_MODE_SHIFT;
641 			if (IS_BROXTON(dev_priv))
642 				temp |= LANE_CONFIGURATION_DUAL_LINK_A;
643 			else
644 				temp |= crtc->pipe ?
645 					LANE_CONFIGURATION_DUAL_LINK_B :
646 					LANE_CONFIGURATION_DUAL_LINK_A;
647 		}
648 
649 		if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
650 			temp |= DITHERING_ENABLE;
651 
652 		/* assert ip_tg_enable signal */
653 		intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE);
654 		intel_de_posting_read(dev_priv, port_ctrl);
655 	}
656 }
657 
658 static void intel_dsi_port_disable(struct intel_encoder *encoder)
659 {
660 	struct drm_device *dev = encoder->base.dev;
661 	struct drm_i915_private *dev_priv = to_i915(dev);
662 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
663 	enum port port;
664 
665 	for_each_dsi_port(port, intel_dsi->ports) {
666 		i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
667 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
668 
669 		/* de-assert ip_tg_enable signal */
670 		intel_de_rmw(dev_priv, port_ctrl, DPI_ENABLE, 0);
671 		intel_de_posting_read(dev_priv, port_ctrl);
672 	}
673 }
674 
675 static void intel_dsi_wait_panel_power_cycle(struct intel_dsi *intel_dsi)
676 {
677 	ktime_t panel_power_on_time;
678 	s64 panel_power_off_duration;
679 
680 	panel_power_on_time = ktime_get_boottime();
681 	panel_power_off_duration = ktime_ms_delta(panel_power_on_time,
682 						  intel_dsi->panel_power_off_time);
683 
684 	if (panel_power_off_duration < (s64)intel_dsi->panel_pwr_cycle_delay)
685 		msleep(intel_dsi->panel_pwr_cycle_delay - panel_power_off_duration);
686 }
687 
688 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
689 			      const struct intel_crtc_state *pipe_config);
690 static void intel_dsi_unprepare(struct intel_encoder *encoder);
691 
692 /*
693  * Panel enable/disable sequences from the VBT spec.
694  *
695  * Note the spec has AssertReset / DeassertReset swapped from their
696  * usual naming. We use the normal names to avoid confusion (so below
697  * they are swapped compared to the spec).
698  *
699  * Steps starting with MIPI refer to VBT sequences, note that for v2
700  * VBTs several steps which have a VBT in v2 are expected to be handled
701  * directly by the driver, by directly driving gpios for example.
702  *
703  * v2 video mode seq         v3 video mode seq         command mode seq
704  * - power on                - MIPIPanelPowerOn        - power on
705  * - wait t1+t2                                        - wait t1+t2
706  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
707  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
708  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
709  *                                                     - MIPITearOn
710  *                                                     - MIPIDisplayOn
711  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
712  * - MIPIDisplayOn           - MIPIDisplayOn
713  * - wait t5                                           - wait t5
714  * - backlight on            - MIPIBacklightOn         - backlight on
715  * ...                       ...                       ... issue mem cmds ...
716  * - backlight off           - MIPIBacklightOff        - backlight off
717  * - wait t6                                           - wait t6
718  * - MIPIDisplayOff
719  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
720  *                                                     - MIPITearOff
721  *                           - MIPIDisplayOff          - MIPIDisplayOff
722  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
723  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
724  * - wait t3                                           - wait t3
725  * - power off               - MIPIPanelPowerOff       - power off
726  * - wait t4                                           - wait t4
727  */
728 
729 /*
730  * DSI port enable has to be done before pipe and plane enable, so we do it in
731  * the pre_enable hook instead of the enable hook.
732  */
733 static void intel_dsi_pre_enable(struct intel_atomic_state *state,
734 				 struct intel_encoder *encoder,
735 				 const struct intel_crtc_state *pipe_config,
736 				 const struct drm_connector_state *conn_state)
737 {
738 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
739 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
740 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
741 	enum pipe pipe = crtc->pipe;
742 	enum port port;
743 	bool glk_cold_boot = false;
744 
745 	drm_dbg_kms(&dev_priv->drm, "\n");
746 
747 	intel_dsi_wait_panel_power_cycle(intel_dsi);
748 
749 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
750 
751 	/*
752 	 * The BIOS may leave the PLL in a wonky state where it doesn't
753 	 * lock. It needs to be fully powered down to fix it.
754 	 */
755 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
756 		bxt_dsi_pll_disable(encoder);
757 		bxt_dsi_pll_enable(encoder, pipe_config);
758 	} else {
759 		vlv_dsi_pll_disable(encoder);
760 		vlv_dsi_pll_enable(encoder, pipe_config);
761 	}
762 
763 	if (IS_BROXTON(dev_priv)) {
764 		/* Add MIPI IO reset programming for modeset */
765 		intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL);
766 
767 		/* Power up DSI regulator */
768 		intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
769 		intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0);
770 	}
771 
772 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
773 		/* Disable DPOunit clock gating, can stall pipe */
774 		intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv),
775 			     0, DPOUNIT_CLOCK_GATE_DISABLE);
776 	}
777 
778 	if (!IS_GEMINILAKE(dev_priv))
779 		intel_dsi_prepare(encoder, pipe_config);
780 
781 	/* Give the panel time to power-on and then deassert its reset */
782 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
783 	msleep(intel_dsi->panel_on_delay);
784 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
785 
786 	if (IS_GEMINILAKE(dev_priv)) {
787 		glk_cold_boot = glk_dsi_enable_io(encoder);
788 
789 		/* Prepare port in cold boot(s3/s4) scenario */
790 		if (glk_cold_boot)
791 			intel_dsi_prepare(encoder, pipe_config);
792 	}
793 
794 	/* Put device in ready state (LP-11) */
795 	intel_dsi_device_ready(encoder);
796 
797 	/* Prepare port in normal boot scenario */
798 	if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
799 		intel_dsi_prepare(encoder, pipe_config);
800 
801 	/* Send initialization commands in LP mode */
802 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
803 
804 	/*
805 	 * Enable port in pre-enable phase itself because as per hw team
806 	 * recommendation, port should be enabled before plane & pipe
807 	 */
808 	if (is_cmd_mode(intel_dsi)) {
809 		for_each_dsi_port(port, intel_dsi->ports)
810 			intel_de_write(dev_priv,
811 				       MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
812 		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
813 		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
814 	} else {
815 		msleep(20); /* XXX */
816 		for_each_dsi_port(port, intel_dsi->ports)
817 			dpi_send_cmd(intel_dsi, TURN_ON, false, port);
818 		msleep(100);
819 
820 		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
821 
822 		intel_dsi_port_enable(encoder, pipe_config);
823 	}
824 
825 	intel_backlight_enable(pipe_config, conn_state);
826 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
827 }
828 
829 static void bxt_dsi_enable(struct intel_atomic_state *state,
830 			   struct intel_encoder *encoder,
831 			   const struct intel_crtc_state *crtc_state,
832 			   const struct drm_connector_state *conn_state)
833 {
834 	drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
835 
836 	intel_crtc_vblank_on(crtc_state);
837 }
838 
839 /*
840  * DSI port disable has to be done after pipe and plane disable, so we do it in
841  * the post_disable hook.
842  */
843 static void intel_dsi_disable(struct intel_atomic_state *state,
844 			      struct intel_encoder *encoder,
845 			      const struct intel_crtc_state *old_crtc_state,
846 			      const struct drm_connector_state *old_conn_state)
847 {
848 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
849 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
850 	enum port port;
851 
852 	drm_dbg_kms(&i915->drm, "\n");
853 
854 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
855 	intel_backlight_disable(old_conn_state);
856 
857 	/*
858 	 * According to the spec we should send SHUTDOWN before
859 	 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
860 	 * has shown that the v3 sequence works for v2 VBTs too
861 	 */
862 	if (is_vid_mode(intel_dsi)) {
863 		/* Send Shutdown command to the panel in LP mode */
864 		for_each_dsi_port(port, intel_dsi->ports)
865 			dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
866 		msleep(10);
867 	}
868 }
869 
870 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
871 {
872 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
873 
874 	if (IS_GEMINILAKE(dev_priv))
875 		glk_dsi_clear_device_ready(encoder);
876 	else
877 		vlv_dsi_clear_device_ready(encoder);
878 }
879 
880 static void intel_dsi_post_disable(struct intel_atomic_state *state,
881 				   struct intel_encoder *encoder,
882 				   const struct intel_crtc_state *old_crtc_state,
883 				   const struct drm_connector_state *old_conn_state)
884 {
885 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
886 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
887 	enum port port;
888 
889 	drm_dbg_kms(&dev_priv->drm, "\n");
890 
891 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
892 		intel_crtc_vblank_off(old_crtc_state);
893 
894 		skl_scaler_disable(old_crtc_state);
895 	}
896 
897 	if (is_vid_mode(intel_dsi)) {
898 		for_each_dsi_port(port, intel_dsi->ports)
899 			vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
900 
901 		intel_dsi_port_disable(encoder);
902 		usleep_range(2000, 5000);
903 	}
904 
905 	intel_dsi_unprepare(encoder);
906 
907 	/*
908 	 * if disable packets are sent before sending shutdown packet then in
909 	 * some next enable sequence send turn on packet error is observed
910 	 */
911 	if (is_cmd_mode(intel_dsi))
912 		intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
913 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
914 
915 	/* Transition to LP-00 */
916 	intel_dsi_clear_device_ready(encoder);
917 
918 	if (IS_BROXTON(dev_priv)) {
919 		/* Power down DSI regulator to save power */
920 		intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
921 		intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL,
922 			       HS_IO_CTRL_SELECT);
923 
924 		/* Add MIPI IO reset programming for modeset */
925 		intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0);
926 	}
927 
928 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
929 		bxt_dsi_pll_disable(encoder);
930 	} else {
931 		vlv_dsi_pll_disable(encoder);
932 
933 		intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv),
934 			     DPOUNIT_CLOCK_GATE_DISABLE, 0);
935 	}
936 
937 	/* Assert reset */
938 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
939 
940 	msleep(intel_dsi->panel_off_delay);
941 	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
942 
943 	intel_dsi->panel_power_off_time = ktime_get_boottime();
944 }
945 
946 static void intel_dsi_shutdown(struct intel_encoder *encoder)
947 {
948 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
949 
950 	intel_dsi_wait_panel_power_cycle(intel_dsi);
951 }
952 
953 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
954 				   enum pipe *pipe)
955 {
956 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
957 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
958 	intel_wakeref_t wakeref;
959 	enum port port;
960 	bool active = false;
961 
962 	drm_dbg_kms(&dev_priv->drm, "\n");
963 
964 	wakeref = intel_display_power_get_if_enabled(dev_priv,
965 						     encoder->power_domain);
966 	if (!wakeref)
967 		return false;
968 
969 	/*
970 	 * On Broxton the PLL needs to be enabled with a valid divider
971 	 * configuration, otherwise accessing DSI registers will hang the
972 	 * machine. See BSpec North Display Engine registers/MIPI[BXT].
973 	 */
974 	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
975 	    !bxt_dsi_pll_is_enabled(dev_priv))
976 		goto out_put_power;
977 
978 	/* XXX: this only works for one DSI output */
979 	for_each_dsi_port(port, intel_dsi->ports) {
980 		i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
981 			BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
982 		bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE;
983 
984 		/*
985 		 * Due to some hardware limitations on VLV/CHV, the DPI enable
986 		 * bit in port C control register does not get set. As a
987 		 * workaround, check pipe B conf instead.
988 		 */
989 		if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
990 		    port == PORT_C)
991 			enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
992 
993 		/* Try command mode if video mode not enabled */
994 		if (!enabled) {
995 			u32 tmp = intel_de_read(dev_priv,
996 						MIPI_DSI_FUNC_PRG(port));
997 			enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
998 		}
999 
1000 		if (!enabled)
1001 			continue;
1002 
1003 		if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
1004 			continue;
1005 
1006 		if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1007 			u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1008 			tmp &= BXT_PIPE_SELECT_MASK;
1009 			tmp >>= BXT_PIPE_SELECT_SHIFT;
1010 
1011 			if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C))
1012 				continue;
1013 
1014 			*pipe = tmp;
1015 		} else {
1016 			*pipe = port == PORT_A ? PIPE_A : PIPE_B;
1017 		}
1018 
1019 		active = true;
1020 		break;
1021 	}
1022 
1023 out_put_power:
1024 	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1025 
1026 	return active;
1027 }
1028 
1029 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1030 				    struct intel_crtc_state *pipe_config)
1031 {
1032 	struct drm_device *dev = encoder->base.dev;
1033 	struct drm_i915_private *dev_priv = to_i915(dev);
1034 	struct drm_display_mode *adjusted_mode =
1035 					&pipe_config->hw.adjusted_mode;
1036 	struct drm_display_mode *adjusted_mode_sw;
1037 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1038 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1039 	unsigned int lane_count = intel_dsi->lane_count;
1040 	unsigned int bpp, fmt;
1041 	enum port port;
1042 	u16 hactive, hfp, hsync, hbp, vfp, vsync;
1043 	u16 hfp_sw, hsync_sw, hbp_sw;
1044 	u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1045 				crtc_hblank_start_sw, crtc_hblank_end_sw;
1046 
1047 	/* FIXME: hw readout should not depend on SW state */
1048 	adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1049 
1050 	/*
1051 	 * Atleast one port is active as encoder->get_config called only if
1052 	 * encoder->get_hw_state() returns true.
1053 	 */
1054 	for_each_dsi_port(port, intel_dsi->ports) {
1055 		if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1056 			break;
1057 	}
1058 
1059 	fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1060 	bpp = mipi_dsi_pixel_format_to_bpp(
1061 			pixel_format_from_register_bits(fmt));
1062 
1063 	pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
1064 
1065 	/* Enable Frame time stamo based scanline reporting */
1066 	pipe_config->mode_flags |=
1067 		I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1068 
1069 	/* In terms of pixels */
1070 	adjusted_mode->crtc_hdisplay =
1071 				intel_de_read(dev_priv,
1072 				              BXT_MIPI_TRANS_HACTIVE(port));
1073 	adjusted_mode->crtc_vdisplay =
1074 				intel_de_read(dev_priv,
1075 				              BXT_MIPI_TRANS_VACTIVE(port));
1076 	adjusted_mode->crtc_vtotal =
1077 				intel_de_read(dev_priv,
1078 				              BXT_MIPI_TRANS_VTOTAL(port));
1079 
1080 	hactive = adjusted_mode->crtc_hdisplay;
1081 	hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port));
1082 
1083 	/*
1084 	 * Meaningful for video mode non-burst sync pulse mode only,
1085 	 * can be zero for non-burst sync events and burst modes
1086 	 */
1087 	hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port));
1088 	hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port));
1089 
1090 	/* harizontal values are in terms of high speed byte clock */
1091 	hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1092 						intel_dsi->burst_mode_ratio);
1093 	hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1094 						intel_dsi->burst_mode_ratio);
1095 	hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1096 						intel_dsi->burst_mode_ratio);
1097 
1098 	if (intel_dsi->dual_link) {
1099 		hfp *= 2;
1100 		hsync *= 2;
1101 		hbp *= 2;
1102 	}
1103 
1104 	/* vertical values are in terms of lines */
1105 	vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port));
1106 	vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port));
1107 
1108 	adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1109 	adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1110 	adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1111 	adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1112 	adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1113 
1114 	adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1115 	adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1116 	adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1117 	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1118 
1119 	/*
1120 	 * In BXT DSI there is no regs programmed with few horizontal timings
1121 	 * in Pixels but txbyteclkhs.. So retrieval process adds some
1122 	 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1123 	 * Actually here for the given adjusted_mode, we are calculating the
1124 	 * value programmed to the port and then back to the horizontal timing
1125 	 * param in pixels. This is the expected value, including roundup errors
1126 	 * And if that is same as retrieved value from port, then
1127 	 * (HW state) adjusted_mode's horizontal timings are corrected to
1128 	 * match with SW state to nullify the errors.
1129 	 */
1130 	/* Calculating the value programmed to the Port register */
1131 	hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1132 					adjusted_mode_sw->crtc_hdisplay;
1133 	hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1134 					adjusted_mode_sw->crtc_hsync_start;
1135 	hbp_sw = adjusted_mode_sw->crtc_htotal -
1136 					adjusted_mode_sw->crtc_hsync_end;
1137 
1138 	if (intel_dsi->dual_link) {
1139 		hfp_sw /= 2;
1140 		hsync_sw /= 2;
1141 		hbp_sw /= 2;
1142 	}
1143 
1144 	hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1145 						intel_dsi->burst_mode_ratio);
1146 	hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1147 			    intel_dsi->burst_mode_ratio);
1148 	hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1149 						intel_dsi->burst_mode_ratio);
1150 
1151 	/* Reverse calculating the adjusted mode parameters from port reg vals*/
1152 	hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1153 						intel_dsi->burst_mode_ratio);
1154 	hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1155 						intel_dsi->burst_mode_ratio);
1156 	hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1157 						intel_dsi->burst_mode_ratio);
1158 
1159 	if (intel_dsi->dual_link) {
1160 		hfp_sw *= 2;
1161 		hsync_sw *= 2;
1162 		hbp_sw *= 2;
1163 	}
1164 
1165 	crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1166 							hsync_sw + hbp_sw;
1167 	crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1168 	crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1169 	crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1170 	crtc_hblank_end_sw = crtc_htotal_sw;
1171 
1172 	if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1173 		adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1174 
1175 	if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1176 		adjusted_mode->crtc_hsync_start =
1177 					adjusted_mode_sw->crtc_hsync_start;
1178 
1179 	if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1180 		adjusted_mode->crtc_hsync_end =
1181 					adjusted_mode_sw->crtc_hsync_end;
1182 
1183 	if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1184 		adjusted_mode->crtc_hblank_start =
1185 					adjusted_mode_sw->crtc_hblank_start;
1186 
1187 	if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1188 		adjusted_mode->crtc_hblank_end =
1189 					adjusted_mode_sw->crtc_hblank_end;
1190 }
1191 
1192 static void intel_dsi_get_config(struct intel_encoder *encoder,
1193 				 struct intel_crtc_state *pipe_config)
1194 {
1195 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1196 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1197 	u32 pclk;
1198 
1199 	drm_dbg_kms(&dev_priv->drm, "\n");
1200 
1201 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1202 
1203 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1204 		bxt_dsi_get_pipe_config(encoder, pipe_config);
1205 		pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1206 	} else {
1207 		pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1208 	}
1209 
1210 	pipe_config->port_clock = pclk;
1211 
1212 	/* FIXME definitely not right for burst/cmd mode/pixel overlap */
1213 	pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1214 	if (intel_dsi->dual_link)
1215 		pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1216 }
1217 
1218 /* return txclkesc cycles in terms of divider and duration in us */
1219 static u16 txclkesc(u32 divider, unsigned int us)
1220 {
1221 	switch (divider) {
1222 	case ESCAPE_CLOCK_DIVIDER_1:
1223 	default:
1224 		return 20 * us;
1225 	case ESCAPE_CLOCK_DIVIDER_2:
1226 		return 10 * us;
1227 	case ESCAPE_CLOCK_DIVIDER_4:
1228 		return 5 * us;
1229 	}
1230 }
1231 
1232 static void set_dsi_timings(struct drm_encoder *encoder,
1233 			    const struct drm_display_mode *adjusted_mode)
1234 {
1235 	struct drm_device *dev = encoder->dev;
1236 	struct drm_i915_private *dev_priv = to_i915(dev);
1237 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1238 	enum port port;
1239 	unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1240 	unsigned int lane_count = intel_dsi->lane_count;
1241 
1242 	u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1243 
1244 	hactive = adjusted_mode->crtc_hdisplay;
1245 	hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1246 	hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1247 	hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1248 
1249 	if (intel_dsi->dual_link) {
1250 		hactive /= 2;
1251 		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1252 			hactive += intel_dsi->pixel_overlap;
1253 		hfp /= 2;
1254 		hsync /= 2;
1255 		hbp /= 2;
1256 	}
1257 
1258 	vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1259 	vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1260 	vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1261 
1262 	/* horizontal values are in terms of high speed byte clock */
1263 	hactive = txbyteclkhs(hactive, bpp, lane_count,
1264 			      intel_dsi->burst_mode_ratio);
1265 	hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1266 	hsync = txbyteclkhs(hsync, bpp, lane_count,
1267 			    intel_dsi->burst_mode_ratio);
1268 	hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1269 
1270 	for_each_dsi_port(port, intel_dsi->ports) {
1271 		if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1272 			/*
1273 			 * Program hdisplay and vdisplay on MIPI transcoder.
1274 			 * This is different from calculated hactive and
1275 			 * vactive, as they are calculated per channel basis,
1276 			 * whereas these values should be based on resolution.
1277 			 */
1278 			intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port),
1279 				       adjusted_mode->crtc_hdisplay);
1280 			intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port),
1281 				       adjusted_mode->crtc_vdisplay);
1282 			intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port),
1283 				       adjusted_mode->crtc_vtotal);
1284 		}
1285 
1286 		intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port),
1287 			       hactive);
1288 		intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp);
1289 
1290 		/* meaningful for video mode non-burst sync pulse mode only,
1291 		 * can be zero for non-burst sync events and burst modes */
1292 		intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port),
1293 			       hsync);
1294 		intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp);
1295 
1296 		/* vertical values are in terms of lines */
1297 		intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp);
1298 		intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port),
1299 			       vsync);
1300 		intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp);
1301 	}
1302 }
1303 
1304 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1305 {
1306 	switch (fmt) {
1307 	case MIPI_DSI_FMT_RGB888:
1308 		return VID_MODE_FORMAT_RGB888;
1309 	case MIPI_DSI_FMT_RGB666:
1310 		return VID_MODE_FORMAT_RGB666;
1311 	case MIPI_DSI_FMT_RGB666_PACKED:
1312 		return VID_MODE_FORMAT_RGB666_PACKED;
1313 	case MIPI_DSI_FMT_RGB565:
1314 		return VID_MODE_FORMAT_RGB565;
1315 	default:
1316 		MISSING_CASE(fmt);
1317 		return VID_MODE_FORMAT_RGB666;
1318 	}
1319 }
1320 
1321 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1322 			      const struct intel_crtc_state *pipe_config)
1323 {
1324 	struct drm_encoder *encoder = &intel_encoder->base;
1325 	struct drm_device *dev = encoder->dev;
1326 	struct drm_i915_private *dev_priv = to_i915(dev);
1327 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1328 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1329 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1330 	enum port port;
1331 	unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1332 	u32 val, tmp;
1333 	u16 mode_hdisplay;
1334 
1335 	drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe));
1336 
1337 	mode_hdisplay = adjusted_mode->crtc_hdisplay;
1338 
1339 	if (intel_dsi->dual_link) {
1340 		mode_hdisplay /= 2;
1341 		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1342 			mode_hdisplay += intel_dsi->pixel_overlap;
1343 	}
1344 
1345 	for_each_dsi_port(port, intel_dsi->ports) {
1346 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1347 			/*
1348 			 * escape clock divider, 20MHz, shared for A and C.
1349 			 * device ready must be off when doing this! txclkesc?
1350 			 */
1351 			tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
1352 			tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1353 			intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
1354 				       tmp | ESCAPE_CLOCK_DIVIDER_1);
1355 
1356 			/* read request priority is per pipe */
1357 			tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1358 			tmp &= ~READ_REQUEST_PRIORITY_MASK;
1359 			intel_de_write(dev_priv, MIPI_CTRL(port),
1360 				       tmp | READ_REQUEST_PRIORITY_HIGH);
1361 		} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1362 			enum pipe pipe = crtc->pipe;
1363 
1364 			intel_de_rmw(dev_priv, MIPI_CTRL(port),
1365 				     BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe));
1366 		}
1367 
1368 		/* XXX: why here, why like this? handling in irq handler?! */
1369 		intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff);
1370 		intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff);
1371 
1372 		intel_de_write(dev_priv, MIPI_DPHY_PARAM(port),
1373 			       intel_dsi->dphy_reg);
1374 
1375 		intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port),
1376 			       adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1377 	}
1378 
1379 	set_dsi_timings(encoder, adjusted_mode);
1380 
1381 	val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1382 	if (is_cmd_mode(intel_dsi)) {
1383 		val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1384 		val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1385 	} else {
1386 		val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1387 		val |= pixel_format_to_reg(intel_dsi->pixel_format);
1388 	}
1389 
1390 	tmp = 0;
1391 	if (intel_dsi->eotp_pkt == 0)
1392 		tmp |= EOT_DISABLE;
1393 	if (intel_dsi->clock_stop)
1394 		tmp |= CLOCKSTOP;
1395 
1396 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1397 		tmp |= BXT_DPHY_DEFEATURE_EN;
1398 		if (!is_cmd_mode(intel_dsi))
1399 			tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1400 	}
1401 
1402 	for_each_dsi_port(port, intel_dsi->ports) {
1403 		intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1404 
1405 		/* timeouts for recovery. one frame IIUC. if counter expires,
1406 		 * EOT and stop state. */
1407 
1408 		/*
1409 		 * In burst mode, value greater than one DPI line Time in byte
1410 		 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1411 		 * said value is recommended.
1412 		 *
1413 		 * In non-burst mode, Value greater than one DPI frame time in
1414 		 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1415 		 * said value is recommended.
1416 		 *
1417 		 * In DBI only mode, value greater than one DBI frame time in
1418 		 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1419 		 * said value is recommended.
1420 		 */
1421 
1422 		if (is_vid_mode(intel_dsi) &&
1423 			intel_dsi->video_mode == BURST_MODE) {
1424 			intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1425 				       txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1426 		} else {
1427 			intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1428 				       txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1429 		}
1430 		intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port),
1431 			       intel_dsi->lp_rx_timeout);
1432 		intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port),
1433 			       intel_dsi->turn_arnd_val);
1434 		intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port),
1435 			       intel_dsi->rst_timer_val);
1436 
1437 		/* dphy stuff */
1438 
1439 		/* in terms of low power clock */
1440 		intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1441 			       txclkesc(intel_dsi->escape_clk_div, 100));
1442 
1443 		if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1444 		    !intel_dsi->dual_link) {
1445 			/*
1446 			 * BXT spec says write MIPI_INIT_COUNT for
1447 			 * both the ports, even if only one is
1448 			 * getting used. So write the other port
1449 			 * if not in dual link mode.
1450 			 */
1451 			intel_de_write(dev_priv,
1452 				       MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A),
1453 				       intel_dsi->init_count);
1454 		}
1455 
1456 		/* recovery disables */
1457 		intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp);
1458 
1459 		/* in terms of low power clock */
1460 		intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1461 			       intel_dsi->init_count);
1462 
1463 		/* in terms of txbyteclkhs. actual high to low switch +
1464 		 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1465 		 *
1466 		 * XXX: write MIPI_STOP_STATE_STALL?
1467 		 */
1468 		intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port),
1469 			       intel_dsi->hs_to_lp_count);
1470 
1471 		/* XXX: low power clock equivalence in terms of byte clock.
1472 		 * the number of byte clocks occupied in one low power clock.
1473 		 * based on txbyteclkhs and txclkesc.
1474 		 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1475 		 * ) / 105.???
1476 		 */
1477 		intel_de_write(dev_priv, MIPI_LP_BYTECLK(port),
1478 			       intel_dsi->lp_byte_clk);
1479 
1480 		if (IS_GEMINILAKE(dev_priv)) {
1481 			intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port),
1482 				       intel_dsi->lp_byte_clk);
1483 			/* Shadow of DPHY reg */
1484 			intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port),
1485 				       intel_dsi->dphy_reg);
1486 		}
1487 
1488 		/* the bw essential for transmitting 16 long packets containing
1489 		 * 252 bytes meant for dcs write memory command is programmed in
1490 		 * this register in terms of byte clocks. based on dsi transfer
1491 		 * rate and the number of lanes configured the time taken to
1492 		 * transmit 16 long packets in a dsi stream varies. */
1493 		intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port),
1494 			       intel_dsi->bw_timer);
1495 
1496 		intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1497 			       intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1498 
1499 		if (is_vid_mode(intel_dsi)) {
1500 			u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG;
1501 
1502 			/*
1503 			 * Some panels might have resolution which is not a
1504 			 * multiple of 64 like 1366 x 768. Enable RANDOM
1505 			 * resolution support for such panels by default.
1506 			 */
1507 			fmt |= RANDOM_DPI_DISPLAY_RESOLUTION;
1508 
1509 			switch (intel_dsi->video_mode) {
1510 			default:
1511 				MISSING_CASE(intel_dsi->video_mode);
1512 				fallthrough;
1513 			case NON_BURST_SYNC_EVENTS:
1514 				fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS;
1515 				break;
1516 			case NON_BURST_SYNC_PULSE:
1517 				fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE;
1518 				break;
1519 			case BURST_MODE:
1520 				fmt |= VIDEO_MODE_BURST;
1521 				break;
1522 			}
1523 
1524 			intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt);
1525 		}
1526 	}
1527 }
1528 
1529 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1530 {
1531 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1532 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1533 	enum port port;
1534 
1535 	if (IS_GEMINILAKE(dev_priv))
1536 		return;
1537 
1538 	for_each_dsi_port(port, intel_dsi->ports) {
1539 		/* Panel commands can be sent when clock is in LP11 */
1540 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0);
1541 
1542 		if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1543 			bxt_dsi_reset_clocks(encoder, port);
1544 		else
1545 			vlv_dsi_reset_clocks(encoder, port);
1546 		intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
1547 
1548 		intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(port), VID_MODE_FORMAT_MASK, 0);
1549 
1550 		intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1);
1551 	}
1552 }
1553 
1554 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1555 {
1556 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1557 
1558 	intel_dsi_vbt_gpio_cleanup(intel_dsi);
1559 	intel_encoder_destroy(encoder);
1560 }
1561 
1562 static const struct drm_encoder_funcs intel_dsi_funcs = {
1563 	.destroy = intel_dsi_encoder_destroy,
1564 };
1565 
1566 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1567 	.get_modes = intel_dsi_get_modes,
1568 	.mode_valid = intel_dsi_mode_valid,
1569 	.atomic_check = intel_digital_connector_atomic_check,
1570 };
1571 
1572 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1573 	.detect = intel_panel_detect,
1574 	.late_register = intel_connector_register,
1575 	.early_unregister = intel_connector_unregister,
1576 	.destroy = intel_connector_destroy,
1577 	.fill_modes = drm_helper_probe_single_connector_modes,
1578 	.atomic_get_property = intel_digital_connector_atomic_get_property,
1579 	.atomic_set_property = intel_digital_connector_atomic_set_property,
1580 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1581 	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
1582 };
1583 
1584 static void vlv_dsi_add_properties(struct intel_connector *connector)
1585 {
1586 	const struct drm_display_mode *fixed_mode =
1587 		intel_panel_preferred_fixed_mode(connector);
1588 
1589 	intel_attach_scaling_mode_property(&connector->base);
1590 
1591 	drm_connector_set_panel_orientation_with_quirk(&connector->base,
1592 						       intel_dsi_get_panel_orientation(connector),
1593 						       fixed_mode->hdisplay,
1594 						       fixed_mode->vdisplay);
1595 }
1596 
1597 #define NS_KHZ_RATIO		1000000
1598 
1599 #define PREPARE_CNT_MAX		0x3F
1600 #define EXIT_ZERO_CNT_MAX	0x3F
1601 #define CLK_ZERO_CNT_MAX	0xFF
1602 #define TRAIL_CNT_MAX		0x1F
1603 
1604 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1605 {
1606 	struct drm_device *dev = intel_dsi->base.base.dev;
1607 	struct drm_i915_private *dev_priv = to_i915(dev);
1608 	struct intel_connector *connector = intel_dsi->attached_connector;
1609 	struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1610 	u32 tlpx_ns, extra_byte_count, tlpx_ui;
1611 	u32 ui_num, ui_den;
1612 	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1613 	u32 ths_prepare_ns, tclk_trail_ns;
1614 	u32 tclk_prepare_clkzero, ths_prepare_hszero;
1615 	u32 lp_to_hs_switch, hs_to_lp_switch;
1616 	u32 mul;
1617 
1618 	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1619 
1620 	switch (intel_dsi->lane_count) {
1621 	case 1:
1622 	case 2:
1623 		extra_byte_count = 2;
1624 		break;
1625 	case 3:
1626 		extra_byte_count = 4;
1627 		break;
1628 	case 4:
1629 	default:
1630 		extra_byte_count = 3;
1631 		break;
1632 	}
1633 
1634 	/* in Kbps */
1635 	ui_num = NS_KHZ_RATIO;
1636 	ui_den = intel_dsi_bitrate(intel_dsi);
1637 
1638 	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1639 	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1640 
1641 	/*
1642 	 * B060
1643 	 * LP byte clock = TLPX/ (8UI)
1644 	 */
1645 	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1646 
1647 	/* DDR clock period = 2 * UI
1648 	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1649 	 * UI(nsec) = 10^6 / bitrate
1650 	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1651 	 * DDR clock count  = ns_value / DDR clock period
1652 	 *
1653 	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
1654 	 * HS byte clock count for other platform in HS ddr clock count
1655 	 */
1656 	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1657 	ths_prepare_ns = max(mipi_config->ths_prepare,
1658 			     mipi_config->tclk_prepare);
1659 
1660 	/* prepare count */
1661 	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1662 
1663 	if (prepare_cnt > PREPARE_CNT_MAX) {
1664 		drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",
1665 			    prepare_cnt);
1666 		prepare_cnt = PREPARE_CNT_MAX;
1667 	}
1668 
1669 	/* exit zero count */
1670 	exit_zero_cnt = DIV_ROUND_UP(
1671 				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
1672 				ui_num * mul
1673 				);
1674 
1675 	/*
1676 	 * Exit zero is unified val ths_zero and ths_exit
1677 	 * minimum value for ths_exit = 110ns
1678 	 * min (exit_zero_cnt * 2) = 110/UI
1679 	 * exit_zero_cnt = 55/UI
1680 	 */
1681 	if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1682 		exit_zero_cnt += 1;
1683 
1684 	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1685 		drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",
1686 			    exit_zero_cnt);
1687 		exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1688 	}
1689 
1690 	/* clk zero count */
1691 	clk_zero_cnt = DIV_ROUND_UP(
1692 				(tclk_prepare_clkzero -	ths_prepare_ns)
1693 				* ui_den, ui_num * mul);
1694 
1695 	if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1696 		drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",
1697 			    clk_zero_cnt);
1698 		clk_zero_cnt = CLK_ZERO_CNT_MAX;
1699 	}
1700 
1701 	/* trail count */
1702 	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1703 	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1704 
1705 	if (trail_cnt > TRAIL_CNT_MAX) {
1706 		drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",
1707 			    trail_cnt);
1708 		trail_cnt = TRAIL_CNT_MAX;
1709 	}
1710 
1711 	/* B080 */
1712 	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1713 						clk_zero_cnt << 8 | prepare_cnt;
1714 
1715 	/*
1716 	 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1717 	 *					mul + 10UI + Extra Byte Count
1718 	 *
1719 	 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1720 	 * Extra Byte Count is calculated according to number of lanes.
1721 	 * High Low Switch Count is the Max of LP to HS and
1722 	 * HS to LP switch count
1723 	 *
1724 	 */
1725 	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1726 
1727 	/* B044 */
1728 	/* FIXME:
1729 	 * The comment above does not match with the code */
1730 	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1731 						exit_zero_cnt * mul + 10, 8);
1732 
1733 	hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1734 
1735 	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1736 	intel_dsi->hs_to_lp_count += extra_byte_count;
1737 
1738 	/* B088 */
1739 	/* LP -> HS for clock lanes
1740 	 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1741 	 *						extra byte count
1742 	 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1743 	 *					2(in UI) + extra byte count
1744 	 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1745 	 *					8 + extra byte count
1746 	 */
1747 	intel_dsi->clk_lp_to_hs_count =
1748 		DIV_ROUND_UP(
1749 			4 * tlpx_ui + prepare_cnt * 2 +
1750 			clk_zero_cnt * 2,
1751 			8);
1752 
1753 	intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1754 
1755 	/* HS->LP for Clock Lanes
1756 	 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1757 	 *						Extra byte count
1758 	 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1759 	 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1760 	 *						Extra byte count
1761 	 */
1762 	intel_dsi->clk_hs_to_lp_count =
1763 		DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1764 			8);
1765 	intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1766 
1767 	intel_dsi_log_params(intel_dsi);
1768 }
1769 
1770 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1771 {
1772 	struct intel_dsi *intel_dsi;
1773 	struct intel_encoder *intel_encoder;
1774 	struct drm_encoder *encoder;
1775 	struct intel_connector *intel_connector;
1776 	struct drm_connector *connector;
1777 	struct drm_display_mode *current_mode;
1778 	enum port port;
1779 	enum pipe pipe;
1780 
1781 	drm_dbg_kms(&dev_priv->drm, "\n");
1782 
1783 	/* There is no detection method for MIPI so rely on VBT */
1784 	if (!intel_bios_is_dsi_present(dev_priv, &port))
1785 		return;
1786 
1787 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1788 		dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;
1789 	else
1790 		dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;
1791 
1792 	intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1793 	if (!intel_dsi)
1794 		return;
1795 
1796 	intel_connector = intel_connector_alloc();
1797 	if (!intel_connector) {
1798 		kfree(intel_dsi);
1799 		return;
1800 	}
1801 
1802 	intel_encoder = &intel_dsi->base;
1803 	encoder = &intel_encoder->base;
1804 	intel_dsi->attached_connector = intel_connector;
1805 
1806 	connector = &intel_connector->base;
1807 
1808 	drm_encoder_init(&dev_priv->drm, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1809 			 "DSI %c", port_name(port));
1810 
1811 	intel_encoder->compute_config = intel_dsi_compute_config;
1812 	intel_encoder->pre_enable = intel_dsi_pre_enable;
1813 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1814 		intel_encoder->enable = bxt_dsi_enable;
1815 	intel_encoder->disable = intel_dsi_disable;
1816 	intel_encoder->post_disable = intel_dsi_post_disable;
1817 	intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1818 	intel_encoder->get_config = intel_dsi_get_config;
1819 	intel_encoder->update_pipe = intel_backlight_update;
1820 	intel_encoder->shutdown = intel_dsi_shutdown;
1821 
1822 	intel_connector->get_hw_state = intel_connector_get_hw_state;
1823 
1824 	intel_encoder->port = port;
1825 	intel_encoder->type = INTEL_OUTPUT_DSI;
1826 	intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1827 	intel_encoder->cloneable = 0;
1828 
1829 	/*
1830 	 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1831 	 * port C. BXT isn't limited like this.
1832 	 */
1833 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1834 		intel_encoder->pipe_mask = ~0;
1835 	else if (port == PORT_A)
1836 		intel_encoder->pipe_mask = BIT(PIPE_A);
1837 	else
1838 		intel_encoder->pipe_mask = BIT(PIPE_B);
1839 
1840 	intel_dsi->panel_power_off_time = ktime_get_boottime();
1841 
1842 	intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL, NULL);
1843 
1844 	if (intel_connector->panel.vbt.dsi.config->dual_link)
1845 		intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1846 	else
1847 		intel_dsi->ports = BIT(port);
1848 
1849 	if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
1850 		intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
1851 
1852 	if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
1853 		intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
1854 
1855 	/* Create a DSI host (and a device) for each port. */
1856 	for_each_dsi_port(port, intel_dsi->ports) {
1857 		struct intel_dsi_host *host;
1858 
1859 		host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1860 					   port);
1861 		if (!host)
1862 			goto err;
1863 
1864 		intel_dsi->dsi_hosts[port] = host;
1865 	}
1866 
1867 	if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1868 		drm_dbg_kms(&dev_priv->drm, "no device found\n");
1869 		goto err;
1870 	}
1871 
1872 	/* Use clock read-back from current hw-state for fastboot */
1873 	current_mode = intel_encoder_current_mode(intel_encoder);
1874 	if (current_mode) {
1875 		drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",
1876 			    intel_dsi->pclk, current_mode->clock);
1877 		if (intel_fuzzy_clock_check(intel_dsi->pclk,
1878 					    current_mode->clock)) {
1879 			drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n");
1880 			intel_dsi->pclk = current_mode->clock;
1881 		}
1882 
1883 		kfree(current_mode);
1884 	}
1885 
1886 	vlv_dphy_param_init(intel_dsi);
1887 
1888 	intel_dsi_vbt_gpio_init(intel_dsi,
1889 				intel_dsi_get_hw_state(intel_encoder, &pipe));
1890 
1891 	drm_connector_init(&dev_priv->drm, connector, &intel_dsi_connector_funcs,
1892 			   DRM_MODE_CONNECTOR_DSI);
1893 
1894 	drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1895 
1896 	connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1897 
1898 	intel_connector_attach_encoder(intel_connector, intel_encoder);
1899 
1900 	mutex_lock(&dev_priv->drm.mode_config.mutex);
1901 	intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
1902 	mutex_unlock(&dev_priv->drm.mode_config.mutex);
1903 
1904 	if (!intel_panel_preferred_fixed_mode(intel_connector)) {
1905 		drm_dbg_kms(&dev_priv->drm, "no fixed mode\n");
1906 		goto err_cleanup_connector;
1907 	}
1908 
1909 	intel_panel_init(intel_connector, NULL);
1910 
1911 	intel_backlight_setup(intel_connector, INVALID_PIPE);
1912 
1913 	vlv_dsi_add_properties(intel_connector);
1914 
1915 	return;
1916 
1917 err_cleanup_connector:
1918 	drm_connector_cleanup(&intel_connector->base);
1919 err:
1920 	drm_encoder_cleanup(&intel_encoder->base);
1921 	kfree(intel_dsi);
1922 	kfree(intel_connector);
1923 }
1924