1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <drm/drm_blend.h> 7 8 #include "i915_drv.h" 9 #include "i915_fixed.h" 10 #include "i915_reg.h" 11 #include "i9xx_wm.h" 12 #include "intel_atomic.h" 13 #include "intel_atomic_plane.h" 14 #include "intel_bw.h" 15 #include "intel_crtc.h" 16 #include "intel_de.h" 17 #include "intel_display.h" 18 #include "intel_display_power.h" 19 #include "intel_display_types.h" 20 #include "intel_fb.h" 21 #include "intel_pcode.h" 22 #include "intel_wm.h" 23 #include "skl_watermark.h" 24 25 static void skl_sagv_disable(struct drm_i915_private *i915); 26 27 /* Stores plane specific WM parameters */ 28 struct skl_wm_params { 29 bool x_tiled, y_tiled; 30 bool rc_surface; 31 bool is_planar; 32 u32 width; 33 u8 cpp; 34 u32 plane_pixel_rate; 35 u32 y_min_scanlines; 36 u32 plane_bytes_per_line; 37 uint_fixed_16_16_t plane_blocks_per_line; 38 uint_fixed_16_16_t y_tile_minimum; 39 u32 linetime_us; 40 u32 dbuf_block_size; 41 }; 42 43 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915) 44 { 45 u8 enabled_slices = 0; 46 enum dbuf_slice slice; 47 48 for_each_dbuf_slice(i915, slice) { 49 if (intel_de_read(i915, DBUF_CTL_S(slice)) & DBUF_POWER_STATE) 50 enabled_slices |= BIT(slice); 51 } 52 53 return enabled_slices; 54 } 55 56 /* 57 * FIXME: We still don't have the proper code detect if we need to apply the WA, 58 * so assume we'll always need it in order to avoid underruns. 59 */ 60 static bool skl_needs_memory_bw_wa(struct drm_i915_private *i915) 61 { 62 return DISPLAY_VER(i915) == 9; 63 } 64 65 static bool 66 intel_has_sagv(struct drm_i915_private *i915) 67 { 68 return HAS_SAGV(i915) && 69 i915->display.sagv.status != I915_SAGV_NOT_CONTROLLED; 70 } 71 72 static u32 73 intel_sagv_block_time(struct drm_i915_private *i915) 74 { 75 if (DISPLAY_VER(i915) >= 14) { 76 u32 val; 77 78 val = intel_de_read(i915, MTL_LATENCY_SAGV); 79 80 return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val); 81 } else if (DISPLAY_VER(i915) >= 12) { 82 u32 val = 0; 83 int ret; 84 85 ret = snb_pcode_read(&i915->uncore, 86 GEN12_PCODE_READ_SAGV_BLOCK_TIME_US, 87 &val, NULL); 88 if (ret) { 89 drm_dbg_kms(&i915->drm, "Couldn't read SAGV block time!\n"); 90 return 0; 91 } 92 93 return val; 94 } else if (DISPLAY_VER(i915) == 11) { 95 return 10; 96 } else if (HAS_SAGV(i915)) { 97 return 30; 98 } else { 99 return 0; 100 } 101 } 102 103 static void intel_sagv_init(struct drm_i915_private *i915) 104 { 105 if (!HAS_SAGV(i915)) 106 i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED; 107 108 /* 109 * Probe to see if we have working SAGV control. 110 * For icl+ this was already determined by intel_bw_init_hw(). 111 */ 112 if (DISPLAY_VER(i915) < 11) 113 skl_sagv_disable(i915); 114 115 drm_WARN_ON(&i915->drm, i915->display.sagv.status == I915_SAGV_UNKNOWN); 116 117 i915->display.sagv.block_time_us = intel_sagv_block_time(i915); 118 119 drm_dbg_kms(&i915->drm, "SAGV supported: %s, original SAGV block time: %u us\n", 120 str_yes_no(intel_has_sagv(i915)), i915->display.sagv.block_time_us); 121 122 /* avoid overflow when adding with wm0 latency/etc. */ 123 if (drm_WARN(&i915->drm, i915->display.sagv.block_time_us > U16_MAX, 124 "Excessive SAGV block time %u, ignoring\n", 125 i915->display.sagv.block_time_us)) 126 i915->display.sagv.block_time_us = 0; 127 128 if (!intel_has_sagv(i915)) 129 i915->display.sagv.block_time_us = 0; 130 } 131 132 /* 133 * SAGV dynamically adjusts the system agent voltage and clock frequencies 134 * depending on power and performance requirements. The display engine access 135 * to system memory is blocked during the adjustment time. Because of the 136 * blocking time, having this enabled can cause full system hangs and/or pipe 137 * underruns if we don't meet all of the following requirements: 138 * 139 * - <= 1 pipe enabled 140 * - All planes can enable watermarks for latencies >= SAGV engine block time 141 * - We're not using an interlaced display configuration 142 */ 143 static void skl_sagv_enable(struct drm_i915_private *i915) 144 { 145 int ret; 146 147 if (!intel_has_sagv(i915)) 148 return; 149 150 if (i915->display.sagv.status == I915_SAGV_ENABLED) 151 return; 152 153 drm_dbg_kms(&i915->drm, "Enabling SAGV\n"); 154 ret = snb_pcode_write(&i915->uncore, GEN9_PCODE_SAGV_CONTROL, 155 GEN9_SAGV_ENABLE); 156 157 /* We don't need to wait for SAGV when enabling */ 158 159 /* 160 * Some skl systems, pre-release machines in particular, 161 * don't actually have SAGV. 162 */ 163 if (IS_SKYLAKE(i915) && ret == -ENXIO) { 164 drm_dbg(&i915->drm, "No SAGV found on system, ignoring\n"); 165 i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED; 166 return; 167 } else if (ret < 0) { 168 drm_err(&i915->drm, "Failed to enable SAGV\n"); 169 return; 170 } 171 172 i915->display.sagv.status = I915_SAGV_ENABLED; 173 } 174 175 static void skl_sagv_disable(struct drm_i915_private *i915) 176 { 177 int ret; 178 179 if (!intel_has_sagv(i915)) 180 return; 181 182 if (i915->display.sagv.status == I915_SAGV_DISABLED) 183 return; 184 185 drm_dbg_kms(&i915->drm, "Disabling SAGV\n"); 186 /* bspec says to keep retrying for at least 1 ms */ 187 ret = skl_pcode_request(&i915->uncore, GEN9_PCODE_SAGV_CONTROL, 188 GEN9_SAGV_DISABLE, 189 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, 190 1); 191 /* 192 * Some skl systems, pre-release machines in particular, 193 * don't actually have SAGV. 194 */ 195 if (IS_SKYLAKE(i915) && ret == -ENXIO) { 196 drm_dbg(&i915->drm, "No SAGV found on system, ignoring\n"); 197 i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED; 198 return; 199 } else if (ret < 0) { 200 drm_err(&i915->drm, "Failed to disable SAGV (%d)\n", ret); 201 return; 202 } 203 204 i915->display.sagv.status = I915_SAGV_DISABLED; 205 } 206 207 static void skl_sagv_pre_plane_update(struct intel_atomic_state *state) 208 { 209 struct drm_i915_private *i915 = to_i915(state->base.dev); 210 const struct intel_bw_state *new_bw_state = 211 intel_atomic_get_new_bw_state(state); 212 213 if (!new_bw_state) 214 return; 215 216 if (!intel_can_enable_sagv(i915, new_bw_state)) 217 skl_sagv_disable(i915); 218 } 219 220 static void skl_sagv_post_plane_update(struct intel_atomic_state *state) 221 { 222 struct drm_i915_private *i915 = to_i915(state->base.dev); 223 const struct intel_bw_state *new_bw_state = 224 intel_atomic_get_new_bw_state(state); 225 226 if (!new_bw_state) 227 return; 228 229 if (intel_can_enable_sagv(i915, new_bw_state)) 230 skl_sagv_enable(i915); 231 } 232 233 static void icl_sagv_pre_plane_update(struct intel_atomic_state *state) 234 { 235 struct drm_i915_private *i915 = to_i915(state->base.dev); 236 const struct intel_bw_state *old_bw_state = 237 intel_atomic_get_old_bw_state(state); 238 const struct intel_bw_state *new_bw_state = 239 intel_atomic_get_new_bw_state(state); 240 u16 old_mask, new_mask; 241 242 if (!new_bw_state) 243 return; 244 245 old_mask = old_bw_state->qgv_points_mask; 246 new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask; 247 248 if (old_mask == new_mask) 249 return; 250 251 WARN_ON(!new_bw_state->base.changed); 252 253 drm_dbg_kms(&i915->drm, "Restricting QGV points: 0x%x -> 0x%x\n", 254 old_mask, new_mask); 255 256 /* 257 * Restrict required qgv points before updating the configuration. 258 * According to BSpec we can't mask and unmask qgv points at the same 259 * time. Also masking should be done before updating the configuration 260 * and unmasking afterwards. 261 */ 262 icl_pcode_restrict_qgv_points(i915, new_mask); 263 } 264 265 static void icl_sagv_post_plane_update(struct intel_atomic_state *state) 266 { 267 struct drm_i915_private *i915 = to_i915(state->base.dev); 268 const struct intel_bw_state *old_bw_state = 269 intel_atomic_get_old_bw_state(state); 270 const struct intel_bw_state *new_bw_state = 271 intel_atomic_get_new_bw_state(state); 272 u16 old_mask, new_mask; 273 274 if (!new_bw_state) 275 return; 276 277 old_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask; 278 new_mask = new_bw_state->qgv_points_mask; 279 280 if (old_mask == new_mask) 281 return; 282 283 WARN_ON(!new_bw_state->base.changed); 284 285 drm_dbg_kms(&i915->drm, "Relaxing QGV points: 0x%x -> 0x%x\n", 286 old_mask, new_mask); 287 288 /* 289 * Allow required qgv points after updating the configuration. 290 * According to BSpec we can't mask and unmask qgv points at the same 291 * time. Also masking should be done before updating the configuration 292 * and unmasking afterwards. 293 */ 294 icl_pcode_restrict_qgv_points(i915, new_mask); 295 } 296 297 void intel_sagv_pre_plane_update(struct intel_atomic_state *state) 298 { 299 struct drm_i915_private *i915 = to_i915(state->base.dev); 300 301 /* 302 * Just return if we can't control SAGV or don't have it. 303 * This is different from situation when we have SAGV but just can't 304 * afford it due to DBuf limitation - in case if SAGV is completely 305 * disabled in a BIOS, we are not even allowed to send a PCode request, 306 * as it will throw an error. So have to check it here. 307 */ 308 if (!intel_has_sagv(i915)) 309 return; 310 311 if (DISPLAY_VER(i915) >= 11) 312 icl_sagv_pre_plane_update(state); 313 else 314 skl_sagv_pre_plane_update(state); 315 } 316 317 void intel_sagv_post_plane_update(struct intel_atomic_state *state) 318 { 319 struct drm_i915_private *i915 = to_i915(state->base.dev); 320 321 /* 322 * Just return if we can't control SAGV or don't have it. 323 * This is different from situation when we have SAGV but just can't 324 * afford it due to DBuf limitation - in case if SAGV is completely 325 * disabled in a BIOS, we are not even allowed to send a PCode request, 326 * as it will throw an error. So have to check it here. 327 */ 328 if (!intel_has_sagv(i915)) 329 return; 330 331 if (DISPLAY_VER(i915) >= 11) 332 icl_sagv_post_plane_update(state); 333 else 334 skl_sagv_post_plane_update(state); 335 } 336 337 static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) 338 { 339 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 340 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 341 enum plane_id plane_id; 342 int max_level = INT_MAX; 343 344 if (!intel_has_sagv(i915)) 345 return false; 346 347 if (!crtc_state->hw.active) 348 return true; 349 350 if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE) 351 return false; 352 353 for_each_plane_id_on_crtc(crtc, plane_id) { 354 const struct skl_plane_wm *wm = 355 &crtc_state->wm.skl.optimal.planes[plane_id]; 356 int level; 357 358 /* Skip this plane if it's not enabled */ 359 if (!wm->wm[0].enable) 360 continue; 361 362 /* Find the highest enabled wm level for this plane */ 363 for (level = i915->display.wm.num_levels - 1; 364 !wm->wm[level].enable; --level) 365 { } 366 367 /* Highest common enabled wm level for all planes */ 368 max_level = min(level, max_level); 369 } 370 371 /* No enabled planes? */ 372 if (max_level == INT_MAX) 373 return true; 374 375 for_each_plane_id_on_crtc(crtc, plane_id) { 376 const struct skl_plane_wm *wm = 377 &crtc_state->wm.skl.optimal.planes[plane_id]; 378 379 /* 380 * All enabled planes must have enabled a common wm level that 381 * can tolerate memory latencies higher than sagv_block_time_us 382 */ 383 if (wm->wm[0].enable && !wm->wm[max_level].can_sagv) 384 return false; 385 } 386 387 return true; 388 } 389 390 static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) 391 { 392 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 393 enum plane_id plane_id; 394 395 if (!crtc_state->hw.active) 396 return true; 397 398 for_each_plane_id_on_crtc(crtc, plane_id) { 399 const struct skl_plane_wm *wm = 400 &crtc_state->wm.skl.optimal.planes[plane_id]; 401 402 if (wm->wm[0].enable && !wm->sagv.wm0.enable) 403 return false; 404 } 405 406 return true; 407 } 408 409 static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) 410 { 411 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 412 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 413 414 if (DISPLAY_VER(i915) >= 12) 415 return tgl_crtc_can_enable_sagv(crtc_state); 416 else 417 return skl_crtc_can_enable_sagv(crtc_state); 418 } 419 420 bool intel_can_enable_sagv(struct drm_i915_private *i915, 421 const struct intel_bw_state *bw_state) 422 { 423 if (DISPLAY_VER(i915) < 11 && 424 bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes)) 425 return false; 426 427 return bw_state->pipe_sagv_reject == 0; 428 } 429 430 static int intel_compute_sagv_mask(struct intel_atomic_state *state) 431 { 432 struct drm_i915_private *i915 = to_i915(state->base.dev); 433 int ret; 434 struct intel_crtc *crtc; 435 struct intel_crtc_state *new_crtc_state; 436 struct intel_bw_state *new_bw_state = NULL; 437 const struct intel_bw_state *old_bw_state = NULL; 438 int i; 439 440 for_each_new_intel_crtc_in_state(state, crtc, 441 new_crtc_state, i) { 442 new_bw_state = intel_atomic_get_bw_state(state); 443 if (IS_ERR(new_bw_state)) 444 return PTR_ERR(new_bw_state); 445 446 old_bw_state = intel_atomic_get_old_bw_state(state); 447 448 if (intel_crtc_can_enable_sagv(new_crtc_state)) 449 new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe); 450 else 451 new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe); 452 } 453 454 if (!new_bw_state) 455 return 0; 456 457 new_bw_state->active_pipes = 458 intel_calc_active_pipes(state, old_bw_state->active_pipes); 459 460 if (new_bw_state->active_pipes != old_bw_state->active_pipes) { 461 ret = intel_atomic_lock_global_state(&new_bw_state->base); 462 if (ret) 463 return ret; 464 } 465 466 if (intel_can_enable_sagv(i915, new_bw_state) != 467 intel_can_enable_sagv(i915, old_bw_state)) { 468 ret = intel_atomic_serialize_global_state(&new_bw_state->base); 469 if (ret) 470 return ret; 471 } else if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) { 472 ret = intel_atomic_lock_global_state(&new_bw_state->base); 473 if (ret) 474 return ret; 475 } 476 477 for_each_new_intel_crtc_in_state(state, crtc, 478 new_crtc_state, i) { 479 struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal; 480 481 /* 482 * We store use_sagv_wm in the crtc state rather than relying on 483 * that bw state since we have no convenient way to get at the 484 * latter from the plane commit hooks (especially in the legacy 485 * cursor case) 486 */ 487 pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(i915) && 488 DISPLAY_VER(i915) >= 12 && 489 intel_can_enable_sagv(i915, new_bw_state); 490 } 491 492 return 0; 493 } 494 495 static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry, 496 u16 start, u16 end) 497 { 498 entry->start = start; 499 entry->end = end; 500 501 return end; 502 } 503 504 static int intel_dbuf_slice_size(struct drm_i915_private *i915) 505 { 506 return INTEL_INFO(i915)->display.dbuf.size / 507 hweight8(INTEL_INFO(i915)->display.dbuf.slice_mask); 508 } 509 510 static void 511 skl_ddb_entry_for_slices(struct drm_i915_private *i915, u8 slice_mask, 512 struct skl_ddb_entry *ddb) 513 { 514 int slice_size = intel_dbuf_slice_size(i915); 515 516 if (!slice_mask) { 517 ddb->start = 0; 518 ddb->end = 0; 519 return; 520 } 521 522 ddb->start = (ffs(slice_mask) - 1) * slice_size; 523 ddb->end = fls(slice_mask) * slice_size; 524 525 WARN_ON(ddb->start >= ddb->end); 526 WARN_ON(ddb->end > INTEL_INFO(i915)->display.dbuf.size); 527 } 528 529 static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask) 530 { 531 struct skl_ddb_entry ddb; 532 533 if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2))) 534 slice_mask = BIT(DBUF_S1); 535 else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4))) 536 slice_mask = BIT(DBUF_S3); 537 538 skl_ddb_entry_for_slices(i915, slice_mask, &ddb); 539 540 return ddb.start; 541 } 542 543 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915, 544 const struct skl_ddb_entry *entry) 545 { 546 int slice_size = intel_dbuf_slice_size(i915); 547 enum dbuf_slice start_slice, end_slice; 548 u8 slice_mask = 0; 549 550 if (!skl_ddb_entry_size(entry)) 551 return 0; 552 553 start_slice = entry->start / slice_size; 554 end_slice = (entry->end - 1) / slice_size; 555 556 /* 557 * Per plane DDB entry can in a really worst case be on multiple slices 558 * but single entry is anyway contigious. 559 */ 560 while (start_slice <= end_slice) { 561 slice_mask |= BIT(start_slice); 562 start_slice++; 563 } 564 565 return slice_mask; 566 } 567 568 static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state *crtc_state) 569 { 570 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 571 int hdisplay, vdisplay; 572 573 if (!crtc_state->hw.active) 574 return 0; 575 576 /* 577 * Watermark/ddb requirement highly depends upon width of the 578 * framebuffer, So instead of allocating DDB equally among pipes 579 * distribute DDB based on resolution/width of the display. 580 */ 581 drm_mode_get_hv_timing(pipe_mode, &hdisplay, &vdisplay); 582 583 return hdisplay; 584 } 585 586 static void intel_crtc_dbuf_weights(const struct intel_dbuf_state *dbuf_state, 587 enum pipe for_pipe, 588 unsigned int *weight_start, 589 unsigned int *weight_end, 590 unsigned int *weight_total) 591 { 592 struct drm_i915_private *i915 = 593 to_i915(dbuf_state->base.state->base.dev); 594 enum pipe pipe; 595 596 *weight_start = 0; 597 *weight_end = 0; 598 *weight_total = 0; 599 600 for_each_pipe(i915, pipe) { 601 int weight = dbuf_state->weight[pipe]; 602 603 /* 604 * Do not account pipes using other slice sets 605 * luckily as of current BSpec slice sets do not partially 606 * intersect(pipes share either same one slice or same slice set 607 * i.e no partial intersection), so it is enough to check for 608 * equality for now. 609 */ 610 if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe]) 611 continue; 612 613 *weight_total += weight; 614 if (pipe < for_pipe) { 615 *weight_start += weight; 616 *weight_end += weight; 617 } else if (pipe == for_pipe) { 618 *weight_end += weight; 619 } 620 } 621 } 622 623 static int 624 skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc) 625 { 626 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 627 unsigned int weight_total, weight_start, weight_end; 628 const struct intel_dbuf_state *old_dbuf_state = 629 intel_atomic_get_old_dbuf_state(state); 630 struct intel_dbuf_state *new_dbuf_state = 631 intel_atomic_get_new_dbuf_state(state); 632 struct intel_crtc_state *crtc_state; 633 struct skl_ddb_entry ddb_slices; 634 enum pipe pipe = crtc->pipe; 635 unsigned int mbus_offset = 0; 636 u32 ddb_range_size; 637 u32 dbuf_slice_mask; 638 u32 start, end; 639 int ret; 640 641 if (new_dbuf_state->weight[pipe] == 0) { 642 skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], 0, 0); 643 goto out; 644 } 645 646 dbuf_slice_mask = new_dbuf_state->slices[pipe]; 647 648 skl_ddb_entry_for_slices(i915, dbuf_slice_mask, &ddb_slices); 649 mbus_offset = mbus_ddb_offset(i915, dbuf_slice_mask); 650 ddb_range_size = skl_ddb_entry_size(&ddb_slices); 651 652 intel_crtc_dbuf_weights(new_dbuf_state, pipe, 653 &weight_start, &weight_end, &weight_total); 654 655 start = ddb_range_size * weight_start / weight_total; 656 end = ddb_range_size * weight_end / weight_total; 657 658 skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], 659 ddb_slices.start - mbus_offset + start, 660 ddb_slices.start - mbus_offset + end); 661 662 out: 663 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] && 664 skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe], 665 &new_dbuf_state->ddb[pipe])) 666 return 0; 667 668 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 669 if (ret) 670 return ret; 671 672 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 673 if (IS_ERR(crtc_state)) 674 return PTR_ERR(crtc_state); 675 676 /* 677 * Used for checking overlaps, so we need absolute 678 * offsets instead of MBUS relative offsets. 679 */ 680 crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start; 681 crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end; 682 683 drm_dbg_kms(&i915->drm, 684 "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n", 685 crtc->base.base.id, crtc->base.name, 686 old_dbuf_state->slices[pipe], new_dbuf_state->slices[pipe], 687 old_dbuf_state->ddb[pipe].start, old_dbuf_state->ddb[pipe].end, 688 new_dbuf_state->ddb[pipe].start, new_dbuf_state->ddb[pipe].end, 689 old_dbuf_state->active_pipes, new_dbuf_state->active_pipes); 690 691 return 0; 692 } 693 694 static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state, 695 int width, const struct drm_format_info *format, 696 u64 modifier, unsigned int rotation, 697 u32 plane_pixel_rate, struct skl_wm_params *wp, 698 int color_plane); 699 700 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, 701 struct intel_plane *plane, 702 int level, 703 unsigned int latency, 704 const struct skl_wm_params *wp, 705 const struct skl_wm_level *result_prev, 706 struct skl_wm_level *result /* out */); 707 708 static unsigned int skl_wm_latency(struct drm_i915_private *i915, int level, 709 const struct skl_wm_params *wp) 710 { 711 unsigned int latency = i915->display.wm.skl_latency[level]; 712 713 if (latency == 0) 714 return 0; 715 716 /* 717 * WaIncreaseLatencyIPCEnabled: kbl,cfl 718 * Display WA #1141: kbl,cfl 719 */ 720 if ((IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) && 721 skl_watermark_ipc_enabled(i915)) 722 latency += 4; 723 724 if (skl_needs_memory_bw_wa(i915) && wp && wp->x_tiled) 725 latency += 15; 726 727 return latency; 728 } 729 730 static unsigned int 731 skl_cursor_allocation(const struct intel_crtc_state *crtc_state, 732 int num_active) 733 { 734 struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->cursor); 735 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 736 struct skl_wm_level wm = {}; 737 int ret, min_ddb_alloc = 0; 738 struct skl_wm_params wp; 739 int level; 740 741 ret = skl_compute_wm_params(crtc_state, 256, 742 drm_format_info(DRM_FORMAT_ARGB8888), 743 DRM_FORMAT_MOD_LINEAR, 744 DRM_MODE_ROTATE_0, 745 crtc_state->pixel_rate, &wp, 0); 746 drm_WARN_ON(&i915->drm, ret); 747 748 for (level = 0; level < i915->display.wm.num_levels; level++) { 749 unsigned int latency = skl_wm_latency(i915, level, &wp); 750 751 skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm); 752 if (wm.min_ddb_alloc == U16_MAX) 753 break; 754 755 min_ddb_alloc = wm.min_ddb_alloc; 756 } 757 758 return max(num_active == 1 ? 32 : 8, min_ddb_alloc); 759 } 760 761 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) 762 { 763 skl_ddb_entry_init(entry, 764 REG_FIELD_GET(PLANE_BUF_START_MASK, reg), 765 REG_FIELD_GET(PLANE_BUF_END_MASK, reg)); 766 if (entry->end) 767 entry->end++; 768 } 769 770 static void 771 skl_ddb_get_hw_plane_state(struct drm_i915_private *i915, 772 const enum pipe pipe, 773 const enum plane_id plane_id, 774 struct skl_ddb_entry *ddb, 775 struct skl_ddb_entry *ddb_y) 776 { 777 u32 val; 778 779 /* Cursor doesn't support NV12/planar, so no extra calculation needed */ 780 if (plane_id == PLANE_CURSOR) { 781 val = intel_de_read(i915, CUR_BUF_CFG(pipe)); 782 skl_ddb_entry_init_from_hw(ddb, val); 783 return; 784 } 785 786 val = intel_de_read(i915, PLANE_BUF_CFG(pipe, plane_id)); 787 skl_ddb_entry_init_from_hw(ddb, val); 788 789 if (DISPLAY_VER(i915) >= 11) 790 return; 791 792 val = intel_de_read(i915, PLANE_NV12_BUF_CFG(pipe, plane_id)); 793 skl_ddb_entry_init_from_hw(ddb_y, val); 794 } 795 796 static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, 797 struct skl_ddb_entry *ddb, 798 struct skl_ddb_entry *ddb_y) 799 { 800 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 801 enum intel_display_power_domain power_domain; 802 enum pipe pipe = crtc->pipe; 803 intel_wakeref_t wakeref; 804 enum plane_id plane_id; 805 806 power_domain = POWER_DOMAIN_PIPE(pipe); 807 wakeref = intel_display_power_get_if_enabled(i915, power_domain); 808 if (!wakeref) 809 return; 810 811 for_each_plane_id_on_crtc(crtc, plane_id) 812 skl_ddb_get_hw_plane_state(i915, pipe, 813 plane_id, 814 &ddb[plane_id], 815 &ddb_y[plane_id]); 816 817 intel_display_power_put(i915, power_domain, wakeref); 818 } 819 820 struct dbuf_slice_conf_entry { 821 u8 active_pipes; 822 u8 dbuf_mask[I915_MAX_PIPES]; 823 bool join_mbus; 824 }; 825 826 /* 827 * Table taken from Bspec 12716 828 * Pipes do have some preferred DBuf slice affinity, 829 * plus there are some hardcoded requirements on how 830 * those should be distributed for multipipe scenarios. 831 * For more DBuf slices algorithm can get even more messy 832 * and less readable, so decided to use a table almost 833 * as is from BSpec itself - that way it is at least easier 834 * to compare, change and check. 835 */ 836 static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] = 837 /* Autogenerated with igt/tools/intel_dbuf_map tool: */ 838 { 839 { 840 .active_pipes = BIT(PIPE_A), 841 .dbuf_mask = { 842 [PIPE_A] = BIT(DBUF_S1), 843 }, 844 }, 845 { 846 .active_pipes = BIT(PIPE_B), 847 .dbuf_mask = { 848 [PIPE_B] = BIT(DBUF_S1), 849 }, 850 }, 851 { 852 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 853 .dbuf_mask = { 854 [PIPE_A] = BIT(DBUF_S1), 855 [PIPE_B] = BIT(DBUF_S2), 856 }, 857 }, 858 { 859 .active_pipes = BIT(PIPE_C), 860 .dbuf_mask = { 861 [PIPE_C] = BIT(DBUF_S2), 862 }, 863 }, 864 { 865 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 866 .dbuf_mask = { 867 [PIPE_A] = BIT(DBUF_S1), 868 [PIPE_C] = BIT(DBUF_S2), 869 }, 870 }, 871 { 872 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 873 .dbuf_mask = { 874 [PIPE_B] = BIT(DBUF_S1), 875 [PIPE_C] = BIT(DBUF_S2), 876 }, 877 }, 878 { 879 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 880 .dbuf_mask = { 881 [PIPE_A] = BIT(DBUF_S1), 882 [PIPE_B] = BIT(DBUF_S1), 883 [PIPE_C] = BIT(DBUF_S2), 884 }, 885 }, 886 {} 887 }; 888 889 /* 890 * Table taken from Bspec 49255 891 * Pipes do have some preferred DBuf slice affinity, 892 * plus there are some hardcoded requirements on how 893 * those should be distributed for multipipe scenarios. 894 * For more DBuf slices algorithm can get even more messy 895 * and less readable, so decided to use a table almost 896 * as is from BSpec itself - that way it is at least easier 897 * to compare, change and check. 898 */ 899 static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = 900 /* Autogenerated with igt/tools/intel_dbuf_map tool: */ 901 { 902 { 903 .active_pipes = BIT(PIPE_A), 904 .dbuf_mask = { 905 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 906 }, 907 }, 908 { 909 .active_pipes = BIT(PIPE_B), 910 .dbuf_mask = { 911 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 912 }, 913 }, 914 { 915 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 916 .dbuf_mask = { 917 [PIPE_A] = BIT(DBUF_S2), 918 [PIPE_B] = BIT(DBUF_S1), 919 }, 920 }, 921 { 922 .active_pipes = BIT(PIPE_C), 923 .dbuf_mask = { 924 [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1), 925 }, 926 }, 927 { 928 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 929 .dbuf_mask = { 930 [PIPE_A] = BIT(DBUF_S1), 931 [PIPE_C] = BIT(DBUF_S2), 932 }, 933 }, 934 { 935 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 936 .dbuf_mask = { 937 [PIPE_B] = BIT(DBUF_S1), 938 [PIPE_C] = BIT(DBUF_S2), 939 }, 940 }, 941 { 942 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 943 .dbuf_mask = { 944 [PIPE_A] = BIT(DBUF_S1), 945 [PIPE_B] = BIT(DBUF_S1), 946 [PIPE_C] = BIT(DBUF_S2), 947 }, 948 }, 949 { 950 .active_pipes = BIT(PIPE_D), 951 .dbuf_mask = { 952 [PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1), 953 }, 954 }, 955 { 956 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D), 957 .dbuf_mask = { 958 [PIPE_A] = BIT(DBUF_S1), 959 [PIPE_D] = BIT(DBUF_S2), 960 }, 961 }, 962 { 963 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D), 964 .dbuf_mask = { 965 [PIPE_B] = BIT(DBUF_S1), 966 [PIPE_D] = BIT(DBUF_S2), 967 }, 968 }, 969 { 970 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D), 971 .dbuf_mask = { 972 [PIPE_A] = BIT(DBUF_S1), 973 [PIPE_B] = BIT(DBUF_S1), 974 [PIPE_D] = BIT(DBUF_S2), 975 }, 976 }, 977 { 978 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D), 979 .dbuf_mask = { 980 [PIPE_C] = BIT(DBUF_S1), 981 [PIPE_D] = BIT(DBUF_S2), 982 }, 983 }, 984 { 985 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D), 986 .dbuf_mask = { 987 [PIPE_A] = BIT(DBUF_S1), 988 [PIPE_C] = BIT(DBUF_S2), 989 [PIPE_D] = BIT(DBUF_S2), 990 }, 991 }, 992 { 993 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 994 .dbuf_mask = { 995 [PIPE_B] = BIT(DBUF_S1), 996 [PIPE_C] = BIT(DBUF_S2), 997 [PIPE_D] = BIT(DBUF_S2), 998 }, 999 }, 1000 { 1001 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1002 .dbuf_mask = { 1003 [PIPE_A] = BIT(DBUF_S1), 1004 [PIPE_B] = BIT(DBUF_S1), 1005 [PIPE_C] = BIT(DBUF_S2), 1006 [PIPE_D] = BIT(DBUF_S2), 1007 }, 1008 }, 1009 {} 1010 }; 1011 1012 static const struct dbuf_slice_conf_entry dg2_allowed_dbufs[] = { 1013 { 1014 .active_pipes = BIT(PIPE_A), 1015 .dbuf_mask = { 1016 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1017 }, 1018 }, 1019 { 1020 .active_pipes = BIT(PIPE_B), 1021 .dbuf_mask = { 1022 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 1023 }, 1024 }, 1025 { 1026 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 1027 .dbuf_mask = { 1028 [PIPE_A] = BIT(DBUF_S1), 1029 [PIPE_B] = BIT(DBUF_S2), 1030 }, 1031 }, 1032 { 1033 .active_pipes = BIT(PIPE_C), 1034 .dbuf_mask = { 1035 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1036 }, 1037 }, 1038 { 1039 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 1040 .dbuf_mask = { 1041 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1042 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1043 }, 1044 }, 1045 { 1046 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 1047 .dbuf_mask = { 1048 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 1049 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1050 }, 1051 }, 1052 { 1053 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 1054 .dbuf_mask = { 1055 [PIPE_A] = BIT(DBUF_S1), 1056 [PIPE_B] = BIT(DBUF_S2), 1057 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1058 }, 1059 }, 1060 { 1061 .active_pipes = BIT(PIPE_D), 1062 .dbuf_mask = { 1063 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 1064 }, 1065 }, 1066 { 1067 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D), 1068 .dbuf_mask = { 1069 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1070 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 1071 }, 1072 }, 1073 { 1074 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D), 1075 .dbuf_mask = { 1076 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 1077 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 1078 }, 1079 }, 1080 { 1081 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D), 1082 .dbuf_mask = { 1083 [PIPE_A] = BIT(DBUF_S1), 1084 [PIPE_B] = BIT(DBUF_S2), 1085 [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4), 1086 }, 1087 }, 1088 { 1089 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D), 1090 .dbuf_mask = { 1091 [PIPE_C] = BIT(DBUF_S3), 1092 [PIPE_D] = BIT(DBUF_S4), 1093 }, 1094 }, 1095 { 1096 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D), 1097 .dbuf_mask = { 1098 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1099 [PIPE_C] = BIT(DBUF_S3), 1100 [PIPE_D] = BIT(DBUF_S4), 1101 }, 1102 }, 1103 { 1104 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1105 .dbuf_mask = { 1106 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2), 1107 [PIPE_C] = BIT(DBUF_S3), 1108 [PIPE_D] = BIT(DBUF_S4), 1109 }, 1110 }, 1111 { 1112 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1113 .dbuf_mask = { 1114 [PIPE_A] = BIT(DBUF_S1), 1115 [PIPE_B] = BIT(DBUF_S2), 1116 [PIPE_C] = BIT(DBUF_S3), 1117 [PIPE_D] = BIT(DBUF_S4), 1118 }, 1119 }, 1120 {} 1121 }; 1122 1123 static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = { 1124 /* 1125 * Keep the join_mbus cases first so check_mbus_joined() 1126 * will prefer them over the !join_mbus cases. 1127 */ 1128 { 1129 .active_pipes = BIT(PIPE_A), 1130 .dbuf_mask = { 1131 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4), 1132 }, 1133 .join_mbus = true, 1134 }, 1135 { 1136 .active_pipes = BIT(PIPE_B), 1137 .dbuf_mask = { 1138 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4), 1139 }, 1140 .join_mbus = true, 1141 }, 1142 { 1143 .active_pipes = BIT(PIPE_A), 1144 .dbuf_mask = { 1145 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1146 }, 1147 .join_mbus = false, 1148 }, 1149 { 1150 .active_pipes = BIT(PIPE_B), 1151 .dbuf_mask = { 1152 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1153 }, 1154 .join_mbus = false, 1155 }, 1156 { 1157 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B), 1158 .dbuf_mask = { 1159 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1160 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1161 }, 1162 }, 1163 { 1164 .active_pipes = BIT(PIPE_C), 1165 .dbuf_mask = { 1166 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1167 }, 1168 }, 1169 { 1170 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C), 1171 .dbuf_mask = { 1172 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1173 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1174 }, 1175 }, 1176 { 1177 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C), 1178 .dbuf_mask = { 1179 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1180 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1181 }, 1182 }, 1183 { 1184 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 1185 .dbuf_mask = { 1186 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1187 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1188 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1189 }, 1190 }, 1191 { 1192 .active_pipes = BIT(PIPE_D), 1193 .dbuf_mask = { 1194 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1195 }, 1196 }, 1197 { 1198 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D), 1199 .dbuf_mask = { 1200 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1201 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1202 }, 1203 }, 1204 { 1205 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D), 1206 .dbuf_mask = { 1207 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1208 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1209 }, 1210 }, 1211 { 1212 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D), 1213 .dbuf_mask = { 1214 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1215 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1216 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1217 }, 1218 }, 1219 { 1220 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D), 1221 .dbuf_mask = { 1222 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1223 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1224 }, 1225 }, 1226 { 1227 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D), 1228 .dbuf_mask = { 1229 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1230 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1231 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1232 }, 1233 }, 1234 { 1235 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1236 .dbuf_mask = { 1237 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1238 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1239 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1240 }, 1241 }, 1242 { 1243 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 1244 .dbuf_mask = { 1245 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2), 1246 [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4), 1247 [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4), 1248 [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2), 1249 }, 1250 }, 1251 {} 1252 1253 }; 1254 1255 static bool check_mbus_joined(u8 active_pipes, 1256 const struct dbuf_slice_conf_entry *dbuf_slices) 1257 { 1258 int i; 1259 1260 for (i = 0; dbuf_slices[i].active_pipes != 0; i++) { 1261 if (dbuf_slices[i].active_pipes == active_pipes) 1262 return dbuf_slices[i].join_mbus; 1263 } 1264 return false; 1265 } 1266 1267 static bool adlp_check_mbus_joined(u8 active_pipes) 1268 { 1269 return check_mbus_joined(active_pipes, adlp_allowed_dbufs); 1270 } 1271 1272 static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus, 1273 const struct dbuf_slice_conf_entry *dbuf_slices) 1274 { 1275 int i; 1276 1277 for (i = 0; dbuf_slices[i].active_pipes != 0; i++) { 1278 if (dbuf_slices[i].active_pipes == active_pipes && 1279 dbuf_slices[i].join_mbus == join_mbus) 1280 return dbuf_slices[i].dbuf_mask[pipe]; 1281 } 1282 return 0; 1283 } 1284 1285 /* 1286 * This function finds an entry with same enabled pipe configuration and 1287 * returns correspondent DBuf slice mask as stated in BSpec for particular 1288 * platform. 1289 */ 1290 static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1291 { 1292 /* 1293 * FIXME: For ICL this is still a bit unclear as prev BSpec revision 1294 * required calculating "pipe ratio" in order to determine 1295 * if one or two slices can be used for single pipe configurations 1296 * as additional constraint to the existing table. 1297 * However based on recent info, it should be not "pipe ratio" 1298 * but rather ratio between pixel_rate and cdclk with additional 1299 * constants, so for now we are using only table until this is 1300 * clarified. Also this is the reason why crtc_state param is 1301 * still here - we will need it once those additional constraints 1302 * pop up. 1303 */ 1304 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1305 icl_allowed_dbufs); 1306 } 1307 1308 static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1309 { 1310 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1311 tgl_allowed_dbufs); 1312 } 1313 1314 static u8 adlp_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1315 { 1316 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1317 adlp_allowed_dbufs); 1318 } 1319 1320 static u8 dg2_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus) 1321 { 1322 return compute_dbuf_slices(pipe, active_pipes, join_mbus, 1323 dg2_allowed_dbufs); 1324 } 1325 1326 static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool join_mbus) 1327 { 1328 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1329 enum pipe pipe = crtc->pipe; 1330 1331 if (IS_DG2(i915)) 1332 return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1333 else if (DISPLAY_VER(i915) >= 13) 1334 return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1335 else if (DISPLAY_VER(i915) == 12) 1336 return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1337 else if (DISPLAY_VER(i915) == 11) 1338 return icl_compute_dbuf_slices(pipe, active_pipes, join_mbus); 1339 /* 1340 * For anything else just return one slice yet. 1341 * Should be extended for other platforms. 1342 */ 1343 return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0; 1344 } 1345 1346 static bool 1347 use_minimal_wm0_only(const struct intel_crtc_state *crtc_state, 1348 struct intel_plane *plane) 1349 { 1350 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1351 1352 return DISPLAY_VER(i915) >= 13 && 1353 crtc_state->uapi.async_flip && 1354 plane->async_flip; 1355 } 1356 1357 static u64 1358 skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state) 1359 { 1360 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1361 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1362 enum plane_id plane_id; 1363 u64 data_rate = 0; 1364 1365 for_each_plane_id_on_crtc(crtc, plane_id) { 1366 if (plane_id == PLANE_CURSOR) 1367 continue; 1368 1369 data_rate += crtc_state->rel_data_rate[plane_id]; 1370 1371 if (DISPLAY_VER(i915) < 11) 1372 data_rate += crtc_state->rel_data_rate_y[plane_id]; 1373 } 1374 1375 return data_rate; 1376 } 1377 1378 static const struct skl_wm_level * 1379 skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm, 1380 enum plane_id plane_id, 1381 int level) 1382 { 1383 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; 1384 1385 if (level == 0 && pipe_wm->use_sagv_wm) 1386 return &wm->sagv.wm0; 1387 1388 return &wm->wm[level]; 1389 } 1390 1391 static const struct skl_wm_level * 1392 skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm, 1393 enum plane_id plane_id) 1394 { 1395 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; 1396 1397 if (pipe_wm->use_sagv_wm) 1398 return &wm->sagv.trans_wm; 1399 1400 return &wm->trans_wm; 1401 } 1402 1403 /* 1404 * We only disable the watermarks for each plane if 1405 * they exceed the ddb allocation of said plane. This 1406 * is done so that we don't end up touching cursor 1407 * watermarks needlessly when some other plane reduces 1408 * our max possible watermark level. 1409 * 1410 * Bspec has this to say about the PLANE_WM enable bit: 1411 * "All the watermarks at this level for all enabled 1412 * planes must be enabled before the level will be used." 1413 * So this is actually safe to do. 1414 */ 1415 static void 1416 skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb) 1417 { 1418 if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) 1419 memset(wm, 0, sizeof(*wm)); 1420 } 1421 1422 static void 1423 skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm, 1424 const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb) 1425 { 1426 if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) || 1427 uv_wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) { 1428 memset(wm, 0, sizeof(*wm)); 1429 memset(uv_wm, 0, sizeof(*uv_wm)); 1430 } 1431 } 1432 1433 static bool skl_need_wm_copy_wa(struct drm_i915_private *i915, int level, 1434 const struct skl_plane_wm *wm) 1435 { 1436 /* 1437 * Wa_1408961008:icl, ehl 1438 * Wa_14012656716:tgl, adl 1439 * Wa_14017887344:icl 1440 * Wa_14017868169:adl, tgl 1441 * Due to some power saving optimizations, different subsystems 1442 * like PSR, might still use even disabled wm level registers, 1443 * for "reference", so lets keep at least the values sane. 1444 * Considering amount of WA requiring us to do similar things, was 1445 * decided to simply do it for all of the platforms, as those wm 1446 * levels are disabled, this isn't going to do harm anyway. 1447 */ 1448 return level > 0 && !wm->wm[level].enable; 1449 } 1450 1451 struct skl_plane_ddb_iter { 1452 u64 data_rate; 1453 u16 start, size; 1454 }; 1455 1456 static void 1457 skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter, 1458 struct skl_ddb_entry *ddb, 1459 const struct skl_wm_level *wm, 1460 u64 data_rate) 1461 { 1462 u16 size, extra = 0; 1463 1464 if (data_rate) { 1465 extra = min_t(u16, iter->size, 1466 DIV64_U64_ROUND_UP(iter->size * data_rate, 1467 iter->data_rate)); 1468 iter->size -= extra; 1469 iter->data_rate -= data_rate; 1470 } 1471 1472 /* 1473 * Keep ddb entry of all disabled planes explicitly zeroed 1474 * to avoid skl_ddb_add_affected_planes() adding them to 1475 * the state when other planes change their allocations. 1476 */ 1477 size = wm->min_ddb_alloc + extra; 1478 if (size) 1479 iter->start = skl_ddb_entry_init(ddb, iter->start, 1480 iter->start + size); 1481 } 1482 1483 static int 1484 skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state, 1485 struct intel_crtc *crtc) 1486 { 1487 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1488 struct intel_crtc_state *crtc_state = 1489 intel_atomic_get_new_crtc_state(state, crtc); 1490 const struct intel_dbuf_state *dbuf_state = 1491 intel_atomic_get_new_dbuf_state(state); 1492 const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe]; 1493 int num_active = hweight8(dbuf_state->active_pipes); 1494 struct skl_plane_ddb_iter iter; 1495 enum plane_id plane_id; 1496 u16 cursor_size; 1497 u32 blocks; 1498 int level; 1499 1500 /* Clear the partitioning for disabled planes. */ 1501 memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb)); 1502 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); 1503 1504 if (!crtc_state->hw.active) 1505 return 0; 1506 1507 iter.start = alloc->start; 1508 iter.size = skl_ddb_entry_size(alloc); 1509 if (iter.size == 0) 1510 return 0; 1511 1512 /* Allocate fixed number of blocks for cursor. */ 1513 cursor_size = skl_cursor_allocation(crtc_state, num_active); 1514 iter.size -= cursor_size; 1515 skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR], 1516 alloc->end - cursor_size, alloc->end); 1517 1518 iter.data_rate = skl_total_relative_data_rate(crtc_state); 1519 1520 /* 1521 * Find the highest watermark level for which we can satisfy the block 1522 * requirement of active planes. 1523 */ 1524 for (level = i915->display.wm.num_levels - 1; level >= 0; level--) { 1525 blocks = 0; 1526 for_each_plane_id_on_crtc(crtc, plane_id) { 1527 const struct skl_plane_wm *wm = 1528 &crtc_state->wm.skl.optimal.planes[plane_id]; 1529 1530 if (plane_id == PLANE_CURSOR) { 1531 const struct skl_ddb_entry *ddb = 1532 &crtc_state->wm.skl.plane_ddb[plane_id]; 1533 1534 if (wm->wm[level].min_ddb_alloc > skl_ddb_entry_size(ddb)) { 1535 drm_WARN_ON(&i915->drm, 1536 wm->wm[level].min_ddb_alloc != U16_MAX); 1537 blocks = U32_MAX; 1538 break; 1539 } 1540 continue; 1541 } 1542 1543 blocks += wm->wm[level].min_ddb_alloc; 1544 blocks += wm->uv_wm[level].min_ddb_alloc; 1545 } 1546 1547 if (blocks <= iter.size) { 1548 iter.size -= blocks; 1549 break; 1550 } 1551 } 1552 1553 if (level < 0) { 1554 drm_dbg_kms(&i915->drm, 1555 "Requested display configuration exceeds system DDB limitations"); 1556 drm_dbg_kms(&i915->drm, "minimum required %d/%d\n", 1557 blocks, iter.size); 1558 return -EINVAL; 1559 } 1560 1561 /* avoid the WARN later when we don't allocate any extra DDB */ 1562 if (iter.data_rate == 0) 1563 iter.size = 0; 1564 1565 /* 1566 * Grant each plane the blocks it requires at the highest achievable 1567 * watermark level, plus an extra share of the leftover blocks 1568 * proportional to its relative data rate. 1569 */ 1570 for_each_plane_id_on_crtc(crtc, plane_id) { 1571 struct skl_ddb_entry *ddb = 1572 &crtc_state->wm.skl.plane_ddb[plane_id]; 1573 struct skl_ddb_entry *ddb_y = 1574 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 1575 const struct skl_plane_wm *wm = 1576 &crtc_state->wm.skl.optimal.planes[plane_id]; 1577 1578 if (plane_id == PLANE_CURSOR) 1579 continue; 1580 1581 if (DISPLAY_VER(i915) < 11 && 1582 crtc_state->nv12_planes & BIT(plane_id)) { 1583 skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level], 1584 crtc_state->rel_data_rate_y[plane_id]); 1585 skl_allocate_plane_ddb(&iter, ddb, &wm->uv_wm[level], 1586 crtc_state->rel_data_rate[plane_id]); 1587 } else { 1588 skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level], 1589 crtc_state->rel_data_rate[plane_id]); 1590 } 1591 } 1592 drm_WARN_ON(&i915->drm, iter.size != 0 || iter.data_rate != 0); 1593 1594 /* 1595 * When we calculated watermark values we didn't know how high 1596 * of a level we'd actually be able to hit, so we just marked 1597 * all levels as "enabled." Go back now and disable the ones 1598 * that aren't actually possible. 1599 */ 1600 for (level++; level < i915->display.wm.num_levels; level++) { 1601 for_each_plane_id_on_crtc(crtc, plane_id) { 1602 const struct skl_ddb_entry *ddb = 1603 &crtc_state->wm.skl.plane_ddb[plane_id]; 1604 const struct skl_ddb_entry *ddb_y = 1605 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 1606 struct skl_plane_wm *wm = 1607 &crtc_state->wm.skl.optimal.planes[plane_id]; 1608 1609 if (DISPLAY_VER(i915) < 11 && 1610 crtc_state->nv12_planes & BIT(plane_id)) 1611 skl_check_nv12_wm_level(&wm->wm[level], 1612 &wm->uv_wm[level], 1613 ddb_y, ddb); 1614 else 1615 skl_check_wm_level(&wm->wm[level], ddb); 1616 1617 if (skl_need_wm_copy_wa(i915, level, wm)) { 1618 wm->wm[level].blocks = wm->wm[level - 1].blocks; 1619 wm->wm[level].lines = wm->wm[level - 1].lines; 1620 wm->wm[level].ignore_lines = wm->wm[level - 1].ignore_lines; 1621 } 1622 } 1623 } 1624 1625 /* 1626 * Go back and disable the transition and SAGV watermarks 1627 * if it turns out we don't have enough DDB blocks for them. 1628 */ 1629 for_each_plane_id_on_crtc(crtc, plane_id) { 1630 const struct skl_ddb_entry *ddb = 1631 &crtc_state->wm.skl.plane_ddb[plane_id]; 1632 const struct skl_ddb_entry *ddb_y = 1633 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 1634 struct skl_plane_wm *wm = 1635 &crtc_state->wm.skl.optimal.planes[plane_id]; 1636 1637 if (DISPLAY_VER(i915) < 11 && 1638 crtc_state->nv12_planes & BIT(plane_id)) { 1639 skl_check_wm_level(&wm->trans_wm, ddb_y); 1640 } else { 1641 WARN_ON(skl_ddb_entry_size(ddb_y)); 1642 1643 skl_check_wm_level(&wm->trans_wm, ddb); 1644 } 1645 1646 skl_check_wm_level(&wm->sagv.wm0, ddb); 1647 skl_check_wm_level(&wm->sagv.trans_wm, ddb); 1648 } 1649 1650 return 0; 1651 } 1652 1653 /* 1654 * The max latency should be 257 (max the punit can code is 255 and we add 2us 1655 * for the read latency) and cpp should always be <= 8, so that 1656 * should allow pixel_rate up to ~2 GHz which seems sufficient since max 1657 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. 1658 */ 1659 static uint_fixed_16_16_t 1660 skl_wm_method1(const struct drm_i915_private *i915, u32 pixel_rate, 1661 u8 cpp, u32 latency, u32 dbuf_block_size) 1662 { 1663 u32 wm_intermediate_val; 1664 uint_fixed_16_16_t ret; 1665 1666 if (latency == 0) 1667 return FP_16_16_MAX; 1668 1669 wm_intermediate_val = latency * pixel_rate * cpp; 1670 ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size); 1671 1672 if (DISPLAY_VER(i915) >= 10) 1673 ret = add_fixed16_u32(ret, 1); 1674 1675 return ret; 1676 } 1677 1678 static uint_fixed_16_16_t 1679 skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency, 1680 uint_fixed_16_16_t plane_blocks_per_line) 1681 { 1682 u32 wm_intermediate_val; 1683 uint_fixed_16_16_t ret; 1684 1685 if (latency == 0) 1686 return FP_16_16_MAX; 1687 1688 wm_intermediate_val = latency * pixel_rate; 1689 wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val, 1690 pipe_htotal * 1000); 1691 ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line); 1692 return ret; 1693 } 1694 1695 static uint_fixed_16_16_t 1696 intel_get_linetime_us(const struct intel_crtc_state *crtc_state) 1697 { 1698 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1699 u32 pixel_rate; 1700 u32 crtc_htotal; 1701 uint_fixed_16_16_t linetime_us; 1702 1703 if (!crtc_state->hw.active) 1704 return u32_to_fixed16(0); 1705 1706 pixel_rate = crtc_state->pixel_rate; 1707 1708 if (drm_WARN_ON(&i915->drm, pixel_rate == 0)) 1709 return u32_to_fixed16(0); 1710 1711 crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal; 1712 linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate); 1713 1714 return linetime_us; 1715 } 1716 1717 static int 1718 skl_compute_wm_params(const struct intel_crtc_state *crtc_state, 1719 int width, const struct drm_format_info *format, 1720 u64 modifier, unsigned int rotation, 1721 u32 plane_pixel_rate, struct skl_wm_params *wp, 1722 int color_plane) 1723 { 1724 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1725 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1726 u32 interm_pbpl; 1727 1728 /* only planar format has two planes */ 1729 if (color_plane == 1 && 1730 !intel_format_info_is_yuv_semiplanar(format, modifier)) { 1731 drm_dbg_kms(&i915->drm, 1732 "Non planar format have single plane\n"); 1733 return -EINVAL; 1734 } 1735 1736 wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED; 1737 wp->y_tiled = modifier != I915_FORMAT_MOD_X_TILED && 1738 intel_fb_is_tiled_modifier(modifier); 1739 wp->rc_surface = intel_fb_is_ccs_modifier(modifier); 1740 wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier); 1741 1742 wp->width = width; 1743 if (color_plane == 1 && wp->is_planar) 1744 wp->width /= 2; 1745 1746 wp->cpp = format->cpp[color_plane]; 1747 wp->plane_pixel_rate = plane_pixel_rate; 1748 1749 if (DISPLAY_VER(i915) >= 11 && 1750 modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1) 1751 wp->dbuf_block_size = 256; 1752 else 1753 wp->dbuf_block_size = 512; 1754 1755 if (drm_rotation_90_or_270(rotation)) { 1756 switch (wp->cpp) { 1757 case 1: 1758 wp->y_min_scanlines = 16; 1759 break; 1760 case 2: 1761 wp->y_min_scanlines = 8; 1762 break; 1763 case 4: 1764 wp->y_min_scanlines = 4; 1765 break; 1766 default: 1767 MISSING_CASE(wp->cpp); 1768 return -EINVAL; 1769 } 1770 } else { 1771 wp->y_min_scanlines = 4; 1772 } 1773 1774 if (skl_needs_memory_bw_wa(i915)) 1775 wp->y_min_scanlines *= 2; 1776 1777 wp->plane_bytes_per_line = wp->width * wp->cpp; 1778 if (wp->y_tiled) { 1779 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line * 1780 wp->y_min_scanlines, 1781 wp->dbuf_block_size); 1782 1783 if (DISPLAY_VER(i915) >= 10) 1784 interm_pbpl++; 1785 1786 wp->plane_blocks_per_line = div_fixed16(interm_pbpl, 1787 wp->y_min_scanlines); 1788 } else { 1789 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 1790 wp->dbuf_block_size); 1791 1792 if (!wp->x_tiled || DISPLAY_VER(i915) >= 10) 1793 interm_pbpl++; 1794 1795 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl); 1796 } 1797 1798 wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines, 1799 wp->plane_blocks_per_line); 1800 1801 wp->linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(crtc_state)); 1802 1803 return 0; 1804 } 1805 1806 static int 1807 skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state, 1808 const struct intel_plane_state *plane_state, 1809 struct skl_wm_params *wp, int color_plane) 1810 { 1811 const struct drm_framebuffer *fb = plane_state->hw.fb; 1812 int width; 1813 1814 /* 1815 * Src coordinates are already rotated by 270 degrees for 1816 * the 90/270 degree plane rotation cases (to match the 1817 * GTT mapping), hence no need to account for rotation here. 1818 */ 1819 width = drm_rect_width(&plane_state->uapi.src) >> 16; 1820 1821 return skl_compute_wm_params(crtc_state, width, 1822 fb->format, fb->modifier, 1823 plane_state->hw.rotation, 1824 intel_plane_pixel_rate(crtc_state, plane_state), 1825 wp, color_plane); 1826 } 1827 1828 static bool skl_wm_has_lines(struct drm_i915_private *i915, int level) 1829 { 1830 if (DISPLAY_VER(i915) >= 10) 1831 return true; 1832 1833 /* The number of lines are ignored for the level 0 watermark. */ 1834 return level > 0; 1835 } 1836 1837 static int skl_wm_max_lines(struct drm_i915_private *i915) 1838 { 1839 if (DISPLAY_VER(i915) >= 13) 1840 return 255; 1841 else 1842 return 31; 1843 } 1844 1845 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, 1846 struct intel_plane *plane, 1847 int level, 1848 unsigned int latency, 1849 const struct skl_wm_params *wp, 1850 const struct skl_wm_level *result_prev, 1851 struct skl_wm_level *result /* out */) 1852 { 1853 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1854 uint_fixed_16_16_t method1, method2; 1855 uint_fixed_16_16_t selected_result; 1856 u32 blocks, lines, min_ddb_alloc = 0; 1857 1858 if (latency == 0 || 1859 (use_minimal_wm0_only(crtc_state, plane) && level > 0)) { 1860 /* reject it */ 1861 result->min_ddb_alloc = U16_MAX; 1862 return; 1863 } 1864 1865 method1 = skl_wm_method1(i915, wp->plane_pixel_rate, 1866 wp->cpp, latency, wp->dbuf_block_size); 1867 method2 = skl_wm_method2(wp->plane_pixel_rate, 1868 crtc_state->hw.pipe_mode.crtc_htotal, 1869 latency, 1870 wp->plane_blocks_per_line); 1871 1872 if (wp->y_tiled) { 1873 selected_result = max_fixed16(method2, wp->y_tile_minimum); 1874 } else { 1875 if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal / 1876 wp->dbuf_block_size < 1) && 1877 (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) { 1878 selected_result = method2; 1879 } else if (latency >= wp->linetime_us) { 1880 if (DISPLAY_VER(i915) == 9) 1881 selected_result = min_fixed16(method1, method2); 1882 else 1883 selected_result = method2; 1884 } else { 1885 selected_result = method1; 1886 } 1887 } 1888 1889 blocks = fixed16_to_u32_round_up(selected_result) + 1; 1890 /* 1891 * Lets have blocks at minimum equivalent to plane_blocks_per_line 1892 * as there will be at minimum one line for lines configuration. This 1893 * is a work around for FIFO underruns observed with resolutions like 1894 * 4k 60 Hz in single channel DRAM configurations. 1895 * 1896 * As per the Bspec 49325, if the ddb allocation can hold at least 1897 * one plane_blocks_per_line, we should have selected method2 in 1898 * the above logic. Assuming that modern versions have enough dbuf 1899 * and method2 guarantees blocks equivalent to at least 1 line, 1900 * select the blocks as plane_blocks_per_line. 1901 * 1902 * TODO: Revisit the logic when we have better understanding on DRAM 1903 * channels' impact on the level 0 memory latency and the relevant 1904 * wm calculations. 1905 */ 1906 if (skl_wm_has_lines(i915, level)) 1907 blocks = max(blocks, 1908 fixed16_to_u32_round_up(wp->plane_blocks_per_line)); 1909 lines = div_round_up_fixed16(selected_result, 1910 wp->plane_blocks_per_line); 1911 1912 if (DISPLAY_VER(i915) == 9) { 1913 /* Display WA #1125: skl,bxt,kbl */ 1914 if (level == 0 && wp->rc_surface) 1915 blocks += fixed16_to_u32_round_up(wp->y_tile_minimum); 1916 1917 /* Display WA #1126: skl,bxt,kbl */ 1918 if (level >= 1 && level <= 7) { 1919 if (wp->y_tiled) { 1920 blocks += fixed16_to_u32_round_up(wp->y_tile_minimum); 1921 lines += wp->y_min_scanlines; 1922 } else { 1923 blocks++; 1924 } 1925 1926 /* 1927 * Make sure result blocks for higher latency levels are 1928 * at least as high as level below the current level. 1929 * Assumption in DDB algorithm optimization for special 1930 * cases. Also covers Display WA #1125 for RC. 1931 */ 1932 if (result_prev->blocks > blocks) 1933 blocks = result_prev->blocks; 1934 } 1935 } 1936 1937 if (DISPLAY_VER(i915) >= 11) { 1938 if (wp->y_tiled) { 1939 int extra_lines; 1940 1941 if (lines % wp->y_min_scanlines == 0) 1942 extra_lines = wp->y_min_scanlines; 1943 else 1944 extra_lines = wp->y_min_scanlines * 2 - 1945 lines % wp->y_min_scanlines; 1946 1947 min_ddb_alloc = mul_round_up_u32_fixed16(lines + extra_lines, 1948 wp->plane_blocks_per_line); 1949 } else { 1950 min_ddb_alloc = blocks + DIV_ROUND_UP(blocks, 10); 1951 } 1952 } 1953 1954 if (!skl_wm_has_lines(i915, level)) 1955 lines = 0; 1956 1957 if (lines > skl_wm_max_lines(i915)) { 1958 /* reject it */ 1959 result->min_ddb_alloc = U16_MAX; 1960 return; 1961 } 1962 1963 /* 1964 * If lines is valid, assume we can use this watermark level 1965 * for now. We'll come back and disable it after we calculate the 1966 * DDB allocation if it turns out we don't actually have enough 1967 * blocks to satisfy it. 1968 */ 1969 result->blocks = blocks; 1970 result->lines = lines; 1971 /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */ 1972 result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1; 1973 result->enable = true; 1974 1975 if (DISPLAY_VER(i915) < 12 && i915->display.sagv.block_time_us) 1976 result->can_sagv = latency >= i915->display.sagv.block_time_us; 1977 } 1978 1979 static void 1980 skl_compute_wm_levels(const struct intel_crtc_state *crtc_state, 1981 struct intel_plane *plane, 1982 const struct skl_wm_params *wm_params, 1983 struct skl_wm_level *levels) 1984 { 1985 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1986 struct skl_wm_level *result_prev = &levels[0]; 1987 int level; 1988 1989 for (level = 0; level < i915->display.wm.num_levels; level++) { 1990 struct skl_wm_level *result = &levels[level]; 1991 unsigned int latency = skl_wm_latency(i915, level, wm_params); 1992 1993 skl_compute_plane_wm(crtc_state, plane, level, latency, 1994 wm_params, result_prev, result); 1995 1996 result_prev = result; 1997 } 1998 } 1999 2000 static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state, 2001 struct intel_plane *plane, 2002 const struct skl_wm_params *wm_params, 2003 struct skl_plane_wm *plane_wm) 2004 { 2005 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2006 struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0; 2007 struct skl_wm_level *levels = plane_wm->wm; 2008 unsigned int latency = 0; 2009 2010 if (i915->display.sagv.block_time_us) 2011 latency = i915->display.sagv.block_time_us + 2012 skl_wm_latency(i915, 0, wm_params); 2013 2014 skl_compute_plane_wm(crtc_state, plane, 0, latency, 2015 wm_params, &levels[0], 2016 sagv_wm); 2017 } 2018 2019 static void skl_compute_transition_wm(struct drm_i915_private *i915, 2020 struct skl_wm_level *trans_wm, 2021 const struct skl_wm_level *wm0, 2022 const struct skl_wm_params *wp) 2023 { 2024 u16 trans_min, trans_amount, trans_y_tile_min; 2025 u16 wm0_blocks, trans_offset, blocks; 2026 2027 /* Transition WM don't make any sense if ipc is disabled */ 2028 if (!skl_watermark_ipc_enabled(i915)) 2029 return; 2030 2031 /* 2032 * WaDisableTWM:skl,kbl,cfl,bxt 2033 * Transition WM are not recommended by HW team for GEN9 2034 */ 2035 if (DISPLAY_VER(i915) == 9) 2036 return; 2037 2038 if (DISPLAY_VER(i915) >= 11) 2039 trans_min = 4; 2040 else 2041 trans_min = 14; 2042 2043 /* Display WA #1140: glk,cnl */ 2044 if (DISPLAY_VER(i915) == 10) 2045 trans_amount = 0; 2046 else 2047 trans_amount = 10; /* This is configurable amount */ 2048 2049 trans_offset = trans_min + trans_amount; 2050 2051 /* 2052 * The spec asks for Selected Result Blocks for wm0 (the real value), 2053 * not Result Blocks (the integer value). Pay attention to the capital 2054 * letters. The value wm_l0->blocks is actually Result Blocks, but 2055 * since Result Blocks is the ceiling of Selected Result Blocks plus 1, 2056 * and since we later will have to get the ceiling of the sum in the 2057 * transition watermarks calculation, we can just pretend Selected 2058 * Result Blocks is Result Blocks minus 1 and it should work for the 2059 * current platforms. 2060 */ 2061 wm0_blocks = wm0->blocks - 1; 2062 2063 if (wp->y_tiled) { 2064 trans_y_tile_min = 2065 (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum); 2066 blocks = max(wm0_blocks, trans_y_tile_min) + trans_offset; 2067 } else { 2068 blocks = wm0_blocks + trans_offset; 2069 } 2070 blocks++; 2071 2072 /* 2073 * Just assume we can enable the transition watermark. After 2074 * computing the DDB we'll come back and disable it if that 2075 * assumption turns out to be false. 2076 */ 2077 trans_wm->blocks = blocks; 2078 trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, blocks + 1); 2079 trans_wm->enable = true; 2080 } 2081 2082 static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state, 2083 const struct intel_plane_state *plane_state, 2084 struct intel_plane *plane, int color_plane) 2085 { 2086 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2087 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2088 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id]; 2089 struct skl_wm_params wm_params; 2090 int ret; 2091 2092 ret = skl_compute_plane_wm_params(crtc_state, plane_state, 2093 &wm_params, color_plane); 2094 if (ret) 2095 return ret; 2096 2097 skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->wm); 2098 2099 skl_compute_transition_wm(i915, &wm->trans_wm, 2100 &wm->wm[0], &wm_params); 2101 2102 if (DISPLAY_VER(i915) >= 12) { 2103 tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm); 2104 2105 skl_compute_transition_wm(i915, &wm->sagv.trans_wm, 2106 &wm->sagv.wm0, &wm_params); 2107 } 2108 2109 return 0; 2110 } 2111 2112 static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state, 2113 const struct intel_plane_state *plane_state, 2114 struct intel_plane *plane) 2115 { 2116 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id]; 2117 struct skl_wm_params wm_params; 2118 int ret; 2119 2120 wm->is_planar = true; 2121 2122 /* uv plane watermarks must also be validated for NV12/Planar */ 2123 ret = skl_compute_plane_wm_params(crtc_state, plane_state, 2124 &wm_params, 1); 2125 if (ret) 2126 return ret; 2127 2128 skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm); 2129 2130 return 0; 2131 } 2132 2133 static int skl_build_plane_wm(struct intel_crtc_state *crtc_state, 2134 const struct intel_plane_state *plane_state) 2135 { 2136 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2137 enum plane_id plane_id = plane->id; 2138 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; 2139 const struct drm_framebuffer *fb = plane_state->hw.fb; 2140 int ret; 2141 2142 memset(wm, 0, sizeof(*wm)); 2143 2144 if (!intel_wm_plane_visible(crtc_state, plane_state)) 2145 return 0; 2146 2147 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2148 plane, 0); 2149 if (ret) 2150 return ret; 2151 2152 if (fb->format->is_yuv && fb->format->num_planes > 1) { 2153 ret = skl_build_plane_wm_uv(crtc_state, plane_state, 2154 plane); 2155 if (ret) 2156 return ret; 2157 } 2158 2159 return 0; 2160 } 2161 2162 static int icl_build_plane_wm(struct intel_crtc_state *crtc_state, 2163 const struct intel_plane_state *plane_state) 2164 { 2165 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2166 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2167 enum plane_id plane_id = plane->id; 2168 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; 2169 int ret; 2170 2171 /* Watermarks calculated in master */ 2172 if (plane_state->planar_slave) 2173 return 0; 2174 2175 memset(wm, 0, sizeof(*wm)); 2176 2177 if (plane_state->planar_linked_plane) { 2178 const struct drm_framebuffer *fb = plane_state->hw.fb; 2179 2180 drm_WARN_ON(&i915->drm, 2181 !intel_wm_plane_visible(crtc_state, plane_state)); 2182 drm_WARN_ON(&i915->drm, !fb->format->is_yuv || 2183 fb->format->num_planes == 1); 2184 2185 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2186 plane_state->planar_linked_plane, 0); 2187 if (ret) 2188 return ret; 2189 2190 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2191 plane, 1); 2192 if (ret) 2193 return ret; 2194 } else if (intel_wm_plane_visible(crtc_state, plane_state)) { 2195 ret = skl_build_plane_wm_single(crtc_state, plane_state, 2196 plane, 0); 2197 if (ret) 2198 return ret; 2199 } 2200 2201 return 0; 2202 } 2203 2204 static bool 2205 skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state, 2206 int wm0_lines, int latency) 2207 { 2208 const struct drm_display_mode *adjusted_mode = 2209 &crtc_state->hw.adjusted_mode; 2210 2211 /* FIXME missing scaler and DSC pre-fill time */ 2212 return crtc_state->framestart_delay + 2213 intel_usecs_to_scanlines(adjusted_mode, latency) + 2214 wm0_lines > 2215 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start; 2216 } 2217 2218 static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state) 2219 { 2220 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2221 enum plane_id plane_id; 2222 int wm0_lines = 0; 2223 2224 for_each_plane_id_on_crtc(crtc, plane_id) { 2225 const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; 2226 2227 /* FIXME what about !skl_wm_has_lines() platforms? */ 2228 wm0_lines = max_t(int, wm0_lines, wm->wm[0].lines); 2229 } 2230 2231 return wm0_lines; 2232 } 2233 2234 static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state, 2235 int wm0_lines) 2236 { 2237 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2238 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2239 int level; 2240 2241 for (level = i915->display.wm.num_levels - 1; level >= 0; level--) { 2242 int latency; 2243 2244 /* FIXME should we care about the latency w/a's? */ 2245 latency = skl_wm_latency(i915, level, NULL); 2246 if (latency == 0) 2247 continue; 2248 2249 /* FIXME is it correct to use 0 latency for wm0 here? */ 2250 if (level == 0) 2251 latency = 0; 2252 2253 if (!skl_is_vblank_too_short(crtc_state, wm0_lines, latency)) 2254 return level; 2255 } 2256 2257 return -EINVAL; 2258 } 2259 2260 static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state) 2261 { 2262 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2263 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2264 int wm0_lines, level; 2265 2266 if (!crtc_state->hw.active) 2267 return 0; 2268 2269 wm0_lines = skl_max_wm0_lines(crtc_state); 2270 2271 level = skl_max_wm_level_for_vblank(crtc_state, wm0_lines); 2272 if (level < 0) 2273 return level; 2274 2275 /* 2276 * FIXME PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_* 2277 * based on whether we're limited by the vblank duration. 2278 * 2279 * FIXME also related to skl+ w/a 1136 (also unimplemented as of 2280 * now) perhaps? 2281 */ 2282 2283 for (level++; level < i915->display.wm.num_levels; level++) { 2284 enum plane_id plane_id; 2285 2286 for_each_plane_id_on_crtc(crtc, plane_id) { 2287 struct skl_plane_wm *wm = 2288 &crtc_state->wm.skl.optimal.planes[plane_id]; 2289 2290 /* 2291 * FIXME just clear enable or flag the entire 2292 * thing as bad via min_ddb_alloc=U16_MAX? 2293 */ 2294 wm->wm[level].enable = false; 2295 wm->uv_wm[level].enable = false; 2296 } 2297 } 2298 2299 if (DISPLAY_VER(i915) >= 12 && 2300 i915->display.sagv.block_time_us && 2301 skl_is_vblank_too_short(crtc_state, wm0_lines, 2302 i915->display.sagv.block_time_us)) { 2303 enum plane_id plane_id; 2304 2305 for_each_plane_id_on_crtc(crtc, plane_id) { 2306 struct skl_plane_wm *wm = 2307 &crtc_state->wm.skl.optimal.planes[plane_id]; 2308 2309 wm->sagv.wm0.enable = false; 2310 wm->sagv.trans_wm.enable = false; 2311 } 2312 } 2313 2314 return 0; 2315 } 2316 2317 static int skl_build_pipe_wm(struct intel_atomic_state *state, 2318 struct intel_crtc *crtc) 2319 { 2320 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2321 struct intel_crtc_state *crtc_state = 2322 intel_atomic_get_new_crtc_state(state, crtc); 2323 const struct intel_plane_state *plane_state; 2324 struct intel_plane *plane; 2325 int ret, i; 2326 2327 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 2328 /* 2329 * FIXME should perhaps check {old,new}_plane_crtc->hw.crtc 2330 * instead but we don't populate that correctly for NV12 Y 2331 * planes so for now hack this. 2332 */ 2333 if (plane->pipe != crtc->pipe) 2334 continue; 2335 2336 if (DISPLAY_VER(i915) >= 11) 2337 ret = icl_build_plane_wm(crtc_state, plane_state); 2338 else 2339 ret = skl_build_plane_wm(crtc_state, plane_state); 2340 if (ret) 2341 return ret; 2342 } 2343 2344 crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw; 2345 2346 return skl_wm_check_vblank(crtc_state); 2347 } 2348 2349 static void skl_ddb_entry_write(struct drm_i915_private *i915, 2350 i915_reg_t reg, 2351 const struct skl_ddb_entry *entry) 2352 { 2353 if (entry->end) 2354 intel_de_write_fw(i915, reg, 2355 PLANE_BUF_END(entry->end - 1) | 2356 PLANE_BUF_START(entry->start)); 2357 else 2358 intel_de_write_fw(i915, reg, 0); 2359 } 2360 2361 static void skl_write_wm_level(struct drm_i915_private *i915, 2362 i915_reg_t reg, 2363 const struct skl_wm_level *level) 2364 { 2365 u32 val = 0; 2366 2367 if (level->enable) 2368 val |= PLANE_WM_EN; 2369 if (level->ignore_lines) 2370 val |= PLANE_WM_IGNORE_LINES; 2371 val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks); 2372 val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines); 2373 2374 intel_de_write_fw(i915, reg, val); 2375 } 2376 2377 void skl_write_plane_wm(struct intel_plane *plane, 2378 const struct intel_crtc_state *crtc_state) 2379 { 2380 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2381 enum plane_id plane_id = plane->id; 2382 enum pipe pipe = plane->pipe; 2383 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; 2384 const struct skl_ddb_entry *ddb = 2385 &crtc_state->wm.skl.plane_ddb[plane_id]; 2386 const struct skl_ddb_entry *ddb_y = 2387 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 2388 int level; 2389 2390 for (level = 0; level < i915->display.wm.num_levels; level++) 2391 skl_write_wm_level(i915, PLANE_WM(pipe, plane_id, level), 2392 skl_plane_wm_level(pipe_wm, plane_id, level)); 2393 2394 skl_write_wm_level(i915, PLANE_WM_TRANS(pipe, plane_id), 2395 skl_plane_trans_wm(pipe_wm, plane_id)); 2396 2397 if (HAS_HW_SAGV_WM(i915)) { 2398 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; 2399 2400 skl_write_wm_level(i915, PLANE_WM_SAGV(pipe, plane_id), 2401 &wm->sagv.wm0); 2402 skl_write_wm_level(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id), 2403 &wm->sagv.trans_wm); 2404 } 2405 2406 skl_ddb_entry_write(i915, 2407 PLANE_BUF_CFG(pipe, plane_id), ddb); 2408 2409 if (DISPLAY_VER(i915) < 11) 2410 skl_ddb_entry_write(i915, 2411 PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_y); 2412 } 2413 2414 void skl_write_cursor_wm(struct intel_plane *plane, 2415 const struct intel_crtc_state *crtc_state) 2416 { 2417 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2418 enum plane_id plane_id = plane->id; 2419 enum pipe pipe = plane->pipe; 2420 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; 2421 const struct skl_ddb_entry *ddb = 2422 &crtc_state->wm.skl.plane_ddb[plane_id]; 2423 int level; 2424 2425 for (level = 0; level < i915->display.wm.num_levels; level++) 2426 skl_write_wm_level(i915, CUR_WM(pipe, level), 2427 skl_plane_wm_level(pipe_wm, plane_id, level)); 2428 2429 skl_write_wm_level(i915, CUR_WM_TRANS(pipe), 2430 skl_plane_trans_wm(pipe_wm, plane_id)); 2431 2432 if (HAS_HW_SAGV_WM(i915)) { 2433 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; 2434 2435 skl_write_wm_level(i915, CUR_WM_SAGV(pipe), 2436 &wm->sagv.wm0); 2437 skl_write_wm_level(i915, CUR_WM_SAGV_TRANS(pipe), 2438 &wm->sagv.trans_wm); 2439 } 2440 2441 skl_ddb_entry_write(i915, CUR_BUF_CFG(pipe), ddb); 2442 } 2443 2444 static bool skl_wm_level_equals(const struct skl_wm_level *l1, 2445 const struct skl_wm_level *l2) 2446 { 2447 return l1->enable == l2->enable && 2448 l1->ignore_lines == l2->ignore_lines && 2449 l1->lines == l2->lines && 2450 l1->blocks == l2->blocks; 2451 } 2452 2453 static bool skl_plane_wm_equals(struct drm_i915_private *i915, 2454 const struct skl_plane_wm *wm1, 2455 const struct skl_plane_wm *wm2) 2456 { 2457 int level; 2458 2459 for (level = 0; level < i915->display.wm.num_levels; level++) { 2460 /* 2461 * We don't check uv_wm as the hardware doesn't actually 2462 * use it. It only gets used for calculating the required 2463 * ddb allocation. 2464 */ 2465 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level])) 2466 return false; 2467 } 2468 2469 return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm) && 2470 skl_wm_level_equals(&wm1->sagv.wm0, &wm2->sagv.wm0) && 2471 skl_wm_level_equals(&wm1->sagv.trans_wm, &wm2->sagv.trans_wm); 2472 } 2473 2474 static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a, 2475 const struct skl_ddb_entry *b) 2476 { 2477 return a->start < b->end && b->start < a->end; 2478 } 2479 2480 static void skl_ddb_entry_union(struct skl_ddb_entry *a, 2481 const struct skl_ddb_entry *b) 2482 { 2483 if (a->end && b->end) { 2484 a->start = min(a->start, b->start); 2485 a->end = max(a->end, b->end); 2486 } else if (b->end) { 2487 a->start = b->start; 2488 a->end = b->end; 2489 } 2490 } 2491 2492 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, 2493 const struct skl_ddb_entry *entries, 2494 int num_entries, int ignore_idx) 2495 { 2496 int i; 2497 2498 for (i = 0; i < num_entries; i++) { 2499 if (i != ignore_idx && 2500 skl_ddb_entries_overlap(ddb, &entries[i])) 2501 return true; 2502 } 2503 2504 return false; 2505 } 2506 2507 static int 2508 skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state, 2509 struct intel_crtc_state *new_crtc_state) 2510 { 2511 struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->uapi.state); 2512 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 2513 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2514 struct intel_plane *plane; 2515 2516 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 2517 struct intel_plane_state *plane_state; 2518 enum plane_id plane_id = plane->id; 2519 2520 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb[plane_id], 2521 &new_crtc_state->wm.skl.plane_ddb[plane_id]) && 2522 skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id], 2523 &new_crtc_state->wm.skl.plane_ddb_y[plane_id])) 2524 continue; 2525 2526 plane_state = intel_atomic_get_plane_state(state, plane); 2527 if (IS_ERR(plane_state)) 2528 return PTR_ERR(plane_state); 2529 2530 new_crtc_state->update_planes |= BIT(plane_id); 2531 new_crtc_state->async_flip_planes = 0; 2532 new_crtc_state->do_async_flip = false; 2533 } 2534 2535 return 0; 2536 } 2537 2538 static u8 intel_dbuf_enabled_slices(const struct intel_dbuf_state *dbuf_state) 2539 { 2540 struct drm_i915_private *i915 = to_i915(dbuf_state->base.state->base.dev); 2541 u8 enabled_slices; 2542 enum pipe pipe; 2543 2544 /* 2545 * FIXME: For now we always enable slice S1 as per 2546 * the Bspec display initialization sequence. 2547 */ 2548 enabled_slices = BIT(DBUF_S1); 2549 2550 for_each_pipe(i915, pipe) 2551 enabled_slices |= dbuf_state->slices[pipe]; 2552 2553 return enabled_slices; 2554 } 2555 2556 static int 2557 skl_compute_ddb(struct intel_atomic_state *state) 2558 { 2559 struct drm_i915_private *i915 = to_i915(state->base.dev); 2560 const struct intel_dbuf_state *old_dbuf_state; 2561 struct intel_dbuf_state *new_dbuf_state = NULL; 2562 const struct intel_crtc_state *old_crtc_state; 2563 struct intel_crtc_state *new_crtc_state; 2564 struct intel_crtc *crtc; 2565 int ret, i; 2566 2567 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2568 new_dbuf_state = intel_atomic_get_dbuf_state(state); 2569 if (IS_ERR(new_dbuf_state)) 2570 return PTR_ERR(new_dbuf_state); 2571 2572 old_dbuf_state = intel_atomic_get_old_dbuf_state(state); 2573 break; 2574 } 2575 2576 if (!new_dbuf_state) 2577 return 0; 2578 2579 new_dbuf_state->active_pipes = 2580 intel_calc_active_pipes(state, old_dbuf_state->active_pipes); 2581 2582 if (old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) { 2583 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 2584 if (ret) 2585 return ret; 2586 } 2587 2588 if (HAS_MBUS_JOINING(i915)) 2589 new_dbuf_state->joined_mbus = 2590 adlp_check_mbus_joined(new_dbuf_state->active_pipes); 2591 2592 for_each_intel_crtc(&i915->drm, crtc) { 2593 enum pipe pipe = crtc->pipe; 2594 2595 new_dbuf_state->slices[pipe] = 2596 skl_compute_dbuf_slices(crtc, new_dbuf_state->active_pipes, 2597 new_dbuf_state->joined_mbus); 2598 2599 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe]) 2600 continue; 2601 2602 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 2603 if (ret) 2604 return ret; 2605 } 2606 2607 new_dbuf_state->enabled_slices = intel_dbuf_enabled_slices(new_dbuf_state); 2608 2609 if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices || 2610 old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) { 2611 ret = intel_atomic_serialize_global_state(&new_dbuf_state->base); 2612 if (ret) 2613 return ret; 2614 2615 if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) { 2616 /* TODO: Implement vblank synchronized MBUS joining changes */ 2617 ret = intel_modeset_all_pipes(state, "MBUS joining change"); 2618 if (ret) 2619 return ret; 2620 } 2621 2622 drm_dbg_kms(&i915->drm, 2623 "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n", 2624 old_dbuf_state->enabled_slices, 2625 new_dbuf_state->enabled_slices, 2626 INTEL_INFO(i915)->display.dbuf.slice_mask, 2627 str_yes_no(old_dbuf_state->joined_mbus), 2628 str_yes_no(new_dbuf_state->joined_mbus)); 2629 } 2630 2631 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2632 enum pipe pipe = crtc->pipe; 2633 2634 new_dbuf_state->weight[pipe] = intel_crtc_ddb_weight(new_crtc_state); 2635 2636 if (old_dbuf_state->weight[pipe] == new_dbuf_state->weight[pipe]) 2637 continue; 2638 2639 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); 2640 if (ret) 2641 return ret; 2642 } 2643 2644 for_each_intel_crtc(&i915->drm, crtc) { 2645 ret = skl_crtc_allocate_ddb(state, crtc); 2646 if (ret) 2647 return ret; 2648 } 2649 2650 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 2651 new_crtc_state, i) { 2652 ret = skl_crtc_allocate_plane_ddb(state, crtc); 2653 if (ret) 2654 return ret; 2655 2656 ret = skl_ddb_add_affected_planes(old_crtc_state, 2657 new_crtc_state); 2658 if (ret) 2659 return ret; 2660 } 2661 2662 return 0; 2663 } 2664 2665 static char enast(bool enable) 2666 { 2667 return enable ? '*' : ' '; 2668 } 2669 2670 static void 2671 skl_print_wm_changes(struct intel_atomic_state *state) 2672 { 2673 struct drm_i915_private *i915 = to_i915(state->base.dev); 2674 const struct intel_crtc_state *old_crtc_state; 2675 const struct intel_crtc_state *new_crtc_state; 2676 struct intel_plane *plane; 2677 struct intel_crtc *crtc; 2678 int i; 2679 2680 if (!drm_debug_enabled(DRM_UT_KMS)) 2681 return; 2682 2683 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 2684 new_crtc_state, i) { 2685 const struct skl_pipe_wm *old_pipe_wm, *new_pipe_wm; 2686 2687 old_pipe_wm = &old_crtc_state->wm.skl.optimal; 2688 new_pipe_wm = &new_crtc_state->wm.skl.optimal; 2689 2690 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 2691 enum plane_id plane_id = plane->id; 2692 const struct skl_ddb_entry *old, *new; 2693 2694 old = &old_crtc_state->wm.skl.plane_ddb[plane_id]; 2695 new = &new_crtc_state->wm.skl.plane_ddb[plane_id]; 2696 2697 if (skl_ddb_entry_equal(old, new)) 2698 continue; 2699 2700 drm_dbg_kms(&i915->drm, 2701 "[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n", 2702 plane->base.base.id, plane->base.name, 2703 old->start, old->end, new->start, new->end, 2704 skl_ddb_entry_size(old), skl_ddb_entry_size(new)); 2705 } 2706 2707 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 2708 enum plane_id plane_id = plane->id; 2709 const struct skl_plane_wm *old_wm, *new_wm; 2710 2711 old_wm = &old_pipe_wm->planes[plane_id]; 2712 new_wm = &new_pipe_wm->planes[plane_id]; 2713 2714 if (skl_plane_wm_equals(i915, old_wm, new_wm)) 2715 continue; 2716 2717 drm_dbg_kms(&i915->drm, 2718 "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm" 2719 " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n", 2720 plane->base.base.id, plane->base.name, 2721 enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable), 2722 enast(old_wm->wm[2].enable), enast(old_wm->wm[3].enable), 2723 enast(old_wm->wm[4].enable), enast(old_wm->wm[5].enable), 2724 enast(old_wm->wm[6].enable), enast(old_wm->wm[7].enable), 2725 enast(old_wm->trans_wm.enable), 2726 enast(old_wm->sagv.wm0.enable), 2727 enast(old_wm->sagv.trans_wm.enable), 2728 enast(new_wm->wm[0].enable), enast(new_wm->wm[1].enable), 2729 enast(new_wm->wm[2].enable), enast(new_wm->wm[3].enable), 2730 enast(new_wm->wm[4].enable), enast(new_wm->wm[5].enable), 2731 enast(new_wm->wm[6].enable), enast(new_wm->wm[7].enable), 2732 enast(new_wm->trans_wm.enable), 2733 enast(new_wm->sagv.wm0.enable), 2734 enast(new_wm->sagv.trans_wm.enable)); 2735 2736 drm_dbg_kms(&i915->drm, 2737 "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d" 2738 " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n", 2739 plane->base.base.id, plane->base.name, 2740 enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines, 2741 enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].lines, 2742 enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].lines, 2743 enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].lines, 2744 enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].lines, 2745 enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].lines, 2746 enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].lines, 2747 enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].lines, 2748 enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.lines, 2749 enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.lines, 2750 enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.lines, 2751 enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].lines, 2752 enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].lines, 2753 enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].lines, 2754 enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].lines, 2755 enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].lines, 2756 enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].lines, 2757 enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].lines, 2758 enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].lines, 2759 enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.lines, 2760 enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.lines, 2761 enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines); 2762 2763 drm_dbg_kms(&i915->drm, 2764 "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" 2765 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", 2766 plane->base.base.id, plane->base.name, 2767 old_wm->wm[0].blocks, old_wm->wm[1].blocks, 2768 old_wm->wm[2].blocks, old_wm->wm[3].blocks, 2769 old_wm->wm[4].blocks, old_wm->wm[5].blocks, 2770 old_wm->wm[6].blocks, old_wm->wm[7].blocks, 2771 old_wm->trans_wm.blocks, 2772 old_wm->sagv.wm0.blocks, 2773 old_wm->sagv.trans_wm.blocks, 2774 new_wm->wm[0].blocks, new_wm->wm[1].blocks, 2775 new_wm->wm[2].blocks, new_wm->wm[3].blocks, 2776 new_wm->wm[4].blocks, new_wm->wm[5].blocks, 2777 new_wm->wm[6].blocks, new_wm->wm[7].blocks, 2778 new_wm->trans_wm.blocks, 2779 new_wm->sagv.wm0.blocks, 2780 new_wm->sagv.trans_wm.blocks); 2781 2782 drm_dbg_kms(&i915->drm, 2783 "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" 2784 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", 2785 plane->base.base.id, plane->base.name, 2786 old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc, 2787 old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc, 2788 old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc, 2789 old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc, 2790 old_wm->trans_wm.min_ddb_alloc, 2791 old_wm->sagv.wm0.min_ddb_alloc, 2792 old_wm->sagv.trans_wm.min_ddb_alloc, 2793 new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc, 2794 new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc, 2795 new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc, 2796 new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc, 2797 new_wm->trans_wm.min_ddb_alloc, 2798 new_wm->sagv.wm0.min_ddb_alloc, 2799 new_wm->sagv.trans_wm.min_ddb_alloc); 2800 } 2801 } 2802 } 2803 2804 static bool skl_plane_selected_wm_equals(struct intel_plane *plane, 2805 const struct skl_pipe_wm *old_pipe_wm, 2806 const struct skl_pipe_wm *new_pipe_wm) 2807 { 2808 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2809 int level; 2810 2811 for (level = 0; level < i915->display.wm.num_levels; level++) { 2812 /* 2813 * We don't check uv_wm as the hardware doesn't actually 2814 * use it. It only gets used for calculating the required 2815 * ddb allocation. 2816 */ 2817 if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm, plane->id, level), 2818 skl_plane_wm_level(new_pipe_wm, plane->id, level))) 2819 return false; 2820 } 2821 2822 if (HAS_HW_SAGV_WM(i915)) { 2823 const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id]; 2824 const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id]; 2825 2826 if (!skl_wm_level_equals(&old_wm->sagv.wm0, &new_wm->sagv.wm0) || 2827 !skl_wm_level_equals(&old_wm->sagv.trans_wm, &new_wm->sagv.trans_wm)) 2828 return false; 2829 } 2830 2831 return skl_wm_level_equals(skl_plane_trans_wm(old_pipe_wm, plane->id), 2832 skl_plane_trans_wm(new_pipe_wm, plane->id)); 2833 } 2834 2835 /* 2836 * To make sure the cursor watermark registers are always consistent 2837 * with our computed state the following scenario needs special 2838 * treatment: 2839 * 2840 * 1. enable cursor 2841 * 2. move cursor entirely offscreen 2842 * 3. disable cursor 2843 * 2844 * Step 2. does call .disable_plane() but does not zero the watermarks 2845 * (since we consider an offscreen cursor still active for the purposes 2846 * of watermarks). Step 3. would not normally call .disable_plane() 2847 * because the actual plane visibility isn't changing, and we don't 2848 * deallocate the cursor ddb until the pipe gets disabled. So we must 2849 * force step 3. to call .disable_plane() to update the watermark 2850 * registers properly. 2851 * 2852 * Other planes do not suffer from this issues as their watermarks are 2853 * calculated based on the actual plane visibility. The only time this 2854 * can trigger for the other planes is during the initial readout as the 2855 * default value of the watermarks registers is not zero. 2856 */ 2857 static int skl_wm_add_affected_planes(struct intel_atomic_state *state, 2858 struct intel_crtc *crtc) 2859 { 2860 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2861 const struct intel_crtc_state *old_crtc_state = 2862 intel_atomic_get_old_crtc_state(state, crtc); 2863 struct intel_crtc_state *new_crtc_state = 2864 intel_atomic_get_new_crtc_state(state, crtc); 2865 struct intel_plane *plane; 2866 2867 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 2868 struct intel_plane_state *plane_state; 2869 enum plane_id plane_id = plane->id; 2870 2871 /* 2872 * Force a full wm update for every plane on modeset. 2873 * Required because the reset value of the wm registers 2874 * is non-zero, whereas we want all disabled planes to 2875 * have zero watermarks. So if we turn off the relevant 2876 * power well the hardware state will go out of sync 2877 * with the software state. 2878 */ 2879 if (!intel_crtc_needs_modeset(new_crtc_state) && 2880 skl_plane_selected_wm_equals(plane, 2881 &old_crtc_state->wm.skl.optimal, 2882 &new_crtc_state->wm.skl.optimal)) 2883 continue; 2884 2885 plane_state = intel_atomic_get_plane_state(state, plane); 2886 if (IS_ERR(plane_state)) 2887 return PTR_ERR(plane_state); 2888 2889 new_crtc_state->update_planes |= BIT(plane_id); 2890 new_crtc_state->async_flip_planes = 0; 2891 new_crtc_state->do_async_flip = false; 2892 } 2893 2894 return 0; 2895 } 2896 2897 static int 2898 skl_compute_wm(struct intel_atomic_state *state) 2899 { 2900 struct intel_crtc *crtc; 2901 struct intel_crtc_state *new_crtc_state; 2902 int ret, i; 2903 2904 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2905 ret = skl_build_pipe_wm(state, crtc); 2906 if (ret) 2907 return ret; 2908 } 2909 2910 ret = skl_compute_ddb(state); 2911 if (ret) 2912 return ret; 2913 2914 ret = intel_compute_sagv_mask(state); 2915 if (ret) 2916 return ret; 2917 2918 /* 2919 * skl_compute_ddb() will have adjusted the final watermarks 2920 * based on how much ddb is available. Now we can actually 2921 * check if the final watermarks changed. 2922 */ 2923 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2924 ret = skl_wm_add_affected_planes(state, crtc); 2925 if (ret) 2926 return ret; 2927 } 2928 2929 skl_print_wm_changes(state); 2930 2931 return 0; 2932 } 2933 2934 static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level) 2935 { 2936 level->enable = val & PLANE_WM_EN; 2937 level->ignore_lines = val & PLANE_WM_IGNORE_LINES; 2938 level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val); 2939 level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val); 2940 } 2941 2942 static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, 2943 struct skl_pipe_wm *out) 2944 { 2945 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2946 enum pipe pipe = crtc->pipe; 2947 enum plane_id plane_id; 2948 int level; 2949 u32 val; 2950 2951 for_each_plane_id_on_crtc(crtc, plane_id) { 2952 struct skl_plane_wm *wm = &out->planes[plane_id]; 2953 2954 for (level = 0; level < i915->display.wm.num_levels; level++) { 2955 if (plane_id != PLANE_CURSOR) 2956 val = intel_de_read(i915, PLANE_WM(pipe, plane_id, level)); 2957 else 2958 val = intel_de_read(i915, CUR_WM(pipe, level)); 2959 2960 skl_wm_level_from_reg_val(val, &wm->wm[level]); 2961 } 2962 2963 if (plane_id != PLANE_CURSOR) 2964 val = intel_de_read(i915, PLANE_WM_TRANS(pipe, plane_id)); 2965 else 2966 val = intel_de_read(i915, CUR_WM_TRANS(pipe)); 2967 2968 skl_wm_level_from_reg_val(val, &wm->trans_wm); 2969 2970 if (HAS_HW_SAGV_WM(i915)) { 2971 if (plane_id != PLANE_CURSOR) 2972 val = intel_de_read(i915, PLANE_WM_SAGV(pipe, plane_id)); 2973 else 2974 val = intel_de_read(i915, CUR_WM_SAGV(pipe)); 2975 2976 skl_wm_level_from_reg_val(val, &wm->sagv.wm0); 2977 2978 if (plane_id != PLANE_CURSOR) 2979 val = intel_de_read(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id)); 2980 else 2981 val = intel_de_read(i915, CUR_WM_SAGV_TRANS(pipe)); 2982 2983 skl_wm_level_from_reg_val(val, &wm->sagv.trans_wm); 2984 } else if (DISPLAY_VER(i915) >= 12) { 2985 wm->sagv.wm0 = wm->wm[0]; 2986 wm->sagv.trans_wm = wm->trans_wm; 2987 } 2988 } 2989 } 2990 2991 static void skl_wm_get_hw_state(struct drm_i915_private *i915) 2992 { 2993 struct intel_dbuf_state *dbuf_state = 2994 to_intel_dbuf_state(i915->display.dbuf.obj.state); 2995 struct intel_crtc *crtc; 2996 2997 if (HAS_MBUS_JOINING(i915)) 2998 dbuf_state->joined_mbus = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN; 2999 3000 for_each_intel_crtc(&i915->drm, crtc) { 3001 struct intel_crtc_state *crtc_state = 3002 to_intel_crtc_state(crtc->base.state); 3003 enum pipe pipe = crtc->pipe; 3004 unsigned int mbus_offset; 3005 enum plane_id plane_id; 3006 u8 slices; 3007 3008 memset(&crtc_state->wm.skl.optimal, 0, 3009 sizeof(crtc_state->wm.skl.optimal)); 3010 if (crtc_state->hw.active) 3011 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal); 3012 crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal; 3013 3014 memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe])); 3015 3016 for_each_plane_id_on_crtc(crtc, plane_id) { 3017 struct skl_ddb_entry *ddb = 3018 &crtc_state->wm.skl.plane_ddb[plane_id]; 3019 struct skl_ddb_entry *ddb_y = 3020 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 3021 3022 if (!crtc_state->hw.active) 3023 continue; 3024 3025 skl_ddb_get_hw_plane_state(i915, crtc->pipe, 3026 plane_id, ddb, ddb_y); 3027 3028 skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb); 3029 skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y); 3030 } 3031 3032 dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state); 3033 3034 /* 3035 * Used for checking overlaps, so we need absolute 3036 * offsets instead of MBUS relative offsets. 3037 */ 3038 slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes, 3039 dbuf_state->joined_mbus); 3040 mbus_offset = mbus_ddb_offset(i915, slices); 3041 crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start; 3042 crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end; 3043 3044 /* The slices actually used by the planes on the pipe */ 3045 dbuf_state->slices[pipe] = 3046 skl_ddb_dbuf_slice_mask(i915, &crtc_state->wm.skl.ddb); 3047 3048 drm_dbg_kms(&i915->drm, 3049 "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n", 3050 crtc->base.base.id, crtc->base.name, 3051 dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start, 3052 dbuf_state->ddb[pipe].end, dbuf_state->active_pipes, 3053 str_yes_no(dbuf_state->joined_mbus)); 3054 } 3055 3056 dbuf_state->enabled_slices = i915->display.dbuf.enabled_slices; 3057 } 3058 3059 static bool skl_dbuf_is_misconfigured(struct drm_i915_private *i915) 3060 { 3061 const struct intel_dbuf_state *dbuf_state = 3062 to_intel_dbuf_state(i915->display.dbuf.obj.state); 3063 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 3064 struct intel_crtc *crtc; 3065 3066 for_each_intel_crtc(&i915->drm, crtc) { 3067 const struct intel_crtc_state *crtc_state = 3068 to_intel_crtc_state(crtc->base.state); 3069 3070 entries[crtc->pipe] = crtc_state->wm.skl.ddb; 3071 } 3072 3073 for_each_intel_crtc(&i915->drm, crtc) { 3074 const struct intel_crtc_state *crtc_state = 3075 to_intel_crtc_state(crtc->base.state); 3076 u8 slices; 3077 3078 slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes, 3079 dbuf_state->joined_mbus); 3080 if (dbuf_state->slices[crtc->pipe] & ~slices) 3081 return true; 3082 3083 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries, 3084 I915_MAX_PIPES, crtc->pipe)) 3085 return true; 3086 } 3087 3088 return false; 3089 } 3090 3091 static void skl_wm_sanitize(struct drm_i915_private *i915) 3092 { 3093 struct intel_crtc *crtc; 3094 3095 /* 3096 * On TGL/RKL (at least) the BIOS likes to assign the planes 3097 * to the wrong DBUF slices. This will cause an infinite loop 3098 * in skl_commit_modeset_enables() as it can't find a way to 3099 * transition between the old bogus DBUF layout to the new 3100 * proper DBUF layout without DBUF allocation overlaps between 3101 * the planes (which cannot be allowed or else the hardware 3102 * may hang). If we detect a bogus DBUF layout just turn off 3103 * all the planes so that skl_commit_modeset_enables() can 3104 * simply ignore them. 3105 */ 3106 if (!skl_dbuf_is_misconfigured(i915)) 3107 return; 3108 3109 drm_dbg_kms(&i915->drm, "BIOS has misprogrammed the DBUF, disabling all planes\n"); 3110 3111 for_each_intel_crtc(&i915->drm, crtc) { 3112 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3113 const struct intel_plane_state *plane_state = 3114 to_intel_plane_state(plane->base.state); 3115 struct intel_crtc_state *crtc_state = 3116 to_intel_crtc_state(crtc->base.state); 3117 3118 if (plane_state->uapi.visible) 3119 intel_plane_disable_noatomic(crtc, plane); 3120 3121 drm_WARN_ON(&i915->drm, crtc_state->active_planes != 0); 3122 3123 memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb)); 3124 } 3125 } 3126 3127 static void skl_wm_get_hw_state_and_sanitize(struct drm_i915_private *i915) 3128 { 3129 skl_wm_get_hw_state(i915); 3130 skl_wm_sanitize(i915); 3131 } 3132 3133 void intel_wm_state_verify(struct intel_crtc *crtc, 3134 struct intel_crtc_state *new_crtc_state) 3135 { 3136 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3137 struct skl_hw_state { 3138 struct skl_ddb_entry ddb[I915_MAX_PLANES]; 3139 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; 3140 struct skl_pipe_wm wm; 3141 } *hw; 3142 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; 3143 struct intel_plane *plane; 3144 u8 hw_enabled_slices; 3145 int level; 3146 3147 if (DISPLAY_VER(i915) < 9 || !new_crtc_state->hw.active) 3148 return; 3149 3150 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 3151 if (!hw) 3152 return; 3153 3154 skl_pipe_wm_get_hw_state(crtc, &hw->wm); 3155 3156 skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y); 3157 3158 hw_enabled_slices = intel_enabled_dbuf_slices_mask(i915); 3159 3160 if (DISPLAY_VER(i915) >= 11 && 3161 hw_enabled_slices != i915->display.dbuf.enabled_slices) 3162 drm_err(&i915->drm, 3163 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", 3164 i915->display.dbuf.enabled_slices, 3165 hw_enabled_slices); 3166 3167 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 3168 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 3169 const struct skl_wm_level *hw_wm_level, *sw_wm_level; 3170 3171 /* Watermarks */ 3172 for (level = 0; level < i915->display.wm.num_levels; level++) { 3173 hw_wm_level = &hw->wm.planes[plane->id].wm[level]; 3174 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); 3175 3176 if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) 3177 continue; 3178 3179 drm_err(&i915->drm, 3180 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3181 plane->base.base.id, plane->base.name, level, 3182 sw_wm_level->enable, 3183 sw_wm_level->blocks, 3184 sw_wm_level->lines, 3185 hw_wm_level->enable, 3186 hw_wm_level->blocks, 3187 hw_wm_level->lines); 3188 } 3189 3190 hw_wm_level = &hw->wm.planes[plane->id].trans_wm; 3191 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); 3192 3193 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3194 drm_err(&i915->drm, 3195 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3196 plane->base.base.id, plane->base.name, 3197 sw_wm_level->enable, 3198 sw_wm_level->blocks, 3199 sw_wm_level->lines, 3200 hw_wm_level->enable, 3201 hw_wm_level->blocks, 3202 hw_wm_level->lines); 3203 } 3204 3205 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; 3206 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; 3207 3208 if (HAS_HW_SAGV_WM(i915) && 3209 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3210 drm_err(&i915->drm, 3211 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3212 plane->base.base.id, plane->base.name, 3213 sw_wm_level->enable, 3214 sw_wm_level->blocks, 3215 sw_wm_level->lines, 3216 hw_wm_level->enable, 3217 hw_wm_level->blocks, 3218 hw_wm_level->lines); 3219 } 3220 3221 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; 3222 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; 3223 3224 if (HAS_HW_SAGV_WM(i915) && 3225 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3226 drm_err(&i915->drm, 3227 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3228 plane->base.base.id, plane->base.name, 3229 sw_wm_level->enable, 3230 sw_wm_level->blocks, 3231 sw_wm_level->lines, 3232 hw_wm_level->enable, 3233 hw_wm_level->blocks, 3234 hw_wm_level->lines); 3235 } 3236 3237 /* DDB */ 3238 hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; 3239 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 3240 3241 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 3242 drm_err(&i915->drm, 3243 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", 3244 plane->base.base.id, plane->base.name, 3245 sw_ddb_entry->start, sw_ddb_entry->end, 3246 hw_ddb_entry->start, hw_ddb_entry->end); 3247 } 3248 } 3249 3250 kfree(hw); 3251 } 3252 3253 bool skl_watermark_ipc_enabled(struct drm_i915_private *i915) 3254 { 3255 return i915->display.wm.ipc_enabled; 3256 } 3257 3258 void skl_watermark_ipc_update(struct drm_i915_private *i915) 3259 { 3260 if (!HAS_IPC(i915)) 3261 return; 3262 3263 intel_de_rmw(i915, DISP_ARB_CTL2, DISP_IPC_ENABLE, 3264 skl_watermark_ipc_enabled(i915) ? DISP_IPC_ENABLE : 0); 3265 } 3266 3267 static bool skl_watermark_ipc_can_enable(struct drm_i915_private *i915) 3268 { 3269 /* Display WA #0477 WaDisableIPC: skl */ 3270 if (IS_SKYLAKE(i915)) 3271 return false; 3272 3273 /* Display WA #1141: SKL:all KBL:all CFL */ 3274 if (IS_KABYLAKE(i915) || 3275 IS_COFFEELAKE(i915) || 3276 IS_COMETLAKE(i915)) 3277 return i915->dram_info.symmetric_memory; 3278 3279 return true; 3280 } 3281 3282 void skl_watermark_ipc_init(struct drm_i915_private *i915) 3283 { 3284 if (!HAS_IPC(i915)) 3285 return; 3286 3287 i915->display.wm.ipc_enabled = skl_watermark_ipc_can_enable(i915); 3288 3289 skl_watermark_ipc_update(i915); 3290 } 3291 3292 static void 3293 adjust_wm_latency(struct drm_i915_private *i915, 3294 u16 wm[], int num_levels, int read_latency) 3295 { 3296 bool wm_lv_0_adjust_needed = i915->dram_info.wm_lv_0_adjust_needed; 3297 int i, level; 3298 3299 /* 3300 * If a level n (n > 1) has a 0us latency, all levels m (m >= n) 3301 * need to be disabled. We make sure to sanitize the values out 3302 * of the punit to satisfy this requirement. 3303 */ 3304 for (level = 1; level < num_levels; level++) { 3305 if (wm[level] == 0) { 3306 for (i = level + 1; i < num_levels; i++) 3307 wm[i] = 0; 3308 3309 num_levels = level; 3310 break; 3311 } 3312 } 3313 3314 /* 3315 * WaWmMemoryReadLatency 3316 * 3317 * punit doesn't take into account the read latency so we need 3318 * to add proper adjustement to each valid level we retrieve 3319 * from the punit when level 0 response data is 0us. 3320 */ 3321 if (wm[0] == 0) { 3322 for (level = 0; level < num_levels; level++) 3323 wm[level] += read_latency; 3324 } 3325 3326 /* 3327 * WA Level-0 adjustment for 16GB DIMMs: SKL+ 3328 * If we could not get dimm info enable this WA to prevent from 3329 * any underrun. If not able to get Dimm info assume 16GB dimm 3330 * to avoid any underrun. 3331 */ 3332 if (wm_lv_0_adjust_needed) 3333 wm[0] += 1; 3334 } 3335 3336 static void mtl_read_wm_latency(struct drm_i915_private *i915, u16 wm[]) 3337 { 3338 int num_levels = i915->display.wm.num_levels; 3339 u32 val; 3340 3341 val = intel_de_read(i915, MTL_LATENCY_LP0_LP1); 3342 wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); 3343 wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); 3344 3345 val = intel_de_read(i915, MTL_LATENCY_LP2_LP3); 3346 wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); 3347 wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); 3348 3349 val = intel_de_read(i915, MTL_LATENCY_LP4_LP5); 3350 wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); 3351 wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); 3352 3353 adjust_wm_latency(i915, wm, num_levels, 6); 3354 } 3355 3356 static void skl_read_wm_latency(struct drm_i915_private *i915, u16 wm[]) 3357 { 3358 int num_levels = i915->display.wm.num_levels; 3359 int read_latency = DISPLAY_VER(i915) >= 12 ? 3 : 2; 3360 int mult = IS_DG2(i915) ? 2 : 1; 3361 u32 val; 3362 int ret; 3363 3364 /* read the first set of memory latencies[0:3] */ 3365 val = 0; /* data0 to be programmed to 0 for first set */ 3366 ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL); 3367 if (ret) { 3368 drm_err(&i915->drm, "SKL Mailbox read error = %d\n", ret); 3369 return; 3370 } 3371 3372 wm[0] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; 3373 wm[1] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; 3374 wm[2] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; 3375 wm[3] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; 3376 3377 /* read the second set of memory latencies[4:7] */ 3378 val = 1; /* data0 to be programmed to 1 for second set */ 3379 ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL); 3380 if (ret) { 3381 drm_err(&i915->drm, "SKL Mailbox read error = %d\n", ret); 3382 return; 3383 } 3384 3385 wm[4] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; 3386 wm[5] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; 3387 wm[6] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; 3388 wm[7] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; 3389 3390 adjust_wm_latency(i915, wm, num_levels, read_latency); 3391 } 3392 3393 static void skl_setup_wm_latency(struct drm_i915_private *i915) 3394 { 3395 if (HAS_HW_SAGV_WM(i915)) 3396 i915->display.wm.num_levels = 6; 3397 else 3398 i915->display.wm.num_levels = 8; 3399 3400 if (DISPLAY_VER(i915) >= 14) 3401 mtl_read_wm_latency(i915, i915->display.wm.skl_latency); 3402 else 3403 skl_read_wm_latency(i915, i915->display.wm.skl_latency); 3404 3405 intel_print_wm_latency(i915, "Gen9 Plane", i915->display.wm.skl_latency); 3406 } 3407 3408 static const struct intel_wm_funcs skl_wm_funcs = { 3409 .compute_global_watermarks = skl_compute_wm, 3410 .get_hw_state = skl_wm_get_hw_state_and_sanitize, 3411 }; 3412 3413 void skl_wm_init(struct drm_i915_private *i915) 3414 { 3415 intel_sagv_init(i915); 3416 3417 skl_setup_wm_latency(i915); 3418 3419 i915->display.funcs.wm = &skl_wm_funcs; 3420 } 3421 3422 static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj) 3423 { 3424 struct intel_dbuf_state *dbuf_state; 3425 3426 dbuf_state = kmemdup(obj->state, sizeof(*dbuf_state), GFP_KERNEL); 3427 if (!dbuf_state) 3428 return NULL; 3429 3430 return &dbuf_state->base; 3431 } 3432 3433 static void intel_dbuf_destroy_state(struct intel_global_obj *obj, 3434 struct intel_global_state *state) 3435 { 3436 kfree(state); 3437 } 3438 3439 static const struct intel_global_state_funcs intel_dbuf_funcs = { 3440 .atomic_duplicate_state = intel_dbuf_duplicate_state, 3441 .atomic_destroy_state = intel_dbuf_destroy_state, 3442 }; 3443 3444 struct intel_dbuf_state * 3445 intel_atomic_get_dbuf_state(struct intel_atomic_state *state) 3446 { 3447 struct drm_i915_private *i915 = to_i915(state->base.dev); 3448 struct intel_global_state *dbuf_state; 3449 3450 dbuf_state = intel_atomic_get_global_obj_state(state, &i915->display.dbuf.obj); 3451 if (IS_ERR(dbuf_state)) 3452 return ERR_CAST(dbuf_state); 3453 3454 return to_intel_dbuf_state(dbuf_state); 3455 } 3456 3457 int intel_dbuf_init(struct drm_i915_private *i915) 3458 { 3459 struct intel_dbuf_state *dbuf_state; 3460 3461 dbuf_state = kzalloc(sizeof(*dbuf_state), GFP_KERNEL); 3462 if (!dbuf_state) 3463 return -ENOMEM; 3464 3465 intel_atomic_global_obj_init(i915, &i915->display.dbuf.obj, 3466 &dbuf_state->base, &intel_dbuf_funcs); 3467 3468 return 0; 3469 } 3470 3471 /* 3472 * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before 3473 * update the request state of all DBUS slices. 3474 */ 3475 static void update_mbus_pre_enable(struct intel_atomic_state *state) 3476 { 3477 struct drm_i915_private *i915 = to_i915(state->base.dev); 3478 u32 mbus_ctl, dbuf_min_tracker_val; 3479 enum dbuf_slice slice; 3480 const struct intel_dbuf_state *dbuf_state = 3481 intel_atomic_get_new_dbuf_state(state); 3482 3483 if (!HAS_MBUS_JOINING(i915)) 3484 return; 3485 3486 /* 3487 * TODO: Implement vblank synchronized MBUS joining changes. 3488 * Must be properly coordinated with dbuf reprogramming. 3489 */ 3490 if (dbuf_state->joined_mbus) { 3491 mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN | 3492 MBUS_JOIN_PIPE_SELECT_NONE; 3493 dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3); 3494 } else { 3495 mbus_ctl = MBUS_HASHING_MODE_2x2 | 3496 MBUS_JOIN_PIPE_SELECT_NONE; 3497 dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1); 3498 } 3499 3500 intel_de_rmw(i915, MBUS_CTL, 3501 MBUS_HASHING_MODE_MASK | MBUS_JOIN | 3502 MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl); 3503 3504 for_each_dbuf_slice(i915, slice) 3505 intel_de_rmw(i915, DBUF_CTL_S(slice), 3506 DBUF_MIN_TRACKER_STATE_SERVICE_MASK, 3507 dbuf_min_tracker_val); 3508 } 3509 3510 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state) 3511 { 3512 struct drm_i915_private *i915 = to_i915(state->base.dev); 3513 const struct intel_dbuf_state *new_dbuf_state = 3514 intel_atomic_get_new_dbuf_state(state); 3515 const struct intel_dbuf_state *old_dbuf_state = 3516 intel_atomic_get_old_dbuf_state(state); 3517 3518 if (!new_dbuf_state || 3519 (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices && 3520 new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus)) 3521 return; 3522 3523 WARN_ON(!new_dbuf_state->base.changed); 3524 3525 update_mbus_pre_enable(state); 3526 gen9_dbuf_slices_update(i915, 3527 old_dbuf_state->enabled_slices | 3528 new_dbuf_state->enabled_slices); 3529 } 3530 3531 void intel_dbuf_post_plane_update(struct intel_atomic_state *state) 3532 { 3533 struct drm_i915_private *i915 = to_i915(state->base.dev); 3534 const struct intel_dbuf_state *new_dbuf_state = 3535 intel_atomic_get_new_dbuf_state(state); 3536 const struct intel_dbuf_state *old_dbuf_state = 3537 intel_atomic_get_old_dbuf_state(state); 3538 3539 if (!new_dbuf_state || 3540 (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices && 3541 new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus)) 3542 return; 3543 3544 WARN_ON(!new_dbuf_state->base.changed); 3545 3546 gen9_dbuf_slices_update(i915, 3547 new_dbuf_state->enabled_slices); 3548 } 3549 3550 static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes) 3551 { 3552 switch (pipe) { 3553 case PIPE_A: 3554 return !(active_pipes & BIT(PIPE_D)); 3555 case PIPE_D: 3556 return !(active_pipes & BIT(PIPE_A)); 3557 case PIPE_B: 3558 return !(active_pipes & BIT(PIPE_C)); 3559 case PIPE_C: 3560 return !(active_pipes & BIT(PIPE_B)); 3561 default: /* to suppress compiler warning */ 3562 MISSING_CASE(pipe); 3563 break; 3564 } 3565 3566 return false; 3567 } 3568 3569 void intel_mbus_dbox_update(struct intel_atomic_state *state) 3570 { 3571 struct drm_i915_private *i915 = to_i915(state->base.dev); 3572 const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state; 3573 const struct intel_crtc_state *new_crtc_state; 3574 const struct intel_crtc *crtc; 3575 u32 val = 0; 3576 int i; 3577 3578 if (DISPLAY_VER(i915) < 11) 3579 return; 3580 3581 new_dbuf_state = intel_atomic_get_new_dbuf_state(state); 3582 old_dbuf_state = intel_atomic_get_old_dbuf_state(state); 3583 if (!new_dbuf_state || 3584 (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus && 3585 new_dbuf_state->active_pipes == old_dbuf_state->active_pipes)) 3586 return; 3587 3588 if (DISPLAY_VER(i915) >= 14) 3589 val |= MBUS_DBOX_I_CREDIT(2); 3590 3591 if (DISPLAY_VER(i915) >= 12) { 3592 val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16); 3593 val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1); 3594 val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN; 3595 } 3596 3597 if (DISPLAY_VER(i915) >= 14) 3598 val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) : 3599 MBUS_DBOX_A_CREDIT(8); 3600 else if (IS_ALDERLAKE_P(i915)) 3601 /* Wa_22010947358:adl-p */ 3602 val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) : 3603 MBUS_DBOX_A_CREDIT(4); 3604 else 3605 val |= MBUS_DBOX_A_CREDIT(2); 3606 3607 if (DISPLAY_VER(i915) >= 14) { 3608 val |= MBUS_DBOX_B_CREDIT(0xA); 3609 } else if (IS_ALDERLAKE_P(i915)) { 3610 val |= MBUS_DBOX_BW_CREDIT(2); 3611 val |= MBUS_DBOX_B_CREDIT(8); 3612 } else if (DISPLAY_VER(i915) >= 12) { 3613 val |= MBUS_DBOX_BW_CREDIT(2); 3614 val |= MBUS_DBOX_B_CREDIT(12); 3615 } else { 3616 val |= MBUS_DBOX_BW_CREDIT(1); 3617 val |= MBUS_DBOX_B_CREDIT(8); 3618 } 3619 3620 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 3621 u32 pipe_val = val; 3622 3623 if (!new_crtc_state->hw.active) 3624 continue; 3625 3626 if (DISPLAY_VER(i915) >= 14) { 3627 if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, 3628 new_dbuf_state->active_pipes)) 3629 pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL; 3630 else 3631 pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL; 3632 } 3633 3634 intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val); 3635 } 3636 } 3637 3638 static int skl_watermark_ipc_status_show(struct seq_file *m, void *data) 3639 { 3640 struct drm_i915_private *i915 = m->private; 3641 3642 seq_printf(m, "Isochronous Priority Control: %s\n", 3643 str_yes_no(skl_watermark_ipc_enabled(i915))); 3644 return 0; 3645 } 3646 3647 static int skl_watermark_ipc_status_open(struct inode *inode, struct file *file) 3648 { 3649 struct drm_i915_private *i915 = inode->i_private; 3650 3651 return single_open(file, skl_watermark_ipc_status_show, i915); 3652 } 3653 3654 static ssize_t skl_watermark_ipc_status_write(struct file *file, 3655 const char __user *ubuf, 3656 size_t len, loff_t *offp) 3657 { 3658 struct seq_file *m = file->private_data; 3659 struct drm_i915_private *i915 = m->private; 3660 intel_wakeref_t wakeref; 3661 bool enable; 3662 int ret; 3663 3664 ret = kstrtobool_from_user(ubuf, len, &enable); 3665 if (ret < 0) 3666 return ret; 3667 3668 with_intel_runtime_pm(&i915->runtime_pm, wakeref) { 3669 if (!skl_watermark_ipc_enabled(i915) && enable) 3670 drm_info(&i915->drm, 3671 "Enabling IPC: WM will be proper only after next commit\n"); 3672 i915->display.wm.ipc_enabled = enable; 3673 skl_watermark_ipc_update(i915); 3674 } 3675 3676 return len; 3677 } 3678 3679 static const struct file_operations skl_watermark_ipc_status_fops = { 3680 .owner = THIS_MODULE, 3681 .open = skl_watermark_ipc_status_open, 3682 .read = seq_read, 3683 .llseek = seq_lseek, 3684 .release = single_release, 3685 .write = skl_watermark_ipc_status_write 3686 }; 3687 3688 static int intel_sagv_status_show(struct seq_file *m, void *unused) 3689 { 3690 struct drm_i915_private *i915 = m->private; 3691 static const char * const sagv_status[] = { 3692 [I915_SAGV_UNKNOWN] = "unknown", 3693 [I915_SAGV_DISABLED] = "disabled", 3694 [I915_SAGV_ENABLED] = "enabled", 3695 [I915_SAGV_NOT_CONTROLLED] = "not controlled", 3696 }; 3697 3698 seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(i915))); 3699 seq_printf(m, "SAGV status: %s\n", sagv_status[i915->display.sagv.status]); 3700 seq_printf(m, "SAGV block time: %d usec\n", i915->display.sagv.block_time_us); 3701 3702 return 0; 3703 } 3704 3705 DEFINE_SHOW_ATTRIBUTE(intel_sagv_status); 3706 3707 void skl_watermark_debugfs_register(struct drm_i915_private *i915) 3708 { 3709 struct drm_minor *minor = i915->drm.primary; 3710 3711 if (HAS_IPC(i915)) 3712 debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root, i915, 3713 &skl_watermark_ipc_status_fops); 3714 3715 if (HAS_SAGV(i915)) 3716 debugfs_create_file("i915_sagv_status", 0444, minor->debugfs_root, i915, 3717 &intel_sagv_status_fops); 3718 } 3719