1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <drm/drm_atomic_helper.h> 7 #include <drm/drm_damage_helper.h> 8 #include <drm/drm_fourcc.h> 9 #include <drm/drm_plane_helper.h> 10 11 #include "i915_drv.h" 12 #include "intel_atomic_plane.h" 13 #include "intel_de.h" 14 #include "intel_display_types.h" 15 #include "intel_fb.h" 16 #include "intel_fbc.h" 17 #include "intel_pm.h" 18 #include "intel_psr.h" 19 #include "intel_sprite.h" 20 #include "skl_scaler.h" 21 #include "skl_universal_plane.h" 22 #include "pxp/intel_pxp.h" 23 24 static const u32 skl_plane_formats[] = { 25 DRM_FORMAT_C8, 26 DRM_FORMAT_RGB565, 27 DRM_FORMAT_XRGB8888, 28 DRM_FORMAT_XBGR8888, 29 DRM_FORMAT_ARGB8888, 30 DRM_FORMAT_ABGR8888, 31 DRM_FORMAT_XRGB2101010, 32 DRM_FORMAT_XBGR2101010, 33 DRM_FORMAT_XRGB16161616F, 34 DRM_FORMAT_XBGR16161616F, 35 DRM_FORMAT_YUYV, 36 DRM_FORMAT_YVYU, 37 DRM_FORMAT_UYVY, 38 DRM_FORMAT_VYUY, 39 DRM_FORMAT_XYUV8888, 40 }; 41 42 static const u32 skl_planar_formats[] = { 43 DRM_FORMAT_C8, 44 DRM_FORMAT_RGB565, 45 DRM_FORMAT_XRGB8888, 46 DRM_FORMAT_XBGR8888, 47 DRM_FORMAT_ARGB8888, 48 DRM_FORMAT_ABGR8888, 49 DRM_FORMAT_XRGB2101010, 50 DRM_FORMAT_XBGR2101010, 51 DRM_FORMAT_XRGB16161616F, 52 DRM_FORMAT_XBGR16161616F, 53 DRM_FORMAT_YUYV, 54 DRM_FORMAT_YVYU, 55 DRM_FORMAT_UYVY, 56 DRM_FORMAT_VYUY, 57 DRM_FORMAT_NV12, 58 DRM_FORMAT_XYUV8888, 59 }; 60 61 static const u32 glk_planar_formats[] = { 62 DRM_FORMAT_C8, 63 DRM_FORMAT_RGB565, 64 DRM_FORMAT_XRGB8888, 65 DRM_FORMAT_XBGR8888, 66 DRM_FORMAT_ARGB8888, 67 DRM_FORMAT_ABGR8888, 68 DRM_FORMAT_XRGB2101010, 69 DRM_FORMAT_XBGR2101010, 70 DRM_FORMAT_XRGB16161616F, 71 DRM_FORMAT_XBGR16161616F, 72 DRM_FORMAT_YUYV, 73 DRM_FORMAT_YVYU, 74 DRM_FORMAT_UYVY, 75 DRM_FORMAT_VYUY, 76 DRM_FORMAT_NV12, 77 DRM_FORMAT_XYUV8888, 78 DRM_FORMAT_P010, 79 DRM_FORMAT_P012, 80 DRM_FORMAT_P016, 81 }; 82 83 static const u32 icl_sdr_y_plane_formats[] = { 84 DRM_FORMAT_C8, 85 DRM_FORMAT_RGB565, 86 DRM_FORMAT_XRGB8888, 87 DRM_FORMAT_XBGR8888, 88 DRM_FORMAT_ARGB8888, 89 DRM_FORMAT_ABGR8888, 90 DRM_FORMAT_XRGB2101010, 91 DRM_FORMAT_XBGR2101010, 92 DRM_FORMAT_ARGB2101010, 93 DRM_FORMAT_ABGR2101010, 94 DRM_FORMAT_YUYV, 95 DRM_FORMAT_YVYU, 96 DRM_FORMAT_UYVY, 97 DRM_FORMAT_VYUY, 98 DRM_FORMAT_Y210, 99 DRM_FORMAT_Y212, 100 DRM_FORMAT_Y216, 101 DRM_FORMAT_XYUV8888, 102 DRM_FORMAT_XVYU2101010, 103 DRM_FORMAT_XVYU12_16161616, 104 DRM_FORMAT_XVYU16161616, 105 }; 106 107 static const u32 icl_sdr_uv_plane_formats[] = { 108 DRM_FORMAT_C8, 109 DRM_FORMAT_RGB565, 110 DRM_FORMAT_XRGB8888, 111 DRM_FORMAT_XBGR8888, 112 DRM_FORMAT_ARGB8888, 113 DRM_FORMAT_ABGR8888, 114 DRM_FORMAT_XRGB2101010, 115 DRM_FORMAT_XBGR2101010, 116 DRM_FORMAT_ARGB2101010, 117 DRM_FORMAT_ABGR2101010, 118 DRM_FORMAT_YUYV, 119 DRM_FORMAT_YVYU, 120 DRM_FORMAT_UYVY, 121 DRM_FORMAT_VYUY, 122 DRM_FORMAT_NV12, 123 DRM_FORMAT_P010, 124 DRM_FORMAT_P012, 125 DRM_FORMAT_P016, 126 DRM_FORMAT_Y210, 127 DRM_FORMAT_Y212, 128 DRM_FORMAT_Y216, 129 DRM_FORMAT_XYUV8888, 130 DRM_FORMAT_XVYU2101010, 131 DRM_FORMAT_XVYU12_16161616, 132 DRM_FORMAT_XVYU16161616, 133 }; 134 135 static const u32 icl_hdr_plane_formats[] = { 136 DRM_FORMAT_C8, 137 DRM_FORMAT_RGB565, 138 DRM_FORMAT_XRGB8888, 139 DRM_FORMAT_XBGR8888, 140 DRM_FORMAT_ARGB8888, 141 DRM_FORMAT_ABGR8888, 142 DRM_FORMAT_XRGB2101010, 143 DRM_FORMAT_XBGR2101010, 144 DRM_FORMAT_ARGB2101010, 145 DRM_FORMAT_ABGR2101010, 146 DRM_FORMAT_XRGB16161616F, 147 DRM_FORMAT_XBGR16161616F, 148 DRM_FORMAT_ARGB16161616F, 149 DRM_FORMAT_ABGR16161616F, 150 DRM_FORMAT_YUYV, 151 DRM_FORMAT_YVYU, 152 DRM_FORMAT_UYVY, 153 DRM_FORMAT_VYUY, 154 DRM_FORMAT_NV12, 155 DRM_FORMAT_P010, 156 DRM_FORMAT_P012, 157 DRM_FORMAT_P016, 158 DRM_FORMAT_Y210, 159 DRM_FORMAT_Y212, 160 DRM_FORMAT_Y216, 161 DRM_FORMAT_XYUV8888, 162 DRM_FORMAT_XVYU2101010, 163 DRM_FORMAT_XVYU12_16161616, 164 DRM_FORMAT_XVYU16161616, 165 }; 166 167 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) 168 { 169 switch (format) { 170 case PLANE_CTL_FORMAT_RGB_565: 171 return DRM_FORMAT_RGB565; 172 case PLANE_CTL_FORMAT_NV12: 173 return DRM_FORMAT_NV12; 174 case PLANE_CTL_FORMAT_XYUV: 175 return DRM_FORMAT_XYUV8888; 176 case PLANE_CTL_FORMAT_P010: 177 return DRM_FORMAT_P010; 178 case PLANE_CTL_FORMAT_P012: 179 return DRM_FORMAT_P012; 180 case PLANE_CTL_FORMAT_P016: 181 return DRM_FORMAT_P016; 182 case PLANE_CTL_FORMAT_Y210: 183 return DRM_FORMAT_Y210; 184 case PLANE_CTL_FORMAT_Y212: 185 return DRM_FORMAT_Y212; 186 case PLANE_CTL_FORMAT_Y216: 187 return DRM_FORMAT_Y216; 188 case PLANE_CTL_FORMAT_Y410: 189 return DRM_FORMAT_XVYU2101010; 190 case PLANE_CTL_FORMAT_Y412: 191 return DRM_FORMAT_XVYU12_16161616; 192 case PLANE_CTL_FORMAT_Y416: 193 return DRM_FORMAT_XVYU16161616; 194 default: 195 case PLANE_CTL_FORMAT_XRGB_8888: 196 if (rgb_order) { 197 if (alpha) 198 return DRM_FORMAT_ABGR8888; 199 else 200 return DRM_FORMAT_XBGR8888; 201 } else { 202 if (alpha) 203 return DRM_FORMAT_ARGB8888; 204 else 205 return DRM_FORMAT_XRGB8888; 206 } 207 case PLANE_CTL_FORMAT_XRGB_2101010: 208 if (rgb_order) { 209 if (alpha) 210 return DRM_FORMAT_ABGR2101010; 211 else 212 return DRM_FORMAT_XBGR2101010; 213 } else { 214 if (alpha) 215 return DRM_FORMAT_ARGB2101010; 216 else 217 return DRM_FORMAT_XRGB2101010; 218 } 219 case PLANE_CTL_FORMAT_XRGB_16161616F: 220 if (rgb_order) { 221 if (alpha) 222 return DRM_FORMAT_ABGR16161616F; 223 else 224 return DRM_FORMAT_XBGR16161616F; 225 } else { 226 if (alpha) 227 return DRM_FORMAT_ARGB16161616F; 228 else 229 return DRM_FORMAT_XRGB16161616F; 230 } 231 } 232 } 233 234 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915) 235 { 236 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) 237 return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3); 238 else 239 return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5); 240 } 241 242 bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, 243 enum plane_id plane_id) 244 { 245 return DISPLAY_VER(dev_priv) >= 11 && 246 icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id); 247 } 248 249 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) 250 { 251 return DISPLAY_VER(dev_priv) >= 11 && 252 icl_hdr_plane_mask() & BIT(plane_id); 253 } 254 255 static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 256 const struct intel_plane_state *plane_state) 257 { 258 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 259 260 /* two pixels per clock */ 261 return DIV_ROUND_UP(pixel_rate, 2); 262 } 263 264 static void 265 glk_plane_ratio(const struct intel_plane_state *plane_state, 266 unsigned int *num, unsigned int *den) 267 { 268 const struct drm_framebuffer *fb = plane_state->hw.fb; 269 270 if (fb->format->cpp[0] == 8) { 271 *num = 10; 272 *den = 8; 273 } else { 274 *num = 1; 275 *den = 1; 276 } 277 } 278 279 static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 280 const struct intel_plane_state *plane_state) 281 { 282 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 283 unsigned int num, den; 284 285 glk_plane_ratio(plane_state, &num, &den); 286 287 /* two pixels per clock */ 288 return DIV_ROUND_UP(pixel_rate * num, 2 * den); 289 } 290 291 static void 292 skl_plane_ratio(const struct intel_plane_state *plane_state, 293 unsigned int *num, unsigned int *den) 294 { 295 const struct drm_framebuffer *fb = plane_state->hw.fb; 296 297 if (fb->format->cpp[0] == 8) { 298 *num = 9; 299 *den = 8; 300 } else { 301 *num = 1; 302 *den = 1; 303 } 304 } 305 306 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 307 const struct intel_plane_state *plane_state) 308 { 309 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 310 unsigned int num, den; 311 312 skl_plane_ratio(plane_state, &num, &den); 313 314 return DIV_ROUND_UP(pixel_rate * num, den); 315 } 316 317 static int skl_plane_max_width(const struct drm_framebuffer *fb, 318 int color_plane, 319 unsigned int rotation) 320 { 321 int cpp = fb->format->cpp[color_plane]; 322 323 switch (fb->modifier) { 324 case DRM_FORMAT_MOD_LINEAR: 325 case I915_FORMAT_MOD_X_TILED: 326 /* 327 * Validated limit is 4k, but has 5k should 328 * work apart from the following features: 329 * - Ytile (already limited to 4k) 330 * - FP16 (already limited to 4k) 331 * - render compression (already limited to 4k) 332 * - KVMR sprite and cursor (don't care) 333 * - horizontal panning (TODO verify this) 334 * - pipe and plane scaling (TODO verify this) 335 */ 336 if (cpp == 8) 337 return 4096; 338 else 339 return 5120; 340 case I915_FORMAT_MOD_Y_TILED_CCS: 341 case I915_FORMAT_MOD_Yf_TILED_CCS: 342 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 343 /* FIXME AUX plane? */ 344 case I915_FORMAT_MOD_Y_TILED: 345 case I915_FORMAT_MOD_Yf_TILED: 346 if (cpp == 8) 347 return 2048; 348 else 349 return 4096; 350 default: 351 MISSING_CASE(fb->modifier); 352 return 2048; 353 } 354 } 355 356 static int glk_plane_max_width(const struct drm_framebuffer *fb, 357 int color_plane, 358 unsigned int rotation) 359 { 360 int cpp = fb->format->cpp[color_plane]; 361 362 switch (fb->modifier) { 363 case DRM_FORMAT_MOD_LINEAR: 364 case I915_FORMAT_MOD_X_TILED: 365 if (cpp == 8) 366 return 4096; 367 else 368 return 5120; 369 case I915_FORMAT_MOD_Y_TILED_CCS: 370 case I915_FORMAT_MOD_Yf_TILED_CCS: 371 /* FIXME AUX plane? */ 372 case I915_FORMAT_MOD_Y_TILED: 373 case I915_FORMAT_MOD_Yf_TILED: 374 if (cpp == 8) 375 return 2048; 376 else 377 return 5120; 378 default: 379 MISSING_CASE(fb->modifier); 380 return 2048; 381 } 382 } 383 384 static int icl_plane_min_width(const struct drm_framebuffer *fb, 385 int color_plane, 386 unsigned int rotation) 387 { 388 /* Wa_14011264657, Wa_14011050563: gen11+ */ 389 switch (fb->format->format) { 390 case DRM_FORMAT_C8: 391 return 18; 392 case DRM_FORMAT_RGB565: 393 return 10; 394 case DRM_FORMAT_XRGB8888: 395 case DRM_FORMAT_XBGR8888: 396 case DRM_FORMAT_ARGB8888: 397 case DRM_FORMAT_ABGR8888: 398 case DRM_FORMAT_XRGB2101010: 399 case DRM_FORMAT_XBGR2101010: 400 case DRM_FORMAT_ARGB2101010: 401 case DRM_FORMAT_ABGR2101010: 402 case DRM_FORMAT_XVYU2101010: 403 case DRM_FORMAT_Y212: 404 case DRM_FORMAT_Y216: 405 return 6; 406 case DRM_FORMAT_NV12: 407 return 20; 408 case DRM_FORMAT_P010: 409 case DRM_FORMAT_P012: 410 case DRM_FORMAT_P016: 411 return 12; 412 case DRM_FORMAT_XRGB16161616F: 413 case DRM_FORMAT_XBGR16161616F: 414 case DRM_FORMAT_ARGB16161616F: 415 case DRM_FORMAT_ABGR16161616F: 416 case DRM_FORMAT_XVYU12_16161616: 417 case DRM_FORMAT_XVYU16161616: 418 return 4; 419 default: 420 return 1; 421 } 422 } 423 424 static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb, 425 int color_plane, 426 unsigned int rotation) 427 { 428 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 429 return 4096; 430 else 431 return 5120; 432 } 433 434 static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb, 435 int color_plane, 436 unsigned int rotation) 437 { 438 return 5120; 439 } 440 441 static int skl_plane_max_height(const struct drm_framebuffer *fb, 442 int color_plane, 443 unsigned int rotation) 444 { 445 return 4096; 446 } 447 448 static int icl_plane_max_height(const struct drm_framebuffer *fb, 449 int color_plane, 450 unsigned int rotation) 451 { 452 return 4320; 453 } 454 455 static unsigned int 456 skl_plane_max_stride(struct intel_plane *plane, 457 u32 pixel_format, u64 modifier, 458 unsigned int rotation) 459 { 460 struct drm_i915_private *i915 = to_i915(plane->base.dev); 461 const struct drm_format_info *info = drm_format_info(pixel_format); 462 int cpp = info->cpp[0]; 463 int max_horizontal_pixels = 8192; 464 int max_stride_bytes; 465 466 if (DISPLAY_VER(i915) >= 13) { 467 /* 468 * The stride in bytes must not exceed of the size 469 * of 128K bytes. For pixel formats of 64bpp will allow 470 * for a 16K pixel surface. 471 */ 472 max_stride_bytes = 131072; 473 if (cpp == 8) 474 max_horizontal_pixels = 16384; 475 else 476 max_horizontal_pixels = 65536; 477 } else { 478 /* 479 * "The stride in bytes must not exceed the 480 * of the size of 8K pixels and 32K bytes." 481 */ 482 max_stride_bytes = 32768; 483 } 484 485 if (drm_rotation_90_or_270(rotation)) 486 return min(max_horizontal_pixels, max_stride_bytes / cpp); 487 else 488 return min(max_horizontal_pixels * cpp, max_stride_bytes); 489 } 490 491 492 /* Preoffset values for YUV to RGB Conversion */ 493 #define PREOFF_YUV_TO_RGB_HI 0x1800 494 #define PREOFF_YUV_TO_RGB_ME 0x0000 495 #define PREOFF_YUV_TO_RGB_LO 0x1800 496 497 #define ROFF(x) (((x) & 0xffff) << 16) 498 #define GOFF(x) (((x) & 0xffff) << 0) 499 #define BOFF(x) (((x) & 0xffff) << 16) 500 501 /* 502 * Programs the input color space conversion stage for ICL HDR planes. 503 * Note that it is assumed that this stage always happens after YUV 504 * range correction. Thus, the input to this stage is assumed to be 505 * in full-range YCbCr. 506 */ 507 static void 508 icl_program_input_csc(struct intel_plane *plane, 509 const struct intel_crtc_state *crtc_state, 510 const struct intel_plane_state *plane_state) 511 { 512 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 513 enum pipe pipe = plane->pipe; 514 enum plane_id plane_id = plane->id; 515 516 static const u16 input_csc_matrix[][9] = { 517 /* 518 * BT.601 full range YCbCr -> full range RGB 519 * The matrix required is : 520 * [1.000, 0.000, 1.371, 521 * 1.000, -0.336, -0.698, 522 * 1.000, 1.732, 0.0000] 523 */ 524 [DRM_COLOR_YCBCR_BT601] = { 525 0x7AF8, 0x7800, 0x0, 526 0x8B28, 0x7800, 0x9AC0, 527 0x0, 0x7800, 0x7DD8, 528 }, 529 /* 530 * BT.709 full range YCbCr -> full range RGB 531 * The matrix required is : 532 * [1.000, 0.000, 1.574, 533 * 1.000, -0.187, -0.468, 534 * 1.000, 1.855, 0.0000] 535 */ 536 [DRM_COLOR_YCBCR_BT709] = { 537 0x7C98, 0x7800, 0x0, 538 0x9EF8, 0x7800, 0xAC00, 539 0x0, 0x7800, 0x7ED8, 540 }, 541 /* 542 * BT.2020 full range YCbCr -> full range RGB 543 * The matrix required is : 544 * [1.000, 0.000, 1.474, 545 * 1.000, -0.1645, -0.5713, 546 * 1.000, 1.8814, 0.0000] 547 */ 548 [DRM_COLOR_YCBCR_BT2020] = { 549 0x7BC8, 0x7800, 0x0, 550 0x8928, 0x7800, 0xAA88, 551 0x0, 0x7800, 0x7F10, 552 }, 553 }; 554 const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding]; 555 556 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), 557 ROFF(csc[0]) | GOFF(csc[1])); 558 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), 559 BOFF(csc[2])); 560 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), 561 ROFF(csc[3]) | GOFF(csc[4])); 562 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), 563 BOFF(csc[5])); 564 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), 565 ROFF(csc[6]) | GOFF(csc[7])); 566 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), 567 BOFF(csc[8])); 568 569 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), 570 PREOFF_YUV_TO_RGB_HI); 571 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 572 PREOFF_YUV_TO_RGB_ME); 573 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), 574 PREOFF_YUV_TO_RGB_LO); 575 intel_de_write_fw(dev_priv, 576 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); 577 intel_de_write_fw(dev_priv, 578 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); 579 intel_de_write_fw(dev_priv, 580 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); 581 } 582 583 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb, 584 int color_plane, unsigned int rotation) 585 { 586 /* 587 * The stride is either expressed as a multiple of 64 bytes chunks for 588 * linear buffers or in number of tiles for tiled buffers. 589 */ 590 if (is_surface_linear(fb, color_plane)) 591 return 64; 592 else if (drm_rotation_90_or_270(rotation)) 593 return intel_tile_height(fb, color_plane); 594 else 595 return intel_tile_width_bytes(fb, color_plane); 596 } 597 598 static u32 skl_plane_stride(const struct intel_plane_state *plane_state, 599 int color_plane) 600 { 601 const struct drm_framebuffer *fb = plane_state->hw.fb; 602 unsigned int rotation = plane_state->hw.rotation; 603 u32 stride = plane_state->view.color_plane[color_plane].scanout_stride; 604 605 if (color_plane >= fb->format->num_planes) 606 return 0; 607 608 return stride / skl_plane_stride_mult(fb, color_plane, rotation); 609 } 610 611 static void 612 skl_plane_disable_arm(struct intel_plane *plane, 613 const struct intel_crtc_state *crtc_state) 614 { 615 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 616 enum plane_id plane_id = plane->id; 617 enum pipe pipe = plane->pipe; 618 unsigned long irqflags; 619 620 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 621 622 if (icl_is_hdr_plane(dev_priv, plane_id)) 623 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0); 624 625 skl_write_plane_wm(plane, crtc_state); 626 627 intel_psr2_disable_plane_sel_fetch(plane, crtc_state); 628 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); 629 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); 630 631 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 632 } 633 634 static bool 635 skl_plane_get_hw_state(struct intel_plane *plane, 636 enum pipe *pipe) 637 { 638 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 639 enum intel_display_power_domain power_domain; 640 enum plane_id plane_id = plane->id; 641 intel_wakeref_t wakeref; 642 bool ret; 643 644 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 645 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 646 if (!wakeref) 647 return false; 648 649 ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; 650 651 *pipe = plane->pipe; 652 653 intel_display_power_put(dev_priv, power_domain, wakeref); 654 655 return ret; 656 } 657 658 static u32 skl_plane_ctl_format(u32 pixel_format) 659 { 660 switch (pixel_format) { 661 case DRM_FORMAT_C8: 662 return PLANE_CTL_FORMAT_INDEXED; 663 case DRM_FORMAT_RGB565: 664 return PLANE_CTL_FORMAT_RGB_565; 665 case DRM_FORMAT_XBGR8888: 666 case DRM_FORMAT_ABGR8888: 667 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; 668 case DRM_FORMAT_XRGB8888: 669 case DRM_FORMAT_ARGB8888: 670 return PLANE_CTL_FORMAT_XRGB_8888; 671 case DRM_FORMAT_XBGR2101010: 672 case DRM_FORMAT_ABGR2101010: 673 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX; 674 case DRM_FORMAT_XRGB2101010: 675 case DRM_FORMAT_ARGB2101010: 676 return PLANE_CTL_FORMAT_XRGB_2101010; 677 case DRM_FORMAT_XBGR16161616F: 678 case DRM_FORMAT_ABGR16161616F: 679 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX; 680 case DRM_FORMAT_XRGB16161616F: 681 case DRM_FORMAT_ARGB16161616F: 682 return PLANE_CTL_FORMAT_XRGB_16161616F; 683 case DRM_FORMAT_XYUV8888: 684 return PLANE_CTL_FORMAT_XYUV; 685 case DRM_FORMAT_YUYV: 686 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV; 687 case DRM_FORMAT_YVYU: 688 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU; 689 case DRM_FORMAT_UYVY: 690 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY; 691 case DRM_FORMAT_VYUY: 692 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY; 693 case DRM_FORMAT_NV12: 694 return PLANE_CTL_FORMAT_NV12; 695 case DRM_FORMAT_P010: 696 return PLANE_CTL_FORMAT_P010; 697 case DRM_FORMAT_P012: 698 return PLANE_CTL_FORMAT_P012; 699 case DRM_FORMAT_P016: 700 return PLANE_CTL_FORMAT_P016; 701 case DRM_FORMAT_Y210: 702 return PLANE_CTL_FORMAT_Y210; 703 case DRM_FORMAT_Y212: 704 return PLANE_CTL_FORMAT_Y212; 705 case DRM_FORMAT_Y216: 706 return PLANE_CTL_FORMAT_Y216; 707 case DRM_FORMAT_XVYU2101010: 708 return PLANE_CTL_FORMAT_Y410; 709 case DRM_FORMAT_XVYU12_16161616: 710 return PLANE_CTL_FORMAT_Y412; 711 case DRM_FORMAT_XVYU16161616: 712 return PLANE_CTL_FORMAT_Y416; 713 default: 714 MISSING_CASE(pixel_format); 715 } 716 717 return 0; 718 } 719 720 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state) 721 { 722 if (!plane_state->hw.fb->format->has_alpha) 723 return PLANE_CTL_ALPHA_DISABLE; 724 725 switch (plane_state->hw.pixel_blend_mode) { 726 case DRM_MODE_BLEND_PIXEL_NONE: 727 return PLANE_CTL_ALPHA_DISABLE; 728 case DRM_MODE_BLEND_PREMULTI: 729 return PLANE_CTL_ALPHA_SW_PREMULTIPLY; 730 case DRM_MODE_BLEND_COVERAGE: 731 return PLANE_CTL_ALPHA_HW_PREMULTIPLY; 732 default: 733 MISSING_CASE(plane_state->hw.pixel_blend_mode); 734 return PLANE_CTL_ALPHA_DISABLE; 735 } 736 } 737 738 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state) 739 { 740 if (!plane_state->hw.fb->format->has_alpha) 741 return PLANE_COLOR_ALPHA_DISABLE; 742 743 switch (plane_state->hw.pixel_blend_mode) { 744 case DRM_MODE_BLEND_PIXEL_NONE: 745 return PLANE_COLOR_ALPHA_DISABLE; 746 case DRM_MODE_BLEND_PREMULTI: 747 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY; 748 case DRM_MODE_BLEND_COVERAGE: 749 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY; 750 default: 751 MISSING_CASE(plane_state->hw.pixel_blend_mode); 752 return PLANE_COLOR_ALPHA_DISABLE; 753 } 754 } 755 756 static u32 skl_plane_ctl_tiling(u64 fb_modifier) 757 { 758 switch (fb_modifier) { 759 case DRM_FORMAT_MOD_LINEAR: 760 break; 761 case I915_FORMAT_MOD_X_TILED: 762 return PLANE_CTL_TILED_X; 763 case I915_FORMAT_MOD_Y_TILED: 764 return PLANE_CTL_TILED_Y; 765 case I915_FORMAT_MOD_Y_TILED_CCS: 766 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 767 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 768 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 769 return PLANE_CTL_TILED_Y | 770 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 771 PLANE_CTL_CLEAR_COLOR_DISABLE; 772 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 773 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE; 774 case I915_FORMAT_MOD_Yf_TILED: 775 return PLANE_CTL_TILED_YF; 776 case I915_FORMAT_MOD_Yf_TILED_CCS: 777 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 778 default: 779 MISSING_CASE(fb_modifier); 780 } 781 782 return 0; 783 } 784 785 static u32 skl_plane_ctl_rotate(unsigned int rotate) 786 { 787 switch (rotate) { 788 case DRM_MODE_ROTATE_0: 789 break; 790 /* 791 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr 792 * while i915 HW rotation is clockwise, thats why this swapping. 793 */ 794 case DRM_MODE_ROTATE_90: 795 return PLANE_CTL_ROTATE_270; 796 case DRM_MODE_ROTATE_180: 797 return PLANE_CTL_ROTATE_180; 798 case DRM_MODE_ROTATE_270: 799 return PLANE_CTL_ROTATE_90; 800 default: 801 MISSING_CASE(rotate); 802 } 803 804 return 0; 805 } 806 807 static u32 icl_plane_ctl_flip(unsigned int reflect) 808 { 809 switch (reflect) { 810 case 0: 811 break; 812 case DRM_MODE_REFLECT_X: 813 return PLANE_CTL_FLIP_HORIZONTAL; 814 case DRM_MODE_REFLECT_Y: 815 default: 816 MISSING_CASE(reflect); 817 } 818 819 return 0; 820 } 821 822 static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state) 823 { 824 const struct drm_framebuffer *fb = plane_state->hw.fb; 825 826 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) { 827 switch (fb->format->cpp[0]) { 828 case 2: 829 return PLANE_CTL_ARB_SLOTS(1); 830 default: 831 return PLANE_CTL_ARB_SLOTS(0); 832 } 833 } else { 834 switch (fb->format->cpp[0]) { 835 case 8: 836 return PLANE_CTL_ARB_SLOTS(3); 837 case 4: 838 return PLANE_CTL_ARB_SLOTS(1); 839 default: 840 return PLANE_CTL_ARB_SLOTS(0); 841 } 842 } 843 } 844 845 static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) 846 { 847 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 848 u32 plane_ctl = 0; 849 850 if (DISPLAY_VER(dev_priv) >= 10) 851 return plane_ctl; 852 853 if (crtc_state->gamma_enable) 854 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE; 855 856 if (crtc_state->csc_enable) 857 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE; 858 859 return plane_ctl; 860 } 861 862 static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, 863 const struct intel_plane_state *plane_state) 864 { 865 struct drm_i915_private *dev_priv = 866 to_i915(plane_state->uapi.plane->dev); 867 const struct drm_framebuffer *fb = plane_state->hw.fb; 868 unsigned int rotation = plane_state->hw.rotation; 869 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 870 u32 plane_ctl; 871 872 plane_ctl = PLANE_CTL_ENABLE; 873 874 if (DISPLAY_VER(dev_priv) < 10) { 875 plane_ctl |= skl_plane_ctl_alpha(plane_state); 876 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; 877 878 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 879 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709; 880 881 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 882 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE; 883 } 884 885 plane_ctl |= skl_plane_ctl_format(fb->format->format); 886 plane_ctl |= skl_plane_ctl_tiling(fb->modifier); 887 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK); 888 889 if (DISPLAY_VER(dev_priv) >= 11) 890 plane_ctl |= icl_plane_ctl_flip(rotation & 891 DRM_MODE_REFLECT_MASK); 892 893 if (key->flags & I915_SET_COLORKEY_DESTINATION) 894 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; 895 else if (key->flags & I915_SET_COLORKEY_SOURCE) 896 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; 897 898 /* Wa_22012358565:adl-p */ 899 if (DISPLAY_VER(dev_priv) == 13) 900 plane_ctl |= adlp_plane_ctl_arb_slots(plane_state); 901 902 return plane_ctl; 903 } 904 905 static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) 906 { 907 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 908 u32 plane_color_ctl = 0; 909 910 if (DISPLAY_VER(dev_priv) >= 11) 911 return plane_color_ctl; 912 913 if (crtc_state->gamma_enable) 914 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE; 915 916 if (crtc_state->csc_enable) 917 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE; 918 919 return plane_color_ctl; 920 } 921 922 static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, 923 const struct intel_plane_state *plane_state) 924 { 925 struct drm_i915_private *dev_priv = 926 to_i915(plane_state->uapi.plane->dev); 927 const struct drm_framebuffer *fb = plane_state->hw.fb; 928 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 929 u32 plane_color_ctl = 0; 930 931 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; 932 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); 933 934 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { 935 switch (plane_state->hw.color_encoding) { 936 case DRM_COLOR_YCBCR_BT709: 937 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; 938 break; 939 case DRM_COLOR_YCBCR_BT2020: 940 plane_color_ctl |= 941 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020; 942 break; 943 default: 944 plane_color_ctl |= 945 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601; 946 } 947 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 948 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; 949 } else if (fb->format->is_yuv) { 950 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE; 951 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 952 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; 953 } 954 955 if (plane_state->force_black) 956 plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE; 957 958 return plane_color_ctl; 959 } 960 961 static u32 skl_surf_address(const struct intel_plane_state *plane_state, 962 int color_plane) 963 { 964 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 965 const struct drm_framebuffer *fb = plane_state->hw.fb; 966 u32 offset = plane_state->view.color_plane[color_plane].offset; 967 968 if (intel_fb_uses_dpt(fb)) { 969 /* 970 * The DPT object contains only one vma, so the VMA's offset 971 * within the DPT is always 0. 972 */ 973 drm_WARN_ON(&i915->drm, plane_state->dpt_vma->node.start); 974 drm_WARN_ON(&i915->drm, offset & 0x1fffff); 975 return offset >> 9; 976 } else { 977 drm_WARN_ON(&i915->drm, offset & 0xfff); 978 return offset; 979 } 980 } 981 982 static u32 skl_plane_surf(const struct intel_plane_state *plane_state, 983 int color_plane) 984 { 985 u32 plane_surf; 986 987 plane_surf = intel_plane_ggtt_offset(plane_state) + 988 skl_surf_address(plane_state, color_plane); 989 990 if (plane_state->decrypt) 991 plane_surf |= PLANE_SURF_DECRYPT; 992 993 return plane_surf; 994 } 995 996 static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, 997 int color_plane) 998 { 999 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1000 const struct drm_framebuffer *fb = plane_state->hw.fb; 1001 int aux_plane = skl_main_to_aux_plane(fb, color_plane); 1002 u32 aux_dist; 1003 1004 if (!aux_plane) 1005 return 0; 1006 1007 aux_dist = skl_surf_address(plane_state, aux_plane) - 1008 skl_surf_address(plane_state, color_plane); 1009 1010 if (DISPLAY_VER(i915) < 12) 1011 aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane)); 1012 1013 return aux_dist; 1014 } 1015 1016 static u32 skl_plane_keyval(const struct intel_plane_state *plane_state) 1017 { 1018 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1019 1020 return key->min_value; 1021 } 1022 1023 static u32 skl_plane_keymax(const struct intel_plane_state *plane_state) 1024 { 1025 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1026 u8 alpha = plane_state->hw.alpha >> 8; 1027 1028 return (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha); 1029 } 1030 1031 static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state) 1032 { 1033 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1034 u8 alpha = plane_state->hw.alpha >> 8; 1035 u32 keymsk; 1036 1037 keymsk = key->channel_mask & 0x7ffffff; 1038 if (alpha < 0xff) 1039 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE; 1040 1041 return keymsk; 1042 } 1043 1044 static void icl_plane_csc_load_black(struct intel_plane *plane) 1045 { 1046 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1047 enum plane_id plane_id = plane->id; 1048 enum pipe pipe = plane->pipe; 1049 1050 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 0), 0); 1051 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 1), 0); 1052 1053 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 2), 0); 1054 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 3), 0); 1055 1056 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 4), 0); 1057 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 5), 0); 1058 1059 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0); 1060 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0); 1061 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0); 1062 1063 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0); 1064 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0); 1065 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0); 1066 } 1067 1068 static int skl_plane_color_plane(const struct intel_plane_state *plane_state) 1069 { 1070 /* Program the UV plane on planar master */ 1071 if (plane_state->planar_linked_plane && !plane_state->planar_slave) 1072 return 1; 1073 else 1074 return 0; 1075 } 1076 1077 static void 1078 skl_plane_update_noarm(struct intel_plane *plane, 1079 const struct intel_crtc_state *crtc_state, 1080 const struct intel_plane_state *plane_state) 1081 { 1082 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1083 enum plane_id plane_id = plane->id; 1084 enum pipe pipe = plane->pipe; 1085 int color_plane = skl_plane_color_plane(plane_state); 1086 u32 stride = skl_plane_stride(plane_state, color_plane); 1087 const struct drm_framebuffer *fb = plane_state->hw.fb; 1088 int crtc_x = plane_state->uapi.dst.x1; 1089 int crtc_y = plane_state->uapi.dst.y1; 1090 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1091 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1092 unsigned long irqflags; 1093 1094 /* The scaler will handle the output position */ 1095 if (plane_state->scaler_id >= 0) { 1096 crtc_x = 0; 1097 crtc_y = 0; 1098 } 1099 1100 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1101 1102 /* 1103 * FIXME: pxp session invalidation can hit any time even at time of commit 1104 * or after the commit, display content will be garbage. 1105 */ 1106 if (plane_state->force_black) 1107 icl_plane_csc_load_black(plane); 1108 1109 intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), 1110 PLANE_STRIDE_(stride)); 1111 intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), 1112 PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x)); 1113 intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), 1114 PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1)); 1115 1116 if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) { 1117 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0), 1118 lower_32_bits(plane_state->ccval)); 1119 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1), 1120 upper_32_bits(plane_state->ccval)); 1121 } 1122 1123 if (icl_is_hdr_plane(dev_priv, plane_id)) 1124 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 1125 plane_state->cus_ctl); 1126 1127 if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) 1128 icl_program_input_csc(plane, crtc_state, plane_state); 1129 1130 skl_write_plane_wm(plane, crtc_state); 1131 1132 intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane); 1133 1134 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1135 } 1136 1137 static void 1138 skl_plane_update_arm(struct intel_plane *plane, 1139 const struct intel_crtc_state *crtc_state, 1140 const struct intel_plane_state *plane_state) 1141 { 1142 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1143 enum plane_id plane_id = plane->id; 1144 enum pipe pipe = plane->pipe; 1145 int color_plane = skl_plane_color_plane(plane_state); 1146 u32 x = plane_state->view.color_plane[color_plane].x; 1147 u32 y = plane_state->view.color_plane[color_plane].y; 1148 u32 plane_color_ctl = 0; 1149 u32 plane_ctl = plane_state->ctl; 1150 unsigned long irqflags; 1151 1152 plane_ctl |= skl_plane_ctl_crtc(crtc_state); 1153 1154 if (DISPLAY_VER(dev_priv) >= 10) 1155 plane_color_ctl = plane_state->color_ctl | 1156 glk_plane_color_ctl_crtc(crtc_state); 1157 1158 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1159 1160 intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state)); 1161 intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state)); 1162 intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state)); 1163 1164 intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id), 1165 PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x)); 1166 1167 intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), 1168 skl_plane_aux_dist(plane_state, color_plane)); 1169 1170 if (DISPLAY_VER(dev_priv) < 11) 1171 intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id), 1172 PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) | 1173 PLANE_OFFSET_X(plane_state->view.color_plane[1].x)); 1174 1175 if (DISPLAY_VER(dev_priv) >= 10) 1176 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); 1177 1178 /* 1179 * Enable the scaler before the plane so that we don't 1180 * get a catastrophic underrun even if the two operations 1181 * end up happening in two different frames. 1182 * 1183 * TODO: split into noarm+arm pair 1184 */ 1185 if (plane_state->scaler_id >= 0) 1186 skl_program_plane_scaler(plane, crtc_state, plane_state); 1187 1188 /* 1189 * The control register self-arms if the plane was previously 1190 * disabled. Try to make the plane enable atomic by writing 1191 * the control register just before the surface register. 1192 */ 1193 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 1194 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 1195 skl_plane_surf(plane_state, color_plane)); 1196 1197 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1198 } 1199 1200 static void 1201 skl_plane_async_flip(struct intel_plane *plane, 1202 const struct intel_crtc_state *crtc_state, 1203 const struct intel_plane_state *plane_state, 1204 bool async_flip) 1205 { 1206 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1207 unsigned long irqflags; 1208 enum plane_id plane_id = plane->id; 1209 enum pipe pipe = plane->pipe; 1210 u32 plane_ctl = plane_state->ctl; 1211 1212 plane_ctl |= skl_plane_ctl_crtc(crtc_state); 1213 1214 if (async_flip) 1215 plane_ctl |= PLANE_CTL_ASYNC_FLIP; 1216 1217 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1218 1219 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 1220 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 1221 skl_plane_surf(plane_state, 0)); 1222 1223 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1224 } 1225 1226 static bool intel_format_is_p01x(u32 format) 1227 { 1228 switch (format) { 1229 case DRM_FORMAT_P010: 1230 case DRM_FORMAT_P012: 1231 case DRM_FORMAT_P016: 1232 return true; 1233 default: 1234 return false; 1235 } 1236 } 1237 1238 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, 1239 const struct intel_plane_state *plane_state) 1240 { 1241 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1242 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1243 const struct drm_framebuffer *fb = plane_state->hw.fb; 1244 unsigned int rotation = plane_state->hw.rotation; 1245 1246 if (!fb) 1247 return 0; 1248 1249 if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) && 1250 intel_fb_is_ccs_modifier(fb->modifier)) { 1251 drm_dbg_kms(&dev_priv->drm, 1252 "RC support only with 0/180 degree rotation (%x)\n", 1253 rotation); 1254 return -EINVAL; 1255 } 1256 1257 if (rotation & DRM_MODE_REFLECT_X && 1258 fb->modifier == DRM_FORMAT_MOD_LINEAR) { 1259 drm_dbg_kms(&dev_priv->drm, 1260 "horizontal flip is not supported with linear surface formats\n"); 1261 return -EINVAL; 1262 } 1263 1264 if (drm_rotation_90_or_270(rotation)) { 1265 if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) { 1266 drm_dbg_kms(&dev_priv->drm, 1267 "Y/Yf tiling required for 90/270!\n"); 1268 return -EINVAL; 1269 } 1270 1271 /* 1272 * 90/270 is not allowed with RGB64 16:16:16:16 and 1273 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards. 1274 */ 1275 switch (fb->format->format) { 1276 case DRM_FORMAT_RGB565: 1277 if (DISPLAY_VER(dev_priv) >= 11) 1278 break; 1279 fallthrough; 1280 case DRM_FORMAT_C8: 1281 case DRM_FORMAT_XRGB16161616F: 1282 case DRM_FORMAT_XBGR16161616F: 1283 case DRM_FORMAT_ARGB16161616F: 1284 case DRM_FORMAT_ABGR16161616F: 1285 case DRM_FORMAT_Y210: 1286 case DRM_FORMAT_Y212: 1287 case DRM_FORMAT_Y216: 1288 case DRM_FORMAT_XVYU12_16161616: 1289 case DRM_FORMAT_XVYU16161616: 1290 drm_dbg_kms(&dev_priv->drm, 1291 "Unsupported pixel format %p4cc for 90/270!\n", 1292 &fb->format->format); 1293 return -EINVAL; 1294 default: 1295 break; 1296 } 1297 } 1298 1299 /* Y-tiling is not supported in IF-ID Interlace mode */ 1300 if (crtc_state->hw.enable && 1301 crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE && 1302 fb->modifier != DRM_FORMAT_MOD_LINEAR && 1303 fb->modifier != I915_FORMAT_MOD_X_TILED) { 1304 drm_dbg_kms(&dev_priv->drm, 1305 "Y/Yf tiling not supported in IF-ID mode\n"); 1306 return -EINVAL; 1307 } 1308 1309 /* Wa_1606054188:tgl,adl-s */ 1310 if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) && 1311 plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE && 1312 intel_format_is_p01x(fb->format->format)) { 1313 drm_dbg_kms(&dev_priv->drm, 1314 "Source color keying not supported with P01x formats\n"); 1315 return -EINVAL; 1316 } 1317 1318 return 0; 1319 } 1320 1321 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state, 1322 const struct intel_plane_state *plane_state) 1323 { 1324 struct drm_i915_private *dev_priv = 1325 to_i915(plane_state->uapi.plane->dev); 1326 int crtc_x = plane_state->uapi.dst.x1; 1327 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 1328 int pipe_src_w = crtc_state->pipe_src_w; 1329 1330 /* 1331 * Display WA #1175: glk 1332 * Planes other than the cursor may cause FIFO underflow and display 1333 * corruption if starting less than 4 pixels from the right edge of 1334 * the screen. 1335 * Besides the above WA fix the similar problem, where planes other 1336 * than the cursor ending less than 4 pixels from the left edge of the 1337 * screen may cause FIFO underflow and display corruption. 1338 */ 1339 if (DISPLAY_VER(dev_priv) == 10 && 1340 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) { 1341 drm_dbg_kms(&dev_priv->drm, 1342 "requested plane X %s position %d invalid (valid range %d-%d)\n", 1343 crtc_x + crtc_w < 4 ? "end" : "start", 1344 crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x, 1345 4, pipe_src_w - 4); 1346 return -ERANGE; 1347 } 1348 1349 return 0; 1350 } 1351 1352 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state) 1353 { 1354 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1355 const struct drm_framebuffer *fb = plane_state->hw.fb; 1356 unsigned int rotation = plane_state->hw.rotation; 1357 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1358 1359 /* Display WA #1106 */ 1360 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 1361 src_w & 3 && 1362 (rotation == DRM_MODE_ROTATE_270 || 1363 rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) { 1364 drm_dbg_kms(&i915->drm, "src width must be multiple of 4 for rotated planar YUV\n"); 1365 return -EINVAL; 1366 } 1367 1368 return 0; 1369 } 1370 1371 static int skl_plane_max_scale(struct drm_i915_private *dev_priv, 1372 const struct drm_framebuffer *fb) 1373 { 1374 /* 1375 * We don't yet know the final source width nor 1376 * whether we can use the HQ scaler mode. Assume 1377 * the best case. 1378 * FIXME need to properly check this later. 1379 */ 1380 if (DISPLAY_VER(dev_priv) >= 10 || 1381 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 1382 return 0x30000 - 1; 1383 else 1384 return 0x20000 - 1; 1385 } 1386 1387 static int intel_plane_min_width(struct intel_plane *plane, 1388 const struct drm_framebuffer *fb, 1389 int color_plane, 1390 unsigned int rotation) 1391 { 1392 if (plane->min_width) 1393 return plane->min_width(fb, color_plane, rotation); 1394 else 1395 return 1; 1396 } 1397 1398 static int intel_plane_max_width(struct intel_plane *plane, 1399 const struct drm_framebuffer *fb, 1400 int color_plane, 1401 unsigned int rotation) 1402 { 1403 if (plane->max_width) 1404 return plane->max_width(fb, color_plane, rotation); 1405 else 1406 return INT_MAX; 1407 } 1408 1409 static int intel_plane_max_height(struct intel_plane *plane, 1410 const struct drm_framebuffer *fb, 1411 int color_plane, 1412 unsigned int rotation) 1413 { 1414 if (plane->max_height) 1415 return plane->max_height(fb, color_plane, rotation); 1416 else 1417 return INT_MAX; 1418 } 1419 1420 static bool 1421 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, 1422 int main_x, int main_y, u32 main_offset, 1423 int ccs_plane) 1424 { 1425 const struct drm_framebuffer *fb = plane_state->hw.fb; 1426 int aux_x = plane_state->view.color_plane[ccs_plane].x; 1427 int aux_y = plane_state->view.color_plane[ccs_plane].y; 1428 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; 1429 u32 alignment = intel_surf_alignment(fb, ccs_plane); 1430 int hsub; 1431 int vsub; 1432 1433 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 1434 while (aux_offset >= main_offset && aux_y <= main_y) { 1435 int x, y; 1436 1437 if (aux_x == main_x && aux_y == main_y) 1438 break; 1439 1440 if (aux_offset == 0) 1441 break; 1442 1443 x = aux_x / hsub; 1444 y = aux_y / vsub; 1445 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, 1446 plane_state, 1447 ccs_plane, 1448 aux_offset, 1449 aux_offset - 1450 alignment); 1451 aux_x = x * hsub + aux_x % hsub; 1452 aux_y = y * vsub + aux_y % vsub; 1453 } 1454 1455 if (aux_x != main_x || aux_y != main_y) 1456 return false; 1457 1458 plane_state->view.color_plane[ccs_plane].offset = aux_offset; 1459 plane_state->view.color_plane[ccs_plane].x = aux_x; 1460 plane_state->view.color_plane[ccs_plane].y = aux_y; 1461 1462 return true; 1463 } 1464 1465 1466 int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, 1467 int *x, int *y, u32 *offset) 1468 { 1469 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1470 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1471 const struct drm_framebuffer *fb = plane_state->hw.fb; 1472 const int aux_plane = skl_main_to_aux_plane(fb, 0); 1473 const u32 aux_offset = plane_state->view.color_plane[aux_plane].offset; 1474 const u32 alignment = intel_surf_alignment(fb, 0); 1475 const int w = drm_rect_width(&plane_state->uapi.src) >> 16; 1476 1477 intel_add_fb_offsets(x, y, plane_state, 0); 1478 *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0); 1479 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) 1480 return -EINVAL; 1481 1482 /* 1483 * AUX surface offset is specified as the distance from the 1484 * main surface offset, and it must be non-negative. Make 1485 * sure that is what we will get. 1486 */ 1487 if (aux_plane && *offset > aux_offset) 1488 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, 1489 *offset, 1490 aux_offset & ~(alignment - 1)); 1491 1492 /* 1493 * When using an X-tiled surface, the plane blows up 1494 * if the x offset + width exceed the stride. 1495 * 1496 * TODO: linear and Y-tiled seem fine, Yf untested, 1497 */ 1498 if (fb->modifier == I915_FORMAT_MOD_X_TILED) { 1499 int cpp = fb->format->cpp[0]; 1500 1501 while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) { 1502 if (*offset == 0) { 1503 drm_dbg_kms(&dev_priv->drm, 1504 "Unable to find suitable display surface offset due to X-tiling\n"); 1505 return -EINVAL; 1506 } 1507 1508 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, 1509 *offset, 1510 *offset - alignment); 1511 } 1512 } 1513 1514 return 0; 1515 } 1516 1517 static int skl_check_main_surface(struct intel_plane_state *plane_state) 1518 { 1519 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1520 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1521 const struct drm_framebuffer *fb = plane_state->hw.fb; 1522 const unsigned int rotation = plane_state->hw.rotation; 1523 int x = plane_state->uapi.src.x1 >> 16; 1524 int y = plane_state->uapi.src.y1 >> 16; 1525 const int w = drm_rect_width(&plane_state->uapi.src) >> 16; 1526 const int h = drm_rect_height(&plane_state->uapi.src) >> 16; 1527 const int min_width = intel_plane_min_width(plane, fb, 0, rotation); 1528 const int max_width = intel_plane_max_width(plane, fb, 0, rotation); 1529 const int max_height = intel_plane_max_height(plane, fb, 0, rotation); 1530 const int aux_plane = skl_main_to_aux_plane(fb, 0); 1531 const u32 alignment = intel_surf_alignment(fb, 0); 1532 u32 offset; 1533 int ret; 1534 1535 if (w > max_width || w < min_width || h > max_height) { 1536 drm_dbg_kms(&dev_priv->drm, 1537 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", 1538 w, h, min_width, max_width, max_height); 1539 return -EINVAL; 1540 } 1541 1542 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); 1543 if (ret) 1544 return ret; 1545 1546 /* 1547 * CCS AUX surface doesn't have its own x/y offsets, we must make sure 1548 * they match with the main surface x/y offsets. 1549 */ 1550 if (intel_fb_is_ccs_modifier(fb->modifier)) { 1551 while (!skl_check_main_ccs_coordinates(plane_state, x, y, 1552 offset, aux_plane)) { 1553 if (offset == 0) 1554 break; 1555 1556 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 1557 offset, offset - alignment); 1558 } 1559 1560 if (x != plane_state->view.color_plane[aux_plane].x || 1561 y != plane_state->view.color_plane[aux_plane].y) { 1562 drm_dbg_kms(&dev_priv->drm, 1563 "Unable to find suitable display surface offset due to CCS\n"); 1564 return -EINVAL; 1565 } 1566 } 1567 1568 if (DISPLAY_VER(dev_priv) >= 13) 1569 drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535); 1570 else 1571 drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191); 1572 1573 plane_state->view.color_plane[0].offset = offset; 1574 plane_state->view.color_plane[0].x = x; 1575 plane_state->view.color_plane[0].y = y; 1576 1577 /* 1578 * Put the final coordinates back so that the src 1579 * coordinate checks will see the right values. 1580 */ 1581 drm_rect_translate_to(&plane_state->uapi.src, 1582 x << 16, y << 16); 1583 1584 return 0; 1585 } 1586 1587 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) 1588 { 1589 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1590 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1591 const struct drm_framebuffer *fb = plane_state->hw.fb; 1592 unsigned int rotation = plane_state->hw.rotation; 1593 int uv_plane = 1; 1594 int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation); 1595 int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation); 1596 int x = plane_state->uapi.src.x1 >> 17; 1597 int y = plane_state->uapi.src.y1 >> 17; 1598 int w = drm_rect_width(&plane_state->uapi.src) >> 17; 1599 int h = drm_rect_height(&plane_state->uapi.src) >> 17; 1600 u32 offset; 1601 1602 /* FIXME not quite sure how/if these apply to the chroma plane */ 1603 if (w > max_width || h > max_height) { 1604 drm_dbg_kms(&i915->drm, 1605 "CbCr source size %dx%d too big (limit %dx%d)\n", 1606 w, h, max_width, max_height); 1607 return -EINVAL; 1608 } 1609 1610 intel_add_fb_offsets(&x, &y, plane_state, uv_plane); 1611 offset = intel_plane_compute_aligned_offset(&x, &y, 1612 plane_state, uv_plane); 1613 1614 if (intel_fb_is_ccs_modifier(fb->modifier)) { 1615 int ccs_plane = main_to_ccs_plane(fb, uv_plane); 1616 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; 1617 u32 alignment = intel_surf_alignment(fb, uv_plane); 1618 1619 if (offset > aux_offset) 1620 offset = intel_plane_adjust_aligned_offset(&x, &y, 1621 plane_state, 1622 uv_plane, 1623 offset, 1624 aux_offset & ~(alignment - 1)); 1625 1626 while (!skl_check_main_ccs_coordinates(plane_state, x, y, 1627 offset, ccs_plane)) { 1628 if (offset == 0) 1629 break; 1630 1631 offset = intel_plane_adjust_aligned_offset(&x, &y, 1632 plane_state, 1633 uv_plane, 1634 offset, offset - alignment); 1635 } 1636 1637 if (x != plane_state->view.color_plane[ccs_plane].x || 1638 y != plane_state->view.color_plane[ccs_plane].y) { 1639 drm_dbg_kms(&i915->drm, 1640 "Unable to find suitable display surface offset due to CCS\n"); 1641 return -EINVAL; 1642 } 1643 } 1644 1645 if (DISPLAY_VER(i915) >= 13) 1646 drm_WARN_ON(&i915->drm, x > 65535 || y > 65535); 1647 else 1648 drm_WARN_ON(&i915->drm, x > 8191 || y > 8191); 1649 1650 plane_state->view.color_plane[uv_plane].offset = offset; 1651 plane_state->view.color_plane[uv_plane].x = x; 1652 plane_state->view.color_plane[uv_plane].y = y; 1653 1654 return 0; 1655 } 1656 1657 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) 1658 { 1659 const struct drm_framebuffer *fb = plane_state->hw.fb; 1660 int src_x = plane_state->uapi.src.x1 >> 16; 1661 int src_y = plane_state->uapi.src.y1 >> 16; 1662 u32 offset; 1663 int ccs_plane; 1664 1665 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) { 1666 int main_hsub, main_vsub; 1667 int hsub, vsub; 1668 int x, y; 1669 1670 if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane)) 1671 continue; 1672 1673 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, 1674 skl_ccs_to_main_plane(fb, ccs_plane)); 1675 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 1676 1677 hsub *= main_hsub; 1678 vsub *= main_vsub; 1679 x = src_x / hsub; 1680 y = src_y / vsub; 1681 1682 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane); 1683 1684 offset = intel_plane_compute_aligned_offset(&x, &y, 1685 plane_state, 1686 ccs_plane); 1687 1688 plane_state->view.color_plane[ccs_plane].offset = offset; 1689 plane_state->view.color_plane[ccs_plane].x = (x * hsub + src_x % hsub) / main_hsub; 1690 plane_state->view.color_plane[ccs_plane].y = (y * vsub + src_y % vsub) / main_vsub; 1691 } 1692 1693 return 0; 1694 } 1695 1696 static int skl_check_plane_surface(struct intel_plane_state *plane_state) 1697 { 1698 const struct drm_framebuffer *fb = plane_state->hw.fb; 1699 int ret; 1700 1701 ret = intel_plane_compute_gtt(plane_state); 1702 if (ret) 1703 return ret; 1704 1705 if (!plane_state->uapi.visible) 1706 return 0; 1707 1708 /* 1709 * Handle the AUX surface first since the main surface setup depends on 1710 * it. 1711 */ 1712 if (intel_fb_is_ccs_modifier(fb->modifier)) { 1713 ret = skl_check_ccs_aux_surface(plane_state); 1714 if (ret) 1715 return ret; 1716 } 1717 1718 if (intel_format_info_is_yuv_semiplanar(fb->format, 1719 fb->modifier)) { 1720 ret = skl_check_nv12_aux_surface(plane_state); 1721 if (ret) 1722 return ret; 1723 } 1724 1725 ret = skl_check_main_surface(plane_state); 1726 if (ret) 1727 return ret; 1728 1729 return 0; 1730 } 1731 1732 static bool skl_fb_scalable(const struct drm_framebuffer *fb) 1733 { 1734 if (!fb) 1735 return false; 1736 1737 switch (fb->format->format) { 1738 case DRM_FORMAT_C8: 1739 return false; 1740 case DRM_FORMAT_XRGB16161616F: 1741 case DRM_FORMAT_ARGB16161616F: 1742 case DRM_FORMAT_XBGR16161616F: 1743 case DRM_FORMAT_ABGR16161616F: 1744 return DISPLAY_VER(to_i915(fb->dev)) >= 11; 1745 default: 1746 return true; 1747 } 1748 } 1749 1750 static bool bo_has_valid_encryption(struct drm_i915_gem_object *obj) 1751 { 1752 struct drm_i915_private *i915 = to_i915(obj->base.dev); 1753 1754 return intel_pxp_key_check(&to_gt(i915)->pxp, obj, false) == 0; 1755 } 1756 1757 static bool pxp_is_borked(struct drm_i915_gem_object *obj) 1758 { 1759 return i915_gem_object_is_protected(obj) && !bo_has_valid_encryption(obj); 1760 } 1761 1762 static int skl_plane_check(struct intel_crtc_state *crtc_state, 1763 struct intel_plane_state *plane_state) 1764 { 1765 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1766 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1767 const struct drm_framebuffer *fb = plane_state->hw.fb; 1768 int min_scale = DRM_PLANE_HELPER_NO_SCALING; 1769 int max_scale = DRM_PLANE_HELPER_NO_SCALING; 1770 int ret; 1771 1772 ret = skl_plane_check_fb(crtc_state, plane_state); 1773 if (ret) 1774 return ret; 1775 1776 /* use scaler when colorkey is not required */ 1777 if (!plane_state->ckey.flags && skl_fb_scalable(fb)) { 1778 min_scale = 1; 1779 max_scale = skl_plane_max_scale(dev_priv, fb); 1780 } 1781 1782 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 1783 min_scale, max_scale, true); 1784 if (ret) 1785 return ret; 1786 1787 ret = skl_check_plane_surface(plane_state); 1788 if (ret) 1789 return ret; 1790 1791 if (!plane_state->uapi.visible) 1792 return 0; 1793 1794 ret = skl_plane_check_dst_coordinates(crtc_state, plane_state); 1795 if (ret) 1796 return ret; 1797 1798 ret = intel_plane_check_src_coordinates(plane_state); 1799 if (ret) 1800 return ret; 1801 1802 ret = skl_plane_check_nv12_rotation(plane_state); 1803 if (ret) 1804 return ret; 1805 1806 if (DISPLAY_VER(dev_priv) >= 11) { 1807 plane_state->decrypt = bo_has_valid_encryption(intel_fb_obj(fb)); 1808 plane_state->force_black = pxp_is_borked(intel_fb_obj(fb)); 1809 } 1810 1811 /* HW only has 8 bits pixel precision, disable plane if invisible */ 1812 if (!(plane_state->hw.alpha >> 8)) 1813 plane_state->uapi.visible = false; 1814 1815 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); 1816 1817 if (DISPLAY_VER(dev_priv) >= 10) 1818 plane_state->color_ctl = glk_plane_color_ctl(crtc_state, 1819 plane_state); 1820 1821 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 1822 icl_is_hdr_plane(dev_priv, plane->id)) 1823 /* Enable and use MPEG-2 chroma siting */ 1824 plane_state->cus_ctl = PLANE_CUS_ENABLE | 1825 PLANE_CUS_HPHASE_0 | 1826 PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25; 1827 else 1828 plane_state->cus_ctl = 0; 1829 1830 return 0; 1831 } 1832 1833 static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe) 1834 { 1835 return pipe - PIPE_A + INTEL_FBC_A; 1836 } 1837 1838 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv, 1839 enum intel_fbc_id fbc_id, enum plane_id plane_id) 1840 { 1841 if ((INTEL_INFO(dev_priv)->display.fbc_mask & BIT(fbc_id)) == 0) 1842 return false; 1843 1844 return plane_id == PLANE_PRIMARY; 1845 } 1846 1847 static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv, 1848 enum pipe pipe, enum plane_id plane_id) 1849 { 1850 enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe); 1851 1852 if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id)) 1853 return dev_priv->fbc[fbc_id]; 1854 else 1855 return NULL; 1856 } 1857 1858 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, 1859 enum pipe pipe, enum plane_id plane_id) 1860 { 1861 /* Display WA #0870: skl, bxt */ 1862 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) 1863 return false; 1864 1865 if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C) 1866 return false; 1867 1868 if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0) 1869 return false; 1870 1871 return true; 1872 } 1873 1874 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv, 1875 enum pipe pipe, enum plane_id plane_id, 1876 int *num_formats) 1877 { 1878 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 1879 *num_formats = ARRAY_SIZE(skl_planar_formats); 1880 return skl_planar_formats; 1881 } else { 1882 *num_formats = ARRAY_SIZE(skl_plane_formats); 1883 return skl_plane_formats; 1884 } 1885 } 1886 1887 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv, 1888 enum pipe pipe, enum plane_id plane_id, 1889 int *num_formats) 1890 { 1891 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 1892 *num_formats = ARRAY_SIZE(glk_planar_formats); 1893 return glk_planar_formats; 1894 } else { 1895 *num_formats = ARRAY_SIZE(skl_plane_formats); 1896 return skl_plane_formats; 1897 } 1898 } 1899 1900 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, 1901 enum pipe pipe, enum plane_id plane_id, 1902 int *num_formats) 1903 { 1904 if (icl_is_hdr_plane(dev_priv, plane_id)) { 1905 *num_formats = ARRAY_SIZE(icl_hdr_plane_formats); 1906 return icl_hdr_plane_formats; 1907 } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) { 1908 *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats); 1909 return icl_sdr_y_plane_formats; 1910 } else { 1911 *num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats); 1912 return icl_sdr_uv_plane_formats; 1913 } 1914 } 1915 1916 static bool skl_plane_format_mod_supported(struct drm_plane *_plane, 1917 u32 format, u64 modifier) 1918 { 1919 struct intel_plane *plane = to_intel_plane(_plane); 1920 1921 if (!intel_fb_plane_supports_modifier(plane, modifier)) 1922 return false; 1923 1924 switch (format) { 1925 case DRM_FORMAT_XRGB8888: 1926 case DRM_FORMAT_XBGR8888: 1927 case DRM_FORMAT_ARGB8888: 1928 case DRM_FORMAT_ABGR8888: 1929 if (intel_fb_is_ccs_modifier(modifier)) 1930 return true; 1931 fallthrough; 1932 case DRM_FORMAT_RGB565: 1933 case DRM_FORMAT_XRGB2101010: 1934 case DRM_FORMAT_XBGR2101010: 1935 case DRM_FORMAT_ARGB2101010: 1936 case DRM_FORMAT_ABGR2101010: 1937 case DRM_FORMAT_YUYV: 1938 case DRM_FORMAT_YVYU: 1939 case DRM_FORMAT_UYVY: 1940 case DRM_FORMAT_VYUY: 1941 case DRM_FORMAT_NV12: 1942 case DRM_FORMAT_XYUV8888: 1943 case DRM_FORMAT_P010: 1944 case DRM_FORMAT_P012: 1945 case DRM_FORMAT_P016: 1946 case DRM_FORMAT_XVYU2101010: 1947 if (modifier == I915_FORMAT_MOD_Yf_TILED) 1948 return true; 1949 fallthrough; 1950 case DRM_FORMAT_C8: 1951 case DRM_FORMAT_XBGR16161616F: 1952 case DRM_FORMAT_ABGR16161616F: 1953 case DRM_FORMAT_XRGB16161616F: 1954 case DRM_FORMAT_ARGB16161616F: 1955 case DRM_FORMAT_Y210: 1956 case DRM_FORMAT_Y212: 1957 case DRM_FORMAT_Y216: 1958 case DRM_FORMAT_XVYU12_16161616: 1959 case DRM_FORMAT_XVYU16161616: 1960 if (modifier == DRM_FORMAT_MOD_LINEAR || 1961 modifier == I915_FORMAT_MOD_X_TILED || 1962 modifier == I915_FORMAT_MOD_Y_TILED) 1963 return true; 1964 fallthrough; 1965 default: 1966 return false; 1967 } 1968 } 1969 1970 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, 1971 u32 format, u64 modifier) 1972 { 1973 struct intel_plane *plane = to_intel_plane(_plane); 1974 1975 if (!intel_fb_plane_supports_modifier(plane, modifier)) 1976 return false; 1977 1978 switch (format) { 1979 case DRM_FORMAT_XRGB8888: 1980 case DRM_FORMAT_XBGR8888: 1981 case DRM_FORMAT_ARGB8888: 1982 case DRM_FORMAT_ABGR8888: 1983 if (intel_fb_is_ccs_modifier(modifier)) 1984 return true; 1985 fallthrough; 1986 case DRM_FORMAT_YUYV: 1987 case DRM_FORMAT_YVYU: 1988 case DRM_FORMAT_UYVY: 1989 case DRM_FORMAT_VYUY: 1990 case DRM_FORMAT_NV12: 1991 case DRM_FORMAT_XYUV8888: 1992 case DRM_FORMAT_P010: 1993 case DRM_FORMAT_P012: 1994 case DRM_FORMAT_P016: 1995 if (intel_fb_is_mc_ccs_modifier(modifier)) 1996 return true; 1997 fallthrough; 1998 case DRM_FORMAT_RGB565: 1999 case DRM_FORMAT_XRGB2101010: 2000 case DRM_FORMAT_XBGR2101010: 2001 case DRM_FORMAT_ARGB2101010: 2002 case DRM_FORMAT_ABGR2101010: 2003 case DRM_FORMAT_XVYU2101010: 2004 case DRM_FORMAT_C8: 2005 case DRM_FORMAT_XBGR16161616F: 2006 case DRM_FORMAT_ABGR16161616F: 2007 case DRM_FORMAT_XRGB16161616F: 2008 case DRM_FORMAT_ARGB16161616F: 2009 case DRM_FORMAT_Y210: 2010 case DRM_FORMAT_Y212: 2011 case DRM_FORMAT_Y216: 2012 case DRM_FORMAT_XVYU12_16161616: 2013 case DRM_FORMAT_XVYU16161616: 2014 if (modifier == DRM_FORMAT_MOD_LINEAR || 2015 modifier == I915_FORMAT_MOD_X_TILED || 2016 modifier == I915_FORMAT_MOD_Y_TILED) 2017 return true; 2018 fallthrough; 2019 default: 2020 return false; 2021 } 2022 } 2023 2024 static const struct drm_plane_funcs skl_plane_funcs = { 2025 .update_plane = drm_atomic_helper_update_plane, 2026 .disable_plane = drm_atomic_helper_disable_plane, 2027 .destroy = intel_plane_destroy, 2028 .atomic_duplicate_state = intel_plane_duplicate_state, 2029 .atomic_destroy_state = intel_plane_destroy_state, 2030 .format_mod_supported = skl_plane_format_mod_supported, 2031 }; 2032 2033 static const struct drm_plane_funcs gen12_plane_funcs = { 2034 .update_plane = drm_atomic_helper_update_plane, 2035 .disable_plane = drm_atomic_helper_disable_plane, 2036 .destroy = intel_plane_destroy, 2037 .atomic_duplicate_state = intel_plane_duplicate_state, 2038 .atomic_destroy_state = intel_plane_destroy_state, 2039 .format_mod_supported = gen12_plane_format_mod_supported, 2040 }; 2041 2042 static void 2043 skl_plane_enable_flip_done(struct intel_plane *plane) 2044 { 2045 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2046 enum pipe pipe = plane->pipe; 2047 2048 spin_lock_irq(&i915->irq_lock); 2049 bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); 2050 spin_unlock_irq(&i915->irq_lock); 2051 } 2052 2053 static void 2054 skl_plane_disable_flip_done(struct intel_plane *plane) 2055 { 2056 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2057 enum pipe pipe = plane->pipe; 2058 2059 spin_lock_irq(&i915->irq_lock); 2060 bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); 2061 spin_unlock_irq(&i915->irq_lock); 2062 } 2063 2064 static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, 2065 enum pipe pipe, enum plane_id plane_id) 2066 { 2067 /* Wa_22011186057 */ 2068 if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) 2069 return false; 2070 2071 if (DISPLAY_VER(i915) >= 11) 2072 return true; 2073 2074 if (IS_GEMINILAKE(i915)) 2075 return pipe != PIPE_C; 2076 2077 return pipe != PIPE_C && 2078 (plane_id == PLANE_PRIMARY || 2079 plane_id == PLANE_SPRITE0); 2080 } 2081 2082 static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, 2083 enum plane_id plane_id) 2084 { 2085 if (DISPLAY_VER(i915) < 12) 2086 return false; 2087 2088 /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */ 2089 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || 2090 IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0)) 2091 return false; 2092 2093 /* Wa_22011186057 */ 2094 if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) 2095 return false; 2096 2097 return plane_id < PLANE_SPRITE4; 2098 } 2099 2100 static u8 skl_get_plane_caps(struct drm_i915_private *i915, 2101 enum pipe pipe, enum plane_id plane_id) 2102 { 2103 u8 caps = INTEL_PLANE_CAP_TILING_X; 2104 2105 if (DISPLAY_VER(i915) < 13 || IS_ALDERLAKE_P(i915)) 2106 caps |= INTEL_PLANE_CAP_TILING_Y; 2107 if (DISPLAY_VER(i915) < 12) 2108 caps |= INTEL_PLANE_CAP_TILING_Yf; 2109 2110 if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) { 2111 caps |= INTEL_PLANE_CAP_CCS_RC; 2112 if (DISPLAY_VER(i915) >= 12) 2113 caps |= INTEL_PLANE_CAP_CCS_RC_CC; 2114 } 2115 2116 if (gen12_plane_has_mc_ccs(i915, plane_id)) 2117 caps |= INTEL_PLANE_CAP_CCS_MC; 2118 2119 return caps; 2120 } 2121 2122 struct intel_plane * 2123 skl_universal_plane_create(struct drm_i915_private *dev_priv, 2124 enum pipe pipe, enum plane_id plane_id) 2125 { 2126 const struct drm_plane_funcs *plane_funcs; 2127 struct intel_plane *plane; 2128 enum drm_plane_type plane_type; 2129 unsigned int supported_rotations; 2130 unsigned int supported_csc; 2131 const u64 *modifiers; 2132 const u32 *formats; 2133 int num_formats; 2134 int ret; 2135 2136 plane = intel_plane_alloc(); 2137 if (IS_ERR(plane)) 2138 return plane; 2139 2140 plane->pipe = pipe; 2141 plane->id = plane_id; 2142 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id); 2143 2144 intel_fbc_add_plane(skl_plane_fbc(dev_priv, pipe, plane_id), plane); 2145 2146 if (DISPLAY_VER(dev_priv) >= 11) { 2147 plane->min_width = icl_plane_min_width; 2148 if (icl_is_hdr_plane(dev_priv, plane_id)) 2149 plane->max_width = icl_hdr_plane_max_width; 2150 else 2151 plane->max_width = icl_sdr_plane_max_width; 2152 plane->max_height = icl_plane_max_height; 2153 plane->min_cdclk = icl_plane_min_cdclk; 2154 } else if (DISPLAY_VER(dev_priv) >= 10) { 2155 plane->max_width = glk_plane_max_width; 2156 plane->max_height = skl_plane_max_height; 2157 plane->min_cdclk = glk_plane_min_cdclk; 2158 } else { 2159 plane->max_width = skl_plane_max_width; 2160 plane->max_height = skl_plane_max_height; 2161 plane->min_cdclk = skl_plane_min_cdclk; 2162 } 2163 2164 plane->max_stride = skl_plane_max_stride; 2165 plane->update_noarm = skl_plane_update_noarm; 2166 plane->update_arm = skl_plane_update_arm; 2167 plane->disable_arm = skl_plane_disable_arm; 2168 plane->get_hw_state = skl_plane_get_hw_state; 2169 plane->check_plane = skl_plane_check; 2170 2171 if (plane_id == PLANE_PRIMARY) { 2172 plane->need_async_flip_disable_wa = IS_DISPLAY_VER(dev_priv, 2173 9, 10); 2174 plane->async_flip = skl_plane_async_flip; 2175 plane->enable_flip_done = skl_plane_enable_flip_done; 2176 plane->disable_flip_done = skl_plane_disable_flip_done; 2177 } 2178 2179 if (DISPLAY_VER(dev_priv) >= 11) 2180 formats = icl_get_plane_formats(dev_priv, pipe, 2181 plane_id, &num_formats); 2182 else if (DISPLAY_VER(dev_priv) >= 10) 2183 formats = glk_get_plane_formats(dev_priv, pipe, 2184 plane_id, &num_formats); 2185 else 2186 formats = skl_get_plane_formats(dev_priv, pipe, 2187 plane_id, &num_formats); 2188 2189 if (DISPLAY_VER(dev_priv) >= 12) 2190 plane_funcs = &gen12_plane_funcs; 2191 else 2192 plane_funcs = &skl_plane_funcs; 2193 2194 if (plane_id == PLANE_PRIMARY) 2195 plane_type = DRM_PLANE_TYPE_PRIMARY; 2196 else 2197 plane_type = DRM_PLANE_TYPE_OVERLAY; 2198 2199 modifiers = intel_fb_plane_get_modifiers(dev_priv, 2200 skl_get_plane_caps(dev_priv, pipe, plane_id)); 2201 2202 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 2203 0, plane_funcs, 2204 formats, num_formats, modifiers, 2205 plane_type, 2206 "plane %d%c", plane_id + 1, 2207 pipe_name(pipe)); 2208 2209 kfree(modifiers); 2210 2211 if (ret) 2212 goto fail; 2213 2214 if (DISPLAY_VER(dev_priv) >= 13) 2215 supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 2216 else 2217 supported_rotations = 2218 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 2219 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 2220 2221 if (DISPLAY_VER(dev_priv) >= 11) 2222 supported_rotations |= DRM_MODE_REFLECT_X; 2223 2224 drm_plane_create_rotation_property(&plane->base, 2225 DRM_MODE_ROTATE_0, 2226 supported_rotations); 2227 2228 supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709); 2229 2230 if (DISPLAY_VER(dev_priv) >= 10) 2231 supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020); 2232 2233 drm_plane_create_color_properties(&plane->base, 2234 supported_csc, 2235 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 2236 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 2237 DRM_COLOR_YCBCR_BT709, 2238 DRM_COLOR_YCBCR_LIMITED_RANGE); 2239 2240 drm_plane_create_alpha_property(&plane->base); 2241 drm_plane_create_blend_mode_property(&plane->base, 2242 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 2243 BIT(DRM_MODE_BLEND_PREMULTI) | 2244 BIT(DRM_MODE_BLEND_COVERAGE)); 2245 2246 drm_plane_create_zpos_immutable_property(&plane->base, plane_id); 2247 2248 if (DISPLAY_VER(dev_priv) >= 12) 2249 drm_plane_enable_fb_damage_clips(&plane->base); 2250 2251 if (DISPLAY_VER(dev_priv) >= 11) 2252 drm_plane_create_scaling_filter_property(&plane->base, 2253 BIT(DRM_SCALING_FILTER_DEFAULT) | 2254 BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); 2255 2256 intel_plane_helper_add(plane); 2257 2258 return plane; 2259 2260 fail: 2261 intel_plane_free(plane); 2262 2263 return ERR_PTR(ret); 2264 } 2265 2266 void 2267 skl_get_initial_plane_config(struct intel_crtc *crtc, 2268 struct intel_initial_plane_config *plane_config) 2269 { 2270 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 2271 struct drm_device *dev = crtc->base.dev; 2272 struct drm_i915_private *dev_priv = to_i915(dev); 2273 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 2274 enum plane_id plane_id = plane->id; 2275 enum pipe pipe; 2276 u32 val, base, offset, stride_mult, tiling, alpha; 2277 int fourcc, pixel_format; 2278 unsigned int aligned_height; 2279 struct drm_framebuffer *fb; 2280 struct intel_framebuffer *intel_fb; 2281 2282 if (!plane->get_hw_state(plane, &pipe)) 2283 return; 2284 2285 drm_WARN_ON(dev, pipe != crtc->pipe); 2286 2287 if (crtc_state->bigjoiner) { 2288 drm_dbg_kms(&dev_priv->drm, 2289 "Unsupported bigjoiner configuration for initial FB\n"); 2290 return; 2291 } 2292 2293 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 2294 if (!intel_fb) { 2295 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); 2296 return; 2297 } 2298 2299 fb = &intel_fb->base; 2300 2301 fb->dev = dev; 2302 2303 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id)); 2304 2305 if (DISPLAY_VER(dev_priv) >= 11) 2306 pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL; 2307 else 2308 pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL; 2309 2310 if (DISPLAY_VER(dev_priv) >= 10) { 2311 u32 color_ctl; 2312 2313 color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id)); 2314 alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl); 2315 } else { 2316 alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val); 2317 } 2318 2319 fourcc = skl_format_to_fourcc(pixel_format, 2320 val & PLANE_CTL_ORDER_RGBX, alpha); 2321 fb->format = drm_format_info(fourcc); 2322 2323 tiling = val & PLANE_CTL_TILED_MASK; 2324 switch (tiling) { 2325 case PLANE_CTL_TILED_LINEAR: 2326 fb->modifier = DRM_FORMAT_MOD_LINEAR; 2327 break; 2328 case PLANE_CTL_TILED_X: 2329 plane_config->tiling = I915_TILING_X; 2330 fb->modifier = I915_FORMAT_MOD_X_TILED; 2331 break; 2332 case PLANE_CTL_TILED_Y: 2333 plane_config->tiling = I915_TILING_Y; 2334 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2335 fb->modifier = DISPLAY_VER(dev_priv) >= 12 ? 2336 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS : 2337 I915_FORMAT_MOD_Y_TILED_CCS; 2338 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) 2339 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; 2340 else 2341 fb->modifier = I915_FORMAT_MOD_Y_TILED; 2342 break; 2343 case PLANE_CTL_TILED_YF: 2344 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2345 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; 2346 else 2347 fb->modifier = I915_FORMAT_MOD_Yf_TILED; 2348 break; 2349 default: 2350 MISSING_CASE(tiling); 2351 goto error; 2352 } 2353 2354 /* 2355 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr 2356 * while i915 HW rotation is clockwise, thats why this swapping. 2357 */ 2358 switch (val & PLANE_CTL_ROTATE_MASK) { 2359 case PLANE_CTL_ROTATE_0: 2360 plane_config->rotation = DRM_MODE_ROTATE_0; 2361 break; 2362 case PLANE_CTL_ROTATE_90: 2363 plane_config->rotation = DRM_MODE_ROTATE_270; 2364 break; 2365 case PLANE_CTL_ROTATE_180: 2366 plane_config->rotation = DRM_MODE_ROTATE_180; 2367 break; 2368 case PLANE_CTL_ROTATE_270: 2369 plane_config->rotation = DRM_MODE_ROTATE_90; 2370 break; 2371 } 2372 2373 if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL) 2374 plane_config->rotation |= DRM_MODE_REFLECT_X; 2375 2376 /* 90/270 degree rotation would require extra work */ 2377 if (drm_rotation_90_or_270(plane_config->rotation)) 2378 goto error; 2379 2380 base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK; 2381 plane_config->base = base; 2382 2383 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id)); 2384 2385 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id)); 2386 fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1; 2387 fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1; 2388 2389 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id)); 2390 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0); 2391 2392 fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult; 2393 2394 aligned_height = intel_fb_align_height(fb, 0, fb->height); 2395 2396 plane_config->size = fb->pitches[0] * aligned_height; 2397 2398 drm_dbg_kms(&dev_priv->drm, 2399 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 2400 crtc->base.name, plane->base.name, fb->width, fb->height, 2401 fb->format->cpp[0] * 8, base, fb->pitches[0], 2402 plane_config->size); 2403 2404 plane_config->fb = intel_fb; 2405 return; 2406 2407 error: 2408 kfree(intel_fb); 2409 } 2410