1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <drm/drm_atomic_helper.h> 7 #include <drm/drm_blend.h> 8 #include <drm/drm_damage_helper.h> 9 #include <drm/drm_fourcc.h> 10 11 #include "i915_drv.h" 12 #include "i915_irq.h" 13 #include "i915_reg.h" 14 #include "intel_atomic_plane.h" 15 #include "intel_de.h" 16 #include "intel_display_types.h" 17 #include "intel_fb.h" 18 #include "intel_fbc.h" 19 #include "intel_psr.h" 20 #include "skl_scaler.h" 21 #include "skl_universal_plane.h" 22 #include "skl_watermark.h" 23 #include "pxp/intel_pxp.h" 24 25 static const u32 skl_plane_formats[] = { 26 DRM_FORMAT_C8, 27 DRM_FORMAT_RGB565, 28 DRM_FORMAT_XRGB8888, 29 DRM_FORMAT_XBGR8888, 30 DRM_FORMAT_ARGB8888, 31 DRM_FORMAT_ABGR8888, 32 DRM_FORMAT_XRGB2101010, 33 DRM_FORMAT_XBGR2101010, 34 DRM_FORMAT_XRGB16161616F, 35 DRM_FORMAT_XBGR16161616F, 36 DRM_FORMAT_YUYV, 37 DRM_FORMAT_YVYU, 38 DRM_FORMAT_UYVY, 39 DRM_FORMAT_VYUY, 40 DRM_FORMAT_XYUV8888, 41 }; 42 43 static const u32 skl_planar_formats[] = { 44 DRM_FORMAT_C8, 45 DRM_FORMAT_RGB565, 46 DRM_FORMAT_XRGB8888, 47 DRM_FORMAT_XBGR8888, 48 DRM_FORMAT_ARGB8888, 49 DRM_FORMAT_ABGR8888, 50 DRM_FORMAT_XRGB2101010, 51 DRM_FORMAT_XBGR2101010, 52 DRM_FORMAT_XRGB16161616F, 53 DRM_FORMAT_XBGR16161616F, 54 DRM_FORMAT_YUYV, 55 DRM_FORMAT_YVYU, 56 DRM_FORMAT_UYVY, 57 DRM_FORMAT_VYUY, 58 DRM_FORMAT_NV12, 59 DRM_FORMAT_XYUV8888, 60 }; 61 62 static const u32 glk_planar_formats[] = { 63 DRM_FORMAT_C8, 64 DRM_FORMAT_RGB565, 65 DRM_FORMAT_XRGB8888, 66 DRM_FORMAT_XBGR8888, 67 DRM_FORMAT_ARGB8888, 68 DRM_FORMAT_ABGR8888, 69 DRM_FORMAT_XRGB2101010, 70 DRM_FORMAT_XBGR2101010, 71 DRM_FORMAT_XRGB16161616F, 72 DRM_FORMAT_XBGR16161616F, 73 DRM_FORMAT_YUYV, 74 DRM_FORMAT_YVYU, 75 DRM_FORMAT_UYVY, 76 DRM_FORMAT_VYUY, 77 DRM_FORMAT_NV12, 78 DRM_FORMAT_XYUV8888, 79 DRM_FORMAT_P010, 80 DRM_FORMAT_P012, 81 DRM_FORMAT_P016, 82 }; 83 84 static const u32 icl_sdr_y_plane_formats[] = { 85 DRM_FORMAT_C8, 86 DRM_FORMAT_RGB565, 87 DRM_FORMAT_XRGB8888, 88 DRM_FORMAT_XBGR8888, 89 DRM_FORMAT_ARGB8888, 90 DRM_FORMAT_ABGR8888, 91 DRM_FORMAT_XRGB2101010, 92 DRM_FORMAT_XBGR2101010, 93 DRM_FORMAT_ARGB2101010, 94 DRM_FORMAT_ABGR2101010, 95 DRM_FORMAT_YUYV, 96 DRM_FORMAT_YVYU, 97 DRM_FORMAT_UYVY, 98 DRM_FORMAT_VYUY, 99 DRM_FORMAT_Y210, 100 DRM_FORMAT_Y212, 101 DRM_FORMAT_Y216, 102 DRM_FORMAT_XYUV8888, 103 DRM_FORMAT_XVYU2101010, 104 DRM_FORMAT_XVYU12_16161616, 105 DRM_FORMAT_XVYU16161616, 106 }; 107 108 static const u32 icl_sdr_uv_plane_formats[] = { 109 DRM_FORMAT_C8, 110 DRM_FORMAT_RGB565, 111 DRM_FORMAT_XRGB8888, 112 DRM_FORMAT_XBGR8888, 113 DRM_FORMAT_ARGB8888, 114 DRM_FORMAT_ABGR8888, 115 DRM_FORMAT_XRGB2101010, 116 DRM_FORMAT_XBGR2101010, 117 DRM_FORMAT_ARGB2101010, 118 DRM_FORMAT_ABGR2101010, 119 DRM_FORMAT_YUYV, 120 DRM_FORMAT_YVYU, 121 DRM_FORMAT_UYVY, 122 DRM_FORMAT_VYUY, 123 DRM_FORMAT_NV12, 124 DRM_FORMAT_P010, 125 DRM_FORMAT_P012, 126 DRM_FORMAT_P016, 127 DRM_FORMAT_Y210, 128 DRM_FORMAT_Y212, 129 DRM_FORMAT_Y216, 130 DRM_FORMAT_XYUV8888, 131 DRM_FORMAT_XVYU2101010, 132 DRM_FORMAT_XVYU12_16161616, 133 DRM_FORMAT_XVYU16161616, 134 }; 135 136 static const u32 icl_hdr_plane_formats[] = { 137 DRM_FORMAT_C8, 138 DRM_FORMAT_RGB565, 139 DRM_FORMAT_XRGB8888, 140 DRM_FORMAT_XBGR8888, 141 DRM_FORMAT_ARGB8888, 142 DRM_FORMAT_ABGR8888, 143 DRM_FORMAT_XRGB2101010, 144 DRM_FORMAT_XBGR2101010, 145 DRM_FORMAT_ARGB2101010, 146 DRM_FORMAT_ABGR2101010, 147 DRM_FORMAT_XRGB16161616F, 148 DRM_FORMAT_XBGR16161616F, 149 DRM_FORMAT_ARGB16161616F, 150 DRM_FORMAT_ABGR16161616F, 151 DRM_FORMAT_YUYV, 152 DRM_FORMAT_YVYU, 153 DRM_FORMAT_UYVY, 154 DRM_FORMAT_VYUY, 155 DRM_FORMAT_NV12, 156 DRM_FORMAT_P010, 157 DRM_FORMAT_P012, 158 DRM_FORMAT_P016, 159 DRM_FORMAT_Y210, 160 DRM_FORMAT_Y212, 161 DRM_FORMAT_Y216, 162 DRM_FORMAT_XYUV8888, 163 DRM_FORMAT_XVYU2101010, 164 DRM_FORMAT_XVYU12_16161616, 165 DRM_FORMAT_XVYU16161616, 166 }; 167 168 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) 169 { 170 switch (format) { 171 case PLANE_CTL_FORMAT_RGB_565: 172 return DRM_FORMAT_RGB565; 173 case PLANE_CTL_FORMAT_NV12: 174 return DRM_FORMAT_NV12; 175 case PLANE_CTL_FORMAT_XYUV: 176 return DRM_FORMAT_XYUV8888; 177 case PLANE_CTL_FORMAT_P010: 178 return DRM_FORMAT_P010; 179 case PLANE_CTL_FORMAT_P012: 180 return DRM_FORMAT_P012; 181 case PLANE_CTL_FORMAT_P016: 182 return DRM_FORMAT_P016; 183 case PLANE_CTL_FORMAT_Y210: 184 return DRM_FORMAT_Y210; 185 case PLANE_CTL_FORMAT_Y212: 186 return DRM_FORMAT_Y212; 187 case PLANE_CTL_FORMAT_Y216: 188 return DRM_FORMAT_Y216; 189 case PLANE_CTL_FORMAT_Y410: 190 return DRM_FORMAT_XVYU2101010; 191 case PLANE_CTL_FORMAT_Y412: 192 return DRM_FORMAT_XVYU12_16161616; 193 case PLANE_CTL_FORMAT_Y416: 194 return DRM_FORMAT_XVYU16161616; 195 default: 196 case PLANE_CTL_FORMAT_XRGB_8888: 197 if (rgb_order) { 198 if (alpha) 199 return DRM_FORMAT_ABGR8888; 200 else 201 return DRM_FORMAT_XBGR8888; 202 } else { 203 if (alpha) 204 return DRM_FORMAT_ARGB8888; 205 else 206 return DRM_FORMAT_XRGB8888; 207 } 208 case PLANE_CTL_FORMAT_XRGB_2101010: 209 if (rgb_order) { 210 if (alpha) 211 return DRM_FORMAT_ABGR2101010; 212 else 213 return DRM_FORMAT_XBGR2101010; 214 } else { 215 if (alpha) 216 return DRM_FORMAT_ARGB2101010; 217 else 218 return DRM_FORMAT_XRGB2101010; 219 } 220 case PLANE_CTL_FORMAT_XRGB_16161616F: 221 if (rgb_order) { 222 if (alpha) 223 return DRM_FORMAT_ABGR16161616F; 224 else 225 return DRM_FORMAT_XBGR16161616F; 226 } else { 227 if (alpha) 228 return DRM_FORMAT_ARGB16161616F; 229 else 230 return DRM_FORMAT_XRGB16161616F; 231 } 232 } 233 } 234 235 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915) 236 { 237 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) 238 return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3); 239 else 240 return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5); 241 } 242 243 bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, 244 enum plane_id plane_id) 245 { 246 return DISPLAY_VER(dev_priv) >= 11 && 247 icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id); 248 } 249 250 u8 icl_hdr_plane_mask(void) 251 { 252 return BIT(PLANE_PRIMARY) | BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1); 253 } 254 255 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) 256 { 257 return DISPLAY_VER(dev_priv) >= 11 && 258 icl_hdr_plane_mask() & BIT(plane_id); 259 } 260 261 static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 262 const struct intel_plane_state *plane_state) 263 { 264 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 265 266 /* two pixels per clock */ 267 return DIV_ROUND_UP(pixel_rate, 2); 268 } 269 270 static void 271 glk_plane_ratio(const struct intel_plane_state *plane_state, 272 unsigned int *num, unsigned int *den) 273 { 274 const struct drm_framebuffer *fb = plane_state->hw.fb; 275 276 if (fb->format->cpp[0] == 8) { 277 *num = 10; 278 *den = 8; 279 } else { 280 *num = 1; 281 *den = 1; 282 } 283 } 284 285 static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 286 const struct intel_plane_state *plane_state) 287 { 288 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 289 unsigned int num, den; 290 291 glk_plane_ratio(plane_state, &num, &den); 292 293 /* two pixels per clock */ 294 return DIV_ROUND_UP(pixel_rate * num, 2 * den); 295 } 296 297 static void 298 skl_plane_ratio(const struct intel_plane_state *plane_state, 299 unsigned int *num, unsigned int *den) 300 { 301 const struct drm_framebuffer *fb = plane_state->hw.fb; 302 303 if (fb->format->cpp[0] == 8) { 304 *num = 9; 305 *den = 8; 306 } else { 307 *num = 1; 308 *den = 1; 309 } 310 } 311 312 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 313 const struct intel_plane_state *plane_state) 314 { 315 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 316 unsigned int num, den; 317 318 skl_plane_ratio(plane_state, &num, &den); 319 320 return DIV_ROUND_UP(pixel_rate * num, den); 321 } 322 323 static int skl_plane_max_width(const struct drm_framebuffer *fb, 324 int color_plane, 325 unsigned int rotation) 326 { 327 int cpp = fb->format->cpp[color_plane]; 328 329 switch (fb->modifier) { 330 case DRM_FORMAT_MOD_LINEAR: 331 case I915_FORMAT_MOD_X_TILED: 332 /* 333 * Validated limit is 4k, but has 5k should 334 * work apart from the following features: 335 * - Ytile (already limited to 4k) 336 * - FP16 (already limited to 4k) 337 * - render compression (already limited to 4k) 338 * - KVMR sprite and cursor (don't care) 339 * - horizontal panning (TODO verify this) 340 * - pipe and plane scaling (TODO verify this) 341 */ 342 if (cpp == 8) 343 return 4096; 344 else 345 return 5120; 346 case I915_FORMAT_MOD_Y_TILED_CCS: 347 case I915_FORMAT_MOD_Yf_TILED_CCS: 348 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 349 /* FIXME AUX plane? */ 350 case I915_FORMAT_MOD_Y_TILED: 351 case I915_FORMAT_MOD_Yf_TILED: 352 if (cpp == 8) 353 return 2048; 354 else 355 return 4096; 356 default: 357 MISSING_CASE(fb->modifier); 358 return 2048; 359 } 360 } 361 362 static int glk_plane_max_width(const struct drm_framebuffer *fb, 363 int color_plane, 364 unsigned int rotation) 365 { 366 int cpp = fb->format->cpp[color_plane]; 367 368 switch (fb->modifier) { 369 case DRM_FORMAT_MOD_LINEAR: 370 case I915_FORMAT_MOD_X_TILED: 371 if (cpp == 8) 372 return 4096; 373 else 374 return 5120; 375 case I915_FORMAT_MOD_Y_TILED_CCS: 376 case I915_FORMAT_MOD_Yf_TILED_CCS: 377 /* FIXME AUX plane? */ 378 case I915_FORMAT_MOD_Y_TILED: 379 case I915_FORMAT_MOD_Yf_TILED: 380 if (cpp == 8) 381 return 2048; 382 else 383 return 5120; 384 default: 385 MISSING_CASE(fb->modifier); 386 return 2048; 387 } 388 } 389 390 static int icl_plane_min_width(const struct drm_framebuffer *fb, 391 int color_plane, 392 unsigned int rotation) 393 { 394 /* Wa_14011264657, Wa_14011050563: gen11+ */ 395 switch (fb->format->format) { 396 case DRM_FORMAT_C8: 397 return 18; 398 case DRM_FORMAT_RGB565: 399 return 10; 400 case DRM_FORMAT_XRGB8888: 401 case DRM_FORMAT_XBGR8888: 402 case DRM_FORMAT_ARGB8888: 403 case DRM_FORMAT_ABGR8888: 404 case DRM_FORMAT_XRGB2101010: 405 case DRM_FORMAT_XBGR2101010: 406 case DRM_FORMAT_ARGB2101010: 407 case DRM_FORMAT_ABGR2101010: 408 case DRM_FORMAT_XVYU2101010: 409 case DRM_FORMAT_Y212: 410 case DRM_FORMAT_Y216: 411 return 6; 412 case DRM_FORMAT_NV12: 413 return 20; 414 case DRM_FORMAT_P010: 415 case DRM_FORMAT_P012: 416 case DRM_FORMAT_P016: 417 return 12; 418 case DRM_FORMAT_XRGB16161616F: 419 case DRM_FORMAT_XBGR16161616F: 420 case DRM_FORMAT_ARGB16161616F: 421 case DRM_FORMAT_ABGR16161616F: 422 case DRM_FORMAT_XVYU12_16161616: 423 case DRM_FORMAT_XVYU16161616: 424 return 4; 425 default: 426 return 1; 427 } 428 } 429 430 static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb, 431 int color_plane, 432 unsigned int rotation) 433 { 434 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 435 return 4096; 436 else 437 return 5120; 438 } 439 440 static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb, 441 int color_plane, 442 unsigned int rotation) 443 { 444 return 5120; 445 } 446 447 static int skl_plane_max_height(const struct drm_framebuffer *fb, 448 int color_plane, 449 unsigned int rotation) 450 { 451 return 4096; 452 } 453 454 static int icl_plane_max_height(const struct drm_framebuffer *fb, 455 int color_plane, 456 unsigned int rotation) 457 { 458 return 4320; 459 } 460 461 static unsigned int 462 skl_plane_max_stride(struct intel_plane *plane, 463 u32 pixel_format, u64 modifier, 464 unsigned int rotation) 465 { 466 struct drm_i915_private *i915 = to_i915(plane->base.dev); 467 const struct drm_format_info *info = drm_format_info(pixel_format); 468 int cpp = info->cpp[0]; 469 int max_horizontal_pixels = 8192; 470 int max_stride_bytes; 471 472 if (DISPLAY_VER(i915) >= 13) { 473 /* 474 * The stride in bytes must not exceed of the size 475 * of 128K bytes. For pixel formats of 64bpp will allow 476 * for a 16K pixel surface. 477 */ 478 max_stride_bytes = 131072; 479 if (cpp == 8) 480 max_horizontal_pixels = 16384; 481 else 482 max_horizontal_pixels = 65536; 483 } else { 484 /* 485 * "The stride in bytes must not exceed the 486 * of the size of 8K pixels and 32K bytes." 487 */ 488 max_stride_bytes = 32768; 489 } 490 491 if (drm_rotation_90_or_270(rotation)) 492 return min(max_horizontal_pixels, max_stride_bytes / cpp); 493 else 494 return min(max_horizontal_pixels * cpp, max_stride_bytes); 495 } 496 497 498 /* Preoffset values for YUV to RGB Conversion */ 499 #define PREOFF_YUV_TO_RGB_HI 0x1800 500 #define PREOFF_YUV_TO_RGB_ME 0x0000 501 #define PREOFF_YUV_TO_RGB_LO 0x1800 502 503 #define ROFF(x) (((x) & 0xffff) << 16) 504 #define GOFF(x) (((x) & 0xffff) << 0) 505 #define BOFF(x) (((x) & 0xffff) << 16) 506 507 /* 508 * Programs the input color space conversion stage for ICL HDR planes. 509 * Note that it is assumed that this stage always happens after YUV 510 * range correction. Thus, the input to this stage is assumed to be 511 * in full-range YCbCr. 512 */ 513 static void 514 icl_program_input_csc(struct intel_plane *plane, 515 const struct intel_crtc_state *crtc_state, 516 const struct intel_plane_state *plane_state) 517 { 518 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 519 enum pipe pipe = plane->pipe; 520 enum plane_id plane_id = plane->id; 521 522 static const u16 input_csc_matrix[][9] = { 523 /* 524 * BT.601 full range YCbCr -> full range RGB 525 * The matrix required is : 526 * [1.000, 0.000, 1.371, 527 * 1.000, -0.336, -0.698, 528 * 1.000, 1.732, 0.0000] 529 */ 530 [DRM_COLOR_YCBCR_BT601] = { 531 0x7AF8, 0x7800, 0x0, 532 0x8B28, 0x7800, 0x9AC0, 533 0x0, 0x7800, 0x7DD8, 534 }, 535 /* 536 * BT.709 full range YCbCr -> full range RGB 537 * The matrix required is : 538 * [1.000, 0.000, 1.574, 539 * 1.000, -0.187, -0.468, 540 * 1.000, 1.855, 0.0000] 541 */ 542 [DRM_COLOR_YCBCR_BT709] = { 543 0x7C98, 0x7800, 0x0, 544 0x9EF8, 0x7800, 0xAC00, 545 0x0, 0x7800, 0x7ED8, 546 }, 547 /* 548 * BT.2020 full range YCbCr -> full range RGB 549 * The matrix required is : 550 * [1.000, 0.000, 1.474, 551 * 1.000, -0.1645, -0.5713, 552 * 1.000, 1.8814, 0.0000] 553 */ 554 [DRM_COLOR_YCBCR_BT2020] = { 555 0x7BC8, 0x7800, 0x0, 556 0x8928, 0x7800, 0xAA88, 557 0x0, 0x7800, 0x7F10, 558 }, 559 }; 560 const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding]; 561 562 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), 563 ROFF(csc[0]) | GOFF(csc[1])); 564 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), 565 BOFF(csc[2])); 566 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), 567 ROFF(csc[3]) | GOFF(csc[4])); 568 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), 569 BOFF(csc[5])); 570 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), 571 ROFF(csc[6]) | GOFF(csc[7])); 572 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), 573 BOFF(csc[8])); 574 575 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), 576 PREOFF_YUV_TO_RGB_HI); 577 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 578 PREOFF_YUV_TO_RGB_ME); 579 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), 580 PREOFF_YUV_TO_RGB_LO); 581 intel_de_write_fw(dev_priv, 582 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); 583 intel_de_write_fw(dev_priv, 584 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); 585 intel_de_write_fw(dev_priv, 586 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); 587 } 588 589 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb, 590 int color_plane, unsigned int rotation) 591 { 592 /* 593 * The stride is either expressed as a multiple of 64 bytes chunks for 594 * linear buffers or in number of tiles for tiled buffers. 595 */ 596 if (is_surface_linear(fb, color_plane)) 597 return 64; 598 else if (drm_rotation_90_or_270(rotation)) 599 return intel_tile_height(fb, color_plane); 600 else 601 return intel_tile_width_bytes(fb, color_plane); 602 } 603 604 static u32 skl_plane_stride(const struct intel_plane_state *plane_state, 605 int color_plane) 606 { 607 const struct drm_framebuffer *fb = plane_state->hw.fb; 608 unsigned int rotation = plane_state->hw.rotation; 609 u32 stride = plane_state->view.color_plane[color_plane].scanout_stride; 610 611 if (color_plane >= fb->format->num_planes) 612 return 0; 613 614 return stride / skl_plane_stride_mult(fb, color_plane, rotation); 615 } 616 617 static void 618 skl_plane_disable_arm(struct intel_plane *plane, 619 const struct intel_crtc_state *crtc_state) 620 { 621 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 622 enum plane_id plane_id = plane->id; 623 enum pipe pipe = plane->pipe; 624 625 skl_write_plane_wm(plane, crtc_state); 626 627 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); 628 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); 629 } 630 631 static void 632 icl_plane_disable_arm(struct intel_plane *plane, 633 const struct intel_crtc_state *crtc_state) 634 { 635 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 636 enum plane_id plane_id = plane->id; 637 enum pipe pipe = plane->pipe; 638 639 if (icl_is_hdr_plane(dev_priv, plane_id)) 640 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0); 641 642 skl_write_plane_wm(plane, crtc_state); 643 644 intel_psr2_disable_plane_sel_fetch_arm(plane, crtc_state); 645 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); 646 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); 647 } 648 649 static bool 650 skl_plane_get_hw_state(struct intel_plane *plane, 651 enum pipe *pipe) 652 { 653 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 654 enum intel_display_power_domain power_domain; 655 enum plane_id plane_id = plane->id; 656 intel_wakeref_t wakeref; 657 bool ret; 658 659 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 660 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 661 if (!wakeref) 662 return false; 663 664 ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; 665 666 *pipe = plane->pipe; 667 668 intel_display_power_put(dev_priv, power_domain, wakeref); 669 670 return ret; 671 } 672 673 static u32 skl_plane_ctl_format(u32 pixel_format) 674 { 675 switch (pixel_format) { 676 case DRM_FORMAT_C8: 677 return PLANE_CTL_FORMAT_INDEXED; 678 case DRM_FORMAT_RGB565: 679 return PLANE_CTL_FORMAT_RGB_565; 680 case DRM_FORMAT_XBGR8888: 681 case DRM_FORMAT_ABGR8888: 682 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; 683 case DRM_FORMAT_XRGB8888: 684 case DRM_FORMAT_ARGB8888: 685 return PLANE_CTL_FORMAT_XRGB_8888; 686 case DRM_FORMAT_XBGR2101010: 687 case DRM_FORMAT_ABGR2101010: 688 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX; 689 case DRM_FORMAT_XRGB2101010: 690 case DRM_FORMAT_ARGB2101010: 691 return PLANE_CTL_FORMAT_XRGB_2101010; 692 case DRM_FORMAT_XBGR16161616F: 693 case DRM_FORMAT_ABGR16161616F: 694 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX; 695 case DRM_FORMAT_XRGB16161616F: 696 case DRM_FORMAT_ARGB16161616F: 697 return PLANE_CTL_FORMAT_XRGB_16161616F; 698 case DRM_FORMAT_XYUV8888: 699 return PLANE_CTL_FORMAT_XYUV; 700 case DRM_FORMAT_YUYV: 701 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV; 702 case DRM_FORMAT_YVYU: 703 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU; 704 case DRM_FORMAT_UYVY: 705 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY; 706 case DRM_FORMAT_VYUY: 707 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY; 708 case DRM_FORMAT_NV12: 709 return PLANE_CTL_FORMAT_NV12; 710 case DRM_FORMAT_P010: 711 return PLANE_CTL_FORMAT_P010; 712 case DRM_FORMAT_P012: 713 return PLANE_CTL_FORMAT_P012; 714 case DRM_FORMAT_P016: 715 return PLANE_CTL_FORMAT_P016; 716 case DRM_FORMAT_Y210: 717 return PLANE_CTL_FORMAT_Y210; 718 case DRM_FORMAT_Y212: 719 return PLANE_CTL_FORMAT_Y212; 720 case DRM_FORMAT_Y216: 721 return PLANE_CTL_FORMAT_Y216; 722 case DRM_FORMAT_XVYU2101010: 723 return PLANE_CTL_FORMAT_Y410; 724 case DRM_FORMAT_XVYU12_16161616: 725 return PLANE_CTL_FORMAT_Y412; 726 case DRM_FORMAT_XVYU16161616: 727 return PLANE_CTL_FORMAT_Y416; 728 default: 729 MISSING_CASE(pixel_format); 730 } 731 732 return 0; 733 } 734 735 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state) 736 { 737 if (!plane_state->hw.fb->format->has_alpha) 738 return PLANE_CTL_ALPHA_DISABLE; 739 740 switch (plane_state->hw.pixel_blend_mode) { 741 case DRM_MODE_BLEND_PIXEL_NONE: 742 return PLANE_CTL_ALPHA_DISABLE; 743 case DRM_MODE_BLEND_PREMULTI: 744 return PLANE_CTL_ALPHA_SW_PREMULTIPLY; 745 case DRM_MODE_BLEND_COVERAGE: 746 return PLANE_CTL_ALPHA_HW_PREMULTIPLY; 747 default: 748 MISSING_CASE(plane_state->hw.pixel_blend_mode); 749 return PLANE_CTL_ALPHA_DISABLE; 750 } 751 } 752 753 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state) 754 { 755 if (!plane_state->hw.fb->format->has_alpha) 756 return PLANE_COLOR_ALPHA_DISABLE; 757 758 switch (plane_state->hw.pixel_blend_mode) { 759 case DRM_MODE_BLEND_PIXEL_NONE: 760 return PLANE_COLOR_ALPHA_DISABLE; 761 case DRM_MODE_BLEND_PREMULTI: 762 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY; 763 case DRM_MODE_BLEND_COVERAGE: 764 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY; 765 default: 766 MISSING_CASE(plane_state->hw.pixel_blend_mode); 767 return PLANE_COLOR_ALPHA_DISABLE; 768 } 769 } 770 771 static u32 skl_plane_ctl_tiling(u64 fb_modifier) 772 { 773 switch (fb_modifier) { 774 case DRM_FORMAT_MOD_LINEAR: 775 break; 776 case I915_FORMAT_MOD_X_TILED: 777 return PLANE_CTL_TILED_X; 778 case I915_FORMAT_MOD_Y_TILED: 779 return PLANE_CTL_TILED_Y; 780 case I915_FORMAT_MOD_4_TILED: 781 return PLANE_CTL_TILED_4; 782 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: 783 return PLANE_CTL_TILED_4 | 784 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 785 PLANE_CTL_CLEAR_COLOR_DISABLE; 786 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: 787 return PLANE_CTL_TILED_4 | 788 PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE | 789 PLANE_CTL_CLEAR_COLOR_DISABLE; 790 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: 791 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 792 case I915_FORMAT_MOD_Y_TILED_CCS: 793 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 794 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 795 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 796 return PLANE_CTL_TILED_Y | 797 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 798 PLANE_CTL_CLEAR_COLOR_DISABLE; 799 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 800 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE; 801 case I915_FORMAT_MOD_Yf_TILED: 802 return PLANE_CTL_TILED_YF; 803 case I915_FORMAT_MOD_Yf_TILED_CCS: 804 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 805 default: 806 MISSING_CASE(fb_modifier); 807 } 808 809 return 0; 810 } 811 812 static u32 skl_plane_ctl_rotate(unsigned int rotate) 813 { 814 switch (rotate) { 815 case DRM_MODE_ROTATE_0: 816 break; 817 /* 818 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr 819 * while i915 HW rotation is clockwise, thats why this swapping. 820 */ 821 case DRM_MODE_ROTATE_90: 822 return PLANE_CTL_ROTATE_270; 823 case DRM_MODE_ROTATE_180: 824 return PLANE_CTL_ROTATE_180; 825 case DRM_MODE_ROTATE_270: 826 return PLANE_CTL_ROTATE_90; 827 default: 828 MISSING_CASE(rotate); 829 } 830 831 return 0; 832 } 833 834 static u32 icl_plane_ctl_flip(unsigned int reflect) 835 { 836 switch (reflect) { 837 case 0: 838 break; 839 case DRM_MODE_REFLECT_X: 840 return PLANE_CTL_FLIP_HORIZONTAL; 841 case DRM_MODE_REFLECT_Y: 842 default: 843 MISSING_CASE(reflect); 844 } 845 846 return 0; 847 } 848 849 static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state) 850 { 851 const struct drm_framebuffer *fb = plane_state->hw.fb; 852 853 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) { 854 switch (fb->format->cpp[0]) { 855 case 2: 856 return PLANE_CTL_ARB_SLOTS(1); 857 default: 858 return PLANE_CTL_ARB_SLOTS(0); 859 } 860 } else { 861 switch (fb->format->cpp[0]) { 862 case 8: 863 return PLANE_CTL_ARB_SLOTS(3); 864 case 4: 865 return PLANE_CTL_ARB_SLOTS(1); 866 default: 867 return PLANE_CTL_ARB_SLOTS(0); 868 } 869 } 870 } 871 872 static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) 873 { 874 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 875 u32 plane_ctl = 0; 876 877 if (DISPLAY_VER(dev_priv) >= 10) 878 return plane_ctl; 879 880 if (crtc_state->gamma_enable) 881 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE; 882 883 if (crtc_state->csc_enable) 884 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE; 885 886 return plane_ctl; 887 } 888 889 static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, 890 const struct intel_plane_state *plane_state) 891 { 892 struct drm_i915_private *dev_priv = 893 to_i915(plane_state->uapi.plane->dev); 894 const struct drm_framebuffer *fb = plane_state->hw.fb; 895 unsigned int rotation = plane_state->hw.rotation; 896 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 897 u32 plane_ctl; 898 899 plane_ctl = PLANE_CTL_ENABLE; 900 901 if (DISPLAY_VER(dev_priv) < 10) { 902 plane_ctl |= skl_plane_ctl_alpha(plane_state); 903 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; 904 905 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 906 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709; 907 908 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 909 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE; 910 } 911 912 plane_ctl |= skl_plane_ctl_format(fb->format->format); 913 plane_ctl |= skl_plane_ctl_tiling(fb->modifier); 914 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK); 915 916 if (DISPLAY_VER(dev_priv) >= 11) 917 plane_ctl |= icl_plane_ctl_flip(rotation & 918 DRM_MODE_REFLECT_MASK); 919 920 if (key->flags & I915_SET_COLORKEY_DESTINATION) 921 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; 922 else if (key->flags & I915_SET_COLORKEY_SOURCE) 923 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; 924 925 /* Wa_22012358565:adl-p */ 926 if (DISPLAY_VER(dev_priv) == 13) 927 plane_ctl |= adlp_plane_ctl_arb_slots(plane_state); 928 929 return plane_ctl; 930 } 931 932 static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) 933 { 934 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 935 u32 plane_color_ctl = 0; 936 937 if (DISPLAY_VER(dev_priv) >= 11) 938 return plane_color_ctl; 939 940 if (crtc_state->gamma_enable) 941 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE; 942 943 if (crtc_state->csc_enable) 944 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE; 945 946 return plane_color_ctl; 947 } 948 949 static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, 950 const struct intel_plane_state *plane_state) 951 { 952 struct drm_i915_private *dev_priv = 953 to_i915(plane_state->uapi.plane->dev); 954 const struct drm_framebuffer *fb = plane_state->hw.fb; 955 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 956 u32 plane_color_ctl = 0; 957 958 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; 959 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); 960 961 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { 962 switch (plane_state->hw.color_encoding) { 963 case DRM_COLOR_YCBCR_BT709: 964 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; 965 break; 966 case DRM_COLOR_YCBCR_BT2020: 967 plane_color_ctl |= 968 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020; 969 break; 970 default: 971 plane_color_ctl |= 972 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601; 973 } 974 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 975 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; 976 } else if (fb->format->is_yuv) { 977 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE; 978 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 979 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; 980 } 981 982 if (plane_state->force_black) 983 plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE; 984 985 return plane_color_ctl; 986 } 987 988 static u32 skl_surf_address(const struct intel_plane_state *plane_state, 989 int color_plane) 990 { 991 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 992 const struct drm_framebuffer *fb = plane_state->hw.fb; 993 u32 offset = plane_state->view.color_plane[color_plane].offset; 994 995 if (intel_fb_uses_dpt(fb)) { 996 /* 997 * The DPT object contains only one vma, so the VMA's offset 998 * within the DPT is always 0. 999 */ 1000 drm_WARN_ON(&i915->drm, plane_state->dpt_vma->node.start); 1001 drm_WARN_ON(&i915->drm, offset & 0x1fffff); 1002 return offset >> 9; 1003 } else { 1004 drm_WARN_ON(&i915->drm, offset & 0xfff); 1005 return offset; 1006 } 1007 } 1008 1009 static u32 skl_plane_surf(const struct intel_plane_state *plane_state, 1010 int color_plane) 1011 { 1012 u32 plane_surf; 1013 1014 plane_surf = intel_plane_ggtt_offset(plane_state) + 1015 skl_surf_address(plane_state, color_plane); 1016 1017 if (plane_state->decrypt) 1018 plane_surf |= PLANE_SURF_DECRYPT; 1019 1020 return plane_surf; 1021 } 1022 1023 static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, 1024 int color_plane) 1025 { 1026 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1027 const struct drm_framebuffer *fb = plane_state->hw.fb; 1028 int aux_plane = skl_main_to_aux_plane(fb, color_plane); 1029 u32 aux_dist; 1030 1031 if (!aux_plane) 1032 return 0; 1033 1034 aux_dist = skl_surf_address(plane_state, aux_plane) - 1035 skl_surf_address(plane_state, color_plane); 1036 1037 if (DISPLAY_VER(i915) < 12) 1038 aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane)); 1039 1040 return aux_dist; 1041 } 1042 1043 static u32 skl_plane_keyval(const struct intel_plane_state *plane_state) 1044 { 1045 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1046 1047 return key->min_value; 1048 } 1049 1050 static u32 skl_plane_keymax(const struct intel_plane_state *plane_state) 1051 { 1052 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1053 u8 alpha = plane_state->hw.alpha >> 8; 1054 1055 return (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha); 1056 } 1057 1058 static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state) 1059 { 1060 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1061 u8 alpha = plane_state->hw.alpha >> 8; 1062 u32 keymsk; 1063 1064 keymsk = key->channel_mask & 0x7ffffff; 1065 if (alpha < 0xff) 1066 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE; 1067 1068 return keymsk; 1069 } 1070 1071 static void icl_plane_csc_load_black(struct intel_plane *plane) 1072 { 1073 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1074 enum plane_id plane_id = plane->id; 1075 enum pipe pipe = plane->pipe; 1076 1077 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 0), 0); 1078 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 1), 0); 1079 1080 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 2), 0); 1081 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 3), 0); 1082 1083 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 4), 0); 1084 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 5), 0); 1085 1086 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0); 1087 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0); 1088 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0); 1089 1090 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0); 1091 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0); 1092 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0); 1093 } 1094 1095 static int icl_plane_color_plane(const struct intel_plane_state *plane_state) 1096 { 1097 /* Program the UV plane on planar master */ 1098 if (plane_state->planar_linked_plane && !plane_state->planar_slave) 1099 return 1; 1100 else 1101 return 0; 1102 } 1103 1104 static void 1105 skl_plane_update_noarm(struct intel_plane *plane, 1106 const struct intel_crtc_state *crtc_state, 1107 const struct intel_plane_state *plane_state) 1108 { 1109 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1110 enum plane_id plane_id = plane->id; 1111 enum pipe pipe = plane->pipe; 1112 u32 stride = skl_plane_stride(plane_state, 0); 1113 int crtc_x = plane_state->uapi.dst.x1; 1114 int crtc_y = plane_state->uapi.dst.y1; 1115 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1116 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1117 1118 /* The scaler will handle the output position */ 1119 if (plane_state->scaler_id >= 0) { 1120 crtc_x = 0; 1121 crtc_y = 0; 1122 } 1123 1124 intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), 1125 PLANE_STRIDE_(stride)); 1126 intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), 1127 PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x)); 1128 intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), 1129 PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1)); 1130 1131 skl_write_plane_wm(plane, crtc_state); 1132 } 1133 1134 static void 1135 skl_plane_update_arm(struct intel_plane *plane, 1136 const struct intel_crtc_state *crtc_state, 1137 const struct intel_plane_state *plane_state) 1138 { 1139 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1140 enum plane_id plane_id = plane->id; 1141 enum pipe pipe = plane->pipe; 1142 u32 x = plane_state->view.color_plane[0].x; 1143 u32 y = plane_state->view.color_plane[0].y; 1144 u32 plane_ctl, plane_color_ctl = 0; 1145 1146 plane_ctl = plane_state->ctl | 1147 skl_plane_ctl_crtc(crtc_state); 1148 1149 if (DISPLAY_VER(dev_priv) >= 10) 1150 plane_color_ctl = plane_state->color_ctl | 1151 glk_plane_color_ctl_crtc(crtc_state); 1152 1153 intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state)); 1154 intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state)); 1155 intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state)); 1156 1157 intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id), 1158 PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x)); 1159 1160 intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), 1161 skl_plane_aux_dist(plane_state, 0)); 1162 1163 intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id), 1164 PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) | 1165 PLANE_OFFSET_X(plane_state->view.color_plane[1].x)); 1166 1167 if (DISPLAY_VER(dev_priv) >= 10) 1168 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); 1169 1170 /* 1171 * Enable the scaler before the plane so that we don't 1172 * get a catastrophic underrun even if the two operations 1173 * end up happening in two different frames. 1174 * 1175 * TODO: split into noarm+arm pair 1176 */ 1177 if (plane_state->scaler_id >= 0) 1178 skl_program_plane_scaler(plane, crtc_state, plane_state); 1179 1180 /* 1181 * The control register self-arms if the plane was previously 1182 * disabled. Try to make the plane enable atomic by writing 1183 * the control register just before the surface register. 1184 */ 1185 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 1186 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 1187 skl_plane_surf(plane_state, 0)); 1188 } 1189 1190 static void 1191 icl_plane_update_noarm(struct intel_plane *plane, 1192 const struct intel_crtc_state *crtc_state, 1193 const struct intel_plane_state *plane_state) 1194 { 1195 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1196 enum plane_id plane_id = plane->id; 1197 enum pipe pipe = plane->pipe; 1198 int color_plane = icl_plane_color_plane(plane_state); 1199 u32 stride = skl_plane_stride(plane_state, color_plane); 1200 const struct drm_framebuffer *fb = plane_state->hw.fb; 1201 int crtc_x = plane_state->uapi.dst.x1; 1202 int crtc_y = plane_state->uapi.dst.y1; 1203 int x = plane_state->view.color_plane[color_plane].x; 1204 int y = plane_state->view.color_plane[color_plane].y; 1205 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1206 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1207 u32 plane_color_ctl; 1208 1209 plane_color_ctl = plane_state->color_ctl | 1210 glk_plane_color_ctl_crtc(crtc_state); 1211 1212 /* The scaler will handle the output position */ 1213 if (plane_state->scaler_id >= 0) { 1214 crtc_x = 0; 1215 crtc_y = 0; 1216 } 1217 1218 intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), 1219 PLANE_STRIDE_(stride)); 1220 intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), 1221 PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x)); 1222 intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), 1223 PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1)); 1224 1225 intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state)); 1226 intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state)); 1227 intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state)); 1228 1229 intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id), 1230 PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x)); 1231 1232 if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) { 1233 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0), 1234 lower_32_bits(plane_state->ccval)); 1235 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1), 1236 upper_32_bits(plane_state->ccval)); 1237 } 1238 1239 /* FLAT CCS doesn't need to program AUX_DIST */ 1240 if (!HAS_FLAT_CCS(dev_priv)) 1241 intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), 1242 skl_plane_aux_dist(plane_state, color_plane)); 1243 1244 if (icl_is_hdr_plane(dev_priv, plane_id)) 1245 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 1246 plane_state->cus_ctl); 1247 1248 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); 1249 1250 if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) 1251 icl_program_input_csc(plane, crtc_state, plane_state); 1252 1253 skl_write_plane_wm(plane, crtc_state); 1254 1255 /* 1256 * FIXME: pxp session invalidation can hit any time even at time of commit 1257 * or after the commit, display content will be garbage. 1258 */ 1259 if (plane_state->force_black) 1260 icl_plane_csc_load_black(plane); 1261 1262 intel_psr2_program_plane_sel_fetch_noarm(plane, crtc_state, plane_state, color_plane); 1263 } 1264 1265 static void 1266 icl_plane_update_arm(struct intel_plane *plane, 1267 const struct intel_crtc_state *crtc_state, 1268 const struct intel_plane_state *plane_state) 1269 { 1270 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1271 enum plane_id plane_id = plane->id; 1272 enum pipe pipe = plane->pipe; 1273 int color_plane = icl_plane_color_plane(plane_state); 1274 u32 plane_ctl; 1275 1276 plane_ctl = plane_state->ctl | 1277 skl_plane_ctl_crtc(crtc_state); 1278 1279 /* 1280 * Enable the scaler before the plane so that we don't 1281 * get a catastrophic underrun even if the two operations 1282 * end up happening in two different frames. 1283 * 1284 * TODO: split into noarm+arm pair 1285 */ 1286 if (plane_state->scaler_id >= 0) 1287 skl_program_plane_scaler(plane, crtc_state, plane_state); 1288 1289 intel_psr2_program_plane_sel_fetch_arm(plane, crtc_state, plane_state); 1290 1291 /* 1292 * The control register self-arms if the plane was previously 1293 * disabled. Try to make the plane enable atomic by writing 1294 * the control register just before the surface register. 1295 */ 1296 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 1297 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 1298 skl_plane_surf(plane_state, color_plane)); 1299 } 1300 1301 static void 1302 skl_plane_async_flip(struct intel_plane *plane, 1303 const struct intel_crtc_state *crtc_state, 1304 const struct intel_plane_state *plane_state, 1305 bool async_flip) 1306 { 1307 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1308 enum plane_id plane_id = plane->id; 1309 enum pipe pipe = plane->pipe; 1310 u32 plane_ctl = plane_state->ctl; 1311 1312 plane_ctl |= skl_plane_ctl_crtc(crtc_state); 1313 1314 if (async_flip) 1315 plane_ctl |= PLANE_CTL_ASYNC_FLIP; 1316 1317 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 1318 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 1319 skl_plane_surf(plane_state, 0)); 1320 } 1321 1322 static bool intel_format_is_p01x(u32 format) 1323 { 1324 switch (format) { 1325 case DRM_FORMAT_P010: 1326 case DRM_FORMAT_P012: 1327 case DRM_FORMAT_P016: 1328 return true; 1329 default: 1330 return false; 1331 } 1332 } 1333 1334 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, 1335 const struct intel_plane_state *plane_state) 1336 { 1337 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1338 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1339 const struct drm_framebuffer *fb = plane_state->hw.fb; 1340 unsigned int rotation = plane_state->hw.rotation; 1341 1342 if (!fb) 1343 return 0; 1344 1345 if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) && 1346 intel_fb_is_ccs_modifier(fb->modifier)) { 1347 drm_dbg_kms(&dev_priv->drm, 1348 "RC support only with 0/180 degree rotation (%x)\n", 1349 rotation); 1350 return -EINVAL; 1351 } 1352 1353 if (rotation & DRM_MODE_REFLECT_X && 1354 fb->modifier == DRM_FORMAT_MOD_LINEAR) { 1355 drm_dbg_kms(&dev_priv->drm, 1356 "horizontal flip is not supported with linear surface formats\n"); 1357 return -EINVAL; 1358 } 1359 1360 if (drm_rotation_90_or_270(rotation)) { 1361 if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) { 1362 drm_dbg_kms(&dev_priv->drm, 1363 "Y/Yf tiling required for 90/270!\n"); 1364 return -EINVAL; 1365 } 1366 1367 /* 1368 * 90/270 is not allowed with RGB64 16:16:16:16 and 1369 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards. 1370 */ 1371 switch (fb->format->format) { 1372 case DRM_FORMAT_RGB565: 1373 if (DISPLAY_VER(dev_priv) >= 11) 1374 break; 1375 fallthrough; 1376 case DRM_FORMAT_C8: 1377 case DRM_FORMAT_XRGB16161616F: 1378 case DRM_FORMAT_XBGR16161616F: 1379 case DRM_FORMAT_ARGB16161616F: 1380 case DRM_FORMAT_ABGR16161616F: 1381 case DRM_FORMAT_Y210: 1382 case DRM_FORMAT_Y212: 1383 case DRM_FORMAT_Y216: 1384 case DRM_FORMAT_XVYU12_16161616: 1385 case DRM_FORMAT_XVYU16161616: 1386 drm_dbg_kms(&dev_priv->drm, 1387 "Unsupported pixel format %p4cc for 90/270!\n", 1388 &fb->format->format); 1389 return -EINVAL; 1390 default: 1391 break; 1392 } 1393 } 1394 1395 /* Y-tiling is not supported in IF-ID Interlace mode */ 1396 if (crtc_state->hw.enable && 1397 crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE && 1398 fb->modifier != DRM_FORMAT_MOD_LINEAR && 1399 fb->modifier != I915_FORMAT_MOD_X_TILED) { 1400 drm_dbg_kms(&dev_priv->drm, 1401 "Y/Yf tiling not supported in IF-ID mode\n"); 1402 return -EINVAL; 1403 } 1404 1405 /* Wa_1606054188:tgl,adl-s */ 1406 if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) && 1407 plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE && 1408 intel_format_is_p01x(fb->format->format)) { 1409 drm_dbg_kms(&dev_priv->drm, 1410 "Source color keying not supported with P01x formats\n"); 1411 return -EINVAL; 1412 } 1413 1414 return 0; 1415 } 1416 1417 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state, 1418 const struct intel_plane_state *plane_state) 1419 { 1420 struct drm_i915_private *dev_priv = 1421 to_i915(plane_state->uapi.plane->dev); 1422 int crtc_x = plane_state->uapi.dst.x1; 1423 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 1424 int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); 1425 1426 /* 1427 * Display WA #1175: glk 1428 * Planes other than the cursor may cause FIFO underflow and display 1429 * corruption if starting less than 4 pixels from the right edge of 1430 * the screen. 1431 * Besides the above WA fix the similar problem, where planes other 1432 * than the cursor ending less than 4 pixels from the left edge of the 1433 * screen may cause FIFO underflow and display corruption. 1434 */ 1435 if (DISPLAY_VER(dev_priv) == 10 && 1436 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) { 1437 drm_dbg_kms(&dev_priv->drm, 1438 "requested plane X %s position %d invalid (valid range %d-%d)\n", 1439 crtc_x + crtc_w < 4 ? "end" : "start", 1440 crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x, 1441 4, pipe_src_w - 4); 1442 return -ERANGE; 1443 } 1444 1445 return 0; 1446 } 1447 1448 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state) 1449 { 1450 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1451 const struct drm_framebuffer *fb = plane_state->hw.fb; 1452 unsigned int rotation = plane_state->hw.rotation; 1453 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1454 1455 /* Display WA #1106 */ 1456 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 1457 src_w & 3 && 1458 (rotation == DRM_MODE_ROTATE_270 || 1459 rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) { 1460 drm_dbg_kms(&i915->drm, "src width must be multiple of 4 for rotated planar YUV\n"); 1461 return -EINVAL; 1462 } 1463 1464 return 0; 1465 } 1466 1467 static int skl_plane_max_scale(struct drm_i915_private *dev_priv, 1468 const struct drm_framebuffer *fb) 1469 { 1470 /* 1471 * We don't yet know the final source width nor 1472 * whether we can use the HQ scaler mode. Assume 1473 * the best case. 1474 * FIXME need to properly check this later. 1475 */ 1476 if (DISPLAY_VER(dev_priv) >= 10 || 1477 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 1478 return 0x30000 - 1; 1479 else 1480 return 0x20000 - 1; 1481 } 1482 1483 static int intel_plane_min_width(struct intel_plane *plane, 1484 const struct drm_framebuffer *fb, 1485 int color_plane, 1486 unsigned int rotation) 1487 { 1488 if (plane->min_width) 1489 return plane->min_width(fb, color_plane, rotation); 1490 else 1491 return 1; 1492 } 1493 1494 static int intel_plane_max_width(struct intel_plane *plane, 1495 const struct drm_framebuffer *fb, 1496 int color_plane, 1497 unsigned int rotation) 1498 { 1499 if (plane->max_width) 1500 return plane->max_width(fb, color_plane, rotation); 1501 else 1502 return INT_MAX; 1503 } 1504 1505 static int intel_plane_max_height(struct intel_plane *plane, 1506 const struct drm_framebuffer *fb, 1507 int color_plane, 1508 unsigned int rotation) 1509 { 1510 if (plane->max_height) 1511 return plane->max_height(fb, color_plane, rotation); 1512 else 1513 return INT_MAX; 1514 } 1515 1516 static bool 1517 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, 1518 int main_x, int main_y, u32 main_offset, 1519 int ccs_plane) 1520 { 1521 const struct drm_framebuffer *fb = plane_state->hw.fb; 1522 int aux_x = plane_state->view.color_plane[ccs_plane].x; 1523 int aux_y = plane_state->view.color_plane[ccs_plane].y; 1524 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; 1525 u32 alignment = intel_surf_alignment(fb, ccs_plane); 1526 int hsub; 1527 int vsub; 1528 1529 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 1530 while (aux_offset >= main_offset && aux_y <= main_y) { 1531 int x, y; 1532 1533 if (aux_x == main_x && aux_y == main_y) 1534 break; 1535 1536 if (aux_offset == 0) 1537 break; 1538 1539 x = aux_x / hsub; 1540 y = aux_y / vsub; 1541 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, 1542 plane_state, 1543 ccs_plane, 1544 aux_offset, 1545 aux_offset - 1546 alignment); 1547 aux_x = x * hsub + aux_x % hsub; 1548 aux_y = y * vsub + aux_y % vsub; 1549 } 1550 1551 if (aux_x != main_x || aux_y != main_y) 1552 return false; 1553 1554 plane_state->view.color_plane[ccs_plane].offset = aux_offset; 1555 plane_state->view.color_plane[ccs_plane].x = aux_x; 1556 plane_state->view.color_plane[ccs_plane].y = aux_y; 1557 1558 return true; 1559 } 1560 1561 1562 int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, 1563 int *x, int *y, u32 *offset) 1564 { 1565 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1566 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1567 const struct drm_framebuffer *fb = plane_state->hw.fb; 1568 const int aux_plane = skl_main_to_aux_plane(fb, 0); 1569 const u32 aux_offset = plane_state->view.color_plane[aux_plane].offset; 1570 const u32 alignment = intel_surf_alignment(fb, 0); 1571 const int w = drm_rect_width(&plane_state->uapi.src) >> 16; 1572 1573 intel_add_fb_offsets(x, y, plane_state, 0); 1574 *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0); 1575 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) 1576 return -EINVAL; 1577 1578 /* 1579 * AUX surface offset is specified as the distance from the 1580 * main surface offset, and it must be non-negative. Make 1581 * sure that is what we will get. 1582 */ 1583 if (aux_plane && *offset > aux_offset) 1584 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, 1585 *offset, 1586 aux_offset & ~(alignment - 1)); 1587 1588 /* 1589 * When using an X-tiled surface, the plane blows up 1590 * if the x offset + width exceed the stride. 1591 * 1592 * TODO: linear and Y-tiled seem fine, Yf untested, 1593 */ 1594 if (fb->modifier == I915_FORMAT_MOD_X_TILED) { 1595 int cpp = fb->format->cpp[0]; 1596 1597 while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) { 1598 if (*offset == 0) { 1599 drm_dbg_kms(&dev_priv->drm, 1600 "Unable to find suitable display surface offset due to X-tiling\n"); 1601 return -EINVAL; 1602 } 1603 1604 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, 1605 *offset, 1606 *offset - alignment); 1607 } 1608 } 1609 1610 return 0; 1611 } 1612 1613 static int skl_check_main_surface(struct intel_plane_state *plane_state) 1614 { 1615 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1616 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1617 const struct drm_framebuffer *fb = plane_state->hw.fb; 1618 const unsigned int rotation = plane_state->hw.rotation; 1619 int x = plane_state->uapi.src.x1 >> 16; 1620 int y = plane_state->uapi.src.y1 >> 16; 1621 const int w = drm_rect_width(&plane_state->uapi.src) >> 16; 1622 const int h = drm_rect_height(&plane_state->uapi.src) >> 16; 1623 const int min_width = intel_plane_min_width(plane, fb, 0, rotation); 1624 const int max_width = intel_plane_max_width(plane, fb, 0, rotation); 1625 const int max_height = intel_plane_max_height(plane, fb, 0, rotation); 1626 const int aux_plane = skl_main_to_aux_plane(fb, 0); 1627 const u32 alignment = intel_surf_alignment(fb, 0); 1628 u32 offset; 1629 int ret; 1630 1631 if (w > max_width || w < min_width || h > max_height || h < 1) { 1632 drm_dbg_kms(&dev_priv->drm, 1633 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", 1634 w, h, min_width, max_width, max_height); 1635 return -EINVAL; 1636 } 1637 1638 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); 1639 if (ret) 1640 return ret; 1641 1642 /* 1643 * CCS AUX surface doesn't have its own x/y offsets, we must make sure 1644 * they match with the main surface x/y offsets. On DG2 1645 * there's no aux plane on fb so skip this checking. 1646 */ 1647 if (intel_fb_is_ccs_modifier(fb->modifier) && aux_plane) { 1648 while (!skl_check_main_ccs_coordinates(plane_state, x, y, 1649 offset, aux_plane)) { 1650 if (offset == 0) 1651 break; 1652 1653 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 1654 offset, offset - alignment); 1655 } 1656 1657 if (x != plane_state->view.color_plane[aux_plane].x || 1658 y != plane_state->view.color_plane[aux_plane].y) { 1659 drm_dbg_kms(&dev_priv->drm, 1660 "Unable to find suitable display surface offset due to CCS\n"); 1661 return -EINVAL; 1662 } 1663 } 1664 1665 if (DISPLAY_VER(dev_priv) >= 13) 1666 drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535); 1667 else 1668 drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191); 1669 1670 plane_state->view.color_plane[0].offset = offset; 1671 plane_state->view.color_plane[0].x = x; 1672 plane_state->view.color_plane[0].y = y; 1673 1674 /* 1675 * Put the final coordinates back so that the src 1676 * coordinate checks will see the right values. 1677 */ 1678 drm_rect_translate_to(&plane_state->uapi.src, 1679 x << 16, y << 16); 1680 1681 return 0; 1682 } 1683 1684 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) 1685 { 1686 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1687 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1688 const struct drm_framebuffer *fb = plane_state->hw.fb; 1689 unsigned int rotation = plane_state->hw.rotation; 1690 int uv_plane = 1; 1691 int ccs_plane = intel_fb_is_ccs_modifier(fb->modifier) ? 1692 skl_main_to_aux_plane(fb, uv_plane) : 0; 1693 int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation); 1694 int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation); 1695 int x = plane_state->uapi.src.x1 >> 17; 1696 int y = plane_state->uapi.src.y1 >> 17; 1697 int w = drm_rect_width(&plane_state->uapi.src) >> 17; 1698 int h = drm_rect_height(&plane_state->uapi.src) >> 17; 1699 u32 offset; 1700 1701 /* FIXME not quite sure how/if these apply to the chroma plane */ 1702 if (w > max_width || h > max_height) { 1703 drm_dbg_kms(&i915->drm, 1704 "CbCr source size %dx%d too big (limit %dx%d)\n", 1705 w, h, max_width, max_height); 1706 return -EINVAL; 1707 } 1708 1709 intel_add_fb_offsets(&x, &y, plane_state, uv_plane); 1710 offset = intel_plane_compute_aligned_offset(&x, &y, 1711 plane_state, uv_plane); 1712 1713 if (ccs_plane) { 1714 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; 1715 u32 alignment = intel_surf_alignment(fb, uv_plane); 1716 1717 if (offset > aux_offset) 1718 offset = intel_plane_adjust_aligned_offset(&x, &y, 1719 plane_state, 1720 uv_plane, 1721 offset, 1722 aux_offset & ~(alignment - 1)); 1723 1724 while (!skl_check_main_ccs_coordinates(plane_state, x, y, 1725 offset, ccs_plane)) { 1726 if (offset == 0) 1727 break; 1728 1729 offset = intel_plane_adjust_aligned_offset(&x, &y, 1730 plane_state, 1731 uv_plane, 1732 offset, offset - alignment); 1733 } 1734 1735 if (x != plane_state->view.color_plane[ccs_plane].x || 1736 y != plane_state->view.color_plane[ccs_plane].y) { 1737 drm_dbg_kms(&i915->drm, 1738 "Unable to find suitable display surface offset due to CCS\n"); 1739 return -EINVAL; 1740 } 1741 } 1742 1743 if (DISPLAY_VER(i915) >= 13) 1744 drm_WARN_ON(&i915->drm, x > 65535 || y > 65535); 1745 else 1746 drm_WARN_ON(&i915->drm, x > 8191 || y > 8191); 1747 1748 plane_state->view.color_plane[uv_plane].offset = offset; 1749 plane_state->view.color_plane[uv_plane].x = x; 1750 plane_state->view.color_plane[uv_plane].y = y; 1751 1752 return 0; 1753 } 1754 1755 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) 1756 { 1757 const struct drm_framebuffer *fb = plane_state->hw.fb; 1758 int src_x = plane_state->uapi.src.x1 >> 16; 1759 int src_y = plane_state->uapi.src.y1 >> 16; 1760 u32 offset; 1761 int ccs_plane; 1762 1763 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) { 1764 int main_hsub, main_vsub; 1765 int hsub, vsub; 1766 int x, y; 1767 1768 if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane)) 1769 continue; 1770 1771 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, 1772 skl_ccs_to_main_plane(fb, ccs_plane)); 1773 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 1774 1775 hsub *= main_hsub; 1776 vsub *= main_vsub; 1777 x = src_x / hsub; 1778 y = src_y / vsub; 1779 1780 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane); 1781 1782 offset = intel_plane_compute_aligned_offset(&x, &y, 1783 plane_state, 1784 ccs_plane); 1785 1786 plane_state->view.color_plane[ccs_plane].offset = offset; 1787 plane_state->view.color_plane[ccs_plane].x = (x * hsub + src_x % hsub) / main_hsub; 1788 plane_state->view.color_plane[ccs_plane].y = (y * vsub + src_y % vsub) / main_vsub; 1789 } 1790 1791 return 0; 1792 } 1793 1794 static int skl_check_plane_surface(struct intel_plane_state *plane_state) 1795 { 1796 const struct drm_framebuffer *fb = plane_state->hw.fb; 1797 int ret; 1798 1799 ret = intel_plane_compute_gtt(plane_state); 1800 if (ret) 1801 return ret; 1802 1803 if (!plane_state->uapi.visible) 1804 return 0; 1805 1806 /* 1807 * Handle the AUX surface first since the main surface setup depends on 1808 * it. 1809 */ 1810 if (intel_fb_is_ccs_modifier(fb->modifier)) { 1811 ret = skl_check_ccs_aux_surface(plane_state); 1812 if (ret) 1813 return ret; 1814 } 1815 1816 if (intel_format_info_is_yuv_semiplanar(fb->format, 1817 fb->modifier)) { 1818 ret = skl_check_nv12_aux_surface(plane_state); 1819 if (ret) 1820 return ret; 1821 } 1822 1823 ret = skl_check_main_surface(plane_state); 1824 if (ret) 1825 return ret; 1826 1827 return 0; 1828 } 1829 1830 static bool skl_fb_scalable(const struct drm_framebuffer *fb) 1831 { 1832 if (!fb) 1833 return false; 1834 1835 switch (fb->format->format) { 1836 case DRM_FORMAT_C8: 1837 return false; 1838 case DRM_FORMAT_XRGB16161616F: 1839 case DRM_FORMAT_ARGB16161616F: 1840 case DRM_FORMAT_XBGR16161616F: 1841 case DRM_FORMAT_ABGR16161616F: 1842 return DISPLAY_VER(to_i915(fb->dev)) >= 11; 1843 default: 1844 return true; 1845 } 1846 } 1847 1848 static bool bo_has_valid_encryption(struct drm_i915_gem_object *obj) 1849 { 1850 struct drm_i915_private *i915 = to_i915(obj->base.dev); 1851 1852 return intel_pxp_key_check(i915->pxp, obj, false) == 0; 1853 } 1854 1855 static bool pxp_is_borked(struct drm_i915_gem_object *obj) 1856 { 1857 return i915_gem_object_is_protected(obj) && !bo_has_valid_encryption(obj); 1858 } 1859 1860 static int skl_plane_check(struct intel_crtc_state *crtc_state, 1861 struct intel_plane_state *plane_state) 1862 { 1863 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1864 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1865 const struct drm_framebuffer *fb = plane_state->hw.fb; 1866 int min_scale = DRM_PLANE_NO_SCALING; 1867 int max_scale = DRM_PLANE_NO_SCALING; 1868 int ret; 1869 1870 ret = skl_plane_check_fb(crtc_state, plane_state); 1871 if (ret) 1872 return ret; 1873 1874 /* use scaler when colorkey is not required */ 1875 if (!plane_state->ckey.flags && skl_fb_scalable(fb)) { 1876 min_scale = 1; 1877 max_scale = skl_plane_max_scale(dev_priv, fb); 1878 } 1879 1880 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 1881 min_scale, max_scale, true); 1882 if (ret) 1883 return ret; 1884 1885 ret = skl_check_plane_surface(plane_state); 1886 if (ret) 1887 return ret; 1888 1889 if (!plane_state->uapi.visible) 1890 return 0; 1891 1892 ret = skl_plane_check_dst_coordinates(crtc_state, plane_state); 1893 if (ret) 1894 return ret; 1895 1896 ret = intel_plane_check_src_coordinates(plane_state); 1897 if (ret) 1898 return ret; 1899 1900 ret = skl_plane_check_nv12_rotation(plane_state); 1901 if (ret) 1902 return ret; 1903 1904 if (DISPLAY_VER(dev_priv) >= 11) { 1905 plane_state->decrypt = bo_has_valid_encryption(intel_fb_obj(fb)); 1906 plane_state->force_black = pxp_is_borked(intel_fb_obj(fb)); 1907 } 1908 1909 /* HW only has 8 bits pixel precision, disable plane if invisible */ 1910 if (!(plane_state->hw.alpha >> 8)) 1911 plane_state->uapi.visible = false; 1912 1913 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); 1914 1915 if (DISPLAY_VER(dev_priv) >= 10) 1916 plane_state->color_ctl = glk_plane_color_ctl(crtc_state, 1917 plane_state); 1918 1919 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 1920 icl_is_hdr_plane(dev_priv, plane->id)) 1921 /* Enable and use MPEG-2 chroma siting */ 1922 plane_state->cus_ctl = PLANE_CUS_ENABLE | 1923 PLANE_CUS_HPHASE_0 | 1924 PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25; 1925 else 1926 plane_state->cus_ctl = 0; 1927 1928 return 0; 1929 } 1930 1931 static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe) 1932 { 1933 return pipe - PIPE_A + INTEL_FBC_A; 1934 } 1935 1936 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv, 1937 enum intel_fbc_id fbc_id, enum plane_id plane_id) 1938 { 1939 if ((RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0) 1940 return false; 1941 1942 return plane_id == PLANE_PRIMARY; 1943 } 1944 1945 static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv, 1946 enum pipe pipe, enum plane_id plane_id) 1947 { 1948 enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe); 1949 1950 if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id)) 1951 return dev_priv->display.fbc[fbc_id]; 1952 else 1953 return NULL; 1954 } 1955 1956 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, 1957 enum pipe pipe, enum plane_id plane_id) 1958 { 1959 /* Display WA #0870: skl, bxt */ 1960 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) 1961 return false; 1962 1963 if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C) 1964 return false; 1965 1966 if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0) 1967 return false; 1968 1969 return true; 1970 } 1971 1972 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv, 1973 enum pipe pipe, enum plane_id plane_id, 1974 int *num_formats) 1975 { 1976 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 1977 *num_formats = ARRAY_SIZE(skl_planar_formats); 1978 return skl_planar_formats; 1979 } else { 1980 *num_formats = ARRAY_SIZE(skl_plane_formats); 1981 return skl_plane_formats; 1982 } 1983 } 1984 1985 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv, 1986 enum pipe pipe, enum plane_id plane_id, 1987 int *num_formats) 1988 { 1989 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 1990 *num_formats = ARRAY_SIZE(glk_planar_formats); 1991 return glk_planar_formats; 1992 } else { 1993 *num_formats = ARRAY_SIZE(skl_plane_formats); 1994 return skl_plane_formats; 1995 } 1996 } 1997 1998 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, 1999 enum pipe pipe, enum plane_id plane_id, 2000 int *num_formats) 2001 { 2002 if (icl_is_hdr_plane(dev_priv, plane_id)) { 2003 *num_formats = ARRAY_SIZE(icl_hdr_plane_formats); 2004 return icl_hdr_plane_formats; 2005 } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) { 2006 *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats); 2007 return icl_sdr_y_plane_formats; 2008 } else { 2009 *num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats); 2010 return icl_sdr_uv_plane_formats; 2011 } 2012 } 2013 2014 static bool skl_plane_format_mod_supported(struct drm_plane *_plane, 2015 u32 format, u64 modifier) 2016 { 2017 struct intel_plane *plane = to_intel_plane(_plane); 2018 2019 if (!intel_fb_plane_supports_modifier(plane, modifier)) 2020 return false; 2021 2022 switch (format) { 2023 case DRM_FORMAT_XRGB8888: 2024 case DRM_FORMAT_XBGR8888: 2025 case DRM_FORMAT_ARGB8888: 2026 case DRM_FORMAT_ABGR8888: 2027 if (intel_fb_is_ccs_modifier(modifier)) 2028 return true; 2029 fallthrough; 2030 case DRM_FORMAT_RGB565: 2031 case DRM_FORMAT_XRGB2101010: 2032 case DRM_FORMAT_XBGR2101010: 2033 case DRM_FORMAT_ARGB2101010: 2034 case DRM_FORMAT_ABGR2101010: 2035 case DRM_FORMAT_YUYV: 2036 case DRM_FORMAT_YVYU: 2037 case DRM_FORMAT_UYVY: 2038 case DRM_FORMAT_VYUY: 2039 case DRM_FORMAT_NV12: 2040 case DRM_FORMAT_XYUV8888: 2041 case DRM_FORMAT_P010: 2042 case DRM_FORMAT_P012: 2043 case DRM_FORMAT_P016: 2044 case DRM_FORMAT_XVYU2101010: 2045 if (modifier == I915_FORMAT_MOD_Yf_TILED) 2046 return true; 2047 fallthrough; 2048 case DRM_FORMAT_C8: 2049 case DRM_FORMAT_XBGR16161616F: 2050 case DRM_FORMAT_ABGR16161616F: 2051 case DRM_FORMAT_XRGB16161616F: 2052 case DRM_FORMAT_ARGB16161616F: 2053 case DRM_FORMAT_Y210: 2054 case DRM_FORMAT_Y212: 2055 case DRM_FORMAT_Y216: 2056 case DRM_FORMAT_XVYU12_16161616: 2057 case DRM_FORMAT_XVYU16161616: 2058 if (modifier == DRM_FORMAT_MOD_LINEAR || 2059 modifier == I915_FORMAT_MOD_X_TILED || 2060 modifier == I915_FORMAT_MOD_Y_TILED) 2061 return true; 2062 fallthrough; 2063 default: 2064 return false; 2065 } 2066 } 2067 2068 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, 2069 u32 format, u64 modifier) 2070 { 2071 struct intel_plane *plane = to_intel_plane(_plane); 2072 2073 if (!intel_fb_plane_supports_modifier(plane, modifier)) 2074 return false; 2075 2076 switch (format) { 2077 case DRM_FORMAT_XRGB8888: 2078 case DRM_FORMAT_XBGR8888: 2079 case DRM_FORMAT_ARGB8888: 2080 case DRM_FORMAT_ABGR8888: 2081 if (intel_fb_is_ccs_modifier(modifier)) 2082 return true; 2083 fallthrough; 2084 case DRM_FORMAT_YUYV: 2085 case DRM_FORMAT_YVYU: 2086 case DRM_FORMAT_UYVY: 2087 case DRM_FORMAT_VYUY: 2088 case DRM_FORMAT_NV12: 2089 case DRM_FORMAT_XYUV8888: 2090 case DRM_FORMAT_P010: 2091 case DRM_FORMAT_P012: 2092 case DRM_FORMAT_P016: 2093 if (intel_fb_is_mc_ccs_modifier(modifier)) 2094 return true; 2095 fallthrough; 2096 case DRM_FORMAT_RGB565: 2097 case DRM_FORMAT_XRGB2101010: 2098 case DRM_FORMAT_XBGR2101010: 2099 case DRM_FORMAT_ARGB2101010: 2100 case DRM_FORMAT_ABGR2101010: 2101 case DRM_FORMAT_XVYU2101010: 2102 case DRM_FORMAT_C8: 2103 case DRM_FORMAT_XBGR16161616F: 2104 case DRM_FORMAT_ABGR16161616F: 2105 case DRM_FORMAT_XRGB16161616F: 2106 case DRM_FORMAT_ARGB16161616F: 2107 case DRM_FORMAT_Y210: 2108 case DRM_FORMAT_Y212: 2109 case DRM_FORMAT_Y216: 2110 case DRM_FORMAT_XVYU12_16161616: 2111 case DRM_FORMAT_XVYU16161616: 2112 if (!intel_fb_is_ccs_modifier(modifier)) 2113 return true; 2114 fallthrough; 2115 default: 2116 return false; 2117 } 2118 } 2119 2120 static const struct drm_plane_funcs skl_plane_funcs = { 2121 .update_plane = drm_atomic_helper_update_plane, 2122 .disable_plane = drm_atomic_helper_disable_plane, 2123 .destroy = intel_plane_destroy, 2124 .atomic_duplicate_state = intel_plane_duplicate_state, 2125 .atomic_destroy_state = intel_plane_destroy_state, 2126 .format_mod_supported = skl_plane_format_mod_supported, 2127 }; 2128 2129 static const struct drm_plane_funcs gen12_plane_funcs = { 2130 .update_plane = drm_atomic_helper_update_plane, 2131 .disable_plane = drm_atomic_helper_disable_plane, 2132 .destroy = intel_plane_destroy, 2133 .atomic_duplicate_state = intel_plane_duplicate_state, 2134 .atomic_destroy_state = intel_plane_destroy_state, 2135 .format_mod_supported = gen12_plane_format_mod_supported, 2136 }; 2137 2138 static void 2139 skl_plane_enable_flip_done(struct intel_plane *plane) 2140 { 2141 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2142 enum pipe pipe = plane->pipe; 2143 2144 spin_lock_irq(&i915->irq_lock); 2145 bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); 2146 spin_unlock_irq(&i915->irq_lock); 2147 } 2148 2149 static void 2150 skl_plane_disable_flip_done(struct intel_plane *plane) 2151 { 2152 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2153 enum pipe pipe = plane->pipe; 2154 2155 spin_lock_irq(&i915->irq_lock); 2156 bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); 2157 spin_unlock_irq(&i915->irq_lock); 2158 } 2159 2160 static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, 2161 enum pipe pipe, enum plane_id plane_id) 2162 { 2163 /* Wa_22011186057 */ 2164 if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) 2165 return false; 2166 2167 if (DISPLAY_VER(i915) >= 11) 2168 return true; 2169 2170 if (IS_GEMINILAKE(i915)) 2171 return pipe != PIPE_C; 2172 2173 return pipe != PIPE_C && 2174 (plane_id == PLANE_PRIMARY || 2175 plane_id == PLANE_SPRITE0); 2176 } 2177 2178 static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, 2179 enum plane_id plane_id) 2180 { 2181 if (DISPLAY_VER(i915) < 12) 2182 return false; 2183 2184 /* Wa_14010477008 */ 2185 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || 2186 IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0)) 2187 return false; 2188 2189 /* Wa_22011186057 */ 2190 if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) 2191 return false; 2192 2193 /* Wa_14013215631 */ 2194 if (IS_DG2_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) 2195 return false; 2196 2197 return plane_id < PLANE_SPRITE4; 2198 } 2199 2200 static u8 skl_get_plane_caps(struct drm_i915_private *i915, 2201 enum pipe pipe, enum plane_id plane_id) 2202 { 2203 u8 caps = INTEL_PLANE_CAP_TILING_X; 2204 2205 if (DISPLAY_VER(i915) < 13 || IS_ALDERLAKE_P(i915)) 2206 caps |= INTEL_PLANE_CAP_TILING_Y; 2207 if (DISPLAY_VER(i915) < 12) 2208 caps |= INTEL_PLANE_CAP_TILING_Yf; 2209 if (HAS_4TILE(i915)) 2210 caps |= INTEL_PLANE_CAP_TILING_4; 2211 2212 if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) { 2213 caps |= INTEL_PLANE_CAP_CCS_RC; 2214 if (DISPLAY_VER(i915) >= 12) 2215 caps |= INTEL_PLANE_CAP_CCS_RC_CC; 2216 } 2217 2218 if (gen12_plane_has_mc_ccs(i915, plane_id)) 2219 caps |= INTEL_PLANE_CAP_CCS_MC; 2220 2221 return caps; 2222 } 2223 2224 struct intel_plane * 2225 skl_universal_plane_create(struct drm_i915_private *dev_priv, 2226 enum pipe pipe, enum plane_id plane_id) 2227 { 2228 const struct drm_plane_funcs *plane_funcs; 2229 struct intel_plane *plane; 2230 enum drm_plane_type plane_type; 2231 unsigned int supported_rotations; 2232 unsigned int supported_csc; 2233 const u64 *modifiers; 2234 const u32 *formats; 2235 int num_formats; 2236 int ret; 2237 2238 plane = intel_plane_alloc(); 2239 if (IS_ERR(plane)) 2240 return plane; 2241 2242 plane->pipe = pipe; 2243 plane->id = plane_id; 2244 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id); 2245 2246 intel_fbc_add_plane(skl_plane_fbc(dev_priv, pipe, plane_id), plane); 2247 2248 if (DISPLAY_VER(dev_priv) >= 11) { 2249 plane->min_width = icl_plane_min_width; 2250 if (icl_is_hdr_plane(dev_priv, plane_id)) 2251 plane->max_width = icl_hdr_plane_max_width; 2252 else 2253 plane->max_width = icl_sdr_plane_max_width; 2254 plane->max_height = icl_plane_max_height; 2255 plane->min_cdclk = icl_plane_min_cdclk; 2256 } else if (DISPLAY_VER(dev_priv) >= 10) { 2257 plane->max_width = glk_plane_max_width; 2258 plane->max_height = skl_plane_max_height; 2259 plane->min_cdclk = glk_plane_min_cdclk; 2260 } else { 2261 plane->max_width = skl_plane_max_width; 2262 plane->max_height = skl_plane_max_height; 2263 plane->min_cdclk = skl_plane_min_cdclk; 2264 } 2265 2266 plane->max_stride = skl_plane_max_stride; 2267 if (DISPLAY_VER(dev_priv) >= 11) { 2268 plane->update_noarm = icl_plane_update_noarm; 2269 plane->update_arm = icl_plane_update_arm; 2270 plane->disable_arm = icl_plane_disable_arm; 2271 } else { 2272 plane->update_noarm = skl_plane_update_noarm; 2273 plane->update_arm = skl_plane_update_arm; 2274 plane->disable_arm = skl_plane_disable_arm; 2275 } 2276 plane->get_hw_state = skl_plane_get_hw_state; 2277 plane->check_plane = skl_plane_check; 2278 2279 if (plane_id == PLANE_PRIMARY) { 2280 plane->need_async_flip_disable_wa = IS_DISPLAY_VER(dev_priv, 2281 9, 10); 2282 plane->async_flip = skl_plane_async_flip; 2283 plane->enable_flip_done = skl_plane_enable_flip_done; 2284 plane->disable_flip_done = skl_plane_disable_flip_done; 2285 } 2286 2287 if (DISPLAY_VER(dev_priv) >= 11) 2288 formats = icl_get_plane_formats(dev_priv, pipe, 2289 plane_id, &num_formats); 2290 else if (DISPLAY_VER(dev_priv) >= 10) 2291 formats = glk_get_plane_formats(dev_priv, pipe, 2292 plane_id, &num_formats); 2293 else 2294 formats = skl_get_plane_formats(dev_priv, pipe, 2295 plane_id, &num_formats); 2296 2297 if (DISPLAY_VER(dev_priv) >= 12) 2298 plane_funcs = &gen12_plane_funcs; 2299 else 2300 plane_funcs = &skl_plane_funcs; 2301 2302 if (plane_id == PLANE_PRIMARY) 2303 plane_type = DRM_PLANE_TYPE_PRIMARY; 2304 else 2305 plane_type = DRM_PLANE_TYPE_OVERLAY; 2306 2307 modifiers = intel_fb_plane_get_modifiers(dev_priv, 2308 skl_get_plane_caps(dev_priv, pipe, plane_id)); 2309 2310 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 2311 0, plane_funcs, 2312 formats, num_formats, modifiers, 2313 plane_type, 2314 "plane %d%c", plane_id + 1, 2315 pipe_name(pipe)); 2316 2317 kfree(modifiers); 2318 2319 if (ret) 2320 goto fail; 2321 2322 if (DISPLAY_VER(dev_priv) >= 13) 2323 supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 2324 else 2325 supported_rotations = 2326 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 2327 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 2328 2329 if (DISPLAY_VER(dev_priv) >= 11) 2330 supported_rotations |= DRM_MODE_REFLECT_X; 2331 2332 drm_plane_create_rotation_property(&plane->base, 2333 DRM_MODE_ROTATE_0, 2334 supported_rotations); 2335 2336 supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709); 2337 2338 if (DISPLAY_VER(dev_priv) >= 10) 2339 supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020); 2340 2341 drm_plane_create_color_properties(&plane->base, 2342 supported_csc, 2343 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 2344 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 2345 DRM_COLOR_YCBCR_BT709, 2346 DRM_COLOR_YCBCR_LIMITED_RANGE); 2347 2348 drm_plane_create_alpha_property(&plane->base); 2349 drm_plane_create_blend_mode_property(&plane->base, 2350 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 2351 BIT(DRM_MODE_BLEND_PREMULTI) | 2352 BIT(DRM_MODE_BLEND_COVERAGE)); 2353 2354 drm_plane_create_zpos_immutable_property(&plane->base, plane_id); 2355 2356 if (DISPLAY_VER(dev_priv) >= 12) 2357 drm_plane_enable_fb_damage_clips(&plane->base); 2358 2359 if (DISPLAY_VER(dev_priv) >= 11) 2360 drm_plane_create_scaling_filter_property(&plane->base, 2361 BIT(DRM_SCALING_FILTER_DEFAULT) | 2362 BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); 2363 2364 intel_plane_helper_add(plane); 2365 2366 return plane; 2367 2368 fail: 2369 intel_plane_free(plane); 2370 2371 return ERR_PTR(ret); 2372 } 2373 2374 void 2375 skl_get_initial_plane_config(struct intel_crtc *crtc, 2376 struct intel_initial_plane_config *plane_config) 2377 { 2378 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 2379 struct drm_device *dev = crtc->base.dev; 2380 struct drm_i915_private *dev_priv = to_i915(dev); 2381 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 2382 enum plane_id plane_id = plane->id; 2383 enum pipe pipe; 2384 u32 val, base, offset, stride_mult, tiling, alpha; 2385 int fourcc, pixel_format; 2386 unsigned int aligned_height; 2387 struct drm_framebuffer *fb; 2388 struct intel_framebuffer *intel_fb; 2389 static_assert(PLANE_CTL_TILED_YF == PLANE_CTL_TILED_4); 2390 2391 if (!plane->get_hw_state(plane, &pipe)) 2392 return; 2393 2394 drm_WARN_ON(dev, pipe != crtc->pipe); 2395 2396 if (crtc_state->bigjoiner_pipes) { 2397 drm_dbg_kms(&dev_priv->drm, 2398 "Unsupported bigjoiner configuration for initial FB\n"); 2399 return; 2400 } 2401 2402 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 2403 if (!intel_fb) { 2404 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); 2405 return; 2406 } 2407 2408 fb = &intel_fb->base; 2409 2410 fb->dev = dev; 2411 2412 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id)); 2413 2414 if (DISPLAY_VER(dev_priv) >= 11) 2415 pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL; 2416 else 2417 pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL; 2418 2419 if (DISPLAY_VER(dev_priv) >= 10) { 2420 u32 color_ctl; 2421 2422 color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id)); 2423 alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl); 2424 } else { 2425 alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val); 2426 } 2427 2428 fourcc = skl_format_to_fourcc(pixel_format, 2429 val & PLANE_CTL_ORDER_RGBX, alpha); 2430 fb->format = drm_format_info(fourcc); 2431 2432 tiling = val & PLANE_CTL_TILED_MASK; 2433 switch (tiling) { 2434 case PLANE_CTL_TILED_LINEAR: 2435 fb->modifier = DRM_FORMAT_MOD_LINEAR; 2436 break; 2437 case PLANE_CTL_TILED_X: 2438 plane_config->tiling = I915_TILING_X; 2439 fb->modifier = I915_FORMAT_MOD_X_TILED; 2440 break; 2441 case PLANE_CTL_TILED_Y: 2442 plane_config->tiling = I915_TILING_Y; 2443 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2444 if (DISPLAY_VER(dev_priv) >= 12) 2445 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS; 2446 else 2447 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; 2448 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) 2449 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; 2450 else 2451 fb->modifier = I915_FORMAT_MOD_Y_TILED; 2452 break; 2453 case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */ 2454 if (HAS_4TILE(dev_priv)) { 2455 u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 2456 PLANE_CTL_CLEAR_COLOR_DISABLE; 2457 2458 if ((val & rc_mask) == rc_mask) 2459 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS; 2460 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) 2461 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS; 2462 else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2463 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC; 2464 else 2465 fb->modifier = I915_FORMAT_MOD_4_TILED; 2466 } else { 2467 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2468 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; 2469 else 2470 fb->modifier = I915_FORMAT_MOD_Yf_TILED; 2471 } 2472 break; 2473 default: 2474 MISSING_CASE(tiling); 2475 goto error; 2476 } 2477 2478 if (!dev_priv->params.enable_dpt && 2479 intel_fb_modifier_uses_dpt(dev_priv, fb->modifier)) { 2480 drm_dbg_kms(&dev_priv->drm, "DPT disabled, skipping initial FB\n"); 2481 goto error; 2482 } 2483 2484 /* 2485 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr 2486 * while i915 HW rotation is clockwise, thats why this swapping. 2487 */ 2488 switch (val & PLANE_CTL_ROTATE_MASK) { 2489 case PLANE_CTL_ROTATE_0: 2490 plane_config->rotation = DRM_MODE_ROTATE_0; 2491 break; 2492 case PLANE_CTL_ROTATE_90: 2493 plane_config->rotation = DRM_MODE_ROTATE_270; 2494 break; 2495 case PLANE_CTL_ROTATE_180: 2496 plane_config->rotation = DRM_MODE_ROTATE_180; 2497 break; 2498 case PLANE_CTL_ROTATE_270: 2499 plane_config->rotation = DRM_MODE_ROTATE_90; 2500 break; 2501 } 2502 2503 if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL) 2504 plane_config->rotation |= DRM_MODE_REFLECT_X; 2505 2506 /* 90/270 degree rotation would require extra work */ 2507 if (drm_rotation_90_or_270(plane_config->rotation)) 2508 goto error; 2509 2510 base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK; 2511 plane_config->base = base; 2512 2513 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id)); 2514 2515 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id)); 2516 fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1; 2517 fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1; 2518 2519 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id)); 2520 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0); 2521 2522 fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult; 2523 2524 aligned_height = intel_fb_align_height(fb, 0, fb->height); 2525 2526 plane_config->size = fb->pitches[0] * aligned_height; 2527 2528 drm_dbg_kms(&dev_priv->drm, 2529 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 2530 crtc->base.name, plane->base.name, fb->width, fb->height, 2531 fb->format->cpp[0] * 8, base, fb->pitches[0], 2532 plane_config->size); 2533 2534 plane_config->fb = intel_fb; 2535 return; 2536 2537 error: 2538 kfree(intel_fb); 2539 } 2540