1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <drm/drm_atomic_helper.h> 7 #include <drm/drm_blend.h> 8 #include <drm/drm_damage_helper.h> 9 #include <drm/drm_fourcc.h> 10 11 #include "i915_drv.h" 12 #include "i915_reg.h" 13 #include "intel_atomic_plane.h" 14 #include "intel_de.h" 15 #include "intel_display_irq.h" 16 #include "intel_display_types.h" 17 #include "intel_fb.h" 18 #include "intel_fbc.h" 19 #include "intel_psr.h" 20 #include "skl_scaler.h" 21 #include "skl_universal_plane.h" 22 #include "skl_watermark.h" 23 #include "pxp/intel_pxp.h" 24 25 static const u32 skl_plane_formats[] = { 26 DRM_FORMAT_C8, 27 DRM_FORMAT_RGB565, 28 DRM_FORMAT_XRGB8888, 29 DRM_FORMAT_XBGR8888, 30 DRM_FORMAT_ARGB8888, 31 DRM_FORMAT_ABGR8888, 32 DRM_FORMAT_XRGB2101010, 33 DRM_FORMAT_XBGR2101010, 34 DRM_FORMAT_XRGB16161616F, 35 DRM_FORMAT_XBGR16161616F, 36 DRM_FORMAT_YUYV, 37 DRM_FORMAT_YVYU, 38 DRM_FORMAT_UYVY, 39 DRM_FORMAT_VYUY, 40 DRM_FORMAT_XYUV8888, 41 }; 42 43 static const u32 skl_planar_formats[] = { 44 DRM_FORMAT_C8, 45 DRM_FORMAT_RGB565, 46 DRM_FORMAT_XRGB8888, 47 DRM_FORMAT_XBGR8888, 48 DRM_FORMAT_ARGB8888, 49 DRM_FORMAT_ABGR8888, 50 DRM_FORMAT_XRGB2101010, 51 DRM_FORMAT_XBGR2101010, 52 DRM_FORMAT_XRGB16161616F, 53 DRM_FORMAT_XBGR16161616F, 54 DRM_FORMAT_YUYV, 55 DRM_FORMAT_YVYU, 56 DRM_FORMAT_UYVY, 57 DRM_FORMAT_VYUY, 58 DRM_FORMAT_NV12, 59 DRM_FORMAT_XYUV8888, 60 }; 61 62 static const u32 glk_planar_formats[] = { 63 DRM_FORMAT_C8, 64 DRM_FORMAT_RGB565, 65 DRM_FORMAT_XRGB8888, 66 DRM_FORMAT_XBGR8888, 67 DRM_FORMAT_ARGB8888, 68 DRM_FORMAT_ABGR8888, 69 DRM_FORMAT_XRGB2101010, 70 DRM_FORMAT_XBGR2101010, 71 DRM_FORMAT_XRGB16161616F, 72 DRM_FORMAT_XBGR16161616F, 73 DRM_FORMAT_YUYV, 74 DRM_FORMAT_YVYU, 75 DRM_FORMAT_UYVY, 76 DRM_FORMAT_VYUY, 77 DRM_FORMAT_NV12, 78 DRM_FORMAT_XYUV8888, 79 DRM_FORMAT_P010, 80 DRM_FORMAT_P012, 81 DRM_FORMAT_P016, 82 }; 83 84 static const u32 icl_sdr_y_plane_formats[] = { 85 DRM_FORMAT_C8, 86 DRM_FORMAT_RGB565, 87 DRM_FORMAT_XRGB8888, 88 DRM_FORMAT_XBGR8888, 89 DRM_FORMAT_ARGB8888, 90 DRM_FORMAT_ABGR8888, 91 DRM_FORMAT_XRGB2101010, 92 DRM_FORMAT_XBGR2101010, 93 DRM_FORMAT_ARGB2101010, 94 DRM_FORMAT_ABGR2101010, 95 DRM_FORMAT_YUYV, 96 DRM_FORMAT_YVYU, 97 DRM_FORMAT_UYVY, 98 DRM_FORMAT_VYUY, 99 DRM_FORMAT_Y210, 100 DRM_FORMAT_Y212, 101 DRM_FORMAT_Y216, 102 DRM_FORMAT_XYUV8888, 103 DRM_FORMAT_XVYU2101010, 104 DRM_FORMAT_XVYU12_16161616, 105 DRM_FORMAT_XVYU16161616, 106 }; 107 108 static const u32 icl_sdr_uv_plane_formats[] = { 109 DRM_FORMAT_C8, 110 DRM_FORMAT_RGB565, 111 DRM_FORMAT_XRGB8888, 112 DRM_FORMAT_XBGR8888, 113 DRM_FORMAT_ARGB8888, 114 DRM_FORMAT_ABGR8888, 115 DRM_FORMAT_XRGB2101010, 116 DRM_FORMAT_XBGR2101010, 117 DRM_FORMAT_ARGB2101010, 118 DRM_FORMAT_ABGR2101010, 119 DRM_FORMAT_YUYV, 120 DRM_FORMAT_YVYU, 121 DRM_FORMAT_UYVY, 122 DRM_FORMAT_VYUY, 123 DRM_FORMAT_NV12, 124 DRM_FORMAT_P010, 125 DRM_FORMAT_P012, 126 DRM_FORMAT_P016, 127 DRM_FORMAT_Y210, 128 DRM_FORMAT_Y212, 129 DRM_FORMAT_Y216, 130 DRM_FORMAT_XYUV8888, 131 DRM_FORMAT_XVYU2101010, 132 DRM_FORMAT_XVYU12_16161616, 133 DRM_FORMAT_XVYU16161616, 134 }; 135 136 static const u32 icl_hdr_plane_formats[] = { 137 DRM_FORMAT_C8, 138 DRM_FORMAT_RGB565, 139 DRM_FORMAT_XRGB8888, 140 DRM_FORMAT_XBGR8888, 141 DRM_FORMAT_ARGB8888, 142 DRM_FORMAT_ABGR8888, 143 DRM_FORMAT_XRGB2101010, 144 DRM_FORMAT_XBGR2101010, 145 DRM_FORMAT_ARGB2101010, 146 DRM_FORMAT_ABGR2101010, 147 DRM_FORMAT_XRGB16161616F, 148 DRM_FORMAT_XBGR16161616F, 149 DRM_FORMAT_ARGB16161616F, 150 DRM_FORMAT_ABGR16161616F, 151 DRM_FORMAT_YUYV, 152 DRM_FORMAT_YVYU, 153 DRM_FORMAT_UYVY, 154 DRM_FORMAT_VYUY, 155 DRM_FORMAT_NV12, 156 DRM_FORMAT_P010, 157 DRM_FORMAT_P012, 158 DRM_FORMAT_P016, 159 DRM_FORMAT_Y210, 160 DRM_FORMAT_Y212, 161 DRM_FORMAT_Y216, 162 DRM_FORMAT_XYUV8888, 163 DRM_FORMAT_XVYU2101010, 164 DRM_FORMAT_XVYU12_16161616, 165 DRM_FORMAT_XVYU16161616, 166 }; 167 168 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) 169 { 170 switch (format) { 171 case PLANE_CTL_FORMAT_RGB_565: 172 return DRM_FORMAT_RGB565; 173 case PLANE_CTL_FORMAT_NV12: 174 return DRM_FORMAT_NV12; 175 case PLANE_CTL_FORMAT_XYUV: 176 return DRM_FORMAT_XYUV8888; 177 case PLANE_CTL_FORMAT_P010: 178 return DRM_FORMAT_P010; 179 case PLANE_CTL_FORMAT_P012: 180 return DRM_FORMAT_P012; 181 case PLANE_CTL_FORMAT_P016: 182 return DRM_FORMAT_P016; 183 case PLANE_CTL_FORMAT_Y210: 184 return DRM_FORMAT_Y210; 185 case PLANE_CTL_FORMAT_Y212: 186 return DRM_FORMAT_Y212; 187 case PLANE_CTL_FORMAT_Y216: 188 return DRM_FORMAT_Y216; 189 case PLANE_CTL_FORMAT_Y410: 190 return DRM_FORMAT_XVYU2101010; 191 case PLANE_CTL_FORMAT_Y412: 192 return DRM_FORMAT_XVYU12_16161616; 193 case PLANE_CTL_FORMAT_Y416: 194 return DRM_FORMAT_XVYU16161616; 195 default: 196 case PLANE_CTL_FORMAT_XRGB_8888: 197 if (rgb_order) { 198 if (alpha) 199 return DRM_FORMAT_ABGR8888; 200 else 201 return DRM_FORMAT_XBGR8888; 202 } else { 203 if (alpha) 204 return DRM_FORMAT_ARGB8888; 205 else 206 return DRM_FORMAT_XRGB8888; 207 } 208 case PLANE_CTL_FORMAT_XRGB_2101010: 209 if (rgb_order) { 210 if (alpha) 211 return DRM_FORMAT_ABGR2101010; 212 else 213 return DRM_FORMAT_XBGR2101010; 214 } else { 215 if (alpha) 216 return DRM_FORMAT_ARGB2101010; 217 else 218 return DRM_FORMAT_XRGB2101010; 219 } 220 case PLANE_CTL_FORMAT_XRGB_16161616F: 221 if (rgb_order) { 222 if (alpha) 223 return DRM_FORMAT_ABGR16161616F; 224 else 225 return DRM_FORMAT_XBGR16161616F; 226 } else { 227 if (alpha) 228 return DRM_FORMAT_ARGB16161616F; 229 else 230 return DRM_FORMAT_XRGB16161616F; 231 } 232 } 233 } 234 235 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915) 236 { 237 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) 238 return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3); 239 else 240 return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5); 241 } 242 243 bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, 244 enum plane_id plane_id) 245 { 246 return DISPLAY_VER(dev_priv) >= 11 && 247 icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id); 248 } 249 250 u8 icl_hdr_plane_mask(void) 251 { 252 return BIT(PLANE_PRIMARY) | BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1); 253 } 254 255 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) 256 { 257 return DISPLAY_VER(dev_priv) >= 11 && 258 icl_hdr_plane_mask() & BIT(plane_id); 259 } 260 261 static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 262 const struct intel_plane_state *plane_state) 263 { 264 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 265 266 /* two pixels per clock */ 267 return DIV_ROUND_UP(pixel_rate, 2); 268 } 269 270 static void 271 glk_plane_ratio(const struct intel_plane_state *plane_state, 272 unsigned int *num, unsigned int *den) 273 { 274 const struct drm_framebuffer *fb = plane_state->hw.fb; 275 276 if (fb->format->cpp[0] == 8) { 277 *num = 10; 278 *den = 8; 279 } else { 280 *num = 1; 281 *den = 1; 282 } 283 } 284 285 static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 286 const struct intel_plane_state *plane_state) 287 { 288 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 289 unsigned int num, den; 290 291 glk_plane_ratio(plane_state, &num, &den); 292 293 /* two pixels per clock */ 294 return DIV_ROUND_UP(pixel_rate * num, 2 * den); 295 } 296 297 static void 298 skl_plane_ratio(const struct intel_plane_state *plane_state, 299 unsigned int *num, unsigned int *den) 300 { 301 const struct drm_framebuffer *fb = plane_state->hw.fb; 302 303 if (fb->format->cpp[0] == 8) { 304 *num = 9; 305 *den = 8; 306 } else { 307 *num = 1; 308 *den = 1; 309 } 310 } 311 312 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 313 const struct intel_plane_state *plane_state) 314 { 315 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 316 unsigned int num, den; 317 318 skl_plane_ratio(plane_state, &num, &den); 319 320 return DIV_ROUND_UP(pixel_rate * num, den); 321 } 322 323 static int skl_plane_max_width(const struct drm_framebuffer *fb, 324 int color_plane, 325 unsigned int rotation) 326 { 327 int cpp = fb->format->cpp[color_plane]; 328 329 switch (fb->modifier) { 330 case DRM_FORMAT_MOD_LINEAR: 331 case I915_FORMAT_MOD_X_TILED: 332 /* 333 * Validated limit is 4k, but has 5k should 334 * work apart from the following features: 335 * - Ytile (already limited to 4k) 336 * - FP16 (already limited to 4k) 337 * - render compression (already limited to 4k) 338 * - KVMR sprite and cursor (don't care) 339 * - horizontal panning (TODO verify this) 340 * - pipe and plane scaling (TODO verify this) 341 */ 342 if (cpp == 8) 343 return 4096; 344 else 345 return 5120; 346 case I915_FORMAT_MOD_Y_TILED_CCS: 347 case I915_FORMAT_MOD_Yf_TILED_CCS: 348 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 349 /* FIXME AUX plane? */ 350 case I915_FORMAT_MOD_Y_TILED: 351 case I915_FORMAT_MOD_Yf_TILED: 352 if (cpp == 8) 353 return 2048; 354 else 355 return 4096; 356 default: 357 MISSING_CASE(fb->modifier); 358 return 2048; 359 } 360 } 361 362 static int glk_plane_max_width(const struct drm_framebuffer *fb, 363 int color_plane, 364 unsigned int rotation) 365 { 366 int cpp = fb->format->cpp[color_plane]; 367 368 switch (fb->modifier) { 369 case DRM_FORMAT_MOD_LINEAR: 370 case I915_FORMAT_MOD_X_TILED: 371 if (cpp == 8) 372 return 4096; 373 else 374 return 5120; 375 case I915_FORMAT_MOD_Y_TILED_CCS: 376 case I915_FORMAT_MOD_Yf_TILED_CCS: 377 /* FIXME AUX plane? */ 378 case I915_FORMAT_MOD_Y_TILED: 379 case I915_FORMAT_MOD_Yf_TILED: 380 if (cpp == 8) 381 return 2048; 382 else 383 return 5120; 384 default: 385 MISSING_CASE(fb->modifier); 386 return 2048; 387 } 388 } 389 390 static int icl_plane_min_width(const struct drm_framebuffer *fb, 391 int color_plane, 392 unsigned int rotation) 393 { 394 /* Wa_14011264657, Wa_14011050563: gen11+ */ 395 switch (fb->format->format) { 396 case DRM_FORMAT_C8: 397 return 18; 398 case DRM_FORMAT_RGB565: 399 return 10; 400 case DRM_FORMAT_XRGB8888: 401 case DRM_FORMAT_XBGR8888: 402 case DRM_FORMAT_ARGB8888: 403 case DRM_FORMAT_ABGR8888: 404 case DRM_FORMAT_XRGB2101010: 405 case DRM_FORMAT_XBGR2101010: 406 case DRM_FORMAT_ARGB2101010: 407 case DRM_FORMAT_ABGR2101010: 408 case DRM_FORMAT_XVYU2101010: 409 case DRM_FORMAT_Y212: 410 case DRM_FORMAT_Y216: 411 return 6; 412 case DRM_FORMAT_NV12: 413 return 20; 414 case DRM_FORMAT_P010: 415 case DRM_FORMAT_P012: 416 case DRM_FORMAT_P016: 417 return 12; 418 case DRM_FORMAT_XRGB16161616F: 419 case DRM_FORMAT_XBGR16161616F: 420 case DRM_FORMAT_ARGB16161616F: 421 case DRM_FORMAT_ABGR16161616F: 422 case DRM_FORMAT_XVYU12_16161616: 423 case DRM_FORMAT_XVYU16161616: 424 return 4; 425 default: 426 return 1; 427 } 428 } 429 430 static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb, 431 int color_plane, 432 unsigned int rotation) 433 { 434 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 435 return 4096; 436 else 437 return 5120; 438 } 439 440 static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb, 441 int color_plane, 442 unsigned int rotation) 443 { 444 return 5120; 445 } 446 447 static int skl_plane_max_height(const struct drm_framebuffer *fb, 448 int color_plane, 449 unsigned int rotation) 450 { 451 return 4096; 452 } 453 454 static int icl_plane_max_height(const struct drm_framebuffer *fb, 455 int color_plane, 456 unsigned int rotation) 457 { 458 return 4320; 459 } 460 461 static unsigned int 462 skl_plane_max_stride(struct intel_plane *plane, 463 u32 pixel_format, u64 modifier, 464 unsigned int rotation) 465 { 466 struct drm_i915_private *i915 = to_i915(plane->base.dev); 467 const struct drm_format_info *info = drm_format_info(pixel_format); 468 int cpp = info->cpp[0]; 469 int max_horizontal_pixels = 8192; 470 int max_stride_bytes; 471 472 if (DISPLAY_VER(i915) >= 13) { 473 /* 474 * The stride in bytes must not exceed of the size 475 * of 128K bytes. For pixel formats of 64bpp will allow 476 * for a 16K pixel surface. 477 */ 478 max_stride_bytes = 131072; 479 if (cpp == 8) 480 max_horizontal_pixels = 16384; 481 else 482 max_horizontal_pixels = 65536; 483 } else { 484 /* 485 * "The stride in bytes must not exceed the 486 * of the size of 8K pixels and 32K bytes." 487 */ 488 max_stride_bytes = 32768; 489 } 490 491 if (drm_rotation_90_or_270(rotation)) 492 return min(max_horizontal_pixels, max_stride_bytes / cpp); 493 else 494 return min(max_horizontal_pixels * cpp, max_stride_bytes); 495 } 496 497 498 /* Preoffset values for YUV to RGB Conversion */ 499 #define PREOFF_YUV_TO_RGB_HI 0x1800 500 #define PREOFF_YUV_TO_RGB_ME 0x0000 501 #define PREOFF_YUV_TO_RGB_LO 0x1800 502 503 #define ROFF(x) (((x) & 0xffff) << 16) 504 #define GOFF(x) (((x) & 0xffff) << 0) 505 #define BOFF(x) (((x) & 0xffff) << 16) 506 507 /* 508 * Programs the input color space conversion stage for ICL HDR planes. 509 * Note that it is assumed that this stage always happens after YUV 510 * range correction. Thus, the input to this stage is assumed to be 511 * in full-range YCbCr. 512 */ 513 static void 514 icl_program_input_csc(struct intel_plane *plane, 515 const struct intel_crtc_state *crtc_state, 516 const struct intel_plane_state *plane_state) 517 { 518 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 519 enum pipe pipe = plane->pipe; 520 enum plane_id plane_id = plane->id; 521 522 static const u16 input_csc_matrix[][9] = { 523 /* 524 * BT.601 full range YCbCr -> full range RGB 525 * The matrix required is : 526 * [1.000, 0.000, 1.371, 527 * 1.000, -0.336, -0.698, 528 * 1.000, 1.732, 0.0000] 529 */ 530 [DRM_COLOR_YCBCR_BT601] = { 531 0x7AF8, 0x7800, 0x0, 532 0x8B28, 0x7800, 0x9AC0, 533 0x0, 0x7800, 0x7DD8, 534 }, 535 /* 536 * BT.709 full range YCbCr -> full range RGB 537 * The matrix required is : 538 * [1.000, 0.000, 1.574, 539 * 1.000, -0.187, -0.468, 540 * 1.000, 1.855, 0.0000] 541 */ 542 [DRM_COLOR_YCBCR_BT709] = { 543 0x7C98, 0x7800, 0x0, 544 0x9EF8, 0x7800, 0xAC00, 545 0x0, 0x7800, 0x7ED8, 546 }, 547 /* 548 * BT.2020 full range YCbCr -> full range RGB 549 * The matrix required is : 550 * [1.000, 0.000, 1.474, 551 * 1.000, -0.1645, -0.5713, 552 * 1.000, 1.8814, 0.0000] 553 */ 554 [DRM_COLOR_YCBCR_BT2020] = { 555 0x7BC8, 0x7800, 0x0, 556 0x8928, 0x7800, 0xAA88, 557 0x0, 0x7800, 0x7F10, 558 }, 559 }; 560 const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding]; 561 562 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), 563 ROFF(csc[0]) | GOFF(csc[1])); 564 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), 565 BOFF(csc[2])); 566 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), 567 ROFF(csc[3]) | GOFF(csc[4])); 568 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), 569 BOFF(csc[5])); 570 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), 571 ROFF(csc[6]) | GOFF(csc[7])); 572 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), 573 BOFF(csc[8])); 574 575 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), 576 PREOFF_YUV_TO_RGB_HI); 577 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 578 PREOFF_YUV_TO_RGB_ME); 579 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), 580 PREOFF_YUV_TO_RGB_LO); 581 intel_de_write_fw(dev_priv, 582 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); 583 intel_de_write_fw(dev_priv, 584 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); 585 intel_de_write_fw(dev_priv, 586 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); 587 } 588 589 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb, 590 int color_plane, unsigned int rotation) 591 { 592 /* 593 * The stride is either expressed as a multiple of 64 bytes chunks for 594 * linear buffers or in number of tiles for tiled buffers. 595 */ 596 if (is_surface_linear(fb, color_plane)) 597 return 64; 598 else if (drm_rotation_90_or_270(rotation)) 599 return intel_tile_height(fb, color_plane); 600 else 601 return intel_tile_width_bytes(fb, color_plane); 602 } 603 604 static u32 skl_plane_stride(const struct intel_plane_state *plane_state, 605 int color_plane) 606 { 607 const struct drm_framebuffer *fb = plane_state->hw.fb; 608 unsigned int rotation = plane_state->hw.rotation; 609 u32 stride = plane_state->view.color_plane[color_plane].scanout_stride; 610 611 if (color_plane >= fb->format->num_planes) 612 return 0; 613 614 return stride / skl_plane_stride_mult(fb, color_plane, rotation); 615 } 616 617 static void 618 skl_plane_disable_arm(struct intel_plane *plane, 619 const struct intel_crtc_state *crtc_state) 620 { 621 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 622 enum plane_id plane_id = plane->id; 623 enum pipe pipe = plane->pipe; 624 625 skl_write_plane_wm(plane, crtc_state); 626 627 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); 628 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); 629 } 630 631 static void 632 icl_plane_disable_arm(struct intel_plane *plane, 633 const struct intel_crtc_state *crtc_state) 634 { 635 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 636 enum plane_id plane_id = plane->id; 637 enum pipe pipe = plane->pipe; 638 639 if (icl_is_hdr_plane(dev_priv, plane_id)) 640 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0); 641 642 skl_write_plane_wm(plane, crtc_state); 643 644 intel_psr2_disable_plane_sel_fetch_arm(plane, crtc_state); 645 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); 646 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); 647 } 648 649 static bool 650 skl_plane_get_hw_state(struct intel_plane *plane, 651 enum pipe *pipe) 652 { 653 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 654 enum intel_display_power_domain power_domain; 655 enum plane_id plane_id = plane->id; 656 intel_wakeref_t wakeref; 657 bool ret; 658 659 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 660 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 661 if (!wakeref) 662 return false; 663 664 ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; 665 666 *pipe = plane->pipe; 667 668 intel_display_power_put(dev_priv, power_domain, wakeref); 669 670 return ret; 671 } 672 673 static u32 skl_plane_ctl_format(u32 pixel_format) 674 { 675 switch (pixel_format) { 676 case DRM_FORMAT_C8: 677 return PLANE_CTL_FORMAT_INDEXED; 678 case DRM_FORMAT_RGB565: 679 return PLANE_CTL_FORMAT_RGB_565; 680 case DRM_FORMAT_XBGR8888: 681 case DRM_FORMAT_ABGR8888: 682 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; 683 case DRM_FORMAT_XRGB8888: 684 case DRM_FORMAT_ARGB8888: 685 return PLANE_CTL_FORMAT_XRGB_8888; 686 case DRM_FORMAT_XBGR2101010: 687 case DRM_FORMAT_ABGR2101010: 688 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX; 689 case DRM_FORMAT_XRGB2101010: 690 case DRM_FORMAT_ARGB2101010: 691 return PLANE_CTL_FORMAT_XRGB_2101010; 692 case DRM_FORMAT_XBGR16161616F: 693 case DRM_FORMAT_ABGR16161616F: 694 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX; 695 case DRM_FORMAT_XRGB16161616F: 696 case DRM_FORMAT_ARGB16161616F: 697 return PLANE_CTL_FORMAT_XRGB_16161616F; 698 case DRM_FORMAT_XYUV8888: 699 return PLANE_CTL_FORMAT_XYUV; 700 case DRM_FORMAT_YUYV: 701 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV; 702 case DRM_FORMAT_YVYU: 703 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU; 704 case DRM_FORMAT_UYVY: 705 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY; 706 case DRM_FORMAT_VYUY: 707 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY; 708 case DRM_FORMAT_NV12: 709 return PLANE_CTL_FORMAT_NV12; 710 case DRM_FORMAT_P010: 711 return PLANE_CTL_FORMAT_P010; 712 case DRM_FORMAT_P012: 713 return PLANE_CTL_FORMAT_P012; 714 case DRM_FORMAT_P016: 715 return PLANE_CTL_FORMAT_P016; 716 case DRM_FORMAT_Y210: 717 return PLANE_CTL_FORMAT_Y210; 718 case DRM_FORMAT_Y212: 719 return PLANE_CTL_FORMAT_Y212; 720 case DRM_FORMAT_Y216: 721 return PLANE_CTL_FORMAT_Y216; 722 case DRM_FORMAT_XVYU2101010: 723 return PLANE_CTL_FORMAT_Y410; 724 case DRM_FORMAT_XVYU12_16161616: 725 return PLANE_CTL_FORMAT_Y412; 726 case DRM_FORMAT_XVYU16161616: 727 return PLANE_CTL_FORMAT_Y416; 728 default: 729 MISSING_CASE(pixel_format); 730 } 731 732 return 0; 733 } 734 735 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state) 736 { 737 if (!plane_state->hw.fb->format->has_alpha) 738 return PLANE_CTL_ALPHA_DISABLE; 739 740 switch (plane_state->hw.pixel_blend_mode) { 741 case DRM_MODE_BLEND_PIXEL_NONE: 742 return PLANE_CTL_ALPHA_DISABLE; 743 case DRM_MODE_BLEND_PREMULTI: 744 return PLANE_CTL_ALPHA_SW_PREMULTIPLY; 745 case DRM_MODE_BLEND_COVERAGE: 746 return PLANE_CTL_ALPHA_HW_PREMULTIPLY; 747 default: 748 MISSING_CASE(plane_state->hw.pixel_blend_mode); 749 return PLANE_CTL_ALPHA_DISABLE; 750 } 751 } 752 753 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state) 754 { 755 if (!plane_state->hw.fb->format->has_alpha) 756 return PLANE_COLOR_ALPHA_DISABLE; 757 758 switch (plane_state->hw.pixel_blend_mode) { 759 case DRM_MODE_BLEND_PIXEL_NONE: 760 return PLANE_COLOR_ALPHA_DISABLE; 761 case DRM_MODE_BLEND_PREMULTI: 762 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY; 763 case DRM_MODE_BLEND_COVERAGE: 764 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY; 765 default: 766 MISSING_CASE(plane_state->hw.pixel_blend_mode); 767 return PLANE_COLOR_ALPHA_DISABLE; 768 } 769 } 770 771 static u32 skl_plane_ctl_tiling(u64 fb_modifier) 772 { 773 switch (fb_modifier) { 774 case DRM_FORMAT_MOD_LINEAR: 775 break; 776 case I915_FORMAT_MOD_X_TILED: 777 return PLANE_CTL_TILED_X; 778 case I915_FORMAT_MOD_Y_TILED: 779 return PLANE_CTL_TILED_Y; 780 case I915_FORMAT_MOD_4_TILED: 781 return PLANE_CTL_TILED_4; 782 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: 783 return PLANE_CTL_TILED_4 | 784 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 785 PLANE_CTL_CLEAR_COLOR_DISABLE; 786 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: 787 return PLANE_CTL_TILED_4 | 788 PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE | 789 PLANE_CTL_CLEAR_COLOR_DISABLE; 790 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: 791 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 792 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: 793 return PLANE_CTL_TILED_4 | 794 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 795 PLANE_CTL_CLEAR_COLOR_DISABLE; 796 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: 797 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 798 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: 799 return PLANE_CTL_TILED_4 | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE; 800 case I915_FORMAT_MOD_Y_TILED_CCS: 801 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 802 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 803 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 804 return PLANE_CTL_TILED_Y | 805 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 806 PLANE_CTL_CLEAR_COLOR_DISABLE; 807 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 808 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE; 809 case I915_FORMAT_MOD_Yf_TILED: 810 return PLANE_CTL_TILED_YF; 811 case I915_FORMAT_MOD_Yf_TILED_CCS: 812 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 813 default: 814 MISSING_CASE(fb_modifier); 815 } 816 817 return 0; 818 } 819 820 static u32 skl_plane_ctl_rotate(unsigned int rotate) 821 { 822 switch (rotate) { 823 case DRM_MODE_ROTATE_0: 824 break; 825 /* 826 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr 827 * while i915 HW rotation is clockwise, thats why this swapping. 828 */ 829 case DRM_MODE_ROTATE_90: 830 return PLANE_CTL_ROTATE_270; 831 case DRM_MODE_ROTATE_180: 832 return PLANE_CTL_ROTATE_180; 833 case DRM_MODE_ROTATE_270: 834 return PLANE_CTL_ROTATE_90; 835 default: 836 MISSING_CASE(rotate); 837 } 838 839 return 0; 840 } 841 842 static u32 icl_plane_ctl_flip(unsigned int reflect) 843 { 844 switch (reflect) { 845 case 0: 846 break; 847 case DRM_MODE_REFLECT_X: 848 return PLANE_CTL_FLIP_HORIZONTAL; 849 case DRM_MODE_REFLECT_Y: 850 default: 851 MISSING_CASE(reflect); 852 } 853 854 return 0; 855 } 856 857 static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state) 858 { 859 const struct drm_framebuffer *fb = plane_state->hw.fb; 860 861 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) { 862 switch (fb->format->cpp[0]) { 863 case 2: 864 return PLANE_CTL_ARB_SLOTS(1); 865 default: 866 return PLANE_CTL_ARB_SLOTS(0); 867 } 868 } else { 869 switch (fb->format->cpp[0]) { 870 case 8: 871 return PLANE_CTL_ARB_SLOTS(3); 872 case 4: 873 return PLANE_CTL_ARB_SLOTS(1); 874 default: 875 return PLANE_CTL_ARB_SLOTS(0); 876 } 877 } 878 } 879 880 static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) 881 { 882 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 883 u32 plane_ctl = 0; 884 885 if (DISPLAY_VER(dev_priv) >= 10) 886 return plane_ctl; 887 888 if (crtc_state->gamma_enable) 889 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE; 890 891 if (crtc_state->csc_enable) 892 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE; 893 894 return plane_ctl; 895 } 896 897 static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, 898 const struct intel_plane_state *plane_state) 899 { 900 struct drm_i915_private *dev_priv = 901 to_i915(plane_state->uapi.plane->dev); 902 const struct drm_framebuffer *fb = plane_state->hw.fb; 903 unsigned int rotation = plane_state->hw.rotation; 904 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 905 u32 plane_ctl; 906 907 plane_ctl = PLANE_CTL_ENABLE; 908 909 if (DISPLAY_VER(dev_priv) < 10) { 910 plane_ctl |= skl_plane_ctl_alpha(plane_state); 911 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; 912 913 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 914 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709; 915 916 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 917 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE; 918 } 919 920 plane_ctl |= skl_plane_ctl_format(fb->format->format); 921 plane_ctl |= skl_plane_ctl_tiling(fb->modifier); 922 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK); 923 924 if (DISPLAY_VER(dev_priv) >= 11) 925 plane_ctl |= icl_plane_ctl_flip(rotation & 926 DRM_MODE_REFLECT_MASK); 927 928 if (key->flags & I915_SET_COLORKEY_DESTINATION) 929 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; 930 else if (key->flags & I915_SET_COLORKEY_SOURCE) 931 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; 932 933 /* Wa_22012358565:adl-p */ 934 if (DISPLAY_VER(dev_priv) == 13) 935 plane_ctl |= adlp_plane_ctl_arb_slots(plane_state); 936 937 return plane_ctl; 938 } 939 940 static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) 941 { 942 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 943 u32 plane_color_ctl = 0; 944 945 if (DISPLAY_VER(dev_priv) >= 11) 946 return plane_color_ctl; 947 948 if (crtc_state->gamma_enable) 949 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE; 950 951 if (crtc_state->csc_enable) 952 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE; 953 954 return plane_color_ctl; 955 } 956 957 static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, 958 const struct intel_plane_state *plane_state) 959 { 960 struct drm_i915_private *dev_priv = 961 to_i915(plane_state->uapi.plane->dev); 962 const struct drm_framebuffer *fb = plane_state->hw.fb; 963 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 964 u32 plane_color_ctl = 0; 965 966 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; 967 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); 968 969 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { 970 switch (plane_state->hw.color_encoding) { 971 case DRM_COLOR_YCBCR_BT709: 972 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; 973 break; 974 case DRM_COLOR_YCBCR_BT2020: 975 plane_color_ctl |= 976 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020; 977 break; 978 default: 979 plane_color_ctl |= 980 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601; 981 } 982 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 983 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; 984 } else if (fb->format->is_yuv) { 985 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE; 986 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 987 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; 988 } 989 990 if (plane_state->force_black) 991 plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE; 992 993 return plane_color_ctl; 994 } 995 996 static u32 skl_surf_address(const struct intel_plane_state *plane_state, 997 int color_plane) 998 { 999 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1000 const struct drm_framebuffer *fb = plane_state->hw.fb; 1001 u32 offset = plane_state->view.color_plane[color_plane].offset; 1002 1003 if (intel_fb_uses_dpt(fb)) { 1004 /* 1005 * The DPT object contains only one vma, so the VMA's offset 1006 * within the DPT is always 0. 1007 */ 1008 drm_WARN_ON(&i915->drm, plane_state->dpt_vma->node.start); 1009 drm_WARN_ON(&i915->drm, offset & 0x1fffff); 1010 return offset >> 9; 1011 } else { 1012 drm_WARN_ON(&i915->drm, offset & 0xfff); 1013 return offset; 1014 } 1015 } 1016 1017 static u32 skl_plane_surf(const struct intel_plane_state *plane_state, 1018 int color_plane) 1019 { 1020 u32 plane_surf; 1021 1022 plane_surf = intel_plane_ggtt_offset(plane_state) + 1023 skl_surf_address(plane_state, color_plane); 1024 1025 if (plane_state->decrypt) 1026 plane_surf |= PLANE_SURF_DECRYPT; 1027 1028 return plane_surf; 1029 } 1030 1031 static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, 1032 int color_plane) 1033 { 1034 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1035 const struct drm_framebuffer *fb = plane_state->hw.fb; 1036 int aux_plane = skl_main_to_aux_plane(fb, color_plane); 1037 u32 aux_dist; 1038 1039 if (!aux_plane) 1040 return 0; 1041 1042 aux_dist = skl_surf_address(plane_state, aux_plane) - 1043 skl_surf_address(plane_state, color_plane); 1044 1045 if (DISPLAY_VER(i915) < 12) 1046 aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane)); 1047 1048 return aux_dist; 1049 } 1050 1051 static u32 skl_plane_keyval(const struct intel_plane_state *plane_state) 1052 { 1053 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1054 1055 return key->min_value; 1056 } 1057 1058 static u32 skl_plane_keymax(const struct intel_plane_state *plane_state) 1059 { 1060 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1061 u8 alpha = plane_state->hw.alpha >> 8; 1062 1063 return (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha); 1064 } 1065 1066 static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state) 1067 { 1068 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1069 u8 alpha = plane_state->hw.alpha >> 8; 1070 u32 keymsk; 1071 1072 keymsk = key->channel_mask & 0x7ffffff; 1073 if (alpha < 0xff) 1074 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE; 1075 1076 return keymsk; 1077 } 1078 1079 static void icl_plane_csc_load_black(struct intel_plane *plane) 1080 { 1081 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1082 enum plane_id plane_id = plane->id; 1083 enum pipe pipe = plane->pipe; 1084 1085 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 0), 0); 1086 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 1), 0); 1087 1088 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 2), 0); 1089 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 3), 0); 1090 1091 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 4), 0); 1092 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 5), 0); 1093 1094 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0); 1095 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0); 1096 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0); 1097 1098 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0); 1099 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0); 1100 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0); 1101 } 1102 1103 static int icl_plane_color_plane(const struct intel_plane_state *plane_state) 1104 { 1105 /* Program the UV plane on planar master */ 1106 if (plane_state->planar_linked_plane && !plane_state->planar_slave) 1107 return 1; 1108 else 1109 return 0; 1110 } 1111 1112 static void 1113 skl_plane_update_noarm(struct intel_plane *plane, 1114 const struct intel_crtc_state *crtc_state, 1115 const struct intel_plane_state *plane_state) 1116 { 1117 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1118 enum plane_id plane_id = plane->id; 1119 enum pipe pipe = plane->pipe; 1120 u32 stride = skl_plane_stride(plane_state, 0); 1121 int crtc_x = plane_state->uapi.dst.x1; 1122 int crtc_y = plane_state->uapi.dst.y1; 1123 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1124 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1125 1126 /* The scaler will handle the output position */ 1127 if (plane_state->scaler_id >= 0) { 1128 crtc_x = 0; 1129 crtc_y = 0; 1130 } 1131 1132 intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), 1133 PLANE_STRIDE_(stride)); 1134 intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), 1135 PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x)); 1136 intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), 1137 PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1)); 1138 1139 skl_write_plane_wm(plane, crtc_state); 1140 } 1141 1142 static void 1143 skl_plane_update_arm(struct intel_plane *plane, 1144 const struct intel_crtc_state *crtc_state, 1145 const struct intel_plane_state *plane_state) 1146 { 1147 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1148 enum plane_id plane_id = plane->id; 1149 enum pipe pipe = plane->pipe; 1150 u32 x = plane_state->view.color_plane[0].x; 1151 u32 y = plane_state->view.color_plane[0].y; 1152 u32 plane_ctl, plane_color_ctl = 0; 1153 1154 plane_ctl = plane_state->ctl | 1155 skl_plane_ctl_crtc(crtc_state); 1156 1157 if (DISPLAY_VER(dev_priv) >= 10) 1158 plane_color_ctl = plane_state->color_ctl | 1159 glk_plane_color_ctl_crtc(crtc_state); 1160 1161 intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state)); 1162 intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state)); 1163 intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state)); 1164 1165 intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id), 1166 PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x)); 1167 1168 intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), 1169 skl_plane_aux_dist(plane_state, 0)); 1170 1171 intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id), 1172 PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) | 1173 PLANE_OFFSET_X(plane_state->view.color_plane[1].x)); 1174 1175 if (DISPLAY_VER(dev_priv) >= 10) 1176 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); 1177 1178 /* 1179 * Enable the scaler before the plane so that we don't 1180 * get a catastrophic underrun even if the two operations 1181 * end up happening in two different frames. 1182 * 1183 * TODO: split into noarm+arm pair 1184 */ 1185 if (plane_state->scaler_id >= 0) 1186 skl_program_plane_scaler(plane, crtc_state, plane_state); 1187 1188 /* 1189 * The control register self-arms if the plane was previously 1190 * disabled. Try to make the plane enable atomic by writing 1191 * the control register just before the surface register. 1192 */ 1193 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 1194 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 1195 skl_plane_surf(plane_state, 0)); 1196 } 1197 1198 static void 1199 icl_plane_update_noarm(struct intel_plane *plane, 1200 const struct intel_crtc_state *crtc_state, 1201 const struct intel_plane_state *plane_state) 1202 { 1203 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1204 enum plane_id plane_id = plane->id; 1205 enum pipe pipe = plane->pipe; 1206 int color_plane = icl_plane_color_plane(plane_state); 1207 u32 stride = skl_plane_stride(plane_state, color_plane); 1208 const struct drm_framebuffer *fb = plane_state->hw.fb; 1209 int crtc_x = plane_state->uapi.dst.x1; 1210 int crtc_y = plane_state->uapi.dst.y1; 1211 int x = plane_state->view.color_plane[color_plane].x; 1212 int y = plane_state->view.color_plane[color_plane].y; 1213 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1214 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1215 u32 plane_color_ctl; 1216 1217 plane_color_ctl = plane_state->color_ctl | 1218 glk_plane_color_ctl_crtc(crtc_state); 1219 1220 /* The scaler will handle the output position */ 1221 if (plane_state->scaler_id >= 0) { 1222 crtc_x = 0; 1223 crtc_y = 0; 1224 } 1225 1226 intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), 1227 PLANE_STRIDE_(stride)); 1228 intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), 1229 PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x)); 1230 intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), 1231 PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1)); 1232 1233 intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state)); 1234 intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state)); 1235 intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state)); 1236 1237 intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id), 1238 PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x)); 1239 1240 if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) { 1241 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0), 1242 lower_32_bits(plane_state->ccval)); 1243 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1), 1244 upper_32_bits(plane_state->ccval)); 1245 } 1246 1247 /* FLAT CCS doesn't need to program AUX_DIST */ 1248 if (!HAS_FLAT_CCS(dev_priv)) 1249 intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), 1250 skl_plane_aux_dist(plane_state, color_plane)); 1251 1252 if (icl_is_hdr_plane(dev_priv, plane_id)) 1253 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 1254 plane_state->cus_ctl); 1255 1256 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); 1257 1258 if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) 1259 icl_program_input_csc(plane, crtc_state, plane_state); 1260 1261 skl_write_plane_wm(plane, crtc_state); 1262 1263 /* 1264 * FIXME: pxp session invalidation can hit any time even at time of commit 1265 * or after the commit, display content will be garbage. 1266 */ 1267 if (plane_state->force_black) 1268 icl_plane_csc_load_black(plane); 1269 1270 intel_psr2_program_plane_sel_fetch_noarm(plane, crtc_state, plane_state, color_plane); 1271 } 1272 1273 static void 1274 icl_plane_update_arm(struct intel_plane *plane, 1275 const struct intel_crtc_state *crtc_state, 1276 const struct intel_plane_state *plane_state) 1277 { 1278 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1279 enum plane_id plane_id = plane->id; 1280 enum pipe pipe = plane->pipe; 1281 int color_plane = icl_plane_color_plane(plane_state); 1282 u32 plane_ctl; 1283 1284 plane_ctl = plane_state->ctl | 1285 skl_plane_ctl_crtc(crtc_state); 1286 1287 /* 1288 * Enable the scaler before the plane so that we don't 1289 * get a catastrophic underrun even if the two operations 1290 * end up happening in two different frames. 1291 * 1292 * TODO: split into noarm+arm pair 1293 */ 1294 if (plane_state->scaler_id >= 0) 1295 skl_program_plane_scaler(plane, crtc_state, plane_state); 1296 1297 intel_psr2_program_plane_sel_fetch_arm(plane, crtc_state, plane_state); 1298 1299 /* 1300 * The control register self-arms if the plane was previously 1301 * disabled. Try to make the plane enable atomic by writing 1302 * the control register just before the surface register. 1303 */ 1304 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 1305 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 1306 skl_plane_surf(plane_state, color_plane)); 1307 } 1308 1309 static void 1310 skl_plane_async_flip(struct intel_plane *plane, 1311 const struct intel_crtc_state *crtc_state, 1312 const struct intel_plane_state *plane_state, 1313 bool async_flip) 1314 { 1315 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1316 enum plane_id plane_id = plane->id; 1317 enum pipe pipe = plane->pipe; 1318 u32 plane_ctl = plane_state->ctl; 1319 1320 plane_ctl |= skl_plane_ctl_crtc(crtc_state); 1321 1322 if (async_flip) 1323 plane_ctl |= PLANE_CTL_ASYNC_FLIP; 1324 1325 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 1326 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 1327 skl_plane_surf(plane_state, 0)); 1328 } 1329 1330 static bool intel_format_is_p01x(u32 format) 1331 { 1332 switch (format) { 1333 case DRM_FORMAT_P010: 1334 case DRM_FORMAT_P012: 1335 case DRM_FORMAT_P016: 1336 return true; 1337 default: 1338 return false; 1339 } 1340 } 1341 1342 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, 1343 const struct intel_plane_state *plane_state) 1344 { 1345 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1346 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1347 const struct drm_framebuffer *fb = plane_state->hw.fb; 1348 unsigned int rotation = plane_state->hw.rotation; 1349 1350 if (!fb) 1351 return 0; 1352 1353 if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) && 1354 intel_fb_is_ccs_modifier(fb->modifier)) { 1355 drm_dbg_kms(&dev_priv->drm, 1356 "RC support only with 0/180 degree rotation (%x)\n", 1357 rotation); 1358 return -EINVAL; 1359 } 1360 1361 if (rotation & DRM_MODE_REFLECT_X && 1362 fb->modifier == DRM_FORMAT_MOD_LINEAR) { 1363 drm_dbg_kms(&dev_priv->drm, 1364 "horizontal flip is not supported with linear surface formats\n"); 1365 return -EINVAL; 1366 } 1367 1368 if (drm_rotation_90_or_270(rotation)) { 1369 if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) { 1370 drm_dbg_kms(&dev_priv->drm, 1371 "Y/Yf tiling required for 90/270!\n"); 1372 return -EINVAL; 1373 } 1374 1375 /* 1376 * 90/270 is not allowed with RGB64 16:16:16:16 and 1377 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards. 1378 */ 1379 switch (fb->format->format) { 1380 case DRM_FORMAT_RGB565: 1381 if (DISPLAY_VER(dev_priv) >= 11) 1382 break; 1383 fallthrough; 1384 case DRM_FORMAT_C8: 1385 case DRM_FORMAT_XRGB16161616F: 1386 case DRM_FORMAT_XBGR16161616F: 1387 case DRM_FORMAT_ARGB16161616F: 1388 case DRM_FORMAT_ABGR16161616F: 1389 case DRM_FORMAT_Y210: 1390 case DRM_FORMAT_Y212: 1391 case DRM_FORMAT_Y216: 1392 case DRM_FORMAT_XVYU12_16161616: 1393 case DRM_FORMAT_XVYU16161616: 1394 drm_dbg_kms(&dev_priv->drm, 1395 "Unsupported pixel format %p4cc for 90/270!\n", 1396 &fb->format->format); 1397 return -EINVAL; 1398 default: 1399 break; 1400 } 1401 } 1402 1403 /* Y-tiling is not supported in IF-ID Interlace mode */ 1404 if (crtc_state->hw.enable && 1405 crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE && 1406 fb->modifier != DRM_FORMAT_MOD_LINEAR && 1407 fb->modifier != I915_FORMAT_MOD_X_TILED) { 1408 drm_dbg_kms(&dev_priv->drm, 1409 "Y/Yf tiling not supported in IF-ID mode\n"); 1410 return -EINVAL; 1411 } 1412 1413 /* Wa_1606054188:tgl,adl-s */ 1414 if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) && 1415 plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE && 1416 intel_format_is_p01x(fb->format->format)) { 1417 drm_dbg_kms(&dev_priv->drm, 1418 "Source color keying not supported with P01x formats\n"); 1419 return -EINVAL; 1420 } 1421 1422 return 0; 1423 } 1424 1425 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state, 1426 const struct intel_plane_state *plane_state) 1427 { 1428 struct drm_i915_private *dev_priv = 1429 to_i915(plane_state->uapi.plane->dev); 1430 int crtc_x = plane_state->uapi.dst.x1; 1431 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 1432 int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); 1433 1434 /* 1435 * Display WA #1175: glk 1436 * Planes other than the cursor may cause FIFO underflow and display 1437 * corruption if starting less than 4 pixels from the right edge of 1438 * the screen. 1439 * Besides the above WA fix the similar problem, where planes other 1440 * than the cursor ending less than 4 pixels from the left edge of the 1441 * screen may cause FIFO underflow and display corruption. 1442 */ 1443 if (DISPLAY_VER(dev_priv) == 10 && 1444 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) { 1445 drm_dbg_kms(&dev_priv->drm, 1446 "requested plane X %s position %d invalid (valid range %d-%d)\n", 1447 crtc_x + crtc_w < 4 ? "end" : "start", 1448 crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x, 1449 4, pipe_src_w - 4); 1450 return -ERANGE; 1451 } 1452 1453 return 0; 1454 } 1455 1456 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state) 1457 { 1458 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1459 const struct drm_framebuffer *fb = plane_state->hw.fb; 1460 unsigned int rotation = plane_state->hw.rotation; 1461 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1462 1463 /* Display WA #1106 */ 1464 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 1465 src_w & 3 && 1466 (rotation == DRM_MODE_ROTATE_270 || 1467 rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) { 1468 drm_dbg_kms(&i915->drm, "src width must be multiple of 4 for rotated planar YUV\n"); 1469 return -EINVAL; 1470 } 1471 1472 return 0; 1473 } 1474 1475 static int skl_plane_max_scale(struct drm_i915_private *dev_priv, 1476 const struct drm_framebuffer *fb) 1477 { 1478 /* 1479 * We don't yet know the final source width nor 1480 * whether we can use the HQ scaler mode. Assume 1481 * the best case. 1482 * FIXME need to properly check this later. 1483 */ 1484 if (DISPLAY_VER(dev_priv) >= 10 || 1485 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 1486 return 0x30000 - 1; 1487 else 1488 return 0x20000 - 1; 1489 } 1490 1491 static int intel_plane_min_width(struct intel_plane *plane, 1492 const struct drm_framebuffer *fb, 1493 int color_plane, 1494 unsigned int rotation) 1495 { 1496 if (plane->min_width) 1497 return plane->min_width(fb, color_plane, rotation); 1498 else 1499 return 1; 1500 } 1501 1502 static int intel_plane_max_width(struct intel_plane *plane, 1503 const struct drm_framebuffer *fb, 1504 int color_plane, 1505 unsigned int rotation) 1506 { 1507 if (plane->max_width) 1508 return plane->max_width(fb, color_plane, rotation); 1509 else 1510 return INT_MAX; 1511 } 1512 1513 static int intel_plane_max_height(struct intel_plane *plane, 1514 const struct drm_framebuffer *fb, 1515 int color_plane, 1516 unsigned int rotation) 1517 { 1518 if (plane->max_height) 1519 return plane->max_height(fb, color_plane, rotation); 1520 else 1521 return INT_MAX; 1522 } 1523 1524 static bool 1525 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, 1526 int main_x, int main_y, u32 main_offset, 1527 int ccs_plane) 1528 { 1529 const struct drm_framebuffer *fb = plane_state->hw.fb; 1530 int aux_x = plane_state->view.color_plane[ccs_plane].x; 1531 int aux_y = plane_state->view.color_plane[ccs_plane].y; 1532 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; 1533 u32 alignment = intel_surf_alignment(fb, ccs_plane); 1534 int hsub; 1535 int vsub; 1536 1537 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 1538 while (aux_offset >= main_offset && aux_y <= main_y) { 1539 int x, y; 1540 1541 if (aux_x == main_x && aux_y == main_y) 1542 break; 1543 1544 if (aux_offset == 0) 1545 break; 1546 1547 x = aux_x / hsub; 1548 y = aux_y / vsub; 1549 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, 1550 plane_state, 1551 ccs_plane, 1552 aux_offset, 1553 aux_offset - 1554 alignment); 1555 aux_x = x * hsub + aux_x % hsub; 1556 aux_y = y * vsub + aux_y % vsub; 1557 } 1558 1559 if (aux_x != main_x || aux_y != main_y) 1560 return false; 1561 1562 plane_state->view.color_plane[ccs_plane].offset = aux_offset; 1563 plane_state->view.color_plane[ccs_plane].x = aux_x; 1564 plane_state->view.color_plane[ccs_plane].y = aux_y; 1565 1566 return true; 1567 } 1568 1569 1570 int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, 1571 int *x, int *y, u32 *offset) 1572 { 1573 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1574 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1575 const struct drm_framebuffer *fb = plane_state->hw.fb; 1576 const int aux_plane = skl_main_to_aux_plane(fb, 0); 1577 const u32 aux_offset = plane_state->view.color_plane[aux_plane].offset; 1578 const u32 alignment = intel_surf_alignment(fb, 0); 1579 const int w = drm_rect_width(&plane_state->uapi.src) >> 16; 1580 1581 intel_add_fb_offsets(x, y, plane_state, 0); 1582 *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0); 1583 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) 1584 return -EINVAL; 1585 1586 /* 1587 * AUX surface offset is specified as the distance from the 1588 * main surface offset, and it must be non-negative. Make 1589 * sure that is what we will get. 1590 */ 1591 if (aux_plane && *offset > aux_offset) 1592 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, 1593 *offset, 1594 aux_offset & ~(alignment - 1)); 1595 1596 /* 1597 * When using an X-tiled surface, the plane blows up 1598 * if the x offset + width exceed the stride. 1599 * 1600 * TODO: linear and Y-tiled seem fine, Yf untested, 1601 */ 1602 if (fb->modifier == I915_FORMAT_MOD_X_TILED) { 1603 int cpp = fb->format->cpp[0]; 1604 1605 while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) { 1606 if (*offset == 0) { 1607 drm_dbg_kms(&dev_priv->drm, 1608 "Unable to find suitable display surface offset due to X-tiling\n"); 1609 return -EINVAL; 1610 } 1611 1612 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, 1613 *offset, 1614 *offset - alignment); 1615 } 1616 } 1617 1618 return 0; 1619 } 1620 1621 static int skl_check_main_surface(struct intel_plane_state *plane_state) 1622 { 1623 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1624 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1625 const struct drm_framebuffer *fb = plane_state->hw.fb; 1626 const unsigned int rotation = plane_state->hw.rotation; 1627 int x = plane_state->uapi.src.x1 >> 16; 1628 int y = plane_state->uapi.src.y1 >> 16; 1629 const int w = drm_rect_width(&plane_state->uapi.src) >> 16; 1630 const int h = drm_rect_height(&plane_state->uapi.src) >> 16; 1631 const int min_width = intel_plane_min_width(plane, fb, 0, rotation); 1632 const int max_width = intel_plane_max_width(plane, fb, 0, rotation); 1633 const int max_height = intel_plane_max_height(plane, fb, 0, rotation); 1634 const int aux_plane = skl_main_to_aux_plane(fb, 0); 1635 const u32 alignment = intel_surf_alignment(fb, 0); 1636 u32 offset; 1637 int ret; 1638 1639 if (w > max_width || w < min_width || h > max_height || h < 1) { 1640 drm_dbg_kms(&dev_priv->drm, 1641 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", 1642 w, h, min_width, max_width, max_height); 1643 return -EINVAL; 1644 } 1645 1646 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); 1647 if (ret) 1648 return ret; 1649 1650 /* 1651 * CCS AUX surface doesn't have its own x/y offsets, we must make sure 1652 * they match with the main surface x/y offsets. On DG2 1653 * there's no aux plane on fb so skip this checking. 1654 */ 1655 if (intel_fb_is_ccs_modifier(fb->modifier) && aux_plane) { 1656 while (!skl_check_main_ccs_coordinates(plane_state, x, y, 1657 offset, aux_plane)) { 1658 if (offset == 0) 1659 break; 1660 1661 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 1662 offset, offset - alignment); 1663 } 1664 1665 if (x != plane_state->view.color_plane[aux_plane].x || 1666 y != plane_state->view.color_plane[aux_plane].y) { 1667 drm_dbg_kms(&dev_priv->drm, 1668 "Unable to find suitable display surface offset due to CCS\n"); 1669 return -EINVAL; 1670 } 1671 } 1672 1673 if (DISPLAY_VER(dev_priv) >= 13) 1674 drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535); 1675 else 1676 drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191); 1677 1678 plane_state->view.color_plane[0].offset = offset; 1679 plane_state->view.color_plane[0].x = x; 1680 plane_state->view.color_plane[0].y = y; 1681 1682 /* 1683 * Put the final coordinates back so that the src 1684 * coordinate checks will see the right values. 1685 */ 1686 drm_rect_translate_to(&plane_state->uapi.src, 1687 x << 16, y << 16); 1688 1689 return 0; 1690 } 1691 1692 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) 1693 { 1694 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1695 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1696 const struct drm_framebuffer *fb = plane_state->hw.fb; 1697 unsigned int rotation = plane_state->hw.rotation; 1698 int uv_plane = 1; 1699 int ccs_plane = intel_fb_is_ccs_modifier(fb->modifier) ? 1700 skl_main_to_aux_plane(fb, uv_plane) : 0; 1701 int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation); 1702 int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation); 1703 int x = plane_state->uapi.src.x1 >> 17; 1704 int y = plane_state->uapi.src.y1 >> 17; 1705 int w = drm_rect_width(&plane_state->uapi.src) >> 17; 1706 int h = drm_rect_height(&plane_state->uapi.src) >> 17; 1707 u32 offset; 1708 1709 /* FIXME not quite sure how/if these apply to the chroma plane */ 1710 if (w > max_width || h > max_height) { 1711 drm_dbg_kms(&i915->drm, 1712 "CbCr source size %dx%d too big (limit %dx%d)\n", 1713 w, h, max_width, max_height); 1714 return -EINVAL; 1715 } 1716 1717 intel_add_fb_offsets(&x, &y, plane_state, uv_plane); 1718 offset = intel_plane_compute_aligned_offset(&x, &y, 1719 plane_state, uv_plane); 1720 1721 if (ccs_plane) { 1722 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; 1723 u32 alignment = intel_surf_alignment(fb, uv_plane); 1724 1725 if (offset > aux_offset) 1726 offset = intel_plane_adjust_aligned_offset(&x, &y, 1727 plane_state, 1728 uv_plane, 1729 offset, 1730 aux_offset & ~(alignment - 1)); 1731 1732 while (!skl_check_main_ccs_coordinates(plane_state, x, y, 1733 offset, ccs_plane)) { 1734 if (offset == 0) 1735 break; 1736 1737 offset = intel_plane_adjust_aligned_offset(&x, &y, 1738 plane_state, 1739 uv_plane, 1740 offset, offset - alignment); 1741 } 1742 1743 if (x != plane_state->view.color_plane[ccs_plane].x || 1744 y != plane_state->view.color_plane[ccs_plane].y) { 1745 drm_dbg_kms(&i915->drm, 1746 "Unable to find suitable display surface offset due to CCS\n"); 1747 return -EINVAL; 1748 } 1749 } 1750 1751 if (DISPLAY_VER(i915) >= 13) 1752 drm_WARN_ON(&i915->drm, x > 65535 || y > 65535); 1753 else 1754 drm_WARN_ON(&i915->drm, x > 8191 || y > 8191); 1755 1756 plane_state->view.color_plane[uv_plane].offset = offset; 1757 plane_state->view.color_plane[uv_plane].x = x; 1758 plane_state->view.color_plane[uv_plane].y = y; 1759 1760 return 0; 1761 } 1762 1763 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) 1764 { 1765 const struct drm_framebuffer *fb = plane_state->hw.fb; 1766 int src_x = plane_state->uapi.src.x1 >> 16; 1767 int src_y = plane_state->uapi.src.y1 >> 16; 1768 u32 offset; 1769 int ccs_plane; 1770 1771 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) { 1772 int main_hsub, main_vsub; 1773 int hsub, vsub; 1774 int x, y; 1775 1776 if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane)) 1777 continue; 1778 1779 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, 1780 skl_ccs_to_main_plane(fb, ccs_plane)); 1781 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 1782 1783 hsub *= main_hsub; 1784 vsub *= main_vsub; 1785 x = src_x / hsub; 1786 y = src_y / vsub; 1787 1788 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane); 1789 1790 offset = intel_plane_compute_aligned_offset(&x, &y, 1791 plane_state, 1792 ccs_plane); 1793 1794 plane_state->view.color_plane[ccs_plane].offset = offset; 1795 plane_state->view.color_plane[ccs_plane].x = (x * hsub + src_x % hsub) / main_hsub; 1796 plane_state->view.color_plane[ccs_plane].y = (y * vsub + src_y % vsub) / main_vsub; 1797 } 1798 1799 return 0; 1800 } 1801 1802 static int skl_check_plane_surface(struct intel_plane_state *plane_state) 1803 { 1804 const struct drm_framebuffer *fb = plane_state->hw.fb; 1805 int ret; 1806 1807 ret = intel_plane_compute_gtt(plane_state); 1808 if (ret) 1809 return ret; 1810 1811 if (!plane_state->uapi.visible) 1812 return 0; 1813 1814 /* 1815 * Handle the AUX surface first since the main surface setup depends on 1816 * it. 1817 */ 1818 if (intel_fb_is_ccs_modifier(fb->modifier)) { 1819 ret = skl_check_ccs_aux_surface(plane_state); 1820 if (ret) 1821 return ret; 1822 } 1823 1824 if (intel_format_info_is_yuv_semiplanar(fb->format, 1825 fb->modifier)) { 1826 ret = skl_check_nv12_aux_surface(plane_state); 1827 if (ret) 1828 return ret; 1829 } 1830 1831 ret = skl_check_main_surface(plane_state); 1832 if (ret) 1833 return ret; 1834 1835 return 0; 1836 } 1837 1838 static bool skl_fb_scalable(const struct drm_framebuffer *fb) 1839 { 1840 if (!fb) 1841 return false; 1842 1843 switch (fb->format->format) { 1844 case DRM_FORMAT_C8: 1845 return false; 1846 case DRM_FORMAT_XRGB16161616F: 1847 case DRM_FORMAT_ARGB16161616F: 1848 case DRM_FORMAT_XBGR16161616F: 1849 case DRM_FORMAT_ABGR16161616F: 1850 return DISPLAY_VER(to_i915(fb->dev)) >= 11; 1851 default: 1852 return true; 1853 } 1854 } 1855 1856 static bool bo_has_valid_encryption(struct drm_i915_gem_object *obj) 1857 { 1858 struct drm_i915_private *i915 = to_i915(obj->base.dev); 1859 1860 return intel_pxp_key_check(i915->pxp, obj, false) == 0; 1861 } 1862 1863 static bool pxp_is_borked(struct drm_i915_gem_object *obj) 1864 { 1865 return i915_gem_object_is_protected(obj) && !bo_has_valid_encryption(obj); 1866 } 1867 1868 static int skl_plane_check(struct intel_crtc_state *crtc_state, 1869 struct intel_plane_state *plane_state) 1870 { 1871 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1872 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1873 const struct drm_framebuffer *fb = plane_state->hw.fb; 1874 int min_scale = DRM_PLANE_NO_SCALING; 1875 int max_scale = DRM_PLANE_NO_SCALING; 1876 int ret; 1877 1878 ret = skl_plane_check_fb(crtc_state, plane_state); 1879 if (ret) 1880 return ret; 1881 1882 /* use scaler when colorkey is not required */ 1883 if (!plane_state->ckey.flags && skl_fb_scalable(fb)) { 1884 min_scale = 1; 1885 max_scale = skl_plane_max_scale(dev_priv, fb); 1886 } 1887 1888 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 1889 min_scale, max_scale, true); 1890 if (ret) 1891 return ret; 1892 1893 ret = skl_check_plane_surface(plane_state); 1894 if (ret) 1895 return ret; 1896 1897 if (!plane_state->uapi.visible) 1898 return 0; 1899 1900 ret = skl_plane_check_dst_coordinates(crtc_state, plane_state); 1901 if (ret) 1902 return ret; 1903 1904 ret = intel_plane_check_src_coordinates(plane_state); 1905 if (ret) 1906 return ret; 1907 1908 ret = skl_plane_check_nv12_rotation(plane_state); 1909 if (ret) 1910 return ret; 1911 1912 if (DISPLAY_VER(dev_priv) >= 11) { 1913 plane_state->decrypt = bo_has_valid_encryption(intel_fb_obj(fb)); 1914 plane_state->force_black = pxp_is_borked(intel_fb_obj(fb)); 1915 } 1916 1917 /* HW only has 8 bits pixel precision, disable plane if invisible */ 1918 if (!(plane_state->hw.alpha >> 8)) 1919 plane_state->uapi.visible = false; 1920 1921 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); 1922 1923 if (DISPLAY_VER(dev_priv) >= 10) 1924 plane_state->color_ctl = glk_plane_color_ctl(crtc_state, 1925 plane_state); 1926 1927 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 1928 icl_is_hdr_plane(dev_priv, plane->id)) 1929 /* Enable and use MPEG-2 chroma siting */ 1930 plane_state->cus_ctl = PLANE_CUS_ENABLE | 1931 PLANE_CUS_HPHASE_0 | 1932 PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25; 1933 else 1934 plane_state->cus_ctl = 0; 1935 1936 return 0; 1937 } 1938 1939 static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe) 1940 { 1941 return pipe - PIPE_A + INTEL_FBC_A; 1942 } 1943 1944 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv, 1945 enum intel_fbc_id fbc_id, enum plane_id plane_id) 1946 { 1947 if ((DISPLAY_RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0) 1948 return false; 1949 1950 return plane_id == PLANE_PRIMARY; 1951 } 1952 1953 static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv, 1954 enum pipe pipe, enum plane_id plane_id) 1955 { 1956 enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe); 1957 1958 if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id)) 1959 return dev_priv->display.fbc[fbc_id]; 1960 else 1961 return NULL; 1962 } 1963 1964 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, 1965 enum pipe pipe, enum plane_id plane_id) 1966 { 1967 /* Display WA #0870: skl, bxt */ 1968 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) 1969 return false; 1970 1971 if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C) 1972 return false; 1973 1974 if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0) 1975 return false; 1976 1977 return true; 1978 } 1979 1980 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv, 1981 enum pipe pipe, enum plane_id plane_id, 1982 int *num_formats) 1983 { 1984 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 1985 *num_formats = ARRAY_SIZE(skl_planar_formats); 1986 return skl_planar_formats; 1987 } else { 1988 *num_formats = ARRAY_SIZE(skl_plane_formats); 1989 return skl_plane_formats; 1990 } 1991 } 1992 1993 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv, 1994 enum pipe pipe, enum plane_id plane_id, 1995 int *num_formats) 1996 { 1997 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 1998 *num_formats = ARRAY_SIZE(glk_planar_formats); 1999 return glk_planar_formats; 2000 } else { 2001 *num_formats = ARRAY_SIZE(skl_plane_formats); 2002 return skl_plane_formats; 2003 } 2004 } 2005 2006 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, 2007 enum pipe pipe, enum plane_id plane_id, 2008 int *num_formats) 2009 { 2010 if (icl_is_hdr_plane(dev_priv, plane_id)) { 2011 *num_formats = ARRAY_SIZE(icl_hdr_plane_formats); 2012 return icl_hdr_plane_formats; 2013 } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) { 2014 *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats); 2015 return icl_sdr_y_plane_formats; 2016 } else { 2017 *num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats); 2018 return icl_sdr_uv_plane_formats; 2019 } 2020 } 2021 2022 static bool skl_plane_format_mod_supported(struct drm_plane *_plane, 2023 u32 format, u64 modifier) 2024 { 2025 struct intel_plane *plane = to_intel_plane(_plane); 2026 2027 if (!intel_fb_plane_supports_modifier(plane, modifier)) 2028 return false; 2029 2030 switch (format) { 2031 case DRM_FORMAT_XRGB8888: 2032 case DRM_FORMAT_XBGR8888: 2033 case DRM_FORMAT_ARGB8888: 2034 case DRM_FORMAT_ABGR8888: 2035 if (intel_fb_is_ccs_modifier(modifier)) 2036 return true; 2037 fallthrough; 2038 case DRM_FORMAT_RGB565: 2039 case DRM_FORMAT_XRGB2101010: 2040 case DRM_FORMAT_XBGR2101010: 2041 case DRM_FORMAT_ARGB2101010: 2042 case DRM_FORMAT_ABGR2101010: 2043 case DRM_FORMAT_YUYV: 2044 case DRM_FORMAT_YVYU: 2045 case DRM_FORMAT_UYVY: 2046 case DRM_FORMAT_VYUY: 2047 case DRM_FORMAT_NV12: 2048 case DRM_FORMAT_XYUV8888: 2049 case DRM_FORMAT_P010: 2050 case DRM_FORMAT_P012: 2051 case DRM_FORMAT_P016: 2052 case DRM_FORMAT_XVYU2101010: 2053 if (modifier == I915_FORMAT_MOD_Yf_TILED) 2054 return true; 2055 fallthrough; 2056 case DRM_FORMAT_C8: 2057 case DRM_FORMAT_XBGR16161616F: 2058 case DRM_FORMAT_ABGR16161616F: 2059 case DRM_FORMAT_XRGB16161616F: 2060 case DRM_FORMAT_ARGB16161616F: 2061 case DRM_FORMAT_Y210: 2062 case DRM_FORMAT_Y212: 2063 case DRM_FORMAT_Y216: 2064 case DRM_FORMAT_XVYU12_16161616: 2065 case DRM_FORMAT_XVYU16161616: 2066 if (modifier == DRM_FORMAT_MOD_LINEAR || 2067 modifier == I915_FORMAT_MOD_X_TILED || 2068 modifier == I915_FORMAT_MOD_Y_TILED) 2069 return true; 2070 fallthrough; 2071 default: 2072 return false; 2073 } 2074 } 2075 2076 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, 2077 u32 format, u64 modifier) 2078 { 2079 struct intel_plane *plane = to_intel_plane(_plane); 2080 2081 if (!intel_fb_plane_supports_modifier(plane, modifier)) 2082 return false; 2083 2084 switch (format) { 2085 case DRM_FORMAT_XRGB8888: 2086 case DRM_FORMAT_XBGR8888: 2087 case DRM_FORMAT_ARGB8888: 2088 case DRM_FORMAT_ABGR8888: 2089 if (intel_fb_is_ccs_modifier(modifier)) 2090 return true; 2091 fallthrough; 2092 case DRM_FORMAT_YUYV: 2093 case DRM_FORMAT_YVYU: 2094 case DRM_FORMAT_UYVY: 2095 case DRM_FORMAT_VYUY: 2096 case DRM_FORMAT_NV12: 2097 case DRM_FORMAT_XYUV8888: 2098 case DRM_FORMAT_P010: 2099 case DRM_FORMAT_P012: 2100 case DRM_FORMAT_P016: 2101 if (intel_fb_is_mc_ccs_modifier(modifier)) 2102 return true; 2103 fallthrough; 2104 case DRM_FORMAT_RGB565: 2105 case DRM_FORMAT_XRGB2101010: 2106 case DRM_FORMAT_XBGR2101010: 2107 case DRM_FORMAT_ARGB2101010: 2108 case DRM_FORMAT_ABGR2101010: 2109 case DRM_FORMAT_XVYU2101010: 2110 case DRM_FORMAT_C8: 2111 case DRM_FORMAT_XBGR16161616F: 2112 case DRM_FORMAT_ABGR16161616F: 2113 case DRM_FORMAT_XRGB16161616F: 2114 case DRM_FORMAT_ARGB16161616F: 2115 case DRM_FORMAT_Y210: 2116 case DRM_FORMAT_Y212: 2117 case DRM_FORMAT_Y216: 2118 case DRM_FORMAT_XVYU12_16161616: 2119 case DRM_FORMAT_XVYU16161616: 2120 if (!intel_fb_is_ccs_modifier(modifier)) 2121 return true; 2122 fallthrough; 2123 default: 2124 return false; 2125 } 2126 } 2127 2128 static const struct drm_plane_funcs skl_plane_funcs = { 2129 .update_plane = drm_atomic_helper_update_plane, 2130 .disable_plane = drm_atomic_helper_disable_plane, 2131 .destroy = intel_plane_destroy, 2132 .atomic_duplicate_state = intel_plane_duplicate_state, 2133 .atomic_destroy_state = intel_plane_destroy_state, 2134 .format_mod_supported = skl_plane_format_mod_supported, 2135 }; 2136 2137 static const struct drm_plane_funcs gen12_plane_funcs = { 2138 .update_plane = drm_atomic_helper_update_plane, 2139 .disable_plane = drm_atomic_helper_disable_plane, 2140 .destroy = intel_plane_destroy, 2141 .atomic_duplicate_state = intel_plane_duplicate_state, 2142 .atomic_destroy_state = intel_plane_destroy_state, 2143 .format_mod_supported = gen12_plane_format_mod_supported, 2144 }; 2145 2146 static void 2147 skl_plane_enable_flip_done(struct intel_plane *plane) 2148 { 2149 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2150 enum pipe pipe = plane->pipe; 2151 2152 spin_lock_irq(&i915->irq_lock); 2153 bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); 2154 spin_unlock_irq(&i915->irq_lock); 2155 } 2156 2157 static void 2158 skl_plane_disable_flip_done(struct intel_plane *plane) 2159 { 2160 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2161 enum pipe pipe = plane->pipe; 2162 2163 spin_lock_irq(&i915->irq_lock); 2164 bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); 2165 spin_unlock_irq(&i915->irq_lock); 2166 } 2167 2168 static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, 2169 enum pipe pipe, enum plane_id plane_id) 2170 { 2171 /* Wa_14017240301 */ 2172 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 2173 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) 2174 return false; 2175 2176 /* Wa_22011186057 */ 2177 if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) 2178 return false; 2179 2180 if (DISPLAY_VER(i915) >= 11) 2181 return true; 2182 2183 if (IS_GEMINILAKE(i915)) 2184 return pipe != PIPE_C; 2185 2186 return pipe != PIPE_C && 2187 (plane_id == PLANE_PRIMARY || 2188 plane_id == PLANE_SPRITE0); 2189 } 2190 2191 static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, 2192 enum plane_id plane_id) 2193 { 2194 if (DISPLAY_VER(i915) < 12) 2195 return false; 2196 2197 /* Wa_14010477008 */ 2198 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || 2199 (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0))) 2200 return false; 2201 2202 /* Wa_22011186057 */ 2203 if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) 2204 return false; 2205 2206 /* Wa_14013215631 */ 2207 if (IS_DG2_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) 2208 return false; 2209 2210 return plane_id < PLANE_SPRITE4; 2211 } 2212 2213 static u8 skl_get_plane_caps(struct drm_i915_private *i915, 2214 enum pipe pipe, enum plane_id plane_id) 2215 { 2216 u8 caps = INTEL_PLANE_CAP_TILING_X; 2217 2218 if (DISPLAY_VER(i915) < 13 || IS_ALDERLAKE_P(i915)) 2219 caps |= INTEL_PLANE_CAP_TILING_Y; 2220 if (DISPLAY_VER(i915) < 12) 2221 caps |= INTEL_PLANE_CAP_TILING_Yf; 2222 if (HAS_4TILE(i915)) 2223 caps |= INTEL_PLANE_CAP_TILING_4; 2224 2225 if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) { 2226 caps |= INTEL_PLANE_CAP_CCS_RC; 2227 if (DISPLAY_VER(i915) >= 12) 2228 caps |= INTEL_PLANE_CAP_CCS_RC_CC; 2229 } 2230 2231 if (gen12_plane_has_mc_ccs(i915, plane_id)) 2232 caps |= INTEL_PLANE_CAP_CCS_MC; 2233 2234 return caps; 2235 } 2236 2237 struct intel_plane * 2238 skl_universal_plane_create(struct drm_i915_private *dev_priv, 2239 enum pipe pipe, enum plane_id plane_id) 2240 { 2241 const struct drm_plane_funcs *plane_funcs; 2242 struct intel_plane *plane; 2243 enum drm_plane_type plane_type; 2244 unsigned int supported_rotations; 2245 unsigned int supported_csc; 2246 const u64 *modifiers; 2247 const u32 *formats; 2248 int num_formats; 2249 int ret; 2250 2251 plane = intel_plane_alloc(); 2252 if (IS_ERR(plane)) 2253 return plane; 2254 2255 plane->pipe = pipe; 2256 plane->id = plane_id; 2257 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id); 2258 2259 intel_fbc_add_plane(skl_plane_fbc(dev_priv, pipe, plane_id), plane); 2260 2261 if (DISPLAY_VER(dev_priv) >= 11) { 2262 plane->min_width = icl_plane_min_width; 2263 if (icl_is_hdr_plane(dev_priv, plane_id)) 2264 plane->max_width = icl_hdr_plane_max_width; 2265 else 2266 plane->max_width = icl_sdr_plane_max_width; 2267 plane->max_height = icl_plane_max_height; 2268 plane->min_cdclk = icl_plane_min_cdclk; 2269 } else if (DISPLAY_VER(dev_priv) >= 10) { 2270 plane->max_width = glk_plane_max_width; 2271 plane->max_height = skl_plane_max_height; 2272 plane->min_cdclk = glk_plane_min_cdclk; 2273 } else { 2274 plane->max_width = skl_plane_max_width; 2275 plane->max_height = skl_plane_max_height; 2276 plane->min_cdclk = skl_plane_min_cdclk; 2277 } 2278 2279 plane->max_stride = skl_plane_max_stride; 2280 if (DISPLAY_VER(dev_priv) >= 11) { 2281 plane->update_noarm = icl_plane_update_noarm; 2282 plane->update_arm = icl_plane_update_arm; 2283 plane->disable_arm = icl_plane_disable_arm; 2284 } else { 2285 plane->update_noarm = skl_plane_update_noarm; 2286 plane->update_arm = skl_plane_update_arm; 2287 plane->disable_arm = skl_plane_disable_arm; 2288 } 2289 plane->get_hw_state = skl_plane_get_hw_state; 2290 plane->check_plane = skl_plane_check; 2291 2292 if (plane_id == PLANE_PRIMARY) { 2293 plane->need_async_flip_disable_wa = IS_DISPLAY_VER(dev_priv, 2294 9, 10); 2295 plane->async_flip = skl_plane_async_flip; 2296 plane->enable_flip_done = skl_plane_enable_flip_done; 2297 plane->disable_flip_done = skl_plane_disable_flip_done; 2298 } 2299 2300 if (DISPLAY_VER(dev_priv) >= 11) 2301 formats = icl_get_plane_formats(dev_priv, pipe, 2302 plane_id, &num_formats); 2303 else if (DISPLAY_VER(dev_priv) >= 10) 2304 formats = glk_get_plane_formats(dev_priv, pipe, 2305 plane_id, &num_formats); 2306 else 2307 formats = skl_get_plane_formats(dev_priv, pipe, 2308 plane_id, &num_formats); 2309 2310 if (DISPLAY_VER(dev_priv) >= 12) 2311 plane_funcs = &gen12_plane_funcs; 2312 else 2313 plane_funcs = &skl_plane_funcs; 2314 2315 if (plane_id == PLANE_PRIMARY) 2316 plane_type = DRM_PLANE_TYPE_PRIMARY; 2317 else 2318 plane_type = DRM_PLANE_TYPE_OVERLAY; 2319 2320 modifiers = intel_fb_plane_get_modifiers(dev_priv, 2321 skl_get_plane_caps(dev_priv, pipe, plane_id)); 2322 2323 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 2324 0, plane_funcs, 2325 formats, num_formats, modifiers, 2326 plane_type, 2327 "plane %d%c", plane_id + 1, 2328 pipe_name(pipe)); 2329 2330 kfree(modifiers); 2331 2332 if (ret) 2333 goto fail; 2334 2335 if (DISPLAY_VER(dev_priv) >= 13) 2336 supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 2337 else 2338 supported_rotations = 2339 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 2340 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 2341 2342 if (DISPLAY_VER(dev_priv) >= 11) 2343 supported_rotations |= DRM_MODE_REFLECT_X; 2344 2345 drm_plane_create_rotation_property(&plane->base, 2346 DRM_MODE_ROTATE_0, 2347 supported_rotations); 2348 2349 supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709); 2350 2351 if (DISPLAY_VER(dev_priv) >= 10) 2352 supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020); 2353 2354 drm_plane_create_color_properties(&plane->base, 2355 supported_csc, 2356 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 2357 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 2358 DRM_COLOR_YCBCR_BT709, 2359 DRM_COLOR_YCBCR_LIMITED_RANGE); 2360 2361 drm_plane_create_alpha_property(&plane->base); 2362 drm_plane_create_blend_mode_property(&plane->base, 2363 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 2364 BIT(DRM_MODE_BLEND_PREMULTI) | 2365 BIT(DRM_MODE_BLEND_COVERAGE)); 2366 2367 drm_plane_create_zpos_immutable_property(&plane->base, plane_id); 2368 2369 if (DISPLAY_VER(dev_priv) >= 12) 2370 drm_plane_enable_fb_damage_clips(&plane->base); 2371 2372 if (DISPLAY_VER(dev_priv) >= 11) 2373 drm_plane_create_scaling_filter_property(&plane->base, 2374 BIT(DRM_SCALING_FILTER_DEFAULT) | 2375 BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); 2376 2377 intel_plane_helper_add(plane); 2378 2379 return plane; 2380 2381 fail: 2382 intel_plane_free(plane); 2383 2384 return ERR_PTR(ret); 2385 } 2386 2387 void 2388 skl_get_initial_plane_config(struct intel_crtc *crtc, 2389 struct intel_initial_plane_config *plane_config) 2390 { 2391 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 2392 struct drm_device *dev = crtc->base.dev; 2393 struct drm_i915_private *dev_priv = to_i915(dev); 2394 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 2395 enum plane_id plane_id = plane->id; 2396 enum pipe pipe; 2397 u32 val, base, offset, stride_mult, tiling, alpha; 2398 int fourcc, pixel_format; 2399 unsigned int aligned_height; 2400 struct drm_framebuffer *fb; 2401 struct intel_framebuffer *intel_fb; 2402 static_assert(PLANE_CTL_TILED_YF == PLANE_CTL_TILED_4); 2403 2404 if (!plane->get_hw_state(plane, &pipe)) 2405 return; 2406 2407 drm_WARN_ON(dev, pipe != crtc->pipe); 2408 2409 if (crtc_state->bigjoiner_pipes) { 2410 drm_dbg_kms(&dev_priv->drm, 2411 "Unsupported bigjoiner configuration for initial FB\n"); 2412 return; 2413 } 2414 2415 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 2416 if (!intel_fb) { 2417 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); 2418 return; 2419 } 2420 2421 fb = &intel_fb->base; 2422 2423 fb->dev = dev; 2424 2425 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id)); 2426 2427 if (DISPLAY_VER(dev_priv) >= 11) 2428 pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL; 2429 else 2430 pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL; 2431 2432 if (DISPLAY_VER(dev_priv) >= 10) { 2433 u32 color_ctl; 2434 2435 color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id)); 2436 alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl); 2437 } else { 2438 alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val); 2439 } 2440 2441 fourcc = skl_format_to_fourcc(pixel_format, 2442 val & PLANE_CTL_ORDER_RGBX, alpha); 2443 fb->format = drm_format_info(fourcc); 2444 2445 tiling = val & PLANE_CTL_TILED_MASK; 2446 switch (tiling) { 2447 case PLANE_CTL_TILED_LINEAR: 2448 fb->modifier = DRM_FORMAT_MOD_LINEAR; 2449 break; 2450 case PLANE_CTL_TILED_X: 2451 plane_config->tiling = I915_TILING_X; 2452 fb->modifier = I915_FORMAT_MOD_X_TILED; 2453 break; 2454 case PLANE_CTL_TILED_Y: 2455 plane_config->tiling = I915_TILING_Y; 2456 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2457 if (DISPLAY_VER(dev_priv) >= 14) 2458 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS; 2459 else if (DISPLAY_VER(dev_priv) >= 12) 2460 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS; 2461 else 2462 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; 2463 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) 2464 if (DISPLAY_VER(dev_priv) >= 14) 2465 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS; 2466 else 2467 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; 2468 else 2469 fb->modifier = I915_FORMAT_MOD_Y_TILED; 2470 break; 2471 case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */ 2472 if (HAS_4TILE(dev_priv)) { 2473 u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 2474 PLANE_CTL_CLEAR_COLOR_DISABLE; 2475 2476 if ((val & rc_mask) == rc_mask) 2477 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS; 2478 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) 2479 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS; 2480 else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2481 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC; 2482 else 2483 fb->modifier = I915_FORMAT_MOD_4_TILED; 2484 } else { 2485 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2486 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; 2487 else 2488 fb->modifier = I915_FORMAT_MOD_Yf_TILED; 2489 } 2490 break; 2491 default: 2492 MISSING_CASE(tiling); 2493 goto error; 2494 } 2495 2496 if (!dev_priv->params.enable_dpt && 2497 intel_fb_modifier_uses_dpt(dev_priv, fb->modifier)) { 2498 drm_dbg_kms(&dev_priv->drm, "DPT disabled, skipping initial FB\n"); 2499 goto error; 2500 } 2501 2502 /* 2503 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr 2504 * while i915 HW rotation is clockwise, thats why this swapping. 2505 */ 2506 switch (val & PLANE_CTL_ROTATE_MASK) { 2507 case PLANE_CTL_ROTATE_0: 2508 plane_config->rotation = DRM_MODE_ROTATE_0; 2509 break; 2510 case PLANE_CTL_ROTATE_90: 2511 plane_config->rotation = DRM_MODE_ROTATE_270; 2512 break; 2513 case PLANE_CTL_ROTATE_180: 2514 plane_config->rotation = DRM_MODE_ROTATE_180; 2515 break; 2516 case PLANE_CTL_ROTATE_270: 2517 plane_config->rotation = DRM_MODE_ROTATE_90; 2518 break; 2519 } 2520 2521 if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL) 2522 plane_config->rotation |= DRM_MODE_REFLECT_X; 2523 2524 /* 90/270 degree rotation would require extra work */ 2525 if (drm_rotation_90_or_270(plane_config->rotation)) 2526 goto error; 2527 2528 base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK; 2529 plane_config->base = base; 2530 2531 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id)); 2532 drm_WARN_ON(&dev_priv->drm, offset != 0); 2533 2534 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id)); 2535 fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1; 2536 fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1; 2537 2538 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id)); 2539 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0); 2540 2541 fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult; 2542 2543 aligned_height = intel_fb_align_height(fb, 0, fb->height); 2544 2545 plane_config->size = fb->pitches[0] * aligned_height; 2546 2547 drm_dbg_kms(&dev_priv->drm, 2548 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 2549 crtc->base.name, plane->base.name, fb->width, fb->height, 2550 fb->format->cpp[0] * 8, base, fb->pitches[0], 2551 plane_config->size); 2552 2553 plane_config->fb = intel_fb; 2554 return; 2555 2556 error: 2557 kfree(intel_fb); 2558 } 2559