1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include "i915_reg.h" 7 #include "intel_de.h" 8 #include "intel_display_types.h" 9 #include "intel_fb.h" 10 #include "skl_scaler.h" 11 #include "skl_universal_plane.h" 12 13 /* 14 * The hardware phase 0.0 refers to the center of the pixel. 15 * We want to start from the top/left edge which is phase 16 * -0.5. That matches how the hardware calculates the scaling 17 * factors (from top-left of the first pixel to bottom-right 18 * of the last pixel, as opposed to the pixel centers). 19 * 20 * For 4:2:0 subsampled chroma planes we obviously have to 21 * adjust that so that the chroma sample position lands in 22 * the right spot. 23 * 24 * Note that for packed YCbCr 4:2:2 formats there is no way to 25 * control chroma siting. The hardware simply replicates the 26 * chroma samples for both of the luma samples, and thus we don't 27 * actually get the expected MPEG2 chroma siting convention :( 28 * The same behaviour is observed on pre-SKL platforms as well. 29 * 30 * Theory behind the formula (note that we ignore sub-pixel 31 * source coordinates): 32 * s = source sample position 33 * d = destination sample position 34 * 35 * Downscaling 4:1: 36 * -0.5 37 * | 0.0 38 * | | 1.5 (initial phase) 39 * | | | 40 * v v v 41 * | s | s | s | s | 42 * | d | 43 * 44 * Upscaling 1:4: 45 * -0.5 46 * | -0.375 (initial phase) 47 * | | 0.0 48 * | | | 49 * v v v 50 * | s | 51 * | d | d | d | d | 52 */ 53 static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited) 54 { 55 int phase = -0x8000; 56 u16 trip = 0; 57 58 if (chroma_cosited) 59 phase += (sub - 1) * 0x8000 / sub; 60 61 phase += scale / (2 * sub); 62 63 /* 64 * Hardware initial phase limited to [-0.5:1.5]. 65 * Since the max hardware scale factor is 3.0, we 66 * should never actually excdeed 1.0 here. 67 */ 68 WARN_ON(phase < -0x8000 || phase > 0x18000); 69 70 if (phase < 0) 71 phase = 0x10000 + phase; 72 else 73 trip = PS_PHASE_TRIP; 74 75 return ((phase >> 2) & PS_PHASE_MASK) | trip; 76 } 77 78 #define SKL_MIN_SRC_W 8 79 #define SKL_MAX_SRC_W 4096 80 #define SKL_MIN_SRC_H 8 81 #define SKL_MAX_SRC_H 4096 82 #define SKL_MIN_DST_W 8 83 #define SKL_MAX_DST_W 4096 84 #define SKL_MIN_DST_H 8 85 #define SKL_MAX_DST_H 4096 86 #define ICL_MAX_SRC_W 5120 87 #define ICL_MAX_SRC_H 4096 88 #define ICL_MAX_DST_W 5120 89 #define ICL_MAX_DST_H 4096 90 #define TGL_MAX_SRC_W 5120 91 #define TGL_MAX_SRC_H 8192 92 #define TGL_MAX_DST_W 8192 93 #define TGL_MAX_DST_H 8192 94 #define MTL_MAX_SRC_W 4096 95 #define MTL_MAX_SRC_H 8192 96 #define MTL_MAX_DST_W 8192 97 #define MTL_MAX_DST_H 8192 98 #define SKL_MIN_YUV_420_SRC_W 16 99 #define SKL_MIN_YUV_420_SRC_H 16 100 101 static int 102 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, 103 unsigned int scaler_user, int *scaler_id, 104 int src_w, int src_h, int dst_w, int dst_h, 105 const struct drm_format_info *format, 106 u64 modifier, bool need_scaler) 107 { 108 struct intel_crtc_scaler_state *scaler_state = 109 &crtc_state->scaler_state; 110 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 111 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 112 const struct drm_display_mode *adjusted_mode = 113 &crtc_state->hw.adjusted_mode; 114 int min_src_w, min_src_h, min_dst_w, min_dst_h; 115 int max_src_w, max_src_h, max_dst_w, max_dst_h; 116 117 /* 118 * Src coordinates are already rotated by 270 degrees for 119 * the 90/270 degree plane rotation cases (to match the 120 * GTT mapping), hence no need to account for rotation here. 121 */ 122 if (src_w != dst_w || src_h != dst_h) 123 need_scaler = true; 124 125 /* 126 * Scaling/fitting not supported in IF-ID mode in GEN9+ 127 * TODO: Interlace fetch mode doesn't support YUV420 planar formats. 128 * Once NV12 is enabled, handle it here while allocating scaler 129 * for NV12. 130 */ 131 if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable && 132 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 133 drm_dbg_kms(&dev_priv->drm, 134 "Pipe/Plane scaling not supported with IF-ID mode\n"); 135 return -EINVAL; 136 } 137 138 /* 139 * if plane is being disabled or scaler is no more required or force detach 140 * - free scaler binded to this plane/crtc 141 * - in order to do this, update crtc->scaler_usage 142 * 143 * Here scaler state in crtc_state is set free so that 144 * scaler can be assigned to other user. Actual register 145 * update to free the scaler is done in plane/panel-fit programming. 146 * For this purpose crtc/plane_state->scaler_id isn't reset here. 147 */ 148 if (force_detach || !need_scaler) { 149 if (*scaler_id >= 0) { 150 scaler_state->scaler_users &= ~(1 << scaler_user); 151 scaler_state->scalers[*scaler_id].in_use = 0; 152 153 drm_dbg_kms(&dev_priv->drm, 154 "scaler_user index %u.%u: " 155 "Staged freeing scaler id %d scaler_users = 0x%x\n", 156 crtc->pipe, scaler_user, *scaler_id, 157 scaler_state->scaler_users); 158 *scaler_id = -1; 159 } 160 return 0; 161 } 162 163 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) && 164 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { 165 drm_dbg_kms(&dev_priv->drm, 166 "Planar YUV: src dimensions not met\n"); 167 return -EINVAL; 168 } 169 170 min_src_w = SKL_MIN_SRC_W; 171 min_src_h = SKL_MIN_SRC_H; 172 min_dst_w = SKL_MIN_DST_W; 173 min_dst_h = SKL_MIN_DST_H; 174 175 if (DISPLAY_VER(dev_priv) < 11) { 176 max_src_w = SKL_MAX_SRC_W; 177 max_src_h = SKL_MAX_SRC_H; 178 max_dst_w = SKL_MAX_DST_W; 179 max_dst_h = SKL_MAX_DST_H; 180 } else if (DISPLAY_VER(dev_priv) < 12) { 181 max_src_w = ICL_MAX_SRC_W; 182 max_src_h = ICL_MAX_SRC_H; 183 max_dst_w = ICL_MAX_DST_W; 184 max_dst_h = ICL_MAX_DST_H; 185 } else if (DISPLAY_VER(dev_priv) < 14) { 186 max_src_w = TGL_MAX_SRC_W; 187 max_src_h = TGL_MAX_SRC_H; 188 max_dst_w = TGL_MAX_DST_W; 189 max_dst_h = TGL_MAX_DST_H; 190 } else { 191 max_src_w = MTL_MAX_SRC_W; 192 max_src_h = MTL_MAX_SRC_H; 193 max_dst_w = MTL_MAX_DST_W; 194 max_dst_h = MTL_MAX_DST_H; 195 } 196 197 /* range checks */ 198 if (src_w < min_src_w || src_h < min_src_h || 199 dst_w < min_dst_w || dst_h < min_dst_h || 200 src_w > max_src_w || src_h > max_src_h || 201 dst_w > max_dst_w || dst_h > max_dst_h) { 202 drm_dbg_kms(&dev_priv->drm, 203 "scaler_user index %u.%u: src %ux%u dst %ux%u " 204 "size is out of scaler range\n", 205 crtc->pipe, scaler_user, src_w, src_h, 206 dst_w, dst_h); 207 return -EINVAL; 208 } 209 210 /* mark this plane as a scaler user in crtc_state */ 211 scaler_state->scaler_users |= (1 << scaler_user); 212 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: " 213 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", 214 crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, 215 scaler_state->scaler_users); 216 217 return 0; 218 } 219 220 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) 221 { 222 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 223 int width, height; 224 225 if (crtc_state->pch_pfit.enabled) { 226 width = drm_rect_width(&crtc_state->pch_pfit.dst); 227 height = drm_rect_height(&crtc_state->pch_pfit.dst); 228 } else { 229 width = pipe_mode->crtc_hdisplay; 230 height = pipe_mode->crtc_vdisplay; 231 } 232 return skl_update_scaler(crtc_state, !crtc_state->hw.active, 233 SKL_CRTC_INDEX, 234 &crtc_state->scaler_state.scaler_id, 235 drm_rect_width(&crtc_state->pipe_src), 236 drm_rect_height(&crtc_state->pipe_src), 237 width, height, NULL, 0, 238 crtc_state->pch_pfit.enabled); 239 } 240 241 /** 242 * skl_update_scaler_plane - Stages update to scaler state for a given plane. 243 * @crtc_state: crtc's scaler state 244 * @plane_state: atomic plane state to update 245 * 246 * Return 247 * 0 - scaler_usage updated successfully 248 * error - requested scaling cannot be supported or other error condition 249 */ 250 int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, 251 struct intel_plane_state *plane_state) 252 { 253 struct intel_plane *intel_plane = 254 to_intel_plane(plane_state->uapi.plane); 255 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); 256 struct drm_framebuffer *fb = plane_state->hw.fb; 257 int ret; 258 bool force_detach = !fb || !plane_state->uapi.visible; 259 bool need_scaler = false; 260 261 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */ 262 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) && 263 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 264 need_scaler = true; 265 266 ret = skl_update_scaler(crtc_state, force_detach, 267 drm_plane_index(&intel_plane->base), 268 &plane_state->scaler_id, 269 drm_rect_width(&plane_state->uapi.src) >> 16, 270 drm_rect_height(&plane_state->uapi.src) >> 16, 271 drm_rect_width(&plane_state->uapi.dst), 272 drm_rect_height(&plane_state->uapi.dst), 273 fb ? fb->format : NULL, 274 fb ? fb->modifier : 0, 275 need_scaler); 276 277 if (ret || plane_state->scaler_id < 0) 278 return ret; 279 280 /* check colorkey */ 281 if (plane_state->ckey.flags) { 282 drm_dbg_kms(&dev_priv->drm, 283 "[PLANE:%d:%s] scaling with color key not allowed", 284 intel_plane->base.base.id, 285 intel_plane->base.name); 286 return -EINVAL; 287 } 288 289 /* Check src format */ 290 switch (fb->format->format) { 291 case DRM_FORMAT_RGB565: 292 case DRM_FORMAT_XBGR8888: 293 case DRM_FORMAT_XRGB8888: 294 case DRM_FORMAT_ABGR8888: 295 case DRM_FORMAT_ARGB8888: 296 case DRM_FORMAT_XRGB2101010: 297 case DRM_FORMAT_XBGR2101010: 298 case DRM_FORMAT_ARGB2101010: 299 case DRM_FORMAT_ABGR2101010: 300 case DRM_FORMAT_YUYV: 301 case DRM_FORMAT_YVYU: 302 case DRM_FORMAT_UYVY: 303 case DRM_FORMAT_VYUY: 304 case DRM_FORMAT_NV12: 305 case DRM_FORMAT_XYUV8888: 306 case DRM_FORMAT_P010: 307 case DRM_FORMAT_P012: 308 case DRM_FORMAT_P016: 309 case DRM_FORMAT_Y210: 310 case DRM_FORMAT_Y212: 311 case DRM_FORMAT_Y216: 312 case DRM_FORMAT_XVYU2101010: 313 case DRM_FORMAT_XVYU12_16161616: 314 case DRM_FORMAT_XVYU16161616: 315 break; 316 case DRM_FORMAT_XBGR16161616F: 317 case DRM_FORMAT_ABGR16161616F: 318 case DRM_FORMAT_XRGB16161616F: 319 case DRM_FORMAT_ARGB16161616F: 320 if (DISPLAY_VER(dev_priv) >= 11) 321 break; 322 fallthrough; 323 default: 324 drm_dbg_kms(&dev_priv->drm, 325 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", 326 intel_plane->base.base.id, intel_plane->base.name, 327 fb->base.id, fb->format->format); 328 return -EINVAL; 329 } 330 331 return 0; 332 } 333 334 static int glk_coef_tap(int i) 335 { 336 return i % 7; 337 } 338 339 static u16 glk_nearest_filter_coef(int t) 340 { 341 return t == 3 ? 0x0800 : 0x3000; 342 } 343 344 /* 345 * Theory behind setting nearest-neighbor integer scaling: 346 * 347 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set. 348 * The letter represents the filter tap (D is the center tap) and the number 349 * represents the coefficient set for a phase (0-16). 350 * 351 * +------------+------------------------+------------------------+ 352 * |Index value | Data value coeffient 1 | Data value coeffient 2 | 353 * +------------+------------------------+------------------------+ 354 * | 00h | B0 | A0 | 355 * +------------+------------------------+------------------------+ 356 * | 01h | D0 | C0 | 357 * +------------+------------------------+------------------------+ 358 * | 02h | F0 | E0 | 359 * +------------+------------------------+------------------------+ 360 * | 03h | A1 | G0 | 361 * +------------+------------------------+------------------------+ 362 * | 04h | C1 | B1 | 363 * +------------+------------------------+------------------------+ 364 * | ... | ... | ... | 365 * +------------+------------------------+------------------------+ 366 * | 38h | B16 | A16 | 367 * +------------+------------------------+------------------------+ 368 * | 39h | D16 | C16 | 369 * +------------+------------------------+------------------------+ 370 * | 3Ah | F16 | C16 | 371 * +------------+------------------------+------------------------+ 372 * | 3Bh | Reserved | G16 | 373 * +------------+------------------------+------------------------+ 374 * 375 * To enable nearest-neighbor scaling: program scaler coefficents with 376 * the center tap (Dxx) values set to 1 and all other values set to 0 as per 377 * SCALER_COEFFICIENT_FORMAT 378 * 379 */ 380 381 static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv, 382 enum pipe pipe, int id, int set) 383 { 384 int i; 385 386 intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 387 PS_COEE_INDEX_AUTO_INC); 388 389 for (i = 0; i < 17 * 7; i += 2) { 390 u32 tmp; 391 int t; 392 393 t = glk_coef_tap(i); 394 tmp = glk_nearest_filter_coef(t); 395 396 t = glk_coef_tap(i + 1); 397 tmp |= glk_nearest_filter_coef(t) << 16; 398 399 intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set), 400 tmp); 401 } 402 403 intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0); 404 } 405 406 static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set) 407 { 408 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) { 409 return (PS_FILTER_PROGRAMMED | 410 PS_Y_VERT_FILTER_SELECT(set) | 411 PS_Y_HORZ_FILTER_SELECT(set) | 412 PS_UV_VERT_FILTER_SELECT(set) | 413 PS_UV_HORZ_FILTER_SELECT(set)); 414 } 415 416 return PS_FILTER_MEDIUM; 417 } 418 419 static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe, 420 int id, int set, enum drm_scaling_filter filter) 421 { 422 switch (filter) { 423 case DRM_SCALING_FILTER_DEFAULT: 424 break; 425 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR: 426 glk_program_nearest_filter_coefs(dev_priv, pipe, id, set); 427 break; 428 default: 429 MISSING_CASE(filter); 430 } 431 } 432 433 void skl_pfit_enable(const struct intel_crtc_state *crtc_state) 434 { 435 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 436 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 437 const struct intel_crtc_scaler_state *scaler_state = 438 &crtc_state->scaler_state; 439 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; 440 u16 uv_rgb_hphase, uv_rgb_vphase; 441 enum pipe pipe = crtc->pipe; 442 int width = drm_rect_width(dst); 443 int height = drm_rect_height(dst); 444 int x = dst->x1; 445 int y = dst->y1; 446 int hscale, vscale; 447 struct drm_rect src; 448 int id; 449 u32 ps_ctrl; 450 451 if (!crtc_state->pch_pfit.enabled) 452 return; 453 454 if (drm_WARN_ON(&dev_priv->drm, 455 crtc_state->scaler_state.scaler_id < 0)) 456 return; 457 458 drm_rect_init(&src, 0, 0, 459 drm_rect_width(&crtc_state->pipe_src) << 16, 460 drm_rect_height(&crtc_state->pipe_src) << 16); 461 462 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX); 463 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX); 464 465 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false); 466 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); 467 468 id = scaler_state->scaler_id; 469 470 ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0); 471 ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode; 472 473 skl_scaler_setup_filter(dev_priv, pipe, id, 0, 474 crtc_state->hw.scaling_filter); 475 476 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl); 477 478 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id), 479 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); 480 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id), 481 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); 482 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id), 483 x << 16 | y); 484 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id), 485 width << 16 | height); 486 } 487 488 void 489 skl_program_plane_scaler(struct intel_plane *plane, 490 const struct intel_crtc_state *crtc_state, 491 const struct intel_plane_state *plane_state) 492 { 493 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 494 const struct drm_framebuffer *fb = plane_state->hw.fb; 495 enum pipe pipe = plane->pipe; 496 int scaler_id = plane_state->scaler_id; 497 const struct intel_scaler *scaler = 498 &crtc_state->scaler_state.scalers[scaler_id]; 499 int crtc_x = plane_state->uapi.dst.x1; 500 int crtc_y = plane_state->uapi.dst.y1; 501 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 502 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 503 u16 y_hphase, uv_rgb_hphase; 504 u16 y_vphase, uv_rgb_vphase; 505 int hscale, vscale; 506 u32 ps_ctrl; 507 508 hscale = drm_rect_calc_hscale(&plane_state->uapi.src, 509 &plane_state->uapi.dst, 510 0, INT_MAX); 511 vscale = drm_rect_calc_vscale(&plane_state->uapi.src, 512 &plane_state->uapi.dst, 513 0, INT_MAX); 514 515 /* TODO: handle sub-pixel coordinates */ 516 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 517 !icl_is_hdr_plane(dev_priv, plane->id)) { 518 y_hphase = skl_scaler_calc_phase(1, hscale, false); 519 y_vphase = skl_scaler_calc_phase(1, vscale, false); 520 521 /* MPEG2 chroma siting convention */ 522 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true); 523 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false); 524 } else { 525 /* not used */ 526 y_hphase = 0; 527 y_vphase = 0; 528 529 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false); 530 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); 531 } 532 533 ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0); 534 ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode; 535 536 skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0, 537 plane_state->hw.scaling_filter); 538 539 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); 540 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id), 541 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); 542 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id), 543 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); 544 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id), 545 (crtc_x << 16) | crtc_y); 546 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id), 547 (crtc_w << 16) | crtc_h); 548 } 549 550 static void skl_detach_scaler(struct intel_crtc *crtc, int id) 551 { 552 struct drm_device *dev = crtc->base.dev; 553 struct drm_i915_private *dev_priv = to_i915(dev); 554 555 intel_de_write_fw(dev_priv, SKL_PS_CTRL(crtc->pipe, id), 0); 556 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(crtc->pipe, id), 0); 557 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, id), 0); 558 } 559 560 /* 561 * This function detaches (aka. unbinds) unused scalers in hardware 562 */ 563 void skl_detach_scalers(const struct intel_crtc_state *crtc_state) 564 { 565 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 566 const struct intel_crtc_scaler_state *scaler_state = 567 &crtc_state->scaler_state; 568 int i; 569 570 /* loop through and disable scalers that aren't in use */ 571 for (i = 0; i < crtc->num_scalers; i++) { 572 if (!scaler_state->scalers[i].in_use) 573 skl_detach_scaler(crtc, i); 574 } 575 } 576 577 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state) 578 { 579 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 580 int i; 581 582 for (i = 0; i < crtc->num_scalers; i++) 583 skl_detach_scaler(crtc, i); 584 } 585