1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2021 Intel Corporation
4  */
5 
6 #ifndef __INTEL_WM_TYPES_H__
7 #define __INTEL_WM_TYPES_H__
8 
9 #include <linux/types.h>
10 
11 #include "intel_display_limits.h"
12 
13 enum intel_ddb_partitioning {
14 	INTEL_DDB_PART_1_2,
15 	INTEL_DDB_PART_5_6, /* IVB+ */
16 };
17 
18 struct ilk_wm_values {
19 	u32 wm_pipe[3];
20 	u32 wm_lp[3];
21 	u32 wm_lp_spr[3];
22 	bool enable_fbc_wm;
23 	enum intel_ddb_partitioning partitioning;
24 };
25 
26 struct g4x_pipe_wm {
27 	u16 plane[I915_MAX_PLANES];
28 	u16 fbc;
29 };
30 
31 struct g4x_sr_wm {
32 	u16 plane;
33 	u16 cursor;
34 	u16 fbc;
35 };
36 
37 struct vlv_wm_ddl_values {
38 	u8 plane[I915_MAX_PLANES];
39 };
40 
41 struct vlv_wm_values {
42 	struct g4x_pipe_wm pipe[3];
43 	struct g4x_sr_wm sr;
44 	struct vlv_wm_ddl_values ddl[3];
45 	u8 level;
46 	bool cxsr;
47 };
48 
49 struct g4x_wm_values {
50 	struct g4x_pipe_wm pipe[2];
51 	struct g4x_sr_wm sr;
52 	struct g4x_sr_wm hpll;
53 	bool cxsr;
54 	bool hpll_en;
55 	bool fbc_en;
56 };
57 
58 struct skl_ddb_entry {
59 	u16 start, end;	/* in number of blocks, 'end' is exclusive */
60 };
61 
62 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
63 {
64 	return entry->end - entry->start;
65 }
66 
67 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
68 				       const struct skl_ddb_entry *e2)
69 {
70 	if (e1->start == e2->start && e1->end == e2->end)
71 		return true;
72 
73 	return false;
74 }
75 
76 #endif /* __INTEL_WM_TYPES_H__ */
77