1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2020 Intel Corporation
4  *
5  */
6 
7 #include "i915_drv.h"
8 #include "i915_reg.h"
9 #include "intel_de.h"
10 #include "intel_display_types.h"
11 #include "intel_vrr.h"
12 
13 bool intel_vrr_is_capable(struct intel_connector *connector)
14 {
15 	const struct drm_display_info *info = &connector->base.display_info;
16 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
17 	struct intel_dp *intel_dp;
18 
19 	/*
20 	 * DP Sink is capable of VRR video timings if
21 	 * Ignore MSA bit is set in DPCD.
22 	 * EDID monitor range also should be atleast 10 for reasonable
23 	 * Adaptive Sync or Variable Refresh Rate end user experience.
24 	 */
25 	switch (connector->base.connector_type) {
26 	case DRM_MODE_CONNECTOR_eDP:
27 		if (!connector->panel.vbt.vrr)
28 			return false;
29 		fallthrough;
30 	case DRM_MODE_CONNECTOR_DisplayPort:
31 		intel_dp = intel_attached_dp(connector);
32 
33 		if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))
34 			return false;
35 
36 		break;
37 	default:
38 		return false;
39 	}
40 
41 	return HAS_VRR(i915) &&
42 		info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
43 }
44 
45 void
46 intel_vrr_check_modeset(struct intel_atomic_state *state)
47 {
48 	int i;
49 	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
50 	struct intel_crtc *crtc;
51 
52 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
53 					    new_crtc_state, i) {
54 		if (new_crtc_state->uapi.vrr_enabled !=
55 		    old_crtc_state->uapi.vrr_enabled)
56 			new_crtc_state->uapi.mode_changed = true;
57 	}
58 }
59 
60 /*
61  * Without VRR registers get latched at:
62  *  vblank_start
63  *
64  * With VRR the earliest registers can get latched is:
65  *  intel_vrr_vmin_vblank_start(), which if we want to maintain
66  *  the correct min vtotal is >=vblank_start+1
67  *
68  * The latest point registers can get latched is the vmax decision boundary:
69  *  intel_vrr_vmax_vblank_start()
70  *
71  * Between those two points the vblank exit starts (and hence registers get
72  * latched) ASAP after a push is sent.
73  *
74  * framestart_delay is programmable 1-4.
75  */
76 static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
77 {
78 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
79 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
80 
81 	if (DISPLAY_VER(i915) >= 13)
82 		return crtc_state->vrr.guardband;
83 	else
84 		/* The hw imposes the extra scanline before frame start */
85 		return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1;
86 }
87 
88 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
89 {
90 	/* Min vblank actually determined by flipline that is always >=vmin+1 */
91 	return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state);
92 }
93 
94 int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
95 {
96 	return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
97 }
98 
99 void
100 intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
101 			 struct drm_connector_state *conn_state)
102 {
103 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
104 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
105 	struct intel_connector *connector =
106 		to_intel_connector(conn_state->connector);
107 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
108 	const struct drm_display_info *info = &connector->base.display_info;
109 	int vmin, vmax;
110 
111 	if (!intel_vrr_is_capable(connector))
112 		return;
113 
114 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
115 		return;
116 
117 	if (!crtc_state->uapi.vrr_enabled)
118 		return;
119 
120 	vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
121 			    adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
122 	vmax = adjusted_mode->crtc_clock * 1000 /
123 		(adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq);
124 
125 	vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal);
126 	vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal);
127 
128 	if (vmin >= vmax)
129 		return;
130 
131 	/*
132 	 * flipline determines the min vblank length the hardware will
133 	 * generate, and flipline>=vmin+1, hence we reduce vmin by one
134 	 * to make sure we can get the actual min vblank length.
135 	 */
136 	crtc_state->vrr.vmin = vmin - 1;
137 	crtc_state->vrr.vmax = vmax;
138 	crtc_state->vrr.enable = true;
139 
140 	crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
141 
142 	/*
143 	 * For XE_LPD+, we use guardband and pipeline override
144 	 * is deprecated.
145 	 */
146 	if (DISPLAY_VER(i915) >= 13) {
147 		crtc_state->vrr.guardband =
148 			crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start;
149 	} else {
150 		crtc_state->vrr.pipeline_full =
151 			min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
152 			    crtc_state->framestart_delay - 1);
153 	}
154 
155 	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
156 }
157 
158 static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
159 {
160 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
161 
162 	if (DISPLAY_VER(i915) >= 13)
163 		return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
164 			XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
165 	else
166 		return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
167 			VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
168 			VRR_CTL_PIPELINE_FULL_OVERRIDE;
169 }
170 
171 void intel_vrr_enable(struct intel_encoder *encoder,
172 		      const struct intel_crtc_state *crtc_state)
173 {
174 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
175 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
176 
177 	if (!crtc_state->vrr.enable)
178 		return;
179 
180 	intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
181 	intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
182 	intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
183 	intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
184 	intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
185 
186 	intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
187 		       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
188 }
189 
190 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
191 {
192 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
193 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
194 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
195 
196 	if (!crtc_state->vrr.enable)
197 		return;
198 
199 	intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder),
200 		       TRANS_PUSH_EN | TRANS_PUSH_SEND);
201 }
202 
203 bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)
204 {
205 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
206 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
207 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
208 
209 	if (!crtc_state->vrr.enable)
210 		return false;
211 
212 	return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND;
213 }
214 
215 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
216 {
217 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
218 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
219 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
220 
221 	if (!old_crtc_state->vrr.enable)
222 		return;
223 
224 	intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
225 		       trans_vrr_ctl(old_crtc_state));
226 	intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(cpu_transcoder),
227 				VRR_STATUS_VRR_EN_LIVE, 1000);
228 
229 	intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0);
230 	intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0);
231 }
232 
233 void intel_vrr_get_config(struct intel_crtc *crtc,
234 			  struct intel_crtc_state *crtc_state)
235 {
236 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
237 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
238 	u32 trans_vrr_ctl;
239 
240 	trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
241 	crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
242 	if (!crtc_state->vrr.enable)
243 		return;
244 
245 	if (DISPLAY_VER(dev_priv) >= 13)
246 		crtc_state->vrr.guardband =
247 			REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
248 	else
249 		if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
250 			crtc_state->vrr.pipeline_full =
251 				REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
252 	if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN)
253 		crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
254 	crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
255 	crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
256 
257 	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
258 }
259