1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 */ 6 7 #include "i915_drv.h" 8 #include "intel_de.h" 9 #include "intel_display_types.h" 10 #include "intel_vrr.h" 11 12 bool intel_vrr_is_capable(struct intel_connector *connector) 13 { 14 const struct drm_display_info *info = &connector->base.display_info; 15 struct drm_i915_private *i915 = to_i915(connector->base.dev); 16 struct intel_dp *intel_dp; 17 18 /* 19 * DP Sink is capable of VRR video timings if 20 * Ignore MSA bit is set in DPCD. 21 * EDID monitor range also should be atleast 10 for reasonable 22 * Adaptive Sync or Variable Refresh Rate end user experience. 23 */ 24 switch (connector->base.connector_type) { 25 case DRM_MODE_CONNECTOR_eDP: 26 if (!connector->panel.vbt.vrr) 27 return false; 28 fallthrough; 29 case DRM_MODE_CONNECTOR_DisplayPort: 30 intel_dp = intel_attached_dp(connector); 31 32 if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd)) 33 return false; 34 35 break; 36 default: 37 return false; 38 } 39 40 return HAS_VRR(i915) && 41 info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; 42 } 43 44 void 45 intel_vrr_check_modeset(struct intel_atomic_state *state) 46 { 47 int i; 48 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 49 struct intel_crtc *crtc; 50 51 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 52 new_crtc_state, i) { 53 if (new_crtc_state->uapi.vrr_enabled != 54 old_crtc_state->uapi.vrr_enabled) 55 new_crtc_state->uapi.mode_changed = true; 56 } 57 } 58 59 /* 60 * Without VRR registers get latched at: 61 * vblank_start 62 * 63 * With VRR the earliest registers can get latched is: 64 * intel_vrr_vmin_vblank_start(), which if we want to maintain 65 * the correct min vtotal is >=vblank_start+1 66 * 67 * The latest point registers can get latched is the vmax decision boundary: 68 * intel_vrr_vmax_vblank_start() 69 * 70 * Between those two points the vblank exit starts (and hence registers get 71 * latched) ASAP after a push is sent. 72 * 73 * framestart_delay is programmable 1-4. 74 */ 75 static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state) 76 { 77 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 78 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 79 80 /* The hw imposes the extra scanline before frame start */ 81 if (DISPLAY_VER(i915) >= 13) 82 return crtc_state->vrr.guardband + crtc_state->framestart_delay + 1; 83 else 84 return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1; 85 } 86 87 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state) 88 { 89 /* Min vblank actually determined by flipline that is always >=vmin+1 */ 90 return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state); 91 } 92 93 int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state) 94 { 95 return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); 96 } 97 98 void 99 intel_vrr_compute_config(struct intel_crtc_state *crtc_state, 100 struct drm_connector_state *conn_state) 101 { 102 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 103 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 104 struct intel_connector *connector = 105 to_intel_connector(conn_state->connector); 106 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 107 const struct drm_display_info *info = &connector->base.display_info; 108 int vmin, vmax; 109 110 if (!intel_vrr_is_capable(connector)) 111 return; 112 113 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 114 return; 115 116 if (!crtc_state->uapi.vrr_enabled) 117 return; 118 119 vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, 120 adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq); 121 vmax = adjusted_mode->crtc_clock * 1000 / 122 (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq); 123 124 vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal); 125 vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal); 126 127 if (vmin >= vmax) 128 return; 129 130 /* 131 * flipline determines the min vblank length the hardware will 132 * generate, and flipline>=vmin+1, hence we reduce vmin by one 133 * to make sure we can get the actual min vblank length. 134 */ 135 crtc_state->vrr.vmin = vmin - 1; 136 crtc_state->vrr.vmax = vmax; 137 crtc_state->vrr.enable = true; 138 139 crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; 140 141 /* 142 * For XE_LPD+, we use guardband and pipeline override 143 * is deprecated. 144 */ 145 if (DISPLAY_VER(i915) >= 13) { 146 /* 147 * FIXME: Subtract Window2 delay from below value. 148 * 149 * Window2 specifies time required to program DSB (Window2) in 150 * number of scan lines. Assuming 0 for no DSB. 151 */ 152 crtc_state->vrr.guardband = 153 crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay; 154 } else { 155 /* 156 * FIXME: s/4/framestart_delay/ to get consistent 157 * earliest/latest points for register latching regardless 158 * of the framestart_delay used? 159 * 160 * FIXME: this really needs the extra scanline to provide consistent 161 * behaviour for all framestart_delay values. Otherwise with 162 * framestart_delay==4 we will end up extending the min vblank by 163 * one extra line. 164 */ 165 crtc_state->vrr.pipeline_full = 166 min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1); 167 } 168 169 crtc_state->mode_flags |= I915_MODE_FLAG_VRR; 170 } 171 172 void intel_vrr_enable(struct intel_encoder *encoder, 173 const struct intel_crtc_state *crtc_state) 174 { 175 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 176 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 177 u32 trans_vrr_ctl; 178 179 if (!crtc_state->vrr.enable) 180 return; 181 182 if (DISPLAY_VER(dev_priv) >= 13) 183 trans_vrr_ctl = VRR_CTL_VRR_ENABLE | 184 VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN | 185 XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband); 186 else 187 trans_vrr_ctl = VRR_CTL_VRR_ENABLE | 188 VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN | 189 VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) | 190 VRR_CTL_PIPELINE_FULL_OVERRIDE; 191 192 intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1); 193 intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1); 194 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl); 195 intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1); 196 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); 197 } 198 199 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) 200 { 201 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 202 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 203 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 204 205 if (!crtc_state->vrr.enable) 206 return; 207 208 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 209 TRANS_PUSH_EN | TRANS_PUSH_SEND); 210 } 211 212 bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) 213 { 214 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 215 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 216 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 217 218 if (!crtc_state->vrr.enable) 219 return false; 220 221 return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND; 222 } 223 224 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) 225 { 226 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 227 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 228 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 229 230 if (!old_crtc_state->vrr.enable) 231 return; 232 233 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0); 234 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0); 235 } 236 237 void intel_vrr_get_config(struct intel_crtc *crtc, 238 struct intel_crtc_state *crtc_state) 239 { 240 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 241 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 242 u32 trans_vrr_ctl; 243 244 trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); 245 crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; 246 if (!crtc_state->vrr.enable) 247 return; 248 249 if (DISPLAY_VER(dev_priv) >= 13) 250 crtc_state->vrr.guardband = 251 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); 252 else 253 if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE) 254 crtc_state->vrr.pipeline_full = 255 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl); 256 if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) 257 crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1; 258 crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1; 259 crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; 260 261 crtc_state->mode_flags |= I915_MODE_FLAG_VRR; 262 } 263