1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 */ 6 7 #include "i915_drv.h" 8 #include "i915_reg.h" 9 #include "intel_de.h" 10 #include "intel_display_types.h" 11 #include "intel_vrr.h" 12 13 bool intel_vrr_is_capable(struct intel_connector *connector) 14 { 15 const struct drm_display_info *info = &connector->base.display_info; 16 struct drm_i915_private *i915 = to_i915(connector->base.dev); 17 struct intel_dp *intel_dp; 18 19 /* 20 * DP Sink is capable of VRR video timings if 21 * Ignore MSA bit is set in DPCD. 22 * EDID monitor range also should be atleast 10 for reasonable 23 * Adaptive Sync or Variable Refresh Rate end user experience. 24 */ 25 switch (connector->base.connector_type) { 26 case DRM_MODE_CONNECTOR_eDP: 27 if (!connector->panel.vbt.vrr) 28 return false; 29 fallthrough; 30 case DRM_MODE_CONNECTOR_DisplayPort: 31 intel_dp = intel_attached_dp(connector); 32 33 if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd)) 34 return false; 35 36 break; 37 default: 38 return false; 39 } 40 41 return HAS_VRR(i915) && 42 info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; 43 } 44 45 void 46 intel_vrr_check_modeset(struct intel_atomic_state *state) 47 { 48 int i; 49 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 50 struct intel_crtc *crtc; 51 52 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 53 new_crtc_state, i) { 54 if (new_crtc_state->uapi.vrr_enabled != 55 old_crtc_state->uapi.vrr_enabled) 56 new_crtc_state->uapi.mode_changed = true; 57 } 58 } 59 60 /* 61 * Without VRR registers get latched at: 62 * vblank_start 63 * 64 * With VRR the earliest registers can get latched is: 65 * intel_vrr_vmin_vblank_start(), which if we want to maintain 66 * the correct min vtotal is >=vblank_start+1 67 * 68 * The latest point registers can get latched is the vmax decision boundary: 69 * intel_vrr_vmax_vblank_start() 70 * 71 * Between those two points the vblank exit starts (and hence registers get 72 * latched) ASAP after a push is sent. 73 * 74 * framestart_delay is programmable 1-4. 75 */ 76 static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state) 77 { 78 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 79 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 80 81 /* The hw imposes the extra scanline before frame start */ 82 if (DISPLAY_VER(i915) >= 13) 83 return crtc_state->vrr.guardband + crtc_state->framestart_delay + 1; 84 else 85 return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1; 86 } 87 88 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state) 89 { 90 /* Min vblank actually determined by flipline that is always >=vmin+1 */ 91 return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state); 92 } 93 94 int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state) 95 { 96 return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); 97 } 98 99 void 100 intel_vrr_compute_config(struct intel_crtc_state *crtc_state, 101 struct drm_connector_state *conn_state) 102 { 103 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 104 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 105 struct intel_connector *connector = 106 to_intel_connector(conn_state->connector); 107 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 108 const struct drm_display_info *info = &connector->base.display_info; 109 int vmin, vmax; 110 111 if (!intel_vrr_is_capable(connector)) 112 return; 113 114 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 115 return; 116 117 if (!crtc_state->uapi.vrr_enabled) 118 return; 119 120 vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, 121 adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq); 122 vmax = adjusted_mode->crtc_clock * 1000 / 123 (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq); 124 125 vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal); 126 vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal); 127 128 if (vmin >= vmax) 129 return; 130 131 /* 132 * flipline determines the min vblank length the hardware will 133 * generate, and flipline>=vmin+1, hence we reduce vmin by one 134 * to make sure we can get the actual min vblank length. 135 */ 136 crtc_state->vrr.vmin = vmin - 1; 137 crtc_state->vrr.vmax = vmax; 138 crtc_state->vrr.enable = true; 139 140 crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; 141 142 /* 143 * For XE_LPD+, we use guardband and pipeline override 144 * is deprecated. 145 */ 146 if (DISPLAY_VER(i915) >= 13) { 147 /* 148 * FIXME: Subtract Window2 delay from below value. 149 * 150 * Window2 specifies time required to program DSB (Window2) in 151 * number of scan lines. Assuming 0 for no DSB. 152 */ 153 crtc_state->vrr.guardband = 154 crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay; 155 } else { 156 /* 157 * FIXME: s/4/framestart_delay/ to get consistent 158 * earliest/latest points for register latching regardless 159 * of the framestart_delay used? 160 * 161 * FIXME: this really needs the extra scanline to provide consistent 162 * behaviour for all framestart_delay values. Otherwise with 163 * framestart_delay==4 we will end up extending the min vblank by 164 * one extra line. 165 */ 166 crtc_state->vrr.pipeline_full = 167 min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1); 168 } 169 170 crtc_state->mode_flags |= I915_MODE_FLAG_VRR; 171 } 172 173 void intel_vrr_enable(struct intel_encoder *encoder, 174 const struct intel_crtc_state *crtc_state) 175 { 176 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 177 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 178 u32 trans_vrr_ctl; 179 180 if (!crtc_state->vrr.enable) 181 return; 182 183 if (DISPLAY_VER(dev_priv) >= 13) 184 trans_vrr_ctl = VRR_CTL_VRR_ENABLE | 185 VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN | 186 XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband); 187 else 188 trans_vrr_ctl = VRR_CTL_VRR_ENABLE | 189 VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN | 190 VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) | 191 VRR_CTL_PIPELINE_FULL_OVERRIDE; 192 193 intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1); 194 intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1); 195 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl); 196 intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1); 197 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); 198 } 199 200 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) 201 { 202 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 203 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 204 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 205 206 if (!crtc_state->vrr.enable) 207 return; 208 209 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 210 TRANS_PUSH_EN | TRANS_PUSH_SEND); 211 } 212 213 bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) 214 { 215 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 216 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 217 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 218 219 if (!crtc_state->vrr.enable) 220 return false; 221 222 return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND; 223 } 224 225 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) 226 { 227 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 228 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 229 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 230 231 if (!old_crtc_state->vrr.enable) 232 return; 233 234 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0); 235 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0); 236 } 237 238 void intel_vrr_get_config(struct intel_crtc *crtc, 239 struct intel_crtc_state *crtc_state) 240 { 241 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 242 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 243 u32 trans_vrr_ctl; 244 245 trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); 246 crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; 247 if (!crtc_state->vrr.enable) 248 return; 249 250 if (DISPLAY_VER(dev_priv) >= 13) 251 crtc_state->vrr.guardband = 252 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); 253 else 254 if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE) 255 crtc_state->vrr.pipeline_full = 256 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl); 257 if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) 258 crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1; 259 crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1; 260 crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; 261 262 crtc_state->mode_flags |= I915_MODE_FLAG_VRR; 263 } 264