1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_VDSC_REGS_H__ 7 #define __INTEL_VDSC_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 /* Display Stream Splitter Control */ 12 #define DSS_CTL1 _MMIO(0x67400) 13 #define SPLITTER_ENABLE (1 << 31) 14 #define JOINER_ENABLE (1 << 30) 15 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24) 16 #define DUAL_LINK_MODE_FRONTBACK (0 << 24) 17 #define OVERLAP_PIXELS_MASK (0xf << 16) 18 #define OVERLAP_PIXELS(pixels) ((pixels) << 16) 19 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 20 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 21 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 22 23 #define DSS_CTL2 _MMIO(0x67404) 24 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) 25 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) 26 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 27 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 28 29 #define _ICL_PIPE_DSS_CTL1_PB 0x78200 30 #define _ICL_PIPE_DSS_CTL1_PC 0x78400 31 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 32 _ICL_PIPE_DSS_CTL1_PB, \ 33 _ICL_PIPE_DSS_CTL1_PC) 34 #define BIG_JOINER_ENABLE (1 << 29) 35 #define MASTER_BIG_JOINER_ENABLE (1 << 28) 36 #define VGA_CENTERING_ENABLE (1 << 27) 37 #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25) 38 #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0) 39 #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1) 40 #define UNCOMPRESSED_JOINER_MASTER (1 << 21) 41 #define UNCOMPRESSED_JOINER_SLAVE (1 << 20) 42 43 #define _ICL_PIPE_DSS_CTL2_PB 0x78204 44 #define _ICL_PIPE_DSS_CTL2_PC 0x78404 45 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 46 _ICL_PIPE_DSS_CTL2_PB, \ 47 _ICL_PIPE_DSS_CTL2_PC) 48 49 /* Icelake Display Stream Compression Registers */ 50 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) 51 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) 52 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 53 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 54 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 55 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 56 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 57 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 58 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) 59 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 60 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 61 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 62 #define DSC_ALT_ICH_SEL (1 << 20) 63 #define DSC_VBR_ENABLE (1 << 19) 64 #define DSC_422_ENABLE (1 << 18) 65 #define DSC_COLOR_SPACE_CONVERSION (1 << 17) 66 #define DSC_BLOCK_PREDICTION (1 << 16) 67 #define DSC_LINE_BUF_DEPTH_SHIFT 12 68 #define DSC_BPC_SHIFT 8 69 #define DSC_VER_MIN_SHIFT 4 70 #define DSC_VER_MAJ (0x1 << 0) 71 72 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204) 73 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04) 74 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274 75 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374 76 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474 77 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574 78 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 79 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \ 80 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC) 81 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 82 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \ 83 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC) 84 #define DSC_BPP(bpp) ((bpp) << 0) 85 86 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208) 87 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08) 88 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278 89 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378 90 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478 91 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578 92 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 93 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \ 94 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC) 95 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 96 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \ 97 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC) 98 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16) 99 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0) 100 101 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C) 102 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C) 103 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C 104 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C 105 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C 106 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C 107 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 108 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \ 109 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC) 110 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 111 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \ 112 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC) 113 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16) 114 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0) 115 116 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210) 117 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10) 118 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280 119 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380 120 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480 121 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580 122 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 123 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \ 124 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC) 125 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 126 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \ 127 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC) 128 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16) 129 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0) 130 131 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214) 132 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14) 133 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284 134 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384 135 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484 136 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584 137 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 138 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \ 139 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC) 140 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 141 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \ 142 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC) 143 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16) 144 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0) 145 146 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218) 147 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18) 148 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288 149 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388 150 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488 151 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588 152 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 153 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \ 154 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC) 155 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 156 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \ 157 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC) 158 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24) 159 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16) 160 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8) 161 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0) 162 163 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C) 164 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C) 165 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C 166 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C 167 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C 168 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C 169 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 170 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \ 171 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC) 172 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 173 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \ 174 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC) 175 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16) 176 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0) 177 178 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220) 179 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20) 180 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290 181 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390 182 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490 183 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590 184 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 185 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \ 186 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC) 187 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 188 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \ 189 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC) 190 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) 191 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0) 192 193 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224) 194 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24) 195 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294 196 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394 197 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494 198 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594 199 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 200 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \ 201 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC) 202 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 203 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \ 204 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC) 205 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16) 206 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0) 207 208 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228) 209 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28) 210 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298 211 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398 212 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498 213 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598 214 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 215 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \ 216 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC) 217 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 218 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \ 219 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC) 220 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20) 221 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16) 222 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8) 223 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0) 224 225 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C) 226 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C) 227 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C 228 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C 229 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C 230 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C 231 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 232 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \ 233 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC) 234 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 235 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \ 236 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC) 237 238 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260) 239 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60) 240 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0 241 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0 242 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0 243 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0 244 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 245 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \ 246 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC) 247 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 248 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \ 249 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC) 250 251 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264) 252 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64) 253 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4 254 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4 255 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4 256 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4 257 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 258 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \ 259 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC) 260 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 261 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \ 262 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC) 263 264 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268) 265 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68) 266 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8 267 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8 268 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8 269 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8 270 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 271 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \ 272 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC) 273 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 274 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \ 275 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC) 276 277 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C) 278 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C) 279 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC 280 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC 281 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC 282 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC 283 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 284 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \ 285 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC) 286 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 287 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \ 288 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC) 289 290 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270) 291 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70) 292 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0 293 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0 294 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0 295 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0 296 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 297 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \ 298 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC) 299 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 300 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ 301 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) 302 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) 303 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) 304 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) 305 306 /* Icelake Rate Control Buffer Threshold Registers */ 307 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) 308 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) 309 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30) 310 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4) 311 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254) 312 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4) 313 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354) 314 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4) 315 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454) 316 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4) 317 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554) 318 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4) 319 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 320 _ICL_DSC0_RC_BUF_THRESH_0_PB, \ 321 _ICL_DSC0_RC_BUF_THRESH_0_PC) 322 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 323 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \ 324 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC) 325 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 326 _ICL_DSC1_RC_BUF_THRESH_0_PB, \ 327 _ICL_DSC1_RC_BUF_THRESH_0_PC) 328 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 329 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \ 330 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC) 331 332 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238) 333 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4) 334 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38) 335 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4) 336 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C) 337 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4) 338 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C) 339 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4) 340 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C) 341 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4) 342 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C) 343 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4) 344 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 345 _ICL_DSC0_RC_BUF_THRESH_1_PB, \ 346 _ICL_DSC0_RC_BUF_THRESH_1_PC) 347 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 348 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \ 349 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC) 350 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 351 _ICL_DSC1_RC_BUF_THRESH_1_PB, \ 352 _ICL_DSC1_RC_BUF_THRESH_1_PC) 353 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 354 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ 355 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) 356 357 /* Icelake DSC Rate Control Range Parameter Registers */ 358 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) 359 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) 360 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) 361 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) 362 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) 363 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) 364 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) 365 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) 366 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) 367 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) 368 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) 369 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) 370 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 371 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ 372 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) 373 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 374 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ 375 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) 376 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 377 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ 378 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) 379 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 380 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ 381 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) 382 #define RC_BPG_OFFSET_SHIFT 10 383 #define RC_MAX_QP_SHIFT 5 384 #define RC_MIN_QP_SHIFT 0 385 386 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) 387 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) 388 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) 389 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) 390 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) 391 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) 392 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) 393 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) 394 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) 395 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) 396 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) 397 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) 398 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 399 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ 400 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) 401 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 402 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ 403 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) 404 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 405 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ 406 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) 407 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 408 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ 409 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) 410 411 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) 412 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) 413 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) 414 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) 415 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) 416 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) 417 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) 418 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) 419 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) 420 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) 421 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) 422 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) 423 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 424 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ 425 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) 426 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 427 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ 428 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) 429 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 430 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ 431 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) 432 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 433 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ 434 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) 435 436 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) 437 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) 438 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) 439 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) 440 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) 441 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) 442 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) 443 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) 444 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) 445 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) 446 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) 447 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) 448 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 449 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ 450 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) 451 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 452 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ 453 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) 454 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 455 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ 456 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) 457 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 458 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ 459 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) 460 461 #endif /* __INTEL_VDSC_REGS_H__ */ 462