1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2018 Intel Corporation 4 * 5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com> 6 * Manasi Navare <manasi.d.navare@intel.com> 7 */ 8 #include <linux/limits.h> 9 #include "i915_drv.h" 10 #include "intel_de.h" 11 #include "intel_display_types.h" 12 #include "intel_dsi.h" 13 #include "intel_vdsc.h" 14 #include "intel_qp_tables.h" 15 16 enum ROW_INDEX_BPP { 17 ROW_INDEX_6BPP = 0, 18 ROW_INDEX_8BPP, 19 ROW_INDEX_10BPP, 20 ROW_INDEX_12BPP, 21 ROW_INDEX_15BPP, 22 MAX_ROW_INDEX 23 }; 24 25 enum COLUMN_INDEX_BPC { 26 COLUMN_INDEX_8BPC = 0, 27 COLUMN_INDEX_10BPC, 28 COLUMN_INDEX_12BPC, 29 COLUMN_INDEX_14BPC, 30 COLUMN_INDEX_16BPC, 31 MAX_COLUMN_INDEX 32 }; 33 34 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ 35 static const u16 rc_buf_thresh[] = { 36 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, 37 7744, 7872, 8000, 8064 38 }; 39 40 struct rc_parameters { 41 u16 initial_xmit_delay; 42 u8 first_line_bpg_offset; 43 u16 initial_offset; 44 u8 flatness_min_qp; 45 u8 flatness_max_qp; 46 u8 rc_quant_incr_limit0; 47 u8 rc_quant_incr_limit1; 48 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; 49 }; 50 51 /* 52 * Selected Rate Control Related Parameter Recommended Values 53 * from DSC_v1.11 spec & C Model release: DSC_model_20161212 54 */ 55 static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { 56 { 57 /* 6BPP/8BPC */ 58 { 768, 15, 6144, 3, 13, 11, 11, { 59 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, 60 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, 61 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, 62 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } 63 } 64 }, 65 /* 6BPP/10BPC */ 66 { 768, 15, 6144, 7, 17, 15, 15, { 67 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, 68 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, 69 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, 70 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, 71 { 17, 18, -12 } 72 } 73 }, 74 /* 6BPP/12BPC */ 75 { 768, 15, 6144, 11, 21, 19, 19, { 76 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, 77 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, 78 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, 79 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, 80 { 21, 22, -12 } 81 } 82 }, 83 /* 6BPP/14BPC */ 84 { 768, 15, 6144, 15, 25, 23, 27, { 85 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, 86 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, 87 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, 88 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, 89 { 25, 26, -12 } 90 } 91 }, 92 /* 6BPP/16BPC */ 93 { 768, 15, 6144, 19, 29, 27, 27, { 94 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, 95 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, 96 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, 97 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, 98 { 29, 30, -12 } 99 } 100 }, 101 }, 102 { 103 /* 8BPP/8BPC */ 104 { 512, 12, 6144, 3, 12, 11, 11, { 105 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 106 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 107 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, 108 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 109 } 110 }, 111 /* 8BPP/10BPC */ 112 { 512, 12, 6144, 7, 16, 15, 15, { 113 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, 114 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 115 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 116 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 117 } 118 }, 119 /* 8BPP/12BPC */ 120 { 512, 12, 6144, 11, 20, 19, 19, { 121 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, 122 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 123 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 124 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 125 { 21, 23, -12 } 126 } 127 }, 128 /* 8BPP/14BPC */ 129 { 512, 12, 6144, 15, 24, 23, 23, { 130 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, 131 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 132 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, 133 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, 134 { 24, 25, -12 } 135 } 136 }, 137 /* 8BPP/16BPC */ 138 { 512, 12, 6144, 19, 28, 27, 27, { 139 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, 140 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 141 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, 142 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, 143 { 28, 29, -12 } 144 } 145 }, 146 }, 147 { 148 /* 10BPP/8BPC */ 149 { 410, 15, 5632, 3, 12, 11, 11, { 150 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, 151 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 152 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, 153 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } 154 } 155 }, 156 /* 10BPP/10BPC */ 157 { 410, 15, 5632, 7, 16, 15, 15, { 158 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, 159 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 160 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, 161 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } 162 } 163 }, 164 /* 10BPP/12BPC */ 165 { 410, 15, 5632, 11, 20, 19, 19, { 166 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, 167 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 168 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, 169 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, 170 { 19, 20, -12 } 171 } 172 }, 173 /* 10BPP/14BPC */ 174 { 410, 15, 5632, 15, 24, 23, 23, { 175 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, 176 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 177 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, 178 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, 179 { 23, 24, -12 } 180 } 181 }, 182 /* 10BPP/16BPC */ 183 { 410, 15, 5632, 19, 28, 27, 27, { 184 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, 185 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 186 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, 187 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, 188 { 27, 28, -12 } 189 } 190 }, 191 }, 192 { 193 /* 12BPP/8BPC */ 194 { 341, 15, 2048, 3, 12, 11, 11, { 195 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 196 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 197 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, 198 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 199 } 200 }, 201 /* 12BPP/10BPC */ 202 { 341, 15, 2048, 7, 16, 15, 15, { 203 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, 204 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 205 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 206 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 207 } 208 }, 209 /* 12BPP/12BPC */ 210 { 341, 15, 2048, 11, 20, 19, 19, { 211 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, 212 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 213 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 214 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 215 { 21, 23, -12 } 216 } 217 }, 218 /* 12BPP/14BPC */ 219 { 341, 15, 2048, 15, 24, 23, 23, { 220 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, 221 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 222 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, 223 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, 224 { 22, 23, -12 } 225 } 226 }, 227 /* 12BPP/16BPC */ 228 { 341, 15, 2048, 19, 28, 27, 27, { 229 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, 230 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 231 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, 232 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, 233 { 26, 27, -12 } 234 } 235 }, 236 }, 237 { 238 /* 15BPP/8BPC */ 239 { 273, 15, 2048, 3, 12, 11, 11, { 240 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, 241 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, 242 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, 243 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } 244 } 245 }, 246 /* 15BPP/10BPC */ 247 { 273, 15, 2048, 7, 16, 15, 15, { 248 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, 249 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, 250 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, 251 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } 252 } 253 }, 254 /* 15BPP/12BPC */ 255 { 273, 15, 2048, 11, 20, 19, 19, { 256 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, 257 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, 258 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, 259 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, 260 { 16, 17, -12 } 261 } 262 }, 263 /* 15BPP/14BPC */ 264 { 273, 15, 2048, 15, 24, 23, 23, { 265 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, 266 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, 267 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, 268 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, 269 { 20, 21, -12 } 270 } 271 }, 272 /* 15BPP/16BPC */ 273 { 273, 15, 2048, 19, 28, 27, 27, { 274 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, 275 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, 276 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, 277 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, 278 { 24, 25, -12 } 279 } 280 } 281 } 282 283 }; 284 285 static int get_row_index_for_rc_params(u16 compressed_bpp) 286 { 287 switch (compressed_bpp) { 288 case 6: 289 return ROW_INDEX_6BPP; 290 case 8: 291 return ROW_INDEX_8BPP; 292 case 10: 293 return ROW_INDEX_10BPP; 294 case 12: 295 return ROW_INDEX_12BPP; 296 case 15: 297 return ROW_INDEX_15BPP; 298 default: 299 return -EINVAL; 300 } 301 } 302 303 static int get_column_index_for_rc_params(u8 bits_per_component) 304 { 305 switch (bits_per_component) { 306 case 8: 307 return COLUMN_INDEX_8BPC; 308 case 10: 309 return COLUMN_INDEX_10BPC; 310 case 12: 311 return COLUMN_INDEX_12BPC; 312 case 14: 313 return COLUMN_INDEX_14BPC; 314 case 16: 315 return COLUMN_INDEX_16BPC; 316 default: 317 return -EINVAL; 318 } 319 } 320 321 static const struct rc_parameters *get_rc_params(u16 compressed_bpp, 322 u8 bits_per_component) 323 { 324 int row_index, column_index; 325 326 row_index = get_row_index_for_rc_params(compressed_bpp); 327 if (row_index < 0) 328 return NULL; 329 330 column_index = get_column_index_for_rc_params(bits_per_component); 331 if (column_index < 0) 332 return NULL; 333 334 return &rc_parameters[row_index][column_index]; 335 } 336 337 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) 338 { 339 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 340 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 341 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 342 enum pipe pipe = crtc->pipe; 343 344 if (!INTEL_INFO(i915)->display.has_dsc) 345 return false; 346 347 /* On TGL, DSC is supported on all Pipes */ 348 if (DISPLAY_VER(i915) >= 12) 349 return true; 350 351 if ((DISPLAY_VER(i915) >= 11 || IS_CANNONLAKE(i915)) && (pipe != PIPE_A || (cpu_transcoder == TRANSCODER_EDP || cpu_transcoder == TRANSCODER_DSI_0 || cpu_transcoder == TRANSCODER_DSI_1))) 352 return true; 353 354 return false; 355 } 356 357 static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state) 358 { 359 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 360 const struct drm_i915_private *i915 = to_i915(crtc->base.dev); 361 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 362 363 if (DISPLAY_VER(i915) >= 12) 364 return true; 365 366 if (cpu_transcoder == TRANSCODER_EDP || 367 cpu_transcoder == TRANSCODER_DSI_0 || 368 cpu_transcoder == TRANSCODER_DSI_1) 369 return false; 370 371 /* There's no pipe A DSC engine on ICL */ 372 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); 373 374 return true; 375 } 376 377 static void 378 calculate_rc_params(struct rc_parameters *rc, 379 struct drm_dsc_config *vdsc_cfg) 380 { 381 int bpc = vdsc_cfg->bits_per_component; 382 int bpp = vdsc_cfg->bits_per_pixel >> 4; 383 int ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 }; 384 int ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; 385 int ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; 386 int ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 }; 387 int qp_bpc_modifier = (bpc - 8) * 2; 388 u32 res, buf_i, bpp_i; 389 390 if (vdsc_cfg->slice_height >= 8) 391 rc->first_line_bpg_offset = 392 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100); 393 else 394 rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); 395 396 /* Our hw supports only 444 modes as of today */ 397 if (bpp >= 12) 398 rc->initial_offset = 2048; 399 else if (bpp >= 10) 400 rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); 401 else if (bpp >= 8) 402 rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); 403 else 404 rc->initial_offset = 6144; 405 406 /* initial_xmit_delay = rc_model_size/2/compression_bpp */ 407 rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp); 408 409 rc->flatness_min_qp = 3 + qp_bpc_modifier; 410 rc->flatness_max_qp = 12 + qp_bpc_modifier; 411 412 rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; 413 rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; 414 415 bpp_i = (2 * (bpp - 6)); 416 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { 417 /* Read range_minqp and range_max_qp from qp tables */ 418 rc->rc_range_params[buf_i].range_min_qp = 419 intel_lookup_range_min_qp(bpc, buf_i, bpp_i); 420 rc->rc_range_params[buf_i].range_max_qp = 421 intel_lookup_range_max_qp(bpc, buf_i, bpp_i); 422 423 /* Calculate range_bgp_offset */ 424 if (bpp <= 6) { 425 rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i]; 426 } else if (bpp <= 8) { 427 res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2); 428 rc->rc_range_params[buf_i].range_bpg_offset = 429 ofs_und6[buf_i] + res; 430 } else if (bpp <= 12) { 431 rc->rc_range_params[buf_i].range_bpg_offset = 432 ofs_und8[buf_i]; 433 } else if (bpp <= 15) { 434 res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3); 435 rc->rc_range_params[buf_i].range_bpg_offset = 436 ofs_und12[buf_i] + res; 437 } else { 438 rc->rc_range_params[buf_i].range_bpg_offset = 439 ofs_und15[buf_i]; 440 } 441 } 442 } 443 444 int intel_dsc_compute_params(struct intel_encoder *encoder, 445 struct intel_crtc_state *pipe_config) 446 { 447 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 448 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; 449 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; 450 const struct rc_parameters *rc_params; 451 struct rc_parameters *rc = NULL; 452 u8 i = 0; 453 454 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; 455 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay; 456 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, 457 pipe_config->dsc.slice_count); 458 459 /* Gen 11 does not support YCbCr */ 460 vdsc_cfg->simple_422 = false; 461 /* Gen 11 does not support VBR */ 462 vdsc_cfg->vbr_enable = false; 463 464 /* Gen 11 only supports integral values of bpp */ 465 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; 466 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; 467 468 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 469 /* 470 * six 0s are appended to the lsb of each threshold value 471 * internally in h/w. 472 * Only 8 bits are allowed for programming RcBufThreshold 473 */ 474 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; 475 } 476 477 /* 478 * For 6bpp, RC Buffer threshold 12 and 13 need a different value 479 * as per C Model 480 */ 481 if (compressed_bpp == 6) { 482 vdsc_cfg->rc_buf_thresh[12] = 0x7C; 483 vdsc_cfg->rc_buf_thresh[13] = 0x7D; 484 } 485 486 /* 487 * From XE_LPD onwards we supports compression bpps in steps of 1 488 * upto uncompressed bpp-1, hence add calculations for all the rc 489 * parameters 490 */ 491 if (DISPLAY_VER(dev_priv) >= 13) { 492 rc = kmalloc(sizeof(*rc), GFP_KERNEL); 493 if (!rc) 494 return -ENOMEM; 495 496 calculate_rc_params(rc, vdsc_cfg); 497 rc_params = rc; 498 } else { 499 rc_params = get_rc_params(compressed_bpp, 500 vdsc_cfg->bits_per_component); 501 if (!rc_params) 502 return -EINVAL; 503 } 504 505 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; 506 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay; 507 vdsc_cfg->initial_offset = rc_params->initial_offset; 508 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp; 509 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp; 510 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0; 511 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1; 512 513 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 514 vdsc_cfg->rc_range_params[i].range_min_qp = 515 rc_params->rc_range_params[i].range_min_qp; 516 vdsc_cfg->rc_range_params[i].range_max_qp = 517 rc_params->rc_range_params[i].range_max_qp; 518 /* 519 * Range BPG Offset uses 2's complement and is only a 6 bits. So 520 * mask it to get only 6 bits. 521 */ 522 vdsc_cfg->rc_range_params[i].range_bpg_offset = 523 rc_params->rc_range_params[i].range_bpg_offset & 524 DSC_RANGE_BPG_OFFSET_MASK; 525 } 526 527 /* 528 * BitsPerComponent value determines mux_word_size: 529 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to 530 * 48 bits otherwise 64 531 */ 532 if (vdsc_cfg->bits_per_component <= 10) 533 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; 534 else 535 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; 536 537 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ 538 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / 539 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); 540 541 kfree(rc); 542 543 return 0; 544 } 545 546 enum intel_display_power_domain 547 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) 548 { 549 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 550 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 551 enum pipe pipe = crtc->pipe; 552 553 /* 554 * VDSC/joining uses a separate power well, PW2, and requires 555 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases: 556 * 557 * - ICL eDP/DSI transcoder 558 * - Display version 12 (except RKL) pipe A 559 * 560 * For any other pipe, VDSC/joining uses the power well associated with 561 * the pipe in use. Hence another reference on the pipe power domain 562 * will suffice. (Except no VDSC/joining on ICL pipe A.) 563 */ 564 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A) 565 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 566 else if (is_pipe_dsc(crtc_state)) 567 return POWER_DOMAIN_PIPE(pipe); 568 else 569 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 570 } 571 572 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) 573 { 574 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 575 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 576 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 577 enum pipe pipe = crtc->pipe; 578 u32 pps_val = 0; 579 u32 rc_buf_thresh_dword[4]; 580 u32 rc_range_params_dword[8]; 581 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; 582 int i = 0; 583 584 if (crtc_state->bigjoiner) 585 num_vdsc_instances *= 2; 586 587 /* Populate PICTURE_PARAMETER_SET_0 registers */ 588 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << 589 DSC_VER_MIN_SHIFT | 590 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | 591 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; 592 if (vdsc_cfg->block_pred_enable) 593 pps_val |= DSC_BLOCK_PREDICTION; 594 if (vdsc_cfg->convert_rgb) 595 pps_val |= DSC_COLOR_SPACE_CONVERSION; 596 if (vdsc_cfg->simple_422) 597 pps_val |= DSC_422_ENABLE; 598 if (vdsc_cfg->vbr_enable) 599 pps_val |= DSC_VBR_ENABLE; 600 drm_info(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); 601 if (!is_pipe_dsc(crtc_state)) { 602 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0, 603 pps_val); 604 /* 605 * If 2 VDSC instances are needed, configure PPS for second 606 * VDSC 607 */ 608 if (crtc_state->dsc.dsc_split) 609 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0, 610 pps_val); 611 } else { 612 intel_de_write(dev_priv, 613 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), 614 pps_val); 615 if (crtc_state->dsc.dsc_split) 616 intel_de_write(dev_priv, 617 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), 618 pps_val); 619 } 620 621 /* Populate PICTURE_PARAMETER_SET_1 registers */ 622 pps_val = 0; 623 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); 624 drm_info(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); 625 if (!is_pipe_dsc(crtc_state)) { 626 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1, 627 pps_val); 628 /* 629 * If 2 VDSC instances are needed, configure PPS for second 630 * VDSC 631 */ 632 if (crtc_state->dsc.dsc_split) 633 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1, 634 pps_val); 635 } else { 636 intel_de_write(dev_priv, 637 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), 638 pps_val); 639 if (crtc_state->dsc.dsc_split) 640 intel_de_write(dev_priv, 641 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), 642 pps_val); 643 } 644 645 /* Populate PICTURE_PARAMETER_SET_2 registers */ 646 pps_val = 0; 647 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | 648 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); 649 drm_info(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); 650 if (!is_pipe_dsc(crtc_state)) { 651 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2, 652 pps_val); 653 /* 654 * If 2 VDSC instances are needed, configure PPS for second 655 * VDSC 656 */ 657 if (crtc_state->dsc.dsc_split) 658 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2, 659 pps_val); 660 } else { 661 intel_de_write(dev_priv, 662 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), 663 pps_val); 664 if (crtc_state->dsc.dsc_split) 665 intel_de_write(dev_priv, 666 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), 667 pps_val); 668 } 669 670 /* Populate PICTURE_PARAMETER_SET_3 registers */ 671 pps_val = 0; 672 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | 673 DSC_SLICE_WIDTH(vdsc_cfg->slice_width); 674 drm_info(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); 675 if (!is_pipe_dsc(crtc_state)) { 676 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3, 677 pps_val); 678 /* 679 * If 2 VDSC instances are needed, configure PPS for second 680 * VDSC 681 */ 682 if (crtc_state->dsc.dsc_split) 683 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3, 684 pps_val); 685 } else { 686 intel_de_write(dev_priv, 687 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), 688 pps_val); 689 if (crtc_state->dsc.dsc_split) 690 intel_de_write(dev_priv, 691 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), 692 pps_val); 693 } 694 695 /* Populate PICTURE_PARAMETER_SET_4 registers */ 696 pps_val = 0; 697 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | 698 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); 699 drm_info(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); 700 if (!is_pipe_dsc(crtc_state)) { 701 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4, 702 pps_val); 703 /* 704 * If 2 VDSC instances are needed, configure PPS for second 705 * VDSC 706 */ 707 if (crtc_state->dsc.dsc_split) 708 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4, 709 pps_val); 710 } else { 711 intel_de_write(dev_priv, 712 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), 713 pps_val); 714 if (crtc_state->dsc.dsc_split) 715 intel_de_write(dev_priv, 716 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), 717 pps_val); 718 } 719 720 /* Populate PICTURE_PARAMETER_SET_5 registers */ 721 pps_val = 0; 722 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | 723 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); 724 drm_info(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); 725 if (!is_pipe_dsc(crtc_state)) { 726 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5, 727 pps_val); 728 /* 729 * If 2 VDSC instances are needed, configure PPS for second 730 * VDSC 731 */ 732 if (crtc_state->dsc.dsc_split) 733 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5, 734 pps_val); 735 } else { 736 intel_de_write(dev_priv, 737 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), 738 pps_val); 739 if (crtc_state->dsc.dsc_split) 740 intel_de_write(dev_priv, 741 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), 742 pps_val); 743 } 744 745 /* Populate PICTURE_PARAMETER_SET_6 registers */ 746 pps_val = 0; 747 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | 748 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | 749 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | 750 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); 751 drm_info(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); 752 if (!is_pipe_dsc(crtc_state)) { 753 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6, 754 pps_val); 755 /* 756 * If 2 VDSC instances are needed, configure PPS for second 757 * VDSC 758 */ 759 if (crtc_state->dsc.dsc_split) 760 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6, 761 pps_val); 762 } else { 763 intel_de_write(dev_priv, 764 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), 765 pps_val); 766 if (crtc_state->dsc.dsc_split) 767 intel_de_write(dev_priv, 768 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), 769 pps_val); 770 } 771 772 /* Populate PICTURE_PARAMETER_SET_7 registers */ 773 pps_val = 0; 774 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | 775 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); 776 drm_info(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); 777 if (!is_pipe_dsc(crtc_state)) { 778 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7, 779 pps_val); 780 /* 781 * If 2 VDSC instances are needed, configure PPS for second 782 * VDSC 783 */ 784 if (crtc_state->dsc.dsc_split) 785 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7, 786 pps_val); 787 } else { 788 intel_de_write(dev_priv, 789 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), 790 pps_val); 791 if (crtc_state->dsc.dsc_split) 792 intel_de_write(dev_priv, 793 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), 794 pps_val); 795 } 796 797 /* Populate PICTURE_PARAMETER_SET_8 registers */ 798 pps_val = 0; 799 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | 800 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); 801 drm_info(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); 802 if (!is_pipe_dsc(crtc_state)) { 803 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8, 804 pps_val); 805 /* 806 * If 2 VDSC instances are needed, configure PPS for second 807 * VDSC 808 */ 809 if (crtc_state->dsc.dsc_split) 810 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8, 811 pps_val); 812 } else { 813 intel_de_write(dev_priv, 814 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), 815 pps_val); 816 if (crtc_state->dsc.dsc_split) 817 intel_de_write(dev_priv, 818 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), 819 pps_val); 820 } 821 822 /* Populate PICTURE_PARAMETER_SET_9 registers */ 823 pps_val = 0; 824 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | 825 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); 826 drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); 827 if (!is_pipe_dsc(crtc_state)) { 828 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9, 829 pps_val); 830 /* 831 * If 2 VDSC instances are needed, configure PPS for second 832 * VDSC 833 */ 834 if (crtc_state->dsc.dsc_split) 835 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9, 836 pps_val); 837 } else { 838 intel_de_write(dev_priv, 839 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), 840 pps_val); 841 if (crtc_state->dsc.dsc_split) 842 intel_de_write(dev_priv, 843 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), 844 pps_val); 845 } 846 847 /* Populate PICTURE_PARAMETER_SET_10 registers */ 848 pps_val = 0; 849 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | 850 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | 851 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | 852 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); 853 drm_info(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); 854 if (!is_pipe_dsc(crtc_state)) { 855 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10, 856 pps_val); 857 /* 858 * If 2 VDSC instances are needed, configure PPS for second 859 * VDSC 860 */ 861 if (crtc_state->dsc.dsc_split) 862 intel_de_write(dev_priv, 863 DSCC_PICTURE_PARAMETER_SET_10, pps_val); 864 } else { 865 intel_de_write(dev_priv, 866 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), 867 pps_val); 868 if (crtc_state->dsc.dsc_split) 869 intel_de_write(dev_priv, 870 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), 871 pps_val); 872 } 873 874 /* Populate Picture parameter set 16 */ 875 pps_val = 0; 876 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | 877 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / 878 vdsc_cfg->slice_width) | 879 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / 880 vdsc_cfg->slice_height); 881 drm_info(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); 882 if (!is_pipe_dsc(crtc_state)) { 883 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16, 884 pps_val); 885 /* 886 * If 2 VDSC instances are needed, configure PPS for second 887 * VDSC 888 */ 889 if (crtc_state->dsc.dsc_split) 890 intel_de_write(dev_priv, 891 DSCC_PICTURE_PARAMETER_SET_16, pps_val); 892 } else { 893 intel_de_write(dev_priv, 894 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), 895 pps_val); 896 if (crtc_state->dsc.dsc_split) 897 intel_de_write(dev_priv, 898 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), 899 pps_val); 900 } 901 902 /* Populate the RC_BUF_THRESH registers */ 903 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); 904 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 905 rc_buf_thresh_dword[i / 4] |= 906 (u32)(vdsc_cfg->rc_buf_thresh[i] << 907 BITS_PER_BYTE * (i % 4)); 908 drm_info(&dev_priv->drm, " RC_BUF_THRESH%d = 0x%08x\n", i, 909 rc_buf_thresh_dword[i / 4]); 910 } 911 if (!is_pipe_dsc(crtc_state)) { 912 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0, 913 rc_buf_thresh_dword[0]); 914 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW, 915 rc_buf_thresh_dword[1]); 916 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1, 917 rc_buf_thresh_dword[2]); 918 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW, 919 rc_buf_thresh_dword[3]); 920 if (crtc_state->dsc.dsc_split) { 921 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0, 922 rc_buf_thresh_dword[0]); 923 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW, 924 rc_buf_thresh_dword[1]); 925 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1, 926 rc_buf_thresh_dword[2]); 927 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW, 928 rc_buf_thresh_dword[3]); 929 } 930 } else { 931 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe), 932 rc_buf_thresh_dword[0]); 933 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), 934 rc_buf_thresh_dword[1]); 935 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe), 936 rc_buf_thresh_dword[2]); 937 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), 938 rc_buf_thresh_dword[3]); 939 if (crtc_state->dsc.dsc_split) { 940 intel_de_write(dev_priv, 941 ICL_DSC1_RC_BUF_THRESH_0(pipe), 942 rc_buf_thresh_dword[0]); 943 intel_de_write(dev_priv, 944 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), 945 rc_buf_thresh_dword[1]); 946 intel_de_write(dev_priv, 947 ICL_DSC1_RC_BUF_THRESH_1(pipe), 948 rc_buf_thresh_dword[2]); 949 intel_de_write(dev_priv, 950 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), 951 rc_buf_thresh_dword[3]); 952 } 953 } 954 955 /* Populate the RC_RANGE_PARAMETERS registers */ 956 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); 957 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 958 rc_range_params_dword[i / 2] |= 959 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << 960 RC_BPG_OFFSET_SHIFT) | 961 (vdsc_cfg->rc_range_params[i].range_max_qp << 962 RC_MAX_QP_SHIFT) | 963 (vdsc_cfg->rc_range_params[i].range_min_qp << 964 RC_MIN_QP_SHIFT)) << 16 * (i % 2)); 965 drm_info(&dev_priv->drm, " RC_RANGE_PARAM_%d = 0x%08x\n", i, 966 rc_range_params_dword[i / 2]); 967 } 968 if (!is_pipe_dsc(crtc_state)) { 969 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0, 970 rc_range_params_dword[0]); 971 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW, 972 rc_range_params_dword[1]); 973 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1, 974 rc_range_params_dword[2]); 975 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW, 976 rc_range_params_dword[3]); 977 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2, 978 rc_range_params_dword[4]); 979 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW, 980 rc_range_params_dword[5]); 981 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3, 982 rc_range_params_dword[6]); 983 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW, 984 rc_range_params_dword[7]); 985 if (crtc_state->dsc.dsc_split) { 986 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0, 987 rc_range_params_dword[0]); 988 intel_de_write(dev_priv, 989 DSCC_RC_RANGE_PARAMETERS_0_UDW, 990 rc_range_params_dword[1]); 991 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1, 992 rc_range_params_dword[2]); 993 intel_de_write(dev_priv, 994 DSCC_RC_RANGE_PARAMETERS_1_UDW, 995 rc_range_params_dword[3]); 996 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2, 997 rc_range_params_dword[4]); 998 intel_de_write(dev_priv, 999 DSCC_RC_RANGE_PARAMETERS_2_UDW, 1000 rc_range_params_dword[5]); 1001 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3, 1002 rc_range_params_dword[6]); 1003 intel_de_write(dev_priv, 1004 DSCC_RC_RANGE_PARAMETERS_3_UDW, 1005 rc_range_params_dword[7]); 1006 } 1007 } else { 1008 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), 1009 rc_range_params_dword[0]); 1010 intel_de_write(dev_priv, 1011 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), 1012 rc_range_params_dword[1]); 1013 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), 1014 rc_range_params_dword[2]); 1015 intel_de_write(dev_priv, 1016 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), 1017 rc_range_params_dword[3]); 1018 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), 1019 rc_range_params_dword[4]); 1020 intel_de_write(dev_priv, 1021 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), 1022 rc_range_params_dword[5]); 1023 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), 1024 rc_range_params_dword[6]); 1025 intel_de_write(dev_priv, 1026 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), 1027 rc_range_params_dword[7]); 1028 if (crtc_state->dsc.dsc_split) { 1029 intel_de_write(dev_priv, 1030 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), 1031 rc_range_params_dword[0]); 1032 intel_de_write(dev_priv, 1033 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), 1034 rc_range_params_dword[1]); 1035 intel_de_write(dev_priv, 1036 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), 1037 rc_range_params_dword[2]); 1038 intel_de_write(dev_priv, 1039 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), 1040 rc_range_params_dword[3]); 1041 intel_de_write(dev_priv, 1042 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), 1043 rc_range_params_dword[4]); 1044 intel_de_write(dev_priv, 1045 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), 1046 rc_range_params_dword[5]); 1047 intel_de_write(dev_priv, 1048 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), 1049 rc_range_params_dword[6]); 1050 intel_de_write(dev_priv, 1051 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), 1052 rc_range_params_dword[7]); 1053 } 1054 } 1055 } 1056 1057 static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, 1058 const struct intel_crtc_state *crtc_state) 1059 { 1060 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1061 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1062 struct mipi_dsi_device *dsi; 1063 struct drm_dsc_picture_parameter_set pps; 1064 enum port port; 1065 1066 drm_dsc_pps_payload_pack(&pps, vdsc_cfg); 1067 1068 for_each_dsi_port(port, intel_dsi->ports) { 1069 dsi = intel_dsi->dsi_hosts[port]->device; 1070 1071 mipi_dsi_picture_parameter_set(dsi, &pps); 1072 mipi_dsi_compression_mode(dsi, true); 1073 } 1074 } 1075 1076 static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, 1077 const struct intel_crtc_state *crtc_state) 1078 { 1079 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1080 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1081 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1082 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; 1083 1084 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ 1085 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header); 1086 1087 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ 1088 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); 1089 1090 dig_port->write_infoframe(encoder, crtc_state, 1091 DP_SDP_PPS, &dp_dsc_pps_sdp, 1092 sizeof(dp_dsc_pps_sdp)); 1093 } 1094 1095 static i915_reg_t dss_ctl1_reg(const struct intel_crtc_state *crtc_state) 1096 { 1097 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1098 1099 return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL1(pipe) : DSS_CTL1; 1100 } 1101 1102 static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state) 1103 { 1104 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1105 1106 return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2; 1107 } 1108 1109 static struct intel_crtc * 1110 _get_crtc_for_pipe(struct drm_i915_private *i915, enum pipe pipe) 1111 { 1112 if (!intel_pipe_valid(i915, pipe)) 1113 return NULL; 1114 1115 return intel_get_crtc_for_pipe(i915, pipe); 1116 } 1117 1118 struct intel_crtc * 1119 intel_dsc_get_bigjoiner_secondary(const struct intel_crtc *primary_crtc) 1120 { 1121 return _get_crtc_for_pipe(to_i915(primary_crtc->base.dev), primary_crtc->pipe + 1); 1122 } 1123 1124 static struct intel_crtc * 1125 intel_dsc_get_bigjoiner_primary(const struct intel_crtc *secondary_crtc) 1126 { 1127 return _get_crtc_for_pipe(to_i915(secondary_crtc->base.dev), secondary_crtc->pipe - 1); 1128 } 1129 1130 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state) 1131 { 1132 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1133 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1134 u32 dss_ctl1_val = 0; 1135 1136 if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) { 1137 if (crtc_state->bigjoiner_slave) 1138 dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE; 1139 else 1140 dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER; 1141 1142 intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val); 1143 } 1144 } 1145 1146 void intel_dsc_enable(struct intel_encoder *encoder, 1147 const struct intel_crtc_state *crtc_state) 1148 { 1149 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1150 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1151 u32 dss_ctl1_val = 0; 1152 u32 dss_ctl2_val = 0; 1153 1154 if (!crtc_state->dsc.compression_enable) 1155 return; 1156 1157 intel_dsc_pps_configure(crtc_state); 1158 1159 if (!crtc_state->bigjoiner_slave) { 1160 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1161 intel_dsc_dsi_pps_write(encoder, crtc_state); 1162 else 1163 intel_dsc_dp_pps_write(encoder, crtc_state); 1164 } 1165 1166 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; 1167 if (crtc_state->dsc.dsc_split) { 1168 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; 1169 dss_ctl1_val |= JOINER_ENABLE; 1170 } 1171 if (crtc_state->bigjoiner) { 1172 dss_ctl1_val |= BIG_JOINER_ENABLE; 1173 if (!crtc_state->bigjoiner_slave) 1174 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE; 1175 } 1176 intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val); 1177 intel_de_write(dev_priv, dss_ctl2_reg(crtc_state), dss_ctl2_val); 1178 } 1179 1180 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) 1181 { 1182 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1183 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1184 1185 /* Disable only if either of them is enabled */ 1186 if (old_crtc_state->dsc.compression_enable || 1187 old_crtc_state->bigjoiner) { 1188 intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0); 1189 intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0); 1190 } 1191 } 1192 1193 void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state) 1194 { 1195 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1196 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1197 u32 dss_ctl1; 1198 1199 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state)); 1200 if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) { 1201 crtc_state->bigjoiner = true; 1202 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_secondary(crtc); 1203 drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc); 1204 } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) { 1205 crtc_state->bigjoiner = true; 1206 crtc_state->bigjoiner_slave = true; 1207 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_primary(crtc); 1208 drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc); 1209 } 1210 } 1211 1212 void intel_dsc_get_config(struct intel_crtc_state *crtc_state) 1213 { 1214 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1215 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1216 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1217 enum pipe pipe = crtc->pipe; 1218 enum intel_display_power_domain power_domain; 1219 intel_wakeref_t wakeref; 1220 u32 dss_ctl1, dss_ctl2, val; 1221 1222 if (!intel_dsc_source_support(crtc_state)) 1223 return; 1224 1225 power_domain = intel_dsc_power_domain(crtc_state); 1226 1227 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1228 if (!wakeref) 1229 return; 1230 1231 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state)); 1232 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc_state)); 1233 1234 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; 1235 if (!crtc_state->dsc.compression_enable) 1236 goto out; 1237 1238 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && 1239 (dss_ctl1 & JOINER_ENABLE); 1240 1241 if (dss_ctl1 & BIG_JOINER_ENABLE) { 1242 crtc_state->bigjoiner = true; 1243 1244 if (!(dss_ctl1 & MASTER_BIG_JOINER_ENABLE)) { 1245 crtc_state->bigjoiner_slave = true; 1246 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_primary(crtc); 1247 } else { 1248 crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_secondary(crtc); 1249 } 1250 drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc); 1251 } 1252 1253 /* FIXME: add more state readout as needed */ 1254 1255 /* PPS1 */ 1256 if (!is_pipe_dsc(crtc_state)) 1257 val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1); 1258 else 1259 val = intel_de_read(dev_priv, 1260 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); 1261 vdsc_cfg->bits_per_pixel = val; 1262 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; 1263 out: 1264 intel_display_power_put(dev_priv, power_domain, wakeref); 1265 } 1266